1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Ingenic SoCs pinctrl driver 4 * 5 * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net> 6 * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> 7 */ 8 9 #include <linux/compiler.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/of_device.h> 14 #include <linux/of_irq.h> 15 #include <linux/of_platform.h> 16 #include <linux/pinctrl/pinctrl.h> 17 #include <linux/pinctrl/pinmux.h> 18 #include <linux/pinctrl/pinconf.h> 19 #include <linux/pinctrl/pinconf-generic.h> 20 #include <linux/platform_device.h> 21 #include <linux/regmap.h> 22 #include <linux/slab.h> 23 24 #include "core.h" 25 #include "pinconf.h" 26 #include "pinmux.h" 27 28 #define GPIO_PIN 0x00 29 #define GPIO_MSK 0x20 30 31 #define JZ4740_GPIO_DATA 0x10 32 #define JZ4740_GPIO_PULL_DIS 0x30 33 #define JZ4740_GPIO_FUNC 0x40 34 #define JZ4740_GPIO_SELECT 0x50 35 #define JZ4740_GPIO_DIR 0x60 36 #define JZ4740_GPIO_TRIG 0x70 37 #define JZ4740_GPIO_FLAG 0x80 38 39 #define JZ4760_GPIO_INT 0x10 40 #define JZ4760_GPIO_PAT1 0x30 41 #define JZ4760_GPIO_PAT0 0x40 42 #define JZ4760_GPIO_FLAG 0x50 43 #define JZ4760_GPIO_PEN 0x70 44 45 #define X1830_GPIO_PEL 0x110 46 #define X1830_GPIO_PEH 0x120 47 48 #define REG_SET(x) ((x) + 0x4) 49 #define REG_CLEAR(x) ((x) + 0x8) 50 51 #define REG_PZ_BASE(x) ((x) * 7) 52 #define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0) 53 54 #define GPIO_PULL_DIS 0 55 #define GPIO_PULL_UP 1 56 #define GPIO_PULL_DOWN 2 57 58 #define PINS_PER_GPIO_CHIP 32 59 60 enum jz_version { 61 ID_JZ4740, 62 ID_JZ4725B, 63 ID_JZ4760, 64 ID_JZ4770, 65 ID_JZ4780, 66 ID_X1000, 67 ID_X1500, 68 ID_X1830, 69 }; 70 71 struct ingenic_chip_info { 72 unsigned int num_chips; 73 unsigned int reg_offset; 74 enum jz_version version; 75 76 const struct group_desc *groups; 77 unsigned int num_groups; 78 79 const struct function_desc *functions; 80 unsigned int num_functions; 81 82 const u32 *pull_ups, *pull_downs; 83 }; 84 85 struct ingenic_pinctrl { 86 struct device *dev; 87 struct regmap *map; 88 struct pinctrl_dev *pctl; 89 struct pinctrl_pin_desc *pdesc; 90 91 const struct ingenic_chip_info *info; 92 }; 93 94 struct ingenic_gpio_chip { 95 struct ingenic_pinctrl *jzpc; 96 struct gpio_chip gc; 97 struct irq_chip irq_chip; 98 unsigned int irq, reg_base; 99 }; 100 101 static const u32 jz4740_pull_ups[4] = { 102 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 103 }; 104 105 static const u32 jz4740_pull_downs[4] = { 106 0x00000000, 0x00000000, 0x00000000, 0x00000000, 107 }; 108 109 static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, }; 110 static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, }; 111 static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, }; 112 static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, }; 113 static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, }; 114 static int jz4740_lcd_8bit_pins[] = { 115 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x52, 0x53, 0x54, 116 }; 117 static int jz4740_lcd_16bit_pins[] = { 118 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x55, 119 }; 120 static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, }; 121 static int jz4740_lcd_18bit_tft_pins[] = { 0x56, 0x57, 0x31, 0x32, }; 122 static int jz4740_nand_cs1_pins[] = { 0x39, }; 123 static int jz4740_nand_cs2_pins[] = { 0x3a, }; 124 static int jz4740_nand_cs3_pins[] = { 0x3b, }; 125 static int jz4740_nand_cs4_pins[] = { 0x3c, }; 126 static int jz4740_pwm_pwm0_pins[] = { 0x77, }; 127 static int jz4740_pwm_pwm1_pins[] = { 0x78, }; 128 static int jz4740_pwm_pwm2_pins[] = { 0x79, }; 129 static int jz4740_pwm_pwm3_pins[] = { 0x7a, }; 130 static int jz4740_pwm_pwm4_pins[] = { 0x7b, }; 131 static int jz4740_pwm_pwm5_pins[] = { 0x7c, }; 132 static int jz4740_pwm_pwm6_pins[] = { 0x7e, }; 133 static int jz4740_pwm_pwm7_pins[] = { 0x7f, }; 134 135 static int jz4740_mmc_1bit_funcs[] = { 0, 0, 0, }; 136 static int jz4740_mmc_4bit_funcs[] = { 0, 0, 0, }; 137 static int jz4740_uart0_data_funcs[] = { 1, 1, }; 138 static int jz4740_uart0_hwflow_funcs[] = { 1, 1, }; 139 static int jz4740_uart1_data_funcs[] = { 2, 2, }; 140 static int jz4740_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 141 static int jz4740_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 142 static int jz4740_lcd_18bit_funcs[] = { 0, 0, }; 143 static int jz4740_lcd_18bit_tft_funcs[] = { 0, 0, 0, 0, }; 144 static int jz4740_nand_cs1_funcs[] = { 0, }; 145 static int jz4740_nand_cs2_funcs[] = { 0, }; 146 static int jz4740_nand_cs3_funcs[] = { 0, }; 147 static int jz4740_nand_cs4_funcs[] = { 0, }; 148 static int jz4740_pwm_pwm0_funcs[] = { 0, }; 149 static int jz4740_pwm_pwm1_funcs[] = { 0, }; 150 static int jz4740_pwm_pwm2_funcs[] = { 0, }; 151 static int jz4740_pwm_pwm3_funcs[] = { 0, }; 152 static int jz4740_pwm_pwm4_funcs[] = { 0, }; 153 static int jz4740_pwm_pwm5_funcs[] = { 0, }; 154 static int jz4740_pwm_pwm6_funcs[] = { 0, }; 155 static int jz4740_pwm_pwm7_funcs[] = { 0, }; 156 157 #define INGENIC_PIN_GROUP(name, id) \ 158 { \ 159 name, \ 160 id##_pins, \ 161 ARRAY_SIZE(id##_pins), \ 162 id##_funcs, \ 163 } 164 165 static const struct group_desc jz4740_groups[] = { 166 INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit), 167 INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit), 168 INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data), 169 INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow), 170 INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data), 171 INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit), 172 INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit), 173 INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit), 174 INGENIC_PIN_GROUP("lcd-18bit-tft", jz4740_lcd_18bit_tft), 175 { "lcd-no-pins", }, 176 INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1), 177 INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2), 178 INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3), 179 INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4), 180 INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0), 181 INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1), 182 INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2), 183 INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3), 184 INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4), 185 INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5), 186 INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6), 187 INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7), 188 }; 189 190 static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 191 static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 192 static const char *jz4740_uart1_groups[] = { "uart1-data", }; 193 static const char *jz4740_lcd_groups[] = { 194 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-18bit-tft", "lcd-no-pins", 195 }; 196 static const char *jz4740_nand_groups[] = { 197 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", 198 }; 199 static const char *jz4740_pwm0_groups[] = { "pwm0", }; 200 static const char *jz4740_pwm1_groups[] = { "pwm1", }; 201 static const char *jz4740_pwm2_groups[] = { "pwm2", }; 202 static const char *jz4740_pwm3_groups[] = { "pwm3", }; 203 static const char *jz4740_pwm4_groups[] = { "pwm4", }; 204 static const char *jz4740_pwm5_groups[] = { "pwm5", }; 205 static const char *jz4740_pwm6_groups[] = { "pwm6", }; 206 static const char *jz4740_pwm7_groups[] = { "pwm7", }; 207 208 static const struct function_desc jz4740_functions[] = { 209 { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), }, 210 { "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), }, 211 { "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), }, 212 { "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), }, 213 { "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), }, 214 { "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), }, 215 { "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), }, 216 { "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), }, 217 { "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), }, 218 { "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), }, 219 { "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), }, 220 { "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), }, 221 { "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), }, 222 }; 223 224 static const struct ingenic_chip_info jz4740_chip_info = { 225 .num_chips = 4, 226 .reg_offset = 0x100, 227 .version = ID_JZ4740, 228 .groups = jz4740_groups, 229 .num_groups = ARRAY_SIZE(jz4740_groups), 230 .functions = jz4740_functions, 231 .num_functions = ARRAY_SIZE(jz4740_functions), 232 .pull_ups = jz4740_pull_ups, 233 .pull_downs = jz4740_pull_downs, 234 }; 235 236 static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, }; 237 static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, }; 238 static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, }; 239 static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, }; 240 static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, }; 241 static int jz4725b_nand_cs1_pins[] = { 0x55, }; 242 static int jz4725b_nand_cs2_pins[] = { 0x56, }; 243 static int jz4725b_nand_cs3_pins[] = { 0x57, }; 244 static int jz4725b_nand_cs4_pins[] = { 0x58, }; 245 static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 }; 246 static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d }; 247 static int jz4725b_pwm_pwm0_pins[] = { 0x4a, }; 248 static int jz4725b_pwm_pwm1_pins[] = { 0x4b, }; 249 static int jz4725b_pwm_pwm2_pins[] = { 0x4c, }; 250 static int jz4725b_pwm_pwm3_pins[] = { 0x4d, }; 251 static int jz4725b_pwm_pwm4_pins[] = { 0x4e, }; 252 static int jz4725b_pwm_pwm5_pins[] = { 0x4f, }; 253 static int jz4725b_lcd_8bit_pins[] = { 254 0x72, 0x73, 0x74, 255 0x60, 0x61, 0x62, 0x63, 256 0x64, 0x65, 0x66, 0x67, 257 }; 258 static int jz4725b_lcd_16bit_pins[] = { 259 0x68, 0x69, 0x6a, 0x6b, 260 0x6c, 0x6d, 0x6e, 0x6f, 261 }; 262 static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, }; 263 static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 264 static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 265 static int jz4725b_lcd_generic_pins[] = { 0x75, }; 266 267 static int jz4725b_mmc0_1bit_funcs[] = { 1, 1, 1, }; 268 static int jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, }; 269 static int jz4725b_mmc1_1bit_funcs[] = { 0, 0, 0, }; 270 static int jz4725b_mmc1_4bit_funcs[] = { 0, 0, 0, }; 271 static int jz4725b_uart_data_funcs[] = { 1, 1, }; 272 static int jz4725b_nand_cs1_funcs[] = { 0, }; 273 static int jz4725b_nand_cs2_funcs[] = { 0, }; 274 static int jz4725b_nand_cs3_funcs[] = { 0, }; 275 static int jz4725b_nand_cs4_funcs[] = { 0, }; 276 static int jz4725b_nand_cle_ale_funcs[] = { 0, 0, }; 277 static int jz4725b_nand_fre_fwe_funcs[] = { 0, 0, }; 278 static int jz4725b_pwm_pwm0_funcs[] = { 0, }; 279 static int jz4725b_pwm_pwm1_funcs[] = { 0, }; 280 static int jz4725b_pwm_pwm2_funcs[] = { 0, }; 281 static int jz4725b_pwm_pwm3_funcs[] = { 0, }; 282 static int jz4725b_pwm_pwm4_funcs[] = { 0, }; 283 static int jz4725b_pwm_pwm5_funcs[] = { 0, }; 284 static int jz4725b_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 285 static int jz4725b_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 286 static int jz4725b_lcd_18bit_funcs[] = { 0, 0, }; 287 static int jz4725b_lcd_24bit_funcs[] = { 1, 1, 1, 1, }; 288 static int jz4725b_lcd_special_funcs[] = { 0, 0, 0, 0, }; 289 static int jz4725b_lcd_generic_funcs[] = { 0, }; 290 291 static const struct group_desc jz4725b_groups[] = { 292 INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit), 293 INGENIC_PIN_GROUP("mmc0-4bit", jz4725b_mmc0_4bit), 294 INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit), 295 INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit), 296 INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data), 297 INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1), 298 INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2), 299 INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3), 300 INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4), 301 INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale), 302 INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe), 303 INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0), 304 INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1), 305 INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2), 306 INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3), 307 INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4), 308 INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5), 309 INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit), 310 INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit), 311 INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit), 312 INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit), 313 INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special), 314 INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic), 315 }; 316 317 static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 318 static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 319 static const char *jz4725b_uart_groups[] = { "uart-data", }; 320 static const char *jz4725b_nand_groups[] = { 321 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", 322 "nand-cle-ale", "nand-fre-fwe", 323 }; 324 static const char *jz4725b_pwm0_groups[] = { "pwm0", }; 325 static const char *jz4725b_pwm1_groups[] = { "pwm1", }; 326 static const char *jz4725b_pwm2_groups[] = { "pwm2", }; 327 static const char *jz4725b_pwm3_groups[] = { "pwm3", }; 328 static const char *jz4725b_pwm4_groups[] = { "pwm4", }; 329 static const char *jz4725b_pwm5_groups[] = { "pwm5", }; 330 static const char *jz4725b_lcd_groups[] = { 331 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 332 "lcd-special", "lcd-generic", 333 }; 334 335 static const struct function_desc jz4725b_functions[] = { 336 { "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), }, 337 { "mmc1", jz4725b_mmc1_groups, ARRAY_SIZE(jz4725b_mmc1_groups), }, 338 { "uart", jz4725b_uart_groups, ARRAY_SIZE(jz4725b_uart_groups), }, 339 { "nand", jz4725b_nand_groups, ARRAY_SIZE(jz4725b_nand_groups), }, 340 { "pwm0", jz4725b_pwm0_groups, ARRAY_SIZE(jz4725b_pwm0_groups), }, 341 { "pwm1", jz4725b_pwm1_groups, ARRAY_SIZE(jz4725b_pwm1_groups), }, 342 { "pwm2", jz4725b_pwm2_groups, ARRAY_SIZE(jz4725b_pwm2_groups), }, 343 { "pwm3", jz4725b_pwm3_groups, ARRAY_SIZE(jz4725b_pwm3_groups), }, 344 { "pwm4", jz4725b_pwm4_groups, ARRAY_SIZE(jz4725b_pwm4_groups), }, 345 { "pwm5", jz4725b_pwm5_groups, ARRAY_SIZE(jz4725b_pwm5_groups), }, 346 { "lcd", jz4725b_lcd_groups, ARRAY_SIZE(jz4725b_lcd_groups), }, 347 }; 348 349 static const struct ingenic_chip_info jz4725b_chip_info = { 350 .num_chips = 4, 351 .reg_offset = 0x100, 352 .version = ID_JZ4725B, 353 .groups = jz4725b_groups, 354 .num_groups = ARRAY_SIZE(jz4725b_groups), 355 .functions = jz4725b_functions, 356 .num_functions = ARRAY_SIZE(jz4725b_functions), 357 .pull_ups = jz4740_pull_ups, 358 .pull_downs = jz4740_pull_downs, 359 }; 360 361 static const u32 jz4760_pull_ups[6] = { 362 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0xfffff00f, 363 }; 364 365 static const u32 jz4760_pull_downs[6] = { 366 0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0, 367 }; 368 369 static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, }; 370 static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 371 static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, }; 372 static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 373 static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, }; 374 static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; 375 static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, }; 376 static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, }; 377 static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 378 static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 379 static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 380 static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 381 static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 382 static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 383 static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 384 static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 385 static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 386 static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 387 static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 388 static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 389 static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 390 static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 391 static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 392 static int jz4760_nemc_8bit_data_pins[] = { 393 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 394 }; 395 static int jz4760_nemc_16bit_data_pins[] = { 396 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 397 }; 398 static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 399 static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 400 static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, }; 401 static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 402 static int jz4760_nemc_wait_pins[] = { 0x1b, }; 403 static int jz4760_nemc_cs1_pins[] = { 0x15, }; 404 static int jz4760_nemc_cs2_pins[] = { 0x16, }; 405 static int jz4760_nemc_cs3_pins[] = { 0x17, }; 406 static int jz4760_nemc_cs4_pins[] = { 0x18, }; 407 static int jz4760_nemc_cs5_pins[] = { 0x19, }; 408 static int jz4760_nemc_cs6_pins[] = { 0x1a, }; 409 static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, }; 410 static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, }; 411 static int jz4760_cim_pins[] = { 412 0x26, 0x27, 0x28, 0x29, 413 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 414 }; 415 static int jz4760_lcd_24bit_pins[] = { 416 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 417 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 418 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 419 0x58, 0x59, 0x5a, 0x5b, 420 }; 421 static int jz4760_pwm_pwm0_pins[] = { 0x80, }; 422 static int jz4760_pwm_pwm1_pins[] = { 0x81, }; 423 static int jz4760_pwm_pwm2_pins[] = { 0x82, }; 424 static int jz4760_pwm_pwm3_pins[] = { 0x83, }; 425 static int jz4760_pwm_pwm4_pins[] = { 0x84, }; 426 static int jz4760_pwm_pwm5_pins[] = { 0x85, }; 427 static int jz4760_pwm_pwm6_pins[] = { 0x6a, }; 428 static int jz4760_pwm_pwm7_pins[] = { 0x6b, }; 429 430 static int jz4760_uart0_data_funcs[] = { 0, 0, }; 431 static int jz4760_uart0_hwflow_funcs[] = { 0, 0, }; 432 static int jz4760_uart1_data_funcs[] = { 0, 0, }; 433 static int jz4760_uart1_hwflow_funcs[] = { 0, 0, }; 434 static int jz4760_uart2_data_funcs[] = { 0, 0, }; 435 static int jz4760_uart2_hwflow_funcs[] = { 0, 0, }; 436 static int jz4760_uart3_data_funcs[] = { 0, 1, }; 437 static int jz4760_uart3_hwflow_funcs[] = { 0, 0, }; 438 static int jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, }; 439 static int jz4760_mmc0_4bit_a_funcs[] = { 1, 1, 1, }; 440 static int jz4760_mmc0_1bit_e_funcs[] = { 0, 0, 0, }; 441 static int jz4760_mmc0_4bit_e_funcs[] = { 0, 0, 0, }; 442 static int jz4760_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, }; 443 static int jz4760_mmc1_1bit_d_funcs[] = { 0, 0, 0, }; 444 static int jz4760_mmc1_4bit_d_funcs[] = { 0, 0, 0, }; 445 static int jz4760_mmc1_1bit_e_funcs[] = { 1, 1, 1, }; 446 static int jz4760_mmc1_4bit_e_funcs[] = { 1, 1, 1, }; 447 static int jz4760_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, }; 448 static int jz4760_mmc2_1bit_b_funcs[] = { 0, 0, 0, }; 449 static int jz4760_mmc2_4bit_b_funcs[] = { 0, 0, 0, }; 450 static int jz4760_mmc2_1bit_e_funcs[] = { 2, 2, 2, }; 451 static int jz4760_mmc2_4bit_e_funcs[] = { 2, 2, 2, }; 452 static int jz4760_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, }; 453 static int jz4760_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 454 static int jz4760_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 455 static int jz4760_nemc_cle_ale_funcs[] = { 0, 0, }; 456 static int jz4760_nemc_addr_funcs[] = { 0, 0, 0, 0, }; 457 static int jz4760_nemc_rd_we_funcs[] = { 0, 0, }; 458 static int jz4760_nemc_frd_fwe_funcs[] = { 0, 0, }; 459 static int jz4760_nemc_wait_funcs[] = { 0, }; 460 static int jz4760_nemc_cs1_funcs[] = { 0, }; 461 static int jz4760_nemc_cs2_funcs[] = { 0, }; 462 static int jz4760_nemc_cs3_funcs[] = { 0, }; 463 static int jz4760_nemc_cs4_funcs[] = { 0, }; 464 static int jz4760_nemc_cs5_funcs[] = { 0, }; 465 static int jz4760_nemc_cs6_funcs[] = { 0, }; 466 static int jz4760_i2c0_funcs[] = { 0, 0, }; 467 static int jz4760_i2c1_funcs[] = { 0, 0, }; 468 static int jz4760_cim_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 469 static int jz4760_lcd_24bit_funcs[] = { 470 0, 0, 0, 0, 0, 0, 0, 0, 471 0, 0, 0, 0, 0, 0, 0, 0, 472 0, 0, 0, 0, 0, 0, 0, 0, 473 0, 0, 0, 0, 474 }; 475 static int jz4760_pwm_pwm0_funcs[] = { 0, }; 476 static int jz4760_pwm_pwm1_funcs[] = { 0, }; 477 static int jz4760_pwm_pwm2_funcs[] = { 0, }; 478 static int jz4760_pwm_pwm3_funcs[] = { 0, }; 479 static int jz4760_pwm_pwm4_funcs[] = { 0, }; 480 static int jz4760_pwm_pwm5_funcs[] = { 0, }; 481 static int jz4760_pwm_pwm6_funcs[] = { 0, }; 482 static int jz4760_pwm_pwm7_funcs[] = { 0, }; 483 484 static const struct group_desc jz4760_groups[] = { 485 INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data), 486 INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow), 487 INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data), 488 INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow), 489 INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data), 490 INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow), 491 INGENIC_PIN_GROUP("uart3-data", jz4760_uart3_data), 492 INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow), 493 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4760_mmc0_1bit_a), 494 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a), 495 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e), 496 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e), 497 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e), 498 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d), 499 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d), 500 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e), 501 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e), 502 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e), 503 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b), 504 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b), 505 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e), 506 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e), 507 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e), 508 INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data), 509 INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data), 510 INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale), 511 INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr), 512 INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we), 513 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe), 514 INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait), 515 INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1), 516 INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2), 517 INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3), 518 INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4), 519 INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5), 520 INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6), 521 INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0), 522 INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1), 523 INGENIC_PIN_GROUP("cim-data", jz4760_cim), 524 INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit), 525 { "lcd-no-pins", }, 526 INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0), 527 INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1), 528 INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2), 529 INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3), 530 INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4), 531 INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5), 532 INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6), 533 INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7), 534 }; 535 536 static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 537 static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 538 static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 539 static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 540 static const char *jz4760_mmc0_groups[] = { 541 "mmc0-1bit-a", "mmc0-4bit-a", 542 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", 543 }; 544 static const char *jz4760_mmc1_groups[] = { 545 "mmc1-1bit-d", "mmc1-4bit-d", 546 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e", 547 }; 548 static const char *jz4760_mmc2_groups[] = { 549 "mmc2-1bit-b", "mmc2-4bit-b", 550 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e", 551 }; 552 static const char *jz4760_nemc_groups[] = { 553 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 554 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 555 }; 556 static const char *jz4760_cs1_groups[] = { "nemc-cs1", }; 557 static const char *jz4760_cs2_groups[] = { "nemc-cs2", }; 558 static const char *jz4760_cs3_groups[] = { "nemc-cs3", }; 559 static const char *jz4760_cs4_groups[] = { "nemc-cs4", }; 560 static const char *jz4760_cs5_groups[] = { "nemc-cs5", }; 561 static const char *jz4760_cs6_groups[] = { "nemc-cs6", }; 562 static const char *jz4760_i2c0_groups[] = { "i2c0-data", }; 563 static const char *jz4760_i2c1_groups[] = { "i2c1-data", }; 564 static const char *jz4760_cim_groups[] = { "cim-data", }; 565 static const char *jz4760_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", }; 566 static const char *jz4760_pwm0_groups[] = { "pwm0", }; 567 static const char *jz4760_pwm1_groups[] = { "pwm1", }; 568 static const char *jz4760_pwm2_groups[] = { "pwm2", }; 569 static const char *jz4760_pwm3_groups[] = { "pwm3", }; 570 static const char *jz4760_pwm4_groups[] = { "pwm4", }; 571 static const char *jz4760_pwm5_groups[] = { "pwm5", }; 572 static const char *jz4760_pwm6_groups[] = { "pwm6", }; 573 static const char *jz4760_pwm7_groups[] = { "pwm7", }; 574 575 static const struct function_desc jz4760_functions[] = { 576 { "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), }, 577 { "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), }, 578 { "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), }, 579 { "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), }, 580 { "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), }, 581 { "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), }, 582 { "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), }, 583 { "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), }, 584 { "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), }, 585 { "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), }, 586 { "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), }, 587 { "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), }, 588 { "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), }, 589 { "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), }, 590 { "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), }, 591 { "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), }, 592 { "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), }, 593 { "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), }, 594 { "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), }, 595 { "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), }, 596 { "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), }, 597 { "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), }, 598 { "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), }, 599 { "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), }, 600 { "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), }, 601 { "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), }, 602 }; 603 604 static const struct ingenic_chip_info jz4760_chip_info = { 605 .num_chips = 6, 606 .reg_offset = 0x100, 607 .version = ID_JZ4760, 608 .groups = jz4760_groups, 609 .num_groups = ARRAY_SIZE(jz4760_groups), 610 .functions = jz4760_functions, 611 .num_functions = ARRAY_SIZE(jz4760_functions), 612 .pull_ups = jz4760_pull_ups, 613 .pull_downs = jz4760_pull_downs, 614 }; 615 616 static const u32 jz4770_pull_ups[6] = { 617 0x3fffffff, 0xfff0030c, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0xffa7f00f, 618 }; 619 620 static const u32 jz4770_pull_downs[6] = { 621 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0, 622 }; 623 624 static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, }; 625 static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 626 static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, }; 627 static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 628 static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, }; 629 static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; 630 static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, }; 631 static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, }; 632 static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 633 static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 634 static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 635 static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 636 static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 637 static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 638 static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 639 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 640 static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 641 static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 642 static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 643 static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 644 static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 645 static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 646 static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 647 static int jz4770_nemc_8bit_data_pins[] = { 648 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 649 }; 650 static int jz4770_nemc_16bit_data_pins[] = { 651 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 652 }; 653 static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 654 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 655 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, }; 656 static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 657 static int jz4770_nemc_wait_pins[] = { 0x1b, }; 658 static int jz4770_nemc_cs1_pins[] = { 0x15, }; 659 static int jz4770_nemc_cs2_pins[] = { 0x16, }; 660 static int jz4770_nemc_cs3_pins[] = { 0x17, }; 661 static int jz4770_nemc_cs4_pins[] = { 0x18, }; 662 static int jz4770_nemc_cs5_pins[] = { 0x19, }; 663 static int jz4770_nemc_cs6_pins[] = { 0x1a, }; 664 static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, }; 665 static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, }; 666 static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, }; 667 static int jz4770_cim_8bit_pins[] = { 668 0x26, 0x27, 0x28, 0x29, 669 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 670 }; 671 static int jz4770_cim_12bit_pins[] = { 672 0x32, 0x33, 0xb0, 0xb1, 673 }; 674 static int jz4770_lcd_24bit_pins[] = { 675 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 676 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 677 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 678 0x58, 0x59, 0x5a, 0x5b, 679 }; 680 static int jz4770_pwm_pwm0_pins[] = { 0x80, }; 681 static int jz4770_pwm_pwm1_pins[] = { 0x81, }; 682 static int jz4770_pwm_pwm2_pins[] = { 0x82, }; 683 static int jz4770_pwm_pwm3_pins[] = { 0x83, }; 684 static int jz4770_pwm_pwm4_pins[] = { 0x84, }; 685 static int jz4770_pwm_pwm5_pins[] = { 0x85, }; 686 static int jz4770_pwm_pwm6_pins[] = { 0x6a, }; 687 static int jz4770_pwm_pwm7_pins[] = { 0x6b, }; 688 static int jz4770_mac_rmii_pins[] = { 689 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8, 690 }; 691 static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, }; 692 static int jz4770_otg_pins[] = { 0x8a, }; 693 694 static int jz4770_uart0_data_funcs[] = { 0, 0, }; 695 static int jz4770_uart0_hwflow_funcs[] = { 0, 0, }; 696 static int jz4770_uart1_data_funcs[] = { 0, 0, }; 697 static int jz4770_uart1_hwflow_funcs[] = { 0, 0, }; 698 static int jz4770_uart2_data_funcs[] = { 0, 0, }; 699 static int jz4770_uart2_hwflow_funcs[] = { 0, 0, }; 700 static int jz4770_uart3_data_funcs[] = { 0, 1, }; 701 static int jz4770_uart3_hwflow_funcs[] = { 0, 0, }; 702 static int jz4770_mmc0_1bit_a_funcs[] = { 1, 1, 0, }; 703 static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, }; 704 static int jz4770_mmc0_1bit_e_funcs[] = { 0, 0, 0, }; 705 static int jz4770_mmc0_4bit_e_funcs[] = { 0, 0, 0, }; 706 static int jz4770_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, }; 707 static int jz4770_mmc1_1bit_d_funcs[] = { 0, 0, 0, }; 708 static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, }; 709 static int jz4770_mmc1_1bit_e_funcs[] = { 1, 1, 1, }; 710 static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, }; 711 static int jz4770_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, }; 712 static int jz4770_mmc2_1bit_b_funcs[] = { 0, 0, 0, }; 713 static int jz4770_mmc2_4bit_b_funcs[] = { 0, 0, 0, }; 714 static int jz4770_mmc2_1bit_e_funcs[] = { 2, 2, 2, }; 715 static int jz4770_mmc2_4bit_e_funcs[] = { 2, 2, 2, }; 716 static int jz4770_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, }; 717 static int jz4770_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 718 static int jz4770_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 719 static int jz4770_nemc_cle_ale_funcs[] = { 0, 0, }; 720 static int jz4770_nemc_addr_funcs[] = { 0, 0, 0, 0, }; 721 static int jz4770_nemc_rd_we_funcs[] = { 0, 0, }; 722 static int jz4770_nemc_frd_fwe_funcs[] = { 0, 0, }; 723 static int jz4770_nemc_wait_funcs[] = { 0, }; 724 static int jz4770_nemc_cs1_funcs[] = { 0, }; 725 static int jz4770_nemc_cs2_funcs[] = { 0, }; 726 static int jz4770_nemc_cs3_funcs[] = { 0, }; 727 static int jz4770_nemc_cs4_funcs[] = { 0, }; 728 static int jz4770_nemc_cs5_funcs[] = { 0, }; 729 static int jz4770_nemc_cs6_funcs[] = { 0, }; 730 static int jz4770_i2c0_funcs[] = { 0, 0, }; 731 static int jz4770_i2c1_funcs[] = { 0, 0, }; 732 static int jz4770_i2c2_funcs[] = { 2, 2, }; 733 static int jz4770_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 734 static int jz4770_cim_12bit_funcs[] = { 0, 0, 0, 0, }; 735 static int jz4770_lcd_24bit_funcs[] = { 736 0, 0, 0, 0, 0, 0, 0, 0, 737 0, 0, 0, 0, 0, 0, 0, 0, 738 0, 0, 0, 0, 0, 0, 0, 0, 739 0, 0, 0, 0, 740 }; 741 static int jz4770_pwm_pwm0_funcs[] = { 0, }; 742 static int jz4770_pwm_pwm1_funcs[] = { 0, }; 743 static int jz4770_pwm_pwm2_funcs[] = { 0, }; 744 static int jz4770_pwm_pwm3_funcs[] = { 0, }; 745 static int jz4770_pwm_pwm4_funcs[] = { 0, }; 746 static int jz4770_pwm_pwm5_funcs[] = { 0, }; 747 static int jz4770_pwm_pwm6_funcs[] = { 0, }; 748 static int jz4770_pwm_pwm7_funcs[] = { 0, }; 749 static int jz4770_mac_rmii_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 750 static int jz4770_mac_mii_funcs[] = { 0, 0, }; 751 static int jz4770_otg_funcs[] = { 0, }; 752 753 static const struct group_desc jz4770_groups[] = { 754 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data), 755 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow), 756 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data), 757 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow), 758 INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data), 759 INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow), 760 INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data), 761 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow), 762 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a), 763 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a), 764 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e), 765 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e), 766 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e), 767 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d), 768 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d), 769 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e), 770 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e), 771 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e), 772 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b), 773 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b), 774 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e), 775 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e), 776 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e), 777 INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data), 778 INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data), 779 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale), 780 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr), 781 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we), 782 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe), 783 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait), 784 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1), 785 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2), 786 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3), 787 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4), 788 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5), 789 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6), 790 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0), 791 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1), 792 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2), 793 INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit), 794 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit), 795 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit), 796 { "lcd-no-pins", }, 797 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0), 798 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1), 799 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2), 800 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3), 801 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4), 802 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5), 803 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6), 804 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7), 805 INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii), 806 INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii), 807 INGENIC_PIN_GROUP("otg-vbus", jz4770_otg), 808 }; 809 810 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 811 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 812 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 813 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 814 static const char *jz4770_mmc0_groups[] = { 815 "mmc0-1bit-a", "mmc0-4bit-a", 816 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", 817 }; 818 static const char *jz4770_mmc1_groups[] = { 819 "mmc1-1bit-d", "mmc1-4bit-d", 820 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e", 821 }; 822 static const char *jz4770_mmc2_groups[] = { 823 "mmc2-1bit-b", "mmc2-4bit-b", 824 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e", 825 }; 826 static const char *jz4770_nemc_groups[] = { 827 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 828 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 829 }; 830 static const char *jz4770_cs1_groups[] = { "nemc-cs1", }; 831 static const char *jz4770_cs2_groups[] = { "nemc-cs2", }; 832 static const char *jz4770_cs3_groups[] = { "nemc-cs3", }; 833 static const char *jz4770_cs4_groups[] = { "nemc-cs4", }; 834 static const char *jz4770_cs5_groups[] = { "nemc-cs5", }; 835 static const char *jz4770_cs6_groups[] = { "nemc-cs6", }; 836 static const char *jz4770_i2c0_groups[] = { "i2c0-data", }; 837 static const char *jz4770_i2c1_groups[] = { "i2c1-data", }; 838 static const char *jz4770_i2c2_groups[] = { "i2c2-data", }; 839 static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", }; 840 static const char *jz4770_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", }; 841 static const char *jz4770_pwm0_groups[] = { "pwm0", }; 842 static const char *jz4770_pwm1_groups[] = { "pwm1", }; 843 static const char *jz4770_pwm2_groups[] = { "pwm2", }; 844 static const char *jz4770_pwm3_groups[] = { "pwm3", }; 845 static const char *jz4770_pwm4_groups[] = { "pwm4", }; 846 static const char *jz4770_pwm5_groups[] = { "pwm5", }; 847 static const char *jz4770_pwm6_groups[] = { "pwm6", }; 848 static const char *jz4770_pwm7_groups[] = { "pwm7", }; 849 static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", }; 850 static const char *jz4770_otg_groups[] = { "otg-vbus", }; 851 852 static const struct function_desc jz4770_functions[] = { 853 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), }, 854 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), }, 855 { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), }, 856 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), }, 857 { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), }, 858 { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), }, 859 { "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), }, 860 { "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), }, 861 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), }, 862 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), }, 863 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), }, 864 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), }, 865 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), }, 866 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), }, 867 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), }, 868 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), }, 869 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), }, 870 { "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), }, 871 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), }, 872 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), }, 873 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), }, 874 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), }, 875 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), }, 876 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), }, 877 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), }, 878 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), }, 879 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), }, 880 { "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), }, 881 { "otg", jz4770_otg_groups, ARRAY_SIZE(jz4770_otg_groups), }, 882 }; 883 884 static const struct ingenic_chip_info jz4770_chip_info = { 885 .num_chips = 6, 886 .reg_offset = 0x100, 887 .version = ID_JZ4770, 888 .groups = jz4770_groups, 889 .num_groups = ARRAY_SIZE(jz4770_groups), 890 .functions = jz4770_functions, 891 .num_functions = ARRAY_SIZE(jz4770_functions), 892 .pull_ups = jz4770_pull_ups, 893 .pull_downs = jz4770_pull_downs, 894 }; 895 896 static int jz4780_uart2_data_pins[] = { 0x66, 0x67, }; 897 static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, }; 898 static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, }; 899 static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, }; 900 static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, }; 901 static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, }; 902 static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, }; 903 904 static int jz4780_uart2_data_funcs[] = { 1, 1, }; 905 static int jz4780_uart2_hwflow_funcs[] = { 1, 1, }; 906 static int jz4780_uart4_data_funcs[] = { 2, 2, }; 907 static int jz4780_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, }; 908 static int jz4780_i2c3_funcs[] = { 1, 1, }; 909 static int jz4780_i2c4_e_funcs[] = { 1, 1, }; 910 static int jz4780_i2c4_f_funcs[] = { 1, 1, }; 911 912 static const struct group_desc jz4780_groups[] = { 913 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data), 914 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow), 915 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data), 916 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow), 917 INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data), 918 INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow), 919 INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data), 920 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow), 921 INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data), 922 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a), 923 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a), 924 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a), 925 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e), 926 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e), 927 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d), 928 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d), 929 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e), 930 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e), 931 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b), 932 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b), 933 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e), 934 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e), 935 INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data), 936 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale), 937 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr), 938 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we), 939 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe), 940 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait), 941 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1), 942 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2), 943 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3), 944 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4), 945 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5), 946 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6), 947 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0), 948 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1), 949 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2), 950 INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3), 951 INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e), 952 INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f), 953 INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit), 954 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit), 955 { "lcd-no-pins", }, 956 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0), 957 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1), 958 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2), 959 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3), 960 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4), 961 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5), 962 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6), 963 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7), 964 }; 965 966 static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 967 static const char *jz4780_uart4_groups[] = { "uart4-data", }; 968 static const char *jz4780_mmc0_groups[] = { 969 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a", 970 "mmc0-1bit-e", "mmc0-4bit-e", 971 }; 972 static const char *jz4780_mmc1_groups[] = { 973 "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e", 974 }; 975 static const char *jz4780_mmc2_groups[] = { 976 "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e", 977 }; 978 static const char *jz4780_nemc_groups[] = { 979 "nemc-data", "nemc-cle-ale", "nemc-addr", 980 "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 981 }; 982 static const char *jz4780_i2c3_groups[] = { "i2c3-data", }; 983 static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", }; 984 static const char *jz4780_cim_groups[] = { "cim-data", }; 985 986 static const struct function_desc jz4780_functions[] = { 987 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), }, 988 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), }, 989 { "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), }, 990 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), }, 991 { "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), }, 992 { "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), }, 993 { "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), }, 994 { "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), }, 995 { "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), }, 996 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), }, 997 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), }, 998 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), }, 999 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), }, 1000 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), }, 1001 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), }, 1002 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), }, 1003 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), }, 1004 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), }, 1005 { "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), }, 1006 { "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), }, 1007 { "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), }, 1008 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), }, 1009 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), }, 1010 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), }, 1011 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), }, 1012 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), }, 1013 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), }, 1014 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), }, 1015 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), }, 1016 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), }, 1017 }; 1018 1019 static const struct ingenic_chip_info jz4780_chip_info = { 1020 .num_chips = 6, 1021 .reg_offset = 0x100, 1022 .version = ID_JZ4780, 1023 .groups = jz4780_groups, 1024 .num_groups = ARRAY_SIZE(jz4780_groups), 1025 .functions = jz4780_functions, 1026 .num_functions = ARRAY_SIZE(jz4780_functions), 1027 .pull_ups = jz4770_pull_ups, 1028 .pull_downs = jz4770_pull_downs, 1029 }; 1030 1031 static const u32 x1000_pull_ups[4] = { 1032 0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f, 1033 }; 1034 1035 static const u32 x1000_pull_downs[4] = { 1036 0x00000000, 0x02000000, 0x02000000, 0x00000000, 1037 }; 1038 1039 static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, }; 1040 static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; 1041 static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, }; 1042 static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, }; 1043 static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, }; 1044 static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, }; 1045 static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, }; 1046 static int x1000_sfc_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, }; 1047 static int x1000_ssi_dt_a_22_pins[] = { 0x16, }; 1048 static int x1000_ssi_dt_a_29_pins[] = { 0x1d, }; 1049 static int x1000_ssi_dt_d_pins[] = { 0x62, }; 1050 static int x1000_ssi_dr_a_23_pins[] = { 0x17, }; 1051 static int x1000_ssi_dr_a_28_pins[] = { 0x1c, }; 1052 static int x1000_ssi_dr_d_pins[] = { 0x63, }; 1053 static int x1000_ssi_clk_a_24_pins[] = { 0x18, }; 1054 static int x1000_ssi_clk_a_26_pins[] = { 0x1a, }; 1055 static int x1000_ssi_clk_d_pins[] = { 0x60, }; 1056 static int x1000_ssi_gpc_a_20_pins[] = { 0x14, }; 1057 static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, }; 1058 static int x1000_ssi_ce0_a_25_pins[] = { 0x19, }; 1059 static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, }; 1060 static int x1000_ssi_ce0_d_pins[] = { 0x61, }; 1061 static int x1000_ssi_ce1_a_21_pins[] = { 0x15, }; 1062 static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, }; 1063 static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, }; 1064 static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, }; 1065 static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, }; 1066 static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, }; 1067 static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, }; 1068 static int x1000_emc_8bit_data_pins[] = { 1069 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1070 }; 1071 static int x1000_emc_16bit_data_pins[] = { 1072 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 1073 }; 1074 static int x1000_emc_addr_pins[] = { 1075 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 1076 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 1077 }; 1078 static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, }; 1079 static int x1000_emc_wait_pins[] = { 0x34, }; 1080 static int x1000_emc_cs1_pins[] = { 0x32, }; 1081 static int x1000_emc_cs2_pins[] = { 0x33, }; 1082 static int x1000_i2c0_pins[] = { 0x38, 0x37, }; 1083 static int x1000_i2c1_a_pins[] = { 0x01, 0x00, }; 1084 static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, }; 1085 static int x1000_i2c2_pins[] = { 0x61, 0x60, }; 1086 static int x1000_cim_pins[] = { 1087 0x08, 0x09, 0x0a, 0x0b, 1088 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 1089 }; 1090 static int x1000_lcd_8bit_pins[] = { 1091 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1092 0x30, 0x31, 0x32, 0x33, 0x34, 1093 }; 1094 static int x1000_lcd_16bit_pins[] = { 1095 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 1096 }; 1097 static int x1000_pwm_pwm0_pins[] = { 0x59, }; 1098 static int x1000_pwm_pwm1_pins[] = { 0x5a, }; 1099 static int x1000_pwm_pwm2_pins[] = { 0x5b, }; 1100 static int x1000_pwm_pwm3_pins[] = { 0x26, }; 1101 static int x1000_pwm_pwm4_pins[] = { 0x58, }; 1102 static int x1000_mac_pins[] = { 1103 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26, 1104 }; 1105 1106 static int x1000_uart0_data_funcs[] = { 0, 0, }; 1107 static int x1000_uart0_hwflow_funcs[] = { 0, 0, }; 1108 static int x1000_uart1_data_a_funcs[] = { 2, 2, }; 1109 static int x1000_uart1_data_d_funcs[] = { 1, 1, }; 1110 static int x1000_uart1_hwflow_funcs[] = { 1, 1, }; 1111 static int x1000_uart2_data_a_funcs[] = { 2, 2, }; 1112 static int x1000_uart2_data_d_funcs[] = { 0, 0, }; 1113 static int x1000_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, }; 1114 static int x1000_ssi_dt_a_22_funcs[] = { 2, }; 1115 static int x1000_ssi_dt_a_29_funcs[] = { 2, }; 1116 static int x1000_ssi_dt_d_funcs[] = { 0, }; 1117 static int x1000_ssi_dr_a_23_funcs[] = { 2, }; 1118 static int x1000_ssi_dr_a_28_funcs[] = { 2, }; 1119 static int x1000_ssi_dr_d_funcs[] = { 0, }; 1120 static int x1000_ssi_clk_a_24_funcs[] = { 2, }; 1121 static int x1000_ssi_clk_a_26_funcs[] = { 2, }; 1122 static int x1000_ssi_clk_d_funcs[] = { 0, }; 1123 static int x1000_ssi_gpc_a_20_funcs[] = { 2, }; 1124 static int x1000_ssi_gpc_a_31_funcs[] = { 2, }; 1125 static int x1000_ssi_ce0_a_25_funcs[] = { 2, }; 1126 static int x1000_ssi_ce0_a_27_funcs[] = { 2, }; 1127 static int x1000_ssi_ce0_d_funcs[] = { 0, }; 1128 static int x1000_ssi_ce1_a_21_funcs[] = { 2, }; 1129 static int x1000_ssi_ce1_a_30_funcs[] = { 2, }; 1130 static int x1000_mmc0_1bit_funcs[] = { 1, 1, 1, }; 1131 static int x1000_mmc0_4bit_funcs[] = { 1, 1, 1, }; 1132 static int x1000_mmc0_8bit_funcs[] = { 1, 1, 1, 1, 1, }; 1133 static int x1000_mmc1_1bit_funcs[] = { 0, 0, 0, }; 1134 static int x1000_mmc1_4bit_funcs[] = { 0, 0, 0, }; 1135 static int x1000_emc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 1136 static int x1000_emc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 1137 static int x1000_emc_addr_funcs[] = { 1138 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1139 }; 1140 static int x1000_emc_rd_we_funcs[] = { 0, 0, }; 1141 static int x1000_emc_wait_funcs[] = { 0, }; 1142 static int x1000_emc_cs1_funcs[] = { 0, }; 1143 static int x1000_emc_cs2_funcs[] = { 0, }; 1144 static int x1000_i2c0_funcs[] = { 0, 0, }; 1145 static int x1000_i2c1_a_funcs[] = { 2, 2, }; 1146 static int x1000_i2c1_c_funcs[] = { 0, 0, }; 1147 static int x1000_i2c2_funcs[] = { 1, 1, }; 1148 static int x1000_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; 1149 static int x1000_lcd_8bit_funcs[] = { 1150 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1151 }; 1152 static int x1000_lcd_16bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, }; 1153 static int x1000_pwm_pwm0_funcs[] = { 0, }; 1154 static int x1000_pwm_pwm1_funcs[] = { 1, }; 1155 static int x1000_pwm_pwm2_funcs[] = { 1, }; 1156 static int x1000_pwm_pwm3_funcs[] = { 2, }; 1157 static int x1000_pwm_pwm4_funcs[] = { 0, }; 1158 static int x1000_mac_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; 1159 1160 static const struct group_desc x1000_groups[] = { 1161 INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data), 1162 INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow), 1163 INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a), 1164 INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d), 1165 INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow), 1166 INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a), 1167 INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d), 1168 INGENIC_PIN_GROUP("sfc", x1000_sfc), 1169 INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22), 1170 INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29), 1171 INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d), 1172 INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23), 1173 INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28), 1174 INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d), 1175 INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24), 1176 INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26), 1177 INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d), 1178 INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20), 1179 INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31), 1180 INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25), 1181 INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27), 1182 INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d), 1183 INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21), 1184 INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30), 1185 INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit), 1186 INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit), 1187 INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit), 1188 INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit), 1189 INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit), 1190 INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data), 1191 INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data), 1192 INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr), 1193 INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we), 1194 INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait), 1195 INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1), 1196 INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2), 1197 INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0), 1198 INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a), 1199 INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c), 1200 INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2), 1201 INGENIC_PIN_GROUP("cim-data", x1000_cim), 1202 INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit), 1203 INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit), 1204 { "lcd-no-pins", }, 1205 INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0), 1206 INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1), 1207 INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2), 1208 INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3), 1209 INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4), 1210 INGENIC_PIN_GROUP("mac", x1000_mac), 1211 }; 1212 1213 static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1214 static const char *x1000_uart1_groups[] = { 1215 "uart1-data-a", "uart1-data-d", "uart1-hwflow", 1216 }; 1217 static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; 1218 static const char *x1000_sfc_groups[] = { "sfc", }; 1219 static const char *x1000_ssi_groups[] = { 1220 "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d", 1221 "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d", 1222 "ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d", 1223 "ssi-gpc-a-20", "ssi-gpc-a-31", 1224 "ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d", 1225 "ssi-ce1-a-21", "ssi-ce1-a-30", 1226 }; 1227 static const char *x1000_mmc0_groups[] = { 1228 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", 1229 }; 1230 static const char *x1000_mmc1_groups[] = { 1231 "mmc1-1bit", "mmc1-4bit", 1232 }; 1233 static const char *x1000_emc_groups[] = { 1234 "emc-8bit-data", "emc-16bit-data", 1235 "emc-addr", "emc-rd-we", "emc-wait", 1236 }; 1237 static const char *x1000_cs1_groups[] = { "emc-cs1", }; 1238 static const char *x1000_cs2_groups[] = { "emc-cs2", }; 1239 static const char *x1000_i2c0_groups[] = { "i2c0-data", }; 1240 static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; 1241 static const char *x1000_i2c2_groups[] = { "i2c2-data", }; 1242 static const char *x1000_cim_groups[] = { "cim-data", }; 1243 static const char *x1000_lcd_groups[] = { 1244 "lcd-8bit", "lcd-16bit", "lcd-no-pins", 1245 }; 1246 static const char *x1000_pwm0_groups[] = { "pwm0", }; 1247 static const char *x1000_pwm1_groups[] = { "pwm1", }; 1248 static const char *x1000_pwm2_groups[] = { "pwm2", }; 1249 static const char *x1000_pwm3_groups[] = { "pwm3", }; 1250 static const char *x1000_pwm4_groups[] = { "pwm4", }; 1251 static const char *x1000_mac_groups[] = { "mac", }; 1252 1253 static const struct function_desc x1000_functions[] = { 1254 { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), }, 1255 { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), }, 1256 { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), }, 1257 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), }, 1258 { "ssi", x1000_ssi_groups, ARRAY_SIZE(x1000_ssi_groups), }, 1259 { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), }, 1260 { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), }, 1261 { "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), }, 1262 { "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), }, 1263 { "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), }, 1264 { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), }, 1265 { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), }, 1266 { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), }, 1267 { "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), }, 1268 { "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), }, 1269 { "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), }, 1270 { "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), }, 1271 { "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), }, 1272 { "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), }, 1273 { "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), }, 1274 { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), }, 1275 }; 1276 1277 static const struct ingenic_chip_info x1000_chip_info = { 1278 .num_chips = 4, 1279 .reg_offset = 0x100, 1280 .version = ID_X1000, 1281 .groups = x1000_groups, 1282 .num_groups = ARRAY_SIZE(x1000_groups), 1283 .functions = x1000_functions, 1284 .num_functions = ARRAY_SIZE(x1000_functions), 1285 .pull_ups = x1000_pull_ups, 1286 .pull_downs = x1000_pull_downs, 1287 }; 1288 1289 static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, }; 1290 static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; 1291 static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, }; 1292 static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, }; 1293 static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, }; 1294 static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, }; 1295 static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, }; 1296 static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, }; 1297 static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, }; 1298 static int x1500_i2c0_pins[] = { 0x38, 0x37, }; 1299 static int x1500_i2c1_a_pins[] = { 0x01, 0x00, }; 1300 static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, }; 1301 static int x1500_i2c2_pins[] = { 0x61, 0x60, }; 1302 static int x1500_cim_pins[] = { 1303 0x08, 0x09, 0x0a, 0x0b, 1304 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 1305 }; 1306 static int x1500_pwm_pwm0_pins[] = { 0x59, }; 1307 static int x1500_pwm_pwm1_pins[] = { 0x5a, }; 1308 static int x1500_pwm_pwm2_pins[] = { 0x5b, }; 1309 static int x1500_pwm_pwm3_pins[] = { 0x26, }; 1310 static int x1500_pwm_pwm4_pins[] = { 0x58, }; 1311 1312 static int x1500_uart0_data_funcs[] = { 0, 0, }; 1313 static int x1500_uart0_hwflow_funcs[] = { 0, 0, }; 1314 static int x1500_uart1_data_a_funcs[] = { 2, 2, }; 1315 static int x1500_uart1_data_d_funcs[] = { 1, 1, }; 1316 static int x1500_uart1_hwflow_funcs[] = { 1, 1, }; 1317 static int x1500_uart2_data_a_funcs[] = { 2, 2, }; 1318 static int x1500_uart2_data_d_funcs[] = { 0, 0, }; 1319 static int x1500_mmc_1bit_funcs[] = { 1, 1, 1, }; 1320 static int x1500_mmc_4bit_funcs[] = { 1, 1, 1, }; 1321 static int x1500_i2c0_funcs[] = { 0, 0, }; 1322 static int x1500_i2c1_a_funcs[] = { 2, 2, }; 1323 static int x1500_i2c1_c_funcs[] = { 0, 0, }; 1324 static int x1500_i2c2_funcs[] = { 1, 1, }; 1325 static int x1500_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; 1326 static int x1500_pwm_pwm0_funcs[] = { 0, }; 1327 static int x1500_pwm_pwm1_funcs[] = { 1, }; 1328 static int x1500_pwm_pwm2_funcs[] = { 1, }; 1329 static int x1500_pwm_pwm3_funcs[] = { 2, }; 1330 static int x1500_pwm_pwm4_funcs[] = { 0, }; 1331 1332 static const struct group_desc x1500_groups[] = { 1333 INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data), 1334 INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow), 1335 INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a), 1336 INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d), 1337 INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow), 1338 INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a), 1339 INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d), 1340 INGENIC_PIN_GROUP("sfc", x1000_sfc), 1341 INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit), 1342 INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit), 1343 INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0), 1344 INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a), 1345 INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c), 1346 INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2), 1347 INGENIC_PIN_GROUP("cim-data", x1500_cim), 1348 { "lcd-no-pins", }, 1349 INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0), 1350 INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1), 1351 INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2), 1352 INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3), 1353 INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4), 1354 }; 1355 1356 static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1357 static const char *x1500_uart1_groups[] = { 1358 "uart1-data-a", "uart1-data-d", "uart1-hwflow", 1359 }; 1360 static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; 1361 static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 1362 static const char *x1500_i2c0_groups[] = { "i2c0-data", }; 1363 static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; 1364 static const char *x1500_i2c2_groups[] = { "i2c2-data", }; 1365 static const char *x1500_cim_groups[] = { "cim-data", }; 1366 static const char *x1500_lcd_groups[] = { "lcd-no-pins", }; 1367 static const char *x1500_pwm0_groups[] = { "pwm0", }; 1368 static const char *x1500_pwm1_groups[] = { "pwm1", }; 1369 static const char *x1500_pwm2_groups[] = { "pwm2", }; 1370 static const char *x1500_pwm3_groups[] = { "pwm3", }; 1371 static const char *x1500_pwm4_groups[] = { "pwm4", }; 1372 1373 static const struct function_desc x1500_functions[] = { 1374 { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), }, 1375 { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), }, 1376 { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), }, 1377 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), }, 1378 { "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), }, 1379 { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), }, 1380 { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), }, 1381 { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), }, 1382 { "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), }, 1383 { "lcd", x1500_lcd_groups, ARRAY_SIZE(x1500_lcd_groups), }, 1384 { "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), }, 1385 { "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), }, 1386 { "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), }, 1387 { "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), }, 1388 { "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), }, 1389 }; 1390 1391 static const struct ingenic_chip_info x1500_chip_info = { 1392 .num_chips = 4, 1393 .reg_offset = 0x100, 1394 .version = ID_X1500, 1395 .groups = x1500_groups, 1396 .num_groups = ARRAY_SIZE(x1500_groups), 1397 .functions = x1500_functions, 1398 .num_functions = ARRAY_SIZE(x1500_functions), 1399 .pull_ups = x1000_pull_ups, 1400 .pull_downs = x1000_pull_downs, 1401 }; 1402 1403 static const u32 x1830_pull_ups[4] = { 1404 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, 1405 }; 1406 1407 static const u32 x1830_pull_downs[4] = { 1408 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, 1409 }; 1410 1411 static int x1830_uart0_data_pins[] = { 0x33, 0x36, }; 1412 static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, }; 1413 static int x1830_uart1_data_pins[] = { 0x38, 0x37, }; 1414 static int x1830_sfc_pins[] = { 0x17, 0x18, 0x1a, 0x19, 0x1b, 0x1c, }; 1415 static int x1830_ssi0_dt_pins[] = { 0x4c, }; 1416 static int x1830_ssi0_dr_pins[] = { 0x4b, }; 1417 static int x1830_ssi0_clk_pins[] = { 0x4f, }; 1418 static int x1830_ssi0_gpc_pins[] = { 0x4d, }; 1419 static int x1830_ssi0_ce0_pins[] = { 0x50, }; 1420 static int x1830_ssi0_ce1_pins[] = { 0x4e, }; 1421 static int x1830_ssi1_dt_c_pins[] = { 0x53, }; 1422 static int x1830_ssi1_dr_c_pins[] = { 0x54, }; 1423 static int x1830_ssi1_clk_c_pins[] = { 0x57, }; 1424 static int x1830_ssi1_gpc_c_pins[] = { 0x55, }; 1425 static int x1830_ssi1_ce0_c_pins[] = { 0x58, }; 1426 static int x1830_ssi1_ce1_c_pins[] = { 0x56, }; 1427 static int x1830_ssi1_dt_d_pins[] = { 0x62, }; 1428 static int x1830_ssi1_dr_d_pins[] = { 0x63, }; 1429 static int x1830_ssi1_clk_d_pins[] = { 0x66, }; 1430 static int x1830_ssi1_gpc_d_pins[] = { 0x64, }; 1431 static int x1830_ssi1_ce0_d_pins[] = { 0x67, }; 1432 static int x1830_ssi1_ce1_d_pins[] = { 0x65, }; 1433 static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, }; 1434 static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, }; 1435 static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, }; 1436 static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, }; 1437 static int x1830_i2c0_pins[] = { 0x0c, 0x0d, }; 1438 static int x1830_i2c1_pins[] = { 0x39, 0x3a, }; 1439 static int x1830_i2c2_pins[] = { 0x5b, 0x5c, }; 1440 static int x1830_pwm_pwm0_b_pins[] = { 0x31, }; 1441 static int x1830_pwm_pwm0_c_pins[] = { 0x4b, }; 1442 static int x1830_pwm_pwm1_b_pins[] = { 0x32, }; 1443 static int x1830_pwm_pwm1_c_pins[] = { 0x4c, }; 1444 static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, }; 1445 static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, }; 1446 static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, }; 1447 static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, }; 1448 static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, }; 1449 static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, }; 1450 static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, }; 1451 static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, }; 1452 static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, }; 1453 static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, }; 1454 static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, }; 1455 static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, }; 1456 static int x1830_mac_pins[] = { 1457 0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27, 1458 }; 1459 1460 static int x1830_uart0_data_funcs[] = { 0, 0, }; 1461 static int x1830_uart0_hwflow_funcs[] = { 0, 0, }; 1462 static int x1830_uart1_data_funcs[] = { 0, 0, }; 1463 static int x1830_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, }; 1464 static int x1830_ssi0_dt_funcs[] = { 0, }; 1465 static int x1830_ssi0_dr_funcs[] = { 0, }; 1466 static int x1830_ssi0_clk_funcs[] = { 0, }; 1467 static int x1830_ssi0_gpc_funcs[] = { 0, }; 1468 static int x1830_ssi0_ce0_funcs[] = { 0, }; 1469 static int x1830_ssi0_ce1_funcs[] = { 0, }; 1470 static int x1830_ssi1_dt_c_funcs[] = { 1, }; 1471 static int x1830_ssi1_dr_c_funcs[] = { 1, }; 1472 static int x1830_ssi1_clk_c_funcs[] = { 1, }; 1473 static int x1830_ssi1_gpc_c_funcs[] = { 1, }; 1474 static int x1830_ssi1_ce0_c_funcs[] = { 1, }; 1475 static int x1830_ssi1_ce1_c_funcs[] = { 1, }; 1476 static int x1830_ssi1_dt_d_funcs[] = { 2, }; 1477 static int x1830_ssi1_dr_d_funcs[] = { 2, }; 1478 static int x1830_ssi1_clk_d_funcs[] = { 2, }; 1479 static int x1830_ssi1_gpc_d_funcs[] = { 2, }; 1480 static int x1830_ssi1_ce0_d_funcs[] = { 2, }; 1481 static int x1830_ssi1_ce1_d_funcs[] = { 2, }; 1482 static int x1830_mmc0_1bit_funcs[] = { 0, 0, 0, }; 1483 static int x1830_mmc0_4bit_funcs[] = { 0, 0, 0, }; 1484 static int x1830_mmc1_1bit_funcs[] = { 0, 0, 0, }; 1485 static int x1830_mmc1_4bit_funcs[] = { 0, 0, 0, }; 1486 static int x1830_i2c0_funcs[] = { 1, 1, }; 1487 static int x1830_i2c1_funcs[] = { 0, 0, }; 1488 static int x1830_i2c2_funcs[] = { 1, 1, }; 1489 static int x1830_pwm_pwm0_b_funcs[] = { 0, }; 1490 static int x1830_pwm_pwm0_c_funcs[] = { 1, }; 1491 static int x1830_pwm_pwm1_b_funcs[] = { 0, }; 1492 static int x1830_pwm_pwm1_c_funcs[] = { 1, }; 1493 static int x1830_pwm_pwm2_c_8_funcs[] = { 0, }; 1494 static int x1830_pwm_pwm2_c_13_funcs[] = { 1, }; 1495 static int x1830_pwm_pwm3_c_9_funcs[] = { 0, }; 1496 static int x1830_pwm_pwm3_c_14_funcs[] = { 1, }; 1497 static int x1830_pwm_pwm4_c_15_funcs[] = { 1, }; 1498 static int x1830_pwm_pwm4_c_25_funcs[] = { 0, }; 1499 static int x1830_pwm_pwm5_c_16_funcs[] = { 1, }; 1500 static int x1830_pwm_pwm5_c_26_funcs[] = { 0, }; 1501 static int x1830_pwm_pwm6_c_17_funcs[] = { 1, }; 1502 static int x1830_pwm_pwm6_c_27_funcs[] = { 0, }; 1503 static int x1830_pwm_pwm7_c_18_funcs[] = { 1, }; 1504 static int x1830_pwm_pwm7_c_28_funcs[] = { 0, }; 1505 static int x1830_mac_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 1506 1507 static const struct group_desc x1830_groups[] = { 1508 INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data), 1509 INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow), 1510 INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data), 1511 INGENIC_PIN_GROUP("sfc", x1830_sfc), 1512 INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt), 1513 INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr), 1514 INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk), 1515 INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc), 1516 INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0), 1517 INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1), 1518 INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c), 1519 INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c), 1520 INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c), 1521 INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c), 1522 INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c), 1523 INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c), 1524 INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d), 1525 INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d), 1526 INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d), 1527 INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d), 1528 INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d), 1529 INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d), 1530 INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit), 1531 INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit), 1532 INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit), 1533 INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit), 1534 INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0), 1535 INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1), 1536 INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2), 1537 INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b), 1538 INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c), 1539 INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b), 1540 INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c), 1541 INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8), 1542 INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13), 1543 INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9), 1544 INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14), 1545 INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15), 1546 INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25), 1547 INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16), 1548 INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26), 1549 INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17), 1550 INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27), 1551 INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18), 1552 INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28), 1553 INGENIC_PIN_GROUP("mac", x1830_mac), 1554 }; 1555 1556 static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1557 static const char *x1830_uart1_groups[] = { "uart1-data", }; 1558 static const char *x1830_sfc_groups[] = { "sfc", }; 1559 static const char *x1830_ssi0_groups[] = { 1560 "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1", 1561 }; 1562 static const char *x1830_ssi1_groups[] = { 1563 "ssi1-dt-c", "ssi1-dt-d", 1564 "ssi1-dr-c", "ssi1-dr-d", 1565 "ssi1-clk-c", "ssi1-clk-d", 1566 "ssi1-gpc-c", "ssi1-gpc-d", 1567 "ssi1-ce0-c", "ssi1-ce0-d", 1568 "ssi1-ce1-c", "ssi1-ce1-d", 1569 }; 1570 static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 1571 static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 1572 static const char *x1830_i2c0_groups[] = { "i2c0-data", }; 1573 static const char *x1830_i2c1_groups[] = { "i2c1-data", }; 1574 static const char *x1830_i2c2_groups[] = { "i2c2-data", }; 1575 static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", }; 1576 static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", }; 1577 static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", }; 1578 static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", }; 1579 static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", }; 1580 static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", }; 1581 static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", }; 1582 static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", }; 1583 static const char *x1830_mac_groups[] = { "mac", }; 1584 1585 static const struct function_desc x1830_functions[] = { 1586 { "uart0", x1830_uart0_groups, ARRAY_SIZE(x1830_uart0_groups), }, 1587 { "uart1", x1830_uart1_groups, ARRAY_SIZE(x1830_uart1_groups), }, 1588 { "sfc", x1830_sfc_groups, ARRAY_SIZE(x1830_sfc_groups), }, 1589 { "ssi0", x1830_ssi0_groups, ARRAY_SIZE(x1830_ssi0_groups), }, 1590 { "ssi1", x1830_ssi1_groups, ARRAY_SIZE(x1830_ssi1_groups), }, 1591 { "mmc0", x1830_mmc0_groups, ARRAY_SIZE(x1830_mmc0_groups), }, 1592 { "mmc1", x1830_mmc1_groups, ARRAY_SIZE(x1830_mmc1_groups), }, 1593 { "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), }, 1594 { "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), }, 1595 { "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), }, 1596 { "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), }, 1597 { "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), }, 1598 { "pwm2", x1830_pwm2_groups, ARRAY_SIZE(x1830_pwm2_groups), }, 1599 { "pwm3", x1830_pwm3_groups, ARRAY_SIZE(x1830_pwm3_groups), }, 1600 { "pwm4", x1830_pwm4_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 1601 { "pwm5", x1830_pwm5_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 1602 { "pwm6", x1830_pwm6_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 1603 { "pwm7", x1830_pwm7_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 1604 { "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), }, 1605 }; 1606 1607 static const struct ingenic_chip_info x1830_chip_info = { 1608 .num_chips = 4, 1609 .reg_offset = 0x1000, 1610 .version = ID_X1830, 1611 .groups = x1830_groups, 1612 .num_groups = ARRAY_SIZE(x1830_groups), 1613 .functions = x1830_functions, 1614 .num_functions = ARRAY_SIZE(x1830_functions), 1615 .pull_ups = x1830_pull_ups, 1616 .pull_downs = x1830_pull_downs, 1617 }; 1618 1619 static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) 1620 { 1621 unsigned int val; 1622 1623 regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val); 1624 1625 return (u32) val; 1626 } 1627 1628 static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc, 1629 u8 reg, u8 offset, bool set) 1630 { 1631 if (set) 1632 reg = REG_SET(reg); 1633 else 1634 reg = REG_CLEAR(reg); 1635 1636 regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset)); 1637 } 1638 1639 static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc, 1640 u8 reg, u8 offset, bool set) 1641 { 1642 if (set) 1643 reg = REG_SET(reg); 1644 else 1645 reg = REG_CLEAR(reg); 1646 1647 regmap_write(jzgc->jzpc->map, REG_PZ_BASE( 1648 jzgc->jzpc->info->reg_offset) + reg, BIT(offset)); 1649 } 1650 1651 static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc) 1652 { 1653 regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD( 1654 jzgc->jzpc->info->reg_offset), 1655 jzgc->gc.base / PINS_PER_GPIO_CHIP); 1656 } 1657 1658 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc, 1659 u8 offset) 1660 { 1661 unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN); 1662 1663 return !!(val & BIT(offset)); 1664 } 1665 1666 static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc, 1667 u8 offset, int value) 1668 { 1669 if (jzgc->jzpc->info->version >= ID_JZ4760) 1670 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_PAT0, offset, !!value); 1671 else 1672 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value); 1673 } 1674 1675 static void irq_set_type(struct ingenic_gpio_chip *jzgc, 1676 u8 offset, unsigned int type) 1677 { 1678 u8 reg1, reg2; 1679 bool val1, val2; 1680 1681 switch (type) { 1682 case IRQ_TYPE_EDGE_RISING: 1683 val1 = val2 = true; 1684 break; 1685 case IRQ_TYPE_EDGE_FALLING: 1686 val1 = false; 1687 val2 = true; 1688 break; 1689 case IRQ_TYPE_LEVEL_HIGH: 1690 val1 = true; 1691 val2 = false; 1692 break; 1693 case IRQ_TYPE_LEVEL_LOW: 1694 default: 1695 val1 = val2 = false; 1696 break; 1697 } 1698 1699 if (jzgc->jzpc->info->version >= ID_JZ4760) { 1700 reg1 = JZ4760_GPIO_PAT1; 1701 reg2 = JZ4760_GPIO_PAT0; 1702 } else { 1703 reg1 = JZ4740_GPIO_TRIG; 1704 reg2 = JZ4740_GPIO_DIR; 1705 } 1706 1707 if (jzgc->jzpc->info->version >= ID_X1000) { 1708 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1); 1709 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2); 1710 ingenic_gpio_shadow_set_bit_load(jzgc); 1711 } else { 1712 ingenic_gpio_set_bit(jzgc, reg2, offset, val1); 1713 ingenic_gpio_set_bit(jzgc, reg1, offset, val2); 1714 } 1715 } 1716 1717 static void ingenic_gpio_irq_mask(struct irq_data *irqd) 1718 { 1719 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1720 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1721 1722 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true); 1723 } 1724 1725 static void ingenic_gpio_irq_unmask(struct irq_data *irqd) 1726 { 1727 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1728 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1729 1730 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false); 1731 } 1732 1733 static void ingenic_gpio_irq_enable(struct irq_data *irqd) 1734 { 1735 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1736 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1737 int irq = irqd->hwirq; 1738 1739 if (jzgc->jzpc->info->version >= ID_JZ4760) 1740 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, true); 1741 else 1742 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true); 1743 1744 ingenic_gpio_irq_unmask(irqd); 1745 } 1746 1747 static void ingenic_gpio_irq_disable(struct irq_data *irqd) 1748 { 1749 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1750 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1751 int irq = irqd->hwirq; 1752 1753 ingenic_gpio_irq_mask(irqd); 1754 1755 if (jzgc->jzpc->info->version >= ID_JZ4760) 1756 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, false); 1757 else 1758 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false); 1759 } 1760 1761 static void ingenic_gpio_irq_ack(struct irq_data *irqd) 1762 { 1763 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1764 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1765 int irq = irqd->hwirq; 1766 bool high; 1767 1768 if (irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) { 1769 /* 1770 * Switch to an interrupt for the opposite edge to the one that 1771 * triggered the interrupt being ACKed. 1772 */ 1773 high = ingenic_gpio_get_value(jzgc, irq); 1774 if (high) 1775 irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_FALLING); 1776 else 1777 irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_RISING); 1778 } 1779 1780 if (jzgc->jzpc->info->version >= ID_JZ4760) 1781 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_FLAG, irq, false); 1782 else 1783 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true); 1784 } 1785 1786 static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) 1787 { 1788 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1789 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1790 1791 switch (type) { 1792 case IRQ_TYPE_EDGE_BOTH: 1793 case IRQ_TYPE_EDGE_RISING: 1794 case IRQ_TYPE_EDGE_FALLING: 1795 irq_set_handler_locked(irqd, handle_edge_irq); 1796 break; 1797 case IRQ_TYPE_LEVEL_HIGH: 1798 case IRQ_TYPE_LEVEL_LOW: 1799 irq_set_handler_locked(irqd, handle_level_irq); 1800 break; 1801 default: 1802 irq_set_handler_locked(irqd, handle_bad_irq); 1803 } 1804 1805 if (type == IRQ_TYPE_EDGE_BOTH) { 1806 /* 1807 * The hardware does not support interrupts on both edges. The 1808 * best we can do is to set up a single-edge interrupt and then 1809 * switch to the opposing edge when ACKing the interrupt. 1810 */ 1811 bool high = ingenic_gpio_get_value(jzgc, irqd->hwirq); 1812 1813 type = high ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING; 1814 } 1815 1816 irq_set_type(jzgc, irqd->hwirq, type); 1817 return 0; 1818 } 1819 1820 static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on) 1821 { 1822 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1823 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1824 1825 return irq_set_irq_wake(jzgc->irq, on); 1826 } 1827 1828 static void ingenic_gpio_irq_handler(struct irq_desc *desc) 1829 { 1830 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1831 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1832 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data); 1833 unsigned long flag, i; 1834 1835 chained_irq_enter(irq_chip, desc); 1836 1837 if (jzgc->jzpc->info->version >= ID_JZ4760) 1838 flag = ingenic_gpio_read_reg(jzgc, JZ4760_GPIO_FLAG); 1839 else 1840 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG); 1841 1842 for_each_set_bit(i, &flag, 32) 1843 generic_handle_irq(irq_linear_revmap(gc->irq.domain, i)); 1844 chained_irq_exit(irq_chip, desc); 1845 } 1846 1847 static void ingenic_gpio_set(struct gpio_chip *gc, 1848 unsigned int offset, int value) 1849 { 1850 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1851 1852 ingenic_gpio_set_value(jzgc, offset, value); 1853 } 1854 1855 static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset) 1856 { 1857 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1858 1859 return (int) ingenic_gpio_get_value(jzgc, offset); 1860 } 1861 1862 static int ingenic_gpio_direction_input(struct gpio_chip *gc, 1863 unsigned int offset) 1864 { 1865 return pinctrl_gpio_direction_input(gc->base + offset); 1866 } 1867 1868 static int ingenic_gpio_direction_output(struct gpio_chip *gc, 1869 unsigned int offset, int value) 1870 { 1871 ingenic_gpio_set(gc, offset, value); 1872 return pinctrl_gpio_direction_output(gc->base + offset); 1873 } 1874 1875 static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc, 1876 unsigned int pin, u8 reg, bool set) 1877 { 1878 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 1879 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 1880 1881 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 1882 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); 1883 } 1884 1885 static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc, 1886 unsigned int pin, u8 reg, bool set) 1887 { 1888 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 1889 1890 regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) + 1891 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); 1892 } 1893 1894 static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc, 1895 unsigned int pin) 1896 { 1897 regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset), 1898 pin / PINS_PER_GPIO_CHIP); 1899 } 1900 1901 static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc, 1902 unsigned int pin, u8 reg) 1903 { 1904 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 1905 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 1906 unsigned int val; 1907 1908 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val); 1909 1910 return val & BIT(idx); 1911 } 1912 1913 static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1914 { 1915 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1916 struct ingenic_pinctrl *jzpc = jzgc->jzpc; 1917 unsigned int pin = gc->base + offset; 1918 1919 if (jzpc->info->version >= ID_JZ4760) 1920 return ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PAT1); 1921 1922 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT)) 1923 return true; 1924 1925 return !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR); 1926 } 1927 1928 static const struct pinctrl_ops ingenic_pctlops = { 1929 .get_groups_count = pinctrl_generic_get_group_count, 1930 .get_group_name = pinctrl_generic_get_group_name, 1931 .get_group_pins = pinctrl_generic_get_group_pins, 1932 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 1933 .dt_free_map = pinconf_generic_dt_free_map, 1934 }; 1935 1936 static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc, 1937 int pin, int func) 1938 { 1939 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 1940 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 1941 1942 dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n", 1943 'A' + offt, idx, func); 1944 1945 if (jzpc->info->version >= ID_X1000) { 1946 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); 1947 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false); 1948 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2); 1949 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1); 1950 ingenic_shadow_config_pin_load(jzpc, pin); 1951 } else if (jzpc->info->version >= ID_JZ4760) { 1952 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); 1953 ingenic_config_pin(jzpc, pin, GPIO_MSK, false); 1954 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2); 1955 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1); 1956 } else { 1957 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true); 1958 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2); 1959 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func > 0); 1960 } 1961 1962 return 0; 1963 } 1964 1965 static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev, 1966 unsigned int selector, unsigned int group) 1967 { 1968 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 1969 struct function_desc *func; 1970 struct group_desc *grp; 1971 unsigned int i; 1972 1973 func = pinmux_generic_get_function(pctldev, selector); 1974 if (!func) 1975 return -EINVAL; 1976 1977 grp = pinctrl_generic_get_group(pctldev, group); 1978 if (!grp) 1979 return -EINVAL; 1980 1981 dev_dbg(pctldev->dev, "enable function %s group %s\n", 1982 func->name, grp->name); 1983 1984 for (i = 0; i < grp->num_pins; i++) { 1985 int *pin_modes = grp->data; 1986 1987 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]); 1988 } 1989 1990 return 0; 1991 } 1992 1993 static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, 1994 struct pinctrl_gpio_range *range, 1995 unsigned int pin, bool input) 1996 { 1997 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 1998 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 1999 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2000 2001 dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n", 2002 'A' + offt, idx, input ? "in" : "out"); 2003 2004 if (jzpc->info->version >= ID_X1000) { 2005 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); 2006 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true); 2007 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input); 2008 ingenic_shadow_config_pin_load(jzpc, pin); 2009 } else if (jzpc->info->version >= ID_JZ4760) { 2010 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); 2011 ingenic_config_pin(jzpc, pin, GPIO_MSK, true); 2012 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input); 2013 } else { 2014 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false); 2015 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input); 2016 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false); 2017 } 2018 2019 return 0; 2020 } 2021 2022 static const struct pinmux_ops ingenic_pmxops = { 2023 .get_functions_count = pinmux_generic_get_function_count, 2024 .get_function_name = pinmux_generic_get_function_name, 2025 .get_function_groups = pinmux_generic_get_function_groups, 2026 .set_mux = ingenic_pinmux_set_mux, 2027 .gpio_set_direction = ingenic_pinmux_gpio_set_direction, 2028 }; 2029 2030 static int ingenic_pinconf_get(struct pinctrl_dev *pctldev, 2031 unsigned int pin, unsigned long *config) 2032 { 2033 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 2034 enum pin_config_param param = pinconf_to_config_param(*config); 2035 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2036 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2037 bool pull; 2038 2039 if (jzpc->info->version >= ID_JZ4760) 2040 pull = !ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PEN); 2041 else 2042 pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS); 2043 2044 switch (param) { 2045 case PIN_CONFIG_BIAS_DISABLE: 2046 if (pull) 2047 return -EINVAL; 2048 break; 2049 2050 case PIN_CONFIG_BIAS_PULL_UP: 2051 if (!pull || !(jzpc->info->pull_ups[offt] & BIT(idx))) 2052 return -EINVAL; 2053 break; 2054 2055 case PIN_CONFIG_BIAS_PULL_DOWN: 2056 if (!pull || !(jzpc->info->pull_downs[offt] & BIT(idx))) 2057 return -EINVAL; 2058 break; 2059 2060 default: 2061 return -ENOTSUPP; 2062 } 2063 2064 *config = pinconf_to_config_packed(param, 1); 2065 return 0; 2066 } 2067 2068 static void ingenic_set_bias(struct ingenic_pinctrl *jzpc, 2069 unsigned int pin, unsigned int bias) 2070 { 2071 if (jzpc->info->version >= ID_X1830) { 2072 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2073 unsigned int half = PINS_PER_GPIO_CHIP / 2; 2074 unsigned int idxh = pin % half * 2; 2075 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2076 2077 if (idx < half) { 2078 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 2079 REG_CLEAR(X1830_GPIO_PEL), 3 << idxh); 2080 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 2081 REG_SET(X1830_GPIO_PEL), bias << idxh); 2082 } else { 2083 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 2084 REG_CLEAR(X1830_GPIO_PEH), 3 << idxh); 2085 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 2086 REG_SET(X1830_GPIO_PEH), bias << idxh); 2087 } 2088 2089 } else if (jzpc->info->version >= ID_JZ4760) { 2090 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PEN, !bias); 2091 } else { 2092 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias); 2093 } 2094 } 2095 2096 static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc, 2097 unsigned int pin, bool high) 2098 { 2099 if (jzpc->info->version >= ID_JZ4760) 2100 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, high); 2101 else 2102 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high); 2103 } 2104 2105 static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 2106 unsigned long *configs, unsigned int num_configs) 2107 { 2108 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 2109 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2110 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2111 unsigned int cfg, arg; 2112 int ret; 2113 2114 for (cfg = 0; cfg < num_configs; cfg++) { 2115 switch (pinconf_to_config_param(configs[cfg])) { 2116 case PIN_CONFIG_BIAS_DISABLE: 2117 case PIN_CONFIG_BIAS_PULL_UP: 2118 case PIN_CONFIG_BIAS_PULL_DOWN: 2119 case PIN_CONFIG_OUTPUT: 2120 continue; 2121 default: 2122 return -ENOTSUPP; 2123 } 2124 } 2125 2126 for (cfg = 0; cfg < num_configs; cfg++) { 2127 arg = pinconf_to_config_argument(configs[cfg]); 2128 2129 switch (pinconf_to_config_param(configs[cfg])) { 2130 case PIN_CONFIG_BIAS_DISABLE: 2131 dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n", 2132 'A' + offt, idx); 2133 ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS); 2134 break; 2135 2136 case PIN_CONFIG_BIAS_PULL_UP: 2137 if (!(jzpc->info->pull_ups[offt] & BIT(idx))) 2138 return -EINVAL; 2139 dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n", 2140 'A' + offt, idx); 2141 ingenic_set_bias(jzpc, pin, GPIO_PULL_UP); 2142 break; 2143 2144 case PIN_CONFIG_BIAS_PULL_DOWN: 2145 if (!(jzpc->info->pull_downs[offt] & BIT(idx))) 2146 return -EINVAL; 2147 dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n", 2148 'A' + offt, idx); 2149 ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN); 2150 break; 2151 2152 case PIN_CONFIG_OUTPUT: 2153 ret = pinctrl_gpio_direction_output(pin); 2154 if (ret) 2155 return ret; 2156 2157 ingenic_set_output_level(jzpc, pin, arg); 2158 break; 2159 2160 default: 2161 unreachable(); 2162 } 2163 } 2164 2165 return 0; 2166 } 2167 2168 static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev, 2169 unsigned int group, unsigned long *config) 2170 { 2171 const unsigned int *pins; 2172 unsigned int i, npins, old = 0; 2173 int ret; 2174 2175 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 2176 if (ret) 2177 return ret; 2178 2179 for (i = 0; i < npins; i++) { 2180 if (ingenic_pinconf_get(pctldev, pins[i], config)) 2181 return -ENOTSUPP; 2182 2183 /* configs do not match between two pins */ 2184 if (i && (old != *config)) 2185 return -ENOTSUPP; 2186 2187 old = *config; 2188 } 2189 2190 return 0; 2191 } 2192 2193 static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev, 2194 unsigned int group, unsigned long *configs, 2195 unsigned int num_configs) 2196 { 2197 const unsigned int *pins; 2198 unsigned int i, npins; 2199 int ret; 2200 2201 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 2202 if (ret) 2203 return ret; 2204 2205 for (i = 0; i < npins; i++) { 2206 ret = ingenic_pinconf_set(pctldev, 2207 pins[i], configs, num_configs); 2208 if (ret) 2209 return ret; 2210 } 2211 2212 return 0; 2213 } 2214 2215 static const struct pinconf_ops ingenic_confops = { 2216 .is_generic = true, 2217 .pin_config_get = ingenic_pinconf_get, 2218 .pin_config_set = ingenic_pinconf_set, 2219 .pin_config_group_get = ingenic_pinconf_group_get, 2220 .pin_config_group_set = ingenic_pinconf_group_set, 2221 }; 2222 2223 static const struct regmap_config ingenic_pinctrl_regmap_config = { 2224 .reg_bits = 32, 2225 .val_bits = 32, 2226 .reg_stride = 4, 2227 }; 2228 2229 static const struct of_device_id ingenic_gpio_of_match[] __initconst = { 2230 { .compatible = "ingenic,jz4740-gpio", }, 2231 { .compatible = "ingenic,jz4760-gpio", }, 2232 { .compatible = "ingenic,jz4770-gpio", }, 2233 { .compatible = "ingenic,jz4780-gpio", }, 2234 { .compatible = "ingenic,x1000-gpio", }, 2235 { .compatible = "ingenic,x1830-gpio", }, 2236 {}, 2237 }; 2238 2239 static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, 2240 struct device_node *node) 2241 { 2242 struct ingenic_gpio_chip *jzgc; 2243 struct device *dev = jzpc->dev; 2244 struct gpio_irq_chip *girq; 2245 unsigned int bank; 2246 int err; 2247 2248 err = of_property_read_u32(node, "reg", &bank); 2249 if (err) { 2250 dev_err(dev, "Cannot read \"reg\" property: %i\n", err); 2251 return err; 2252 } 2253 2254 jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL); 2255 if (!jzgc) 2256 return -ENOMEM; 2257 2258 jzgc->jzpc = jzpc; 2259 jzgc->reg_base = bank * jzpc->info->reg_offset; 2260 2261 jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank); 2262 if (!jzgc->gc.label) 2263 return -ENOMEM; 2264 2265 /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY 2266 * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN 2267 * <linux/gpio/consumer.h> INSTEAD. 2268 */ 2269 jzgc->gc.base = bank * 32; 2270 2271 jzgc->gc.ngpio = 32; 2272 jzgc->gc.parent = dev; 2273 jzgc->gc.of_node = node; 2274 jzgc->gc.owner = THIS_MODULE; 2275 2276 jzgc->gc.set = ingenic_gpio_set; 2277 jzgc->gc.get = ingenic_gpio_get; 2278 jzgc->gc.direction_input = ingenic_gpio_direction_input; 2279 jzgc->gc.direction_output = ingenic_gpio_direction_output; 2280 jzgc->gc.get_direction = ingenic_gpio_get_direction; 2281 2282 if (of_property_read_bool(node, "gpio-ranges")) { 2283 jzgc->gc.request = gpiochip_generic_request; 2284 jzgc->gc.free = gpiochip_generic_free; 2285 } 2286 2287 jzgc->irq = irq_of_parse_and_map(node, 0); 2288 if (!jzgc->irq) 2289 return -EINVAL; 2290 2291 jzgc->irq_chip.name = jzgc->gc.label; 2292 jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable; 2293 jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable; 2294 jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask; 2295 jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask; 2296 jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack; 2297 jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type; 2298 jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake; 2299 jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND; 2300 2301 girq = &jzgc->gc.irq; 2302 girq->chip = &jzgc->irq_chip; 2303 girq->parent_handler = ingenic_gpio_irq_handler; 2304 girq->num_parents = 1; 2305 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 2306 GFP_KERNEL); 2307 if (!girq->parents) 2308 return -ENOMEM; 2309 girq->parents[0] = jzgc->irq; 2310 girq->default_type = IRQ_TYPE_NONE; 2311 girq->handler = handle_level_irq; 2312 2313 err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc); 2314 if (err) 2315 return err; 2316 2317 return 0; 2318 } 2319 2320 static int __init ingenic_pinctrl_probe(struct platform_device *pdev) 2321 { 2322 struct device *dev = &pdev->dev; 2323 struct ingenic_pinctrl *jzpc; 2324 struct pinctrl_desc *pctl_desc; 2325 void __iomem *base; 2326 const struct ingenic_chip_info *chip_info; 2327 struct device_node *node; 2328 unsigned int i; 2329 int err; 2330 2331 jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL); 2332 if (!jzpc) 2333 return -ENOMEM; 2334 2335 base = devm_platform_ioremap_resource(pdev, 0); 2336 if (IS_ERR(base)) 2337 return PTR_ERR(base); 2338 2339 jzpc->map = devm_regmap_init_mmio(dev, base, 2340 &ingenic_pinctrl_regmap_config); 2341 if (IS_ERR(jzpc->map)) { 2342 dev_err(dev, "Failed to create regmap\n"); 2343 return PTR_ERR(jzpc->map); 2344 } 2345 2346 jzpc->dev = dev; 2347 jzpc->info = chip_info = of_device_get_match_data(dev); 2348 2349 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); 2350 if (!pctl_desc) 2351 return -ENOMEM; 2352 2353 /* fill in pinctrl_desc structure */ 2354 pctl_desc->name = dev_name(dev); 2355 pctl_desc->owner = THIS_MODULE; 2356 pctl_desc->pctlops = &ingenic_pctlops; 2357 pctl_desc->pmxops = &ingenic_pmxops; 2358 pctl_desc->confops = &ingenic_confops; 2359 pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP; 2360 pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev, 2361 pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL); 2362 if (!jzpc->pdesc) 2363 return -ENOMEM; 2364 2365 for (i = 0; i < pctl_desc->npins; i++) { 2366 jzpc->pdesc[i].number = i; 2367 jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d", 2368 'A' + (i / PINS_PER_GPIO_CHIP), 2369 i % PINS_PER_GPIO_CHIP); 2370 } 2371 2372 jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc); 2373 if (IS_ERR(jzpc->pctl)) { 2374 dev_err(dev, "Failed to register pinctrl\n"); 2375 return PTR_ERR(jzpc->pctl); 2376 } 2377 2378 for (i = 0; i < chip_info->num_groups; i++) { 2379 const struct group_desc *group = &chip_info->groups[i]; 2380 2381 err = pinctrl_generic_add_group(jzpc->pctl, group->name, 2382 group->pins, group->num_pins, group->data); 2383 if (err < 0) { 2384 dev_err(dev, "Failed to register group %s\n", 2385 group->name); 2386 return err; 2387 } 2388 } 2389 2390 for (i = 0; i < chip_info->num_functions; i++) { 2391 const struct function_desc *func = &chip_info->functions[i]; 2392 2393 err = pinmux_generic_add_function(jzpc->pctl, func->name, 2394 func->group_names, func->num_group_names, 2395 func->data); 2396 if (err < 0) { 2397 dev_err(dev, "Failed to register function %s\n", 2398 func->name); 2399 return err; 2400 } 2401 } 2402 2403 dev_set_drvdata(dev, jzpc->map); 2404 2405 for_each_child_of_node(dev->of_node, node) { 2406 if (of_match_node(ingenic_gpio_of_match, node)) { 2407 err = ingenic_gpio_probe(jzpc, node); 2408 if (err) 2409 return err; 2410 } 2411 } 2412 2413 return 0; 2414 } 2415 2416 static const struct of_device_id ingenic_pinctrl_of_match[] = { 2417 { .compatible = "ingenic,jz4740-pinctrl", .data = &jz4740_chip_info }, 2418 { .compatible = "ingenic,jz4725b-pinctrl", .data = &jz4725b_chip_info }, 2419 { .compatible = "ingenic,jz4760-pinctrl", .data = &jz4760_chip_info }, 2420 { .compatible = "ingenic,jz4760b-pinctrl", .data = &jz4760_chip_info }, 2421 { .compatible = "ingenic,jz4770-pinctrl", .data = &jz4770_chip_info }, 2422 { .compatible = "ingenic,jz4780-pinctrl", .data = &jz4780_chip_info }, 2423 { .compatible = "ingenic,x1000-pinctrl", .data = &x1000_chip_info }, 2424 { .compatible = "ingenic,x1000e-pinctrl", .data = &x1000_chip_info }, 2425 { .compatible = "ingenic,x1500-pinctrl", .data = &x1500_chip_info }, 2426 { .compatible = "ingenic,x1830-pinctrl", .data = &x1830_chip_info }, 2427 {}, 2428 }; 2429 2430 static struct platform_driver ingenic_pinctrl_driver = { 2431 .driver = { 2432 .name = "pinctrl-ingenic", 2433 .of_match_table = ingenic_pinctrl_of_match, 2434 }, 2435 }; 2436 2437 static int __init ingenic_pinctrl_drv_register(void) 2438 { 2439 return platform_driver_probe(&ingenic_pinctrl_driver, 2440 ingenic_pinctrl_probe); 2441 } 2442 subsys_initcall(ingenic_pinctrl_drv_register); 2443