1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander 4 * 5 * Copyright (C) 2019 STMicroelectronics 6 * Author(s): Amelie Delaunay <amelie.delaunay@st.com>. 7 */ 8 #include <linux/gpio/driver.h> 9 #include <linux/interrupt.h> 10 #include <linux/mfd/stmfx.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/pinctrl/pinconf.h> 14 #include <linux/pinctrl/pinmux.h> 15 16 #include "core.h" 17 #include "pinctrl-utils.h" 18 19 /* GPIOs expander */ 20 /* GPIO_STATE1 0x10, GPIO_STATE2 0x11, GPIO_STATE3 0x12 */ 21 #define STMFX_REG_GPIO_STATE STMFX_REG_GPIO_STATE1 /* R */ 22 /* GPIO_DIR1 0x60, GPIO_DIR2 0x61, GPIO_DIR3 0x63 */ 23 #define STMFX_REG_GPIO_DIR STMFX_REG_GPIO_DIR1 /* RW */ 24 /* GPIO_TYPE1 0x64, GPIO_TYPE2 0x65, GPIO_TYPE3 0x66 */ 25 #define STMFX_REG_GPIO_TYPE STMFX_REG_GPIO_TYPE1 /* RW */ 26 /* GPIO_PUPD1 0x68, GPIO_PUPD2 0x69, GPIO_PUPD3 0x6A */ 27 #define STMFX_REG_GPIO_PUPD STMFX_REG_GPIO_PUPD1 /* RW */ 28 /* GPO_SET1 0x6C, GPO_SET2 0x6D, GPO_SET3 0x6E */ 29 #define STMFX_REG_GPO_SET STMFX_REG_GPO_SET1 /* RW */ 30 /* GPO_CLR1 0x70, GPO_CLR2 0x71, GPO_CLR3 0x72 */ 31 #define STMFX_REG_GPO_CLR STMFX_REG_GPO_CLR1 /* RW */ 32 /* IRQ_GPI_SRC1 0x48, IRQ_GPI_SRC2 0x49, IRQ_GPI_SRC3 0x4A */ 33 #define STMFX_REG_IRQ_GPI_SRC STMFX_REG_IRQ_GPI_SRC1 /* RW */ 34 /* IRQ_GPI_EVT1 0x4C, IRQ_GPI_EVT2 0x4D, IRQ_GPI_EVT3 0x4E */ 35 #define STMFX_REG_IRQ_GPI_EVT STMFX_REG_IRQ_GPI_EVT1 /* RW */ 36 /* IRQ_GPI_TYPE1 0x50, IRQ_GPI_TYPE2 0x51, IRQ_GPI_TYPE3 0x52 */ 37 #define STMFX_REG_IRQ_GPI_TYPE STMFX_REG_IRQ_GPI_TYPE1 /* RW */ 38 /* IRQ_GPI_PENDING1 0x0C, IRQ_GPI_PENDING2 0x0D, IRQ_GPI_PENDING3 0x0E*/ 39 #define STMFX_REG_IRQ_GPI_PENDING STMFX_REG_IRQ_GPI_PENDING1 /* R */ 40 /* IRQ_GPI_ACK1 0x54, IRQ_GPI_ACK2 0x55, IRQ_GPI_ACK3 0x56 */ 41 #define STMFX_REG_IRQ_GPI_ACK STMFX_REG_IRQ_GPI_ACK1 /* RW */ 42 43 #define NR_GPIO_REGS 3 44 #define NR_GPIOS_PER_REG 8 45 #define get_reg(offset) ((offset) / NR_GPIOS_PER_REG) 46 #define get_shift(offset) ((offset) % NR_GPIOS_PER_REG) 47 #define get_mask(offset) (BIT(get_shift(offset))) 48 49 /* 50 * STMFX pinctrl can have up to 24 pins if STMFX other functions are not used. 51 * Pins availability is managed thanks to gpio-ranges property. 52 */ 53 static const struct pinctrl_pin_desc stmfx_pins[] = { 54 PINCTRL_PIN(0, "gpio0"), 55 PINCTRL_PIN(1, "gpio1"), 56 PINCTRL_PIN(2, "gpio2"), 57 PINCTRL_PIN(3, "gpio3"), 58 PINCTRL_PIN(4, "gpio4"), 59 PINCTRL_PIN(5, "gpio5"), 60 PINCTRL_PIN(6, "gpio6"), 61 PINCTRL_PIN(7, "gpio7"), 62 PINCTRL_PIN(8, "gpio8"), 63 PINCTRL_PIN(9, "gpio9"), 64 PINCTRL_PIN(10, "gpio10"), 65 PINCTRL_PIN(11, "gpio11"), 66 PINCTRL_PIN(12, "gpio12"), 67 PINCTRL_PIN(13, "gpio13"), 68 PINCTRL_PIN(14, "gpio14"), 69 PINCTRL_PIN(15, "gpio15"), 70 PINCTRL_PIN(16, "agpio0"), 71 PINCTRL_PIN(17, "agpio1"), 72 PINCTRL_PIN(18, "agpio2"), 73 PINCTRL_PIN(19, "agpio3"), 74 PINCTRL_PIN(20, "agpio4"), 75 PINCTRL_PIN(21, "agpio5"), 76 PINCTRL_PIN(22, "agpio6"), 77 PINCTRL_PIN(23, "agpio7"), 78 }; 79 80 struct stmfx_pinctrl { 81 struct device *dev; 82 struct stmfx *stmfx; 83 struct pinctrl_dev *pctl_dev; 84 struct pinctrl_desc pctl_desc; 85 struct gpio_chip gpio_chip; 86 struct irq_chip irq_chip; 87 struct mutex lock; /* IRQ bus lock */ 88 unsigned long gpio_valid_mask; 89 /* Cache of IRQ_GPI_* registers for bus_lock */ 90 u8 irq_gpi_src[NR_GPIO_REGS]; 91 u8 irq_gpi_type[NR_GPIO_REGS]; 92 u8 irq_gpi_evt[NR_GPIO_REGS]; 93 u8 irq_toggle_edge[NR_GPIO_REGS]; 94 #ifdef CONFIG_PM 95 /* Backup of GPIO_* registers for suspend/resume */ 96 u8 bkp_gpio_state[NR_GPIO_REGS]; 97 u8 bkp_gpio_dir[NR_GPIO_REGS]; 98 u8 bkp_gpio_type[NR_GPIO_REGS]; 99 u8 bkp_gpio_pupd[NR_GPIO_REGS]; 100 #endif 101 }; 102 103 static int stmfx_gpio_get(struct gpio_chip *gc, unsigned int offset) 104 { 105 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 106 u32 reg = STMFX_REG_GPIO_STATE + get_reg(offset); 107 u32 mask = get_mask(offset); 108 u32 value; 109 int ret; 110 111 ret = regmap_read(pctl->stmfx->map, reg, &value); 112 113 return ret ? ret : !!(value & mask); 114 } 115 116 static void stmfx_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 117 { 118 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 119 u32 reg = value ? STMFX_REG_GPO_SET : STMFX_REG_GPO_CLR; 120 u32 mask = get_mask(offset); 121 122 regmap_write_bits(pctl->stmfx->map, reg + get_reg(offset), 123 mask, mask); 124 } 125 126 static int stmfx_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 127 { 128 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 129 u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); 130 u32 mask = get_mask(offset); 131 u32 val; 132 int ret; 133 134 ret = regmap_read(pctl->stmfx->map, reg, &val); 135 /* 136 * On stmfx, gpio pins direction is (0)input, (1)output. 137 * .get_direction returns 0=out, 1=in 138 */ 139 140 return ret ? ret : !(val & mask); 141 } 142 143 static int stmfx_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 144 { 145 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 146 u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); 147 u32 mask = get_mask(offset); 148 149 return regmap_write_bits(pctl->stmfx->map, reg, mask, 0); 150 } 151 152 static int stmfx_gpio_direction_output(struct gpio_chip *gc, 153 unsigned int offset, int value) 154 { 155 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 156 u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); 157 u32 mask = get_mask(offset); 158 159 stmfx_gpio_set(gc, offset, value); 160 161 return regmap_write_bits(pctl->stmfx->map, reg, mask, mask); 162 } 163 164 static int stmfx_pinconf_get_pupd(struct stmfx_pinctrl *pctl, 165 unsigned int offset) 166 { 167 u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset); 168 u32 pupd, mask = get_mask(offset); 169 int ret; 170 171 ret = regmap_read(pctl->stmfx->map, reg, &pupd); 172 if (ret) 173 return ret; 174 175 return !!(pupd & mask); 176 } 177 178 static int stmfx_pinconf_set_pupd(struct stmfx_pinctrl *pctl, 179 unsigned int offset, u32 pupd) 180 { 181 u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset); 182 u32 mask = get_mask(offset); 183 184 return regmap_write_bits(pctl->stmfx->map, reg, mask, pupd ? mask : 0); 185 } 186 187 static int stmfx_pinconf_get_type(struct stmfx_pinctrl *pctl, 188 unsigned int offset) 189 { 190 u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset); 191 u32 type, mask = get_mask(offset); 192 int ret; 193 194 ret = regmap_read(pctl->stmfx->map, reg, &type); 195 if (ret) 196 return ret; 197 198 return !!(type & mask); 199 } 200 201 static int stmfx_pinconf_set_type(struct stmfx_pinctrl *pctl, 202 unsigned int offset, u32 type) 203 { 204 u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset); 205 u32 mask = get_mask(offset); 206 207 return regmap_write_bits(pctl->stmfx->map, reg, mask, type ? mask : 0); 208 } 209 210 static int stmfx_pinconf_get(struct pinctrl_dev *pctldev, 211 unsigned int pin, unsigned long *config) 212 { 213 struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 214 u32 param = pinconf_to_config_param(*config); 215 struct pinctrl_gpio_range *range; 216 u32 arg = 0; 217 int ret, dir, type, pupd; 218 219 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 220 if (!range) 221 return -EINVAL; 222 223 dir = stmfx_gpio_get_direction(&pctl->gpio_chip, pin); 224 if (dir < 0) 225 return dir; 226 type = stmfx_pinconf_get_type(pctl, pin); 227 if (type < 0) 228 return type; 229 pupd = stmfx_pinconf_get_pupd(pctl, pin); 230 if (pupd < 0) 231 return pupd; 232 233 switch (param) { 234 case PIN_CONFIG_BIAS_DISABLE: 235 if ((!dir && (!type || !pupd)) || (dir && !type)) 236 arg = 1; 237 break; 238 case PIN_CONFIG_BIAS_PULL_DOWN: 239 if (dir && type && !pupd) 240 arg = 1; 241 break; 242 case PIN_CONFIG_BIAS_PULL_UP: 243 if (type && pupd) 244 arg = 1; 245 break; 246 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 247 if ((!dir && type) || (dir && !type)) 248 arg = 1; 249 break; 250 case PIN_CONFIG_DRIVE_PUSH_PULL: 251 if ((!dir && !type) || (dir && type)) 252 arg = 1; 253 break; 254 case PIN_CONFIG_OUTPUT: 255 if (dir) 256 return -EINVAL; 257 258 ret = stmfx_gpio_get(&pctl->gpio_chip, pin); 259 if (ret < 0) 260 return ret; 261 262 arg = ret; 263 break; 264 default: 265 return -ENOTSUPP; 266 } 267 268 *config = pinconf_to_config_packed(param, arg); 269 270 return 0; 271 } 272 273 static int stmfx_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 274 unsigned long *configs, unsigned int num_configs) 275 { 276 struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 277 struct pinctrl_gpio_range *range; 278 enum pin_config_param param; 279 u32 arg; 280 int dir, i, ret; 281 282 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); 283 if (!range) { 284 dev_err(pctldev->dev, "pin %d is not available\n", pin); 285 return -EINVAL; 286 } 287 288 dir = stmfx_gpio_get_direction(&pctl->gpio_chip, pin); 289 if (dir < 0) 290 return dir; 291 292 for (i = 0; i < num_configs; i++) { 293 param = pinconf_to_config_param(configs[i]); 294 arg = pinconf_to_config_argument(configs[i]); 295 296 switch (param) { 297 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 298 case PIN_CONFIG_BIAS_DISABLE: 299 case PIN_CONFIG_DRIVE_PUSH_PULL: 300 ret = stmfx_pinconf_set_type(pctl, pin, 0); 301 if (ret) 302 return ret; 303 break; 304 case PIN_CONFIG_BIAS_PULL_DOWN: 305 ret = stmfx_pinconf_set_type(pctl, pin, 1); 306 if (ret) 307 return ret; 308 ret = stmfx_pinconf_set_pupd(pctl, pin, 0); 309 if (ret) 310 return ret; 311 break; 312 case PIN_CONFIG_BIAS_PULL_UP: 313 ret = stmfx_pinconf_set_type(pctl, pin, 1); 314 if (ret) 315 return ret; 316 ret = stmfx_pinconf_set_pupd(pctl, pin, 1); 317 if (ret) 318 return ret; 319 break; 320 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 321 ret = stmfx_pinconf_set_type(pctl, pin, 1); 322 if (ret) 323 return ret; 324 break; 325 case PIN_CONFIG_OUTPUT: 326 ret = stmfx_gpio_direction_output(&pctl->gpio_chip, 327 pin, arg); 328 if (ret) 329 return ret; 330 break; 331 default: 332 return -ENOTSUPP; 333 } 334 } 335 336 return 0; 337 } 338 339 static void stmfx_pinconf_dbg_show(struct pinctrl_dev *pctldev, 340 struct seq_file *s, unsigned int offset) 341 { 342 struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 343 struct pinctrl_gpio_range *range; 344 int dir, type, pupd, val; 345 346 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, offset); 347 if (!range) 348 return; 349 350 dir = stmfx_gpio_get_direction(&pctl->gpio_chip, offset); 351 if (dir < 0) 352 return; 353 type = stmfx_pinconf_get_type(pctl, offset); 354 if (type < 0) 355 return; 356 pupd = stmfx_pinconf_get_pupd(pctl, offset); 357 if (pupd < 0) 358 return; 359 val = stmfx_gpio_get(&pctl->gpio_chip, offset); 360 if (val < 0) 361 return; 362 363 if (!dir) { 364 seq_printf(s, "output %s ", val ? "high" : "low"); 365 if (type) 366 seq_printf(s, "open drain %s internal pull-up ", 367 pupd ? "with" : "without"); 368 else 369 seq_puts(s, "push pull no pull "); 370 } else { 371 seq_printf(s, "input %s ", val ? "high" : "low"); 372 if (type) 373 seq_printf(s, "with internal pull-%s ", 374 pupd ? "up" : "down"); 375 else 376 seq_printf(s, "%s ", pupd ? "floating" : "analog"); 377 } 378 } 379 380 static const struct pinconf_ops stmfx_pinconf_ops = { 381 .pin_config_get = stmfx_pinconf_get, 382 .pin_config_set = stmfx_pinconf_set, 383 .pin_config_dbg_show = stmfx_pinconf_dbg_show, 384 }; 385 386 static int stmfx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 387 { 388 return 0; 389 } 390 391 static const char *stmfx_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 392 unsigned int selector) 393 { 394 return NULL; 395 } 396 397 static int stmfx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 398 unsigned int selector, 399 const unsigned int **pins, 400 unsigned int *num_pins) 401 { 402 return -ENOTSUPP; 403 } 404 405 static const struct pinctrl_ops stmfx_pinctrl_ops = { 406 .get_groups_count = stmfx_pinctrl_get_groups_count, 407 .get_group_name = stmfx_pinctrl_get_group_name, 408 .get_group_pins = stmfx_pinctrl_get_group_pins, 409 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 410 .dt_free_map = pinctrl_utils_free_map, 411 }; 412 413 static void stmfx_pinctrl_irq_mask(struct irq_data *data) 414 { 415 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 416 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); 417 u32 reg = get_reg(data->hwirq); 418 u32 mask = get_mask(data->hwirq); 419 420 pctl->irq_gpi_src[reg] &= ~mask; 421 } 422 423 static void stmfx_pinctrl_irq_unmask(struct irq_data *data) 424 { 425 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 426 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); 427 u32 reg = get_reg(data->hwirq); 428 u32 mask = get_mask(data->hwirq); 429 430 pctl->irq_gpi_src[reg] |= mask; 431 } 432 433 static int stmfx_pinctrl_irq_set_type(struct irq_data *data, unsigned int type) 434 { 435 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 436 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); 437 u32 reg = get_reg(data->hwirq); 438 u32 mask = get_mask(data->hwirq); 439 440 if (type == IRQ_TYPE_NONE) 441 return -EINVAL; 442 443 if (type & IRQ_TYPE_EDGE_BOTH) { 444 pctl->irq_gpi_evt[reg] |= mask; 445 irq_set_handler_locked(data, handle_edge_irq); 446 } else { 447 pctl->irq_gpi_evt[reg] &= ~mask; 448 irq_set_handler_locked(data, handle_level_irq); 449 } 450 451 if ((type & IRQ_TYPE_EDGE_RISING) || (type & IRQ_TYPE_LEVEL_HIGH)) 452 pctl->irq_gpi_type[reg] |= mask; 453 else 454 pctl->irq_gpi_type[reg] &= ~mask; 455 456 /* 457 * In case of (type & IRQ_TYPE_EDGE_BOTH), we need to know current 458 * GPIO value to set the right edge trigger. But in atomic context 459 * here we can't access registers over I2C. That's why (type & 460 * IRQ_TYPE_EDGE_BOTH) will be managed in .irq_sync_unlock. 461 */ 462 463 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 464 pctl->irq_toggle_edge[reg] |= mask; 465 else 466 pctl->irq_toggle_edge[reg] &= mask; 467 468 return 0; 469 } 470 471 static void stmfx_pinctrl_irq_bus_lock(struct irq_data *data) 472 { 473 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 474 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); 475 476 mutex_lock(&pctl->lock); 477 } 478 479 static void stmfx_pinctrl_irq_bus_sync_unlock(struct irq_data *data) 480 { 481 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 482 struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip); 483 u32 reg = get_reg(data->hwirq); 484 u32 mask = get_mask(data->hwirq); 485 486 /* 487 * In case of IRQ_TYPE_EDGE_BOTH), read the current GPIO value 488 * (this couldn't be done in .irq_set_type because of atomic context) 489 * to set the right irq trigger type. 490 */ 491 if (pctl->irq_toggle_edge[reg] & mask) { 492 if (stmfx_gpio_get(gpio_chip, data->hwirq)) 493 pctl->irq_gpi_type[reg] &= ~mask; 494 else 495 pctl->irq_gpi_type[reg] |= mask; 496 } 497 498 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT, 499 pctl->irq_gpi_evt, NR_GPIO_REGS); 500 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE, 501 pctl->irq_gpi_type, NR_GPIO_REGS); 502 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC, 503 pctl->irq_gpi_src, NR_GPIO_REGS); 504 505 mutex_unlock(&pctl->lock); 506 } 507 508 static void stmfx_pinctrl_irq_toggle_trigger(struct stmfx_pinctrl *pctl, 509 unsigned int offset) 510 { 511 u32 reg = get_reg(offset); 512 u32 mask = get_mask(offset); 513 int val; 514 515 if (!(pctl->irq_toggle_edge[reg] & mask)) 516 return; 517 518 val = stmfx_gpio_get(&pctl->gpio_chip, offset); 519 if (val < 0) 520 return; 521 522 if (val) { 523 pctl->irq_gpi_type[reg] &= mask; 524 regmap_write_bits(pctl->stmfx->map, 525 STMFX_REG_IRQ_GPI_TYPE + reg, 526 mask, 0); 527 528 } else { 529 pctl->irq_gpi_type[reg] |= mask; 530 regmap_write_bits(pctl->stmfx->map, 531 STMFX_REG_IRQ_GPI_TYPE + reg, 532 mask, mask); 533 } 534 } 535 536 static irqreturn_t stmfx_pinctrl_irq_thread_fn(int irq, void *dev_id) 537 { 538 struct stmfx_pinctrl *pctl = (struct stmfx_pinctrl *)dev_id; 539 struct gpio_chip *gc = &pctl->gpio_chip; 540 u8 pending[NR_GPIO_REGS]; 541 u8 src[NR_GPIO_REGS] = {0, 0, 0}; 542 unsigned long n, status; 543 int ret; 544 545 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_IRQ_GPI_PENDING, 546 &pending, NR_GPIO_REGS); 547 if (ret) 548 return IRQ_NONE; 549 550 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC, 551 src, NR_GPIO_REGS); 552 553 status = *(unsigned long *)pending; 554 for_each_set_bit(n, &status, gc->ngpio) { 555 handle_nested_irq(irq_find_mapping(gc->irq.domain, n)); 556 stmfx_pinctrl_irq_toggle_trigger(pctl, n); 557 } 558 559 regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC, 560 pctl->irq_gpi_src, NR_GPIO_REGS); 561 562 return IRQ_HANDLED; 563 } 564 565 static int stmfx_pinctrl_gpio_function_enable(struct stmfx_pinctrl *pctl) 566 { 567 struct pinctrl_gpio_range *gpio_range; 568 struct pinctrl_dev *pctl_dev = pctl->pctl_dev; 569 u32 func = STMFX_FUNC_GPIO; 570 571 pctl->gpio_valid_mask = GENMASK(15, 0); 572 573 gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 16); 574 if (gpio_range) { 575 func |= STMFX_FUNC_ALTGPIO_LOW; 576 pctl->gpio_valid_mask |= GENMASK(19, 16); 577 } 578 579 gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 20); 580 if (gpio_range) { 581 func |= STMFX_FUNC_ALTGPIO_HIGH; 582 pctl->gpio_valid_mask |= GENMASK(23, 20); 583 } 584 585 return stmfx_function_enable(pctl->stmfx, func); 586 } 587 588 static int stmfx_pinctrl_gpio_init_valid_mask(struct gpio_chip *gc, 589 unsigned long *valid_mask, 590 unsigned int ngpios) 591 { 592 struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); 593 u32 n; 594 595 for_each_clear_bit(n, &pctl->gpio_valid_mask, ngpios) 596 clear_bit(n, valid_mask); 597 598 return 0; 599 } 600 601 static int stmfx_pinctrl_probe(struct platform_device *pdev) 602 { 603 struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent); 604 struct device_node *np = pdev->dev.of_node; 605 struct stmfx_pinctrl *pctl; 606 int irq, ret; 607 608 pctl = devm_kzalloc(stmfx->dev, sizeof(*pctl), GFP_KERNEL); 609 if (!pctl) 610 return -ENOMEM; 611 612 platform_set_drvdata(pdev, pctl); 613 614 pctl->dev = &pdev->dev; 615 pctl->stmfx = stmfx; 616 617 if (!of_find_property(np, "gpio-ranges", NULL)) { 618 dev_err(pctl->dev, "missing required gpio-ranges property\n"); 619 return -EINVAL; 620 } 621 622 irq = platform_get_irq(pdev, 0); 623 if (irq <= 0) 624 return -ENXIO; 625 626 mutex_init(&pctl->lock); 627 628 /* Register pin controller */ 629 pctl->pctl_desc.name = "stmfx-pinctrl"; 630 pctl->pctl_desc.pctlops = &stmfx_pinctrl_ops; 631 pctl->pctl_desc.confops = &stmfx_pinconf_ops; 632 pctl->pctl_desc.pins = stmfx_pins; 633 pctl->pctl_desc.npins = ARRAY_SIZE(stmfx_pins); 634 pctl->pctl_desc.owner = THIS_MODULE; 635 pctl->pctl_desc.link_consumers = true; 636 637 ret = devm_pinctrl_register_and_init(pctl->dev, &pctl->pctl_desc, 638 pctl, &pctl->pctl_dev); 639 if (ret) { 640 dev_err(pctl->dev, "pinctrl registration failed\n"); 641 return ret; 642 } 643 644 ret = pinctrl_enable(pctl->pctl_dev); 645 if (ret) { 646 dev_err(pctl->dev, "pinctrl enable failed\n"); 647 return ret; 648 } 649 650 /* Register gpio controller */ 651 pctl->gpio_chip.label = "stmfx-gpio"; 652 pctl->gpio_chip.parent = pctl->dev; 653 pctl->gpio_chip.get_direction = stmfx_gpio_get_direction; 654 pctl->gpio_chip.direction_input = stmfx_gpio_direction_input; 655 pctl->gpio_chip.direction_output = stmfx_gpio_direction_output; 656 pctl->gpio_chip.get = stmfx_gpio_get; 657 pctl->gpio_chip.set = stmfx_gpio_set; 658 pctl->gpio_chip.set_config = gpiochip_generic_config; 659 pctl->gpio_chip.base = -1; 660 pctl->gpio_chip.ngpio = pctl->pctl_desc.npins; 661 pctl->gpio_chip.can_sleep = true; 662 pctl->gpio_chip.of_node = np; 663 pctl->gpio_chip.init_valid_mask = stmfx_pinctrl_gpio_init_valid_mask; 664 665 ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl); 666 if (ret) { 667 dev_err(pctl->dev, "gpio_chip registration failed\n"); 668 return ret; 669 } 670 671 ret = stmfx_pinctrl_gpio_function_enable(pctl); 672 if (ret) 673 return ret; 674 675 pctl->irq_chip.name = dev_name(pctl->dev); 676 pctl->irq_chip.irq_mask = stmfx_pinctrl_irq_mask; 677 pctl->irq_chip.irq_unmask = stmfx_pinctrl_irq_unmask; 678 pctl->irq_chip.irq_set_type = stmfx_pinctrl_irq_set_type; 679 pctl->irq_chip.irq_bus_lock = stmfx_pinctrl_irq_bus_lock; 680 pctl->irq_chip.irq_bus_sync_unlock = stmfx_pinctrl_irq_bus_sync_unlock; 681 682 ret = gpiochip_irqchip_add_nested(&pctl->gpio_chip, &pctl->irq_chip, 683 0, handle_bad_irq, IRQ_TYPE_NONE); 684 if (ret) { 685 dev_err(pctl->dev, "cannot add irqchip to gpiochip\n"); 686 return ret; 687 } 688 689 ret = devm_request_threaded_irq(pctl->dev, irq, NULL, 690 stmfx_pinctrl_irq_thread_fn, 691 IRQF_ONESHOT, 692 pctl->irq_chip.name, pctl); 693 if (ret) { 694 dev_err(pctl->dev, "cannot request irq%d\n", irq); 695 return ret; 696 } 697 698 gpiochip_set_nested_irqchip(&pctl->gpio_chip, &pctl->irq_chip, irq); 699 700 dev_info(pctl->dev, 701 "%ld GPIOs available\n", hweight_long(pctl->gpio_valid_mask)); 702 703 return 0; 704 } 705 706 static int stmfx_pinctrl_remove(struct platform_device *pdev) 707 { 708 struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent); 709 710 return stmfx_function_disable(stmfx, 711 STMFX_FUNC_GPIO | 712 STMFX_FUNC_ALTGPIO_LOW | 713 STMFX_FUNC_ALTGPIO_HIGH); 714 } 715 716 #ifdef CONFIG_PM_SLEEP 717 static int stmfx_pinctrl_backup_regs(struct stmfx_pinctrl *pctl) 718 { 719 int ret; 720 721 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_STATE, 722 &pctl->bkp_gpio_state, NR_GPIO_REGS); 723 if (ret) 724 return ret; 725 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_DIR, 726 &pctl->bkp_gpio_dir, NR_GPIO_REGS); 727 if (ret) 728 return ret; 729 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_TYPE, 730 &pctl->bkp_gpio_type, NR_GPIO_REGS); 731 if (ret) 732 return ret; 733 ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_PUPD, 734 &pctl->bkp_gpio_pupd, NR_GPIO_REGS); 735 if (ret) 736 return ret; 737 738 return 0; 739 } 740 741 static int stmfx_pinctrl_restore_regs(struct stmfx_pinctrl *pctl) 742 { 743 int ret; 744 745 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_DIR, 746 pctl->bkp_gpio_dir, NR_GPIO_REGS); 747 if (ret) 748 return ret; 749 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_TYPE, 750 pctl->bkp_gpio_type, NR_GPIO_REGS); 751 if (ret) 752 return ret; 753 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_PUPD, 754 pctl->bkp_gpio_pupd, NR_GPIO_REGS); 755 if (ret) 756 return ret; 757 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPO_SET, 758 pctl->bkp_gpio_state, NR_GPIO_REGS); 759 if (ret) 760 return ret; 761 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT, 762 pctl->irq_gpi_evt, NR_GPIO_REGS); 763 if (ret) 764 return ret; 765 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE, 766 pctl->irq_gpi_type, NR_GPIO_REGS); 767 if (ret) 768 return ret; 769 ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC, 770 pctl->irq_gpi_src, NR_GPIO_REGS); 771 if (ret) 772 return ret; 773 774 return 0; 775 } 776 777 static int stmfx_pinctrl_suspend(struct device *dev) 778 { 779 struct stmfx_pinctrl *pctl = dev_get_drvdata(dev); 780 int ret; 781 782 ret = stmfx_pinctrl_backup_regs(pctl); 783 if (ret) { 784 dev_err(pctl->dev, "registers backup failure\n"); 785 return ret; 786 } 787 788 return 0; 789 } 790 791 static int stmfx_pinctrl_resume(struct device *dev) 792 { 793 struct stmfx_pinctrl *pctl = dev_get_drvdata(dev); 794 int ret; 795 796 ret = stmfx_pinctrl_restore_regs(pctl); 797 if (ret) { 798 dev_err(pctl->dev, "registers restoration failure\n"); 799 return ret; 800 } 801 802 return 0; 803 } 804 #endif 805 806 static SIMPLE_DEV_PM_OPS(stmfx_pinctrl_dev_pm_ops, 807 stmfx_pinctrl_suspend, stmfx_pinctrl_resume); 808 809 static const struct of_device_id stmfx_pinctrl_of_match[] = { 810 { .compatible = "st,stmfx-0300-pinctrl", }, 811 {}, 812 }; 813 MODULE_DEVICE_TABLE(of, stmfx_pinctrl_of_match); 814 815 static struct platform_driver stmfx_pinctrl_driver = { 816 .driver = { 817 .name = "stmfx-pinctrl", 818 .of_match_table = stmfx_pinctrl_of_match, 819 .pm = &stmfx_pinctrl_dev_pm_ops, 820 }, 821 .probe = stmfx_pinctrl_probe, 822 .remove = stmfx_pinctrl_remove, 823 }; 824 module_platform_driver(stmfx_pinctrl_driver); 825 826 MODULE_DESCRIPTION("STMFX pinctrl/GPIO driver"); 827 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>"); 828 MODULE_LICENSE("GPL v2"); 829