1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/module.h>
7 #include <linux/of.h>
8 #include <linux/platform_device.h>
9 
10 #include "pinctrl-msm.h"
11 
12 static const struct pinctrl_pin_desc apq8084_pins[] = {
13 	PINCTRL_PIN(0, "GPIO_0"),
14 	PINCTRL_PIN(1, "GPIO_1"),
15 	PINCTRL_PIN(2, "GPIO_2"),
16 	PINCTRL_PIN(3, "GPIO_3"),
17 	PINCTRL_PIN(4, "GPIO_4"),
18 	PINCTRL_PIN(5, "GPIO_5"),
19 	PINCTRL_PIN(6, "GPIO_6"),
20 	PINCTRL_PIN(7, "GPIO_7"),
21 	PINCTRL_PIN(8, "GPIO_8"),
22 	PINCTRL_PIN(9, "GPIO_9"),
23 	PINCTRL_PIN(10, "GPIO_10"),
24 	PINCTRL_PIN(11, "GPIO_11"),
25 	PINCTRL_PIN(12, "GPIO_12"),
26 	PINCTRL_PIN(13, "GPIO_13"),
27 	PINCTRL_PIN(14, "GPIO_14"),
28 	PINCTRL_PIN(15, "GPIO_15"),
29 	PINCTRL_PIN(16, "GPIO_16"),
30 	PINCTRL_PIN(17, "GPIO_17"),
31 	PINCTRL_PIN(18, "GPIO_18"),
32 	PINCTRL_PIN(19, "GPIO_19"),
33 	PINCTRL_PIN(20, "GPIO_20"),
34 	PINCTRL_PIN(21, "GPIO_21"),
35 	PINCTRL_PIN(22, "GPIO_22"),
36 	PINCTRL_PIN(23, "GPIO_23"),
37 	PINCTRL_PIN(24, "GPIO_24"),
38 	PINCTRL_PIN(25, "GPIO_25"),
39 	PINCTRL_PIN(26, "GPIO_26"),
40 	PINCTRL_PIN(27, "GPIO_27"),
41 	PINCTRL_PIN(28, "GPIO_28"),
42 	PINCTRL_PIN(29, "GPIO_29"),
43 	PINCTRL_PIN(30, "GPIO_30"),
44 	PINCTRL_PIN(31, "GPIO_31"),
45 	PINCTRL_PIN(32, "GPIO_32"),
46 	PINCTRL_PIN(33, "GPIO_33"),
47 	PINCTRL_PIN(34, "GPIO_34"),
48 	PINCTRL_PIN(35, "GPIO_35"),
49 	PINCTRL_PIN(36, "GPIO_36"),
50 	PINCTRL_PIN(37, "GPIO_37"),
51 	PINCTRL_PIN(38, "GPIO_38"),
52 	PINCTRL_PIN(39, "GPIO_39"),
53 	PINCTRL_PIN(40, "GPIO_40"),
54 	PINCTRL_PIN(41, "GPIO_41"),
55 	PINCTRL_PIN(42, "GPIO_42"),
56 	PINCTRL_PIN(43, "GPIO_43"),
57 	PINCTRL_PIN(44, "GPIO_44"),
58 	PINCTRL_PIN(45, "GPIO_45"),
59 	PINCTRL_PIN(46, "GPIO_46"),
60 	PINCTRL_PIN(47, "GPIO_47"),
61 	PINCTRL_PIN(48, "GPIO_48"),
62 	PINCTRL_PIN(49, "GPIO_49"),
63 	PINCTRL_PIN(50, "GPIO_50"),
64 	PINCTRL_PIN(51, "GPIO_51"),
65 	PINCTRL_PIN(52, "GPIO_52"),
66 	PINCTRL_PIN(53, "GPIO_53"),
67 	PINCTRL_PIN(54, "GPIO_54"),
68 	PINCTRL_PIN(55, "GPIO_55"),
69 	PINCTRL_PIN(56, "GPIO_56"),
70 	PINCTRL_PIN(57, "GPIO_57"),
71 	PINCTRL_PIN(58, "GPIO_58"),
72 	PINCTRL_PIN(59, "GPIO_59"),
73 	PINCTRL_PIN(60, "GPIO_60"),
74 	PINCTRL_PIN(61, "GPIO_61"),
75 	PINCTRL_PIN(62, "GPIO_62"),
76 	PINCTRL_PIN(63, "GPIO_63"),
77 	PINCTRL_PIN(64, "GPIO_64"),
78 	PINCTRL_PIN(65, "GPIO_65"),
79 	PINCTRL_PIN(66, "GPIO_66"),
80 	PINCTRL_PIN(67, "GPIO_67"),
81 	PINCTRL_PIN(68, "GPIO_68"),
82 	PINCTRL_PIN(69, "GPIO_69"),
83 	PINCTRL_PIN(70, "GPIO_70"),
84 	PINCTRL_PIN(71, "GPIO_71"),
85 	PINCTRL_PIN(72, "GPIO_72"),
86 	PINCTRL_PIN(73, "GPIO_73"),
87 	PINCTRL_PIN(74, "GPIO_74"),
88 	PINCTRL_PIN(75, "GPIO_75"),
89 	PINCTRL_PIN(76, "GPIO_76"),
90 	PINCTRL_PIN(77, "GPIO_77"),
91 	PINCTRL_PIN(78, "GPIO_78"),
92 	PINCTRL_PIN(79, "GPIO_79"),
93 	PINCTRL_PIN(80, "GPIO_80"),
94 	PINCTRL_PIN(81, "GPIO_81"),
95 	PINCTRL_PIN(82, "GPIO_82"),
96 	PINCTRL_PIN(83, "GPIO_83"),
97 	PINCTRL_PIN(84, "GPIO_84"),
98 	PINCTRL_PIN(85, "GPIO_85"),
99 	PINCTRL_PIN(86, "GPIO_86"),
100 	PINCTRL_PIN(87, "GPIO_87"),
101 	PINCTRL_PIN(88, "GPIO_88"),
102 	PINCTRL_PIN(89, "GPIO_89"),
103 	PINCTRL_PIN(90, "GPIO_90"),
104 	PINCTRL_PIN(91, "GPIO_91"),
105 	PINCTRL_PIN(92, "GPIO_92"),
106 	PINCTRL_PIN(93, "GPIO_93"),
107 	PINCTRL_PIN(94, "GPIO_94"),
108 	PINCTRL_PIN(95, "GPIO_95"),
109 	PINCTRL_PIN(96, "GPIO_96"),
110 	PINCTRL_PIN(97, "GPIO_97"),
111 	PINCTRL_PIN(98, "GPIO_98"),
112 	PINCTRL_PIN(99, "GPIO_99"),
113 	PINCTRL_PIN(100, "GPIO_100"),
114 	PINCTRL_PIN(101, "GPIO_101"),
115 	PINCTRL_PIN(102, "GPIO_102"),
116 	PINCTRL_PIN(103, "GPIO_103"),
117 	PINCTRL_PIN(104, "GPIO_104"),
118 	PINCTRL_PIN(105, "GPIO_105"),
119 	PINCTRL_PIN(106, "GPIO_106"),
120 	PINCTRL_PIN(107, "GPIO_107"),
121 	PINCTRL_PIN(108, "GPIO_108"),
122 	PINCTRL_PIN(109, "GPIO_109"),
123 	PINCTRL_PIN(110, "GPIO_110"),
124 	PINCTRL_PIN(111, "GPIO_111"),
125 	PINCTRL_PIN(112, "GPIO_112"),
126 	PINCTRL_PIN(113, "GPIO_113"),
127 	PINCTRL_PIN(114, "GPIO_114"),
128 	PINCTRL_PIN(115, "GPIO_115"),
129 	PINCTRL_PIN(116, "GPIO_116"),
130 	PINCTRL_PIN(117, "GPIO_117"),
131 	PINCTRL_PIN(118, "GPIO_118"),
132 	PINCTRL_PIN(119, "GPIO_119"),
133 	PINCTRL_PIN(120, "GPIO_120"),
134 	PINCTRL_PIN(121, "GPIO_121"),
135 	PINCTRL_PIN(122, "GPIO_122"),
136 	PINCTRL_PIN(123, "GPIO_123"),
137 	PINCTRL_PIN(124, "GPIO_124"),
138 	PINCTRL_PIN(125, "GPIO_125"),
139 	PINCTRL_PIN(126, "GPIO_126"),
140 	PINCTRL_PIN(127, "GPIO_127"),
141 	PINCTRL_PIN(128, "GPIO_128"),
142 	PINCTRL_PIN(129, "GPIO_129"),
143 	PINCTRL_PIN(130, "GPIO_130"),
144 	PINCTRL_PIN(131, "GPIO_131"),
145 	PINCTRL_PIN(132, "GPIO_132"),
146 	PINCTRL_PIN(133, "GPIO_133"),
147 	PINCTRL_PIN(134, "GPIO_134"),
148 	PINCTRL_PIN(135, "GPIO_135"),
149 	PINCTRL_PIN(136, "GPIO_136"),
150 	PINCTRL_PIN(137, "GPIO_137"),
151 	PINCTRL_PIN(138, "GPIO_138"),
152 	PINCTRL_PIN(139, "GPIO_139"),
153 	PINCTRL_PIN(140, "GPIO_140"),
154 	PINCTRL_PIN(141, "GPIO_141"),
155 	PINCTRL_PIN(142, "GPIO_142"),
156 	PINCTRL_PIN(143, "GPIO_143"),
157 	PINCTRL_PIN(144, "GPIO_144"),
158 	PINCTRL_PIN(145, "GPIO_145"),
159 	PINCTRL_PIN(146, "GPIO_146"),
160 
161 	PINCTRL_PIN(147, "SDC1_CLK"),
162 	PINCTRL_PIN(148, "SDC1_CMD"),
163 	PINCTRL_PIN(149, "SDC1_DATA"),
164 	PINCTRL_PIN(150, "SDC2_CLK"),
165 	PINCTRL_PIN(151, "SDC2_CMD"),
166 	PINCTRL_PIN(152, "SDC2_DATA"),
167 };
168 
169 #define DECLARE_APQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
170 
171 DECLARE_APQ_GPIO_PINS(0);
172 DECLARE_APQ_GPIO_PINS(1);
173 DECLARE_APQ_GPIO_PINS(2);
174 DECLARE_APQ_GPIO_PINS(3);
175 DECLARE_APQ_GPIO_PINS(4);
176 DECLARE_APQ_GPIO_PINS(5);
177 DECLARE_APQ_GPIO_PINS(6);
178 DECLARE_APQ_GPIO_PINS(7);
179 DECLARE_APQ_GPIO_PINS(8);
180 DECLARE_APQ_GPIO_PINS(9);
181 DECLARE_APQ_GPIO_PINS(10);
182 DECLARE_APQ_GPIO_PINS(11);
183 DECLARE_APQ_GPIO_PINS(12);
184 DECLARE_APQ_GPIO_PINS(13);
185 DECLARE_APQ_GPIO_PINS(14);
186 DECLARE_APQ_GPIO_PINS(15);
187 DECLARE_APQ_GPIO_PINS(16);
188 DECLARE_APQ_GPIO_PINS(17);
189 DECLARE_APQ_GPIO_PINS(18);
190 DECLARE_APQ_GPIO_PINS(19);
191 DECLARE_APQ_GPIO_PINS(20);
192 DECLARE_APQ_GPIO_PINS(21);
193 DECLARE_APQ_GPIO_PINS(22);
194 DECLARE_APQ_GPIO_PINS(23);
195 DECLARE_APQ_GPIO_PINS(24);
196 DECLARE_APQ_GPIO_PINS(25);
197 DECLARE_APQ_GPIO_PINS(26);
198 DECLARE_APQ_GPIO_PINS(27);
199 DECLARE_APQ_GPIO_PINS(28);
200 DECLARE_APQ_GPIO_PINS(29);
201 DECLARE_APQ_GPIO_PINS(30);
202 DECLARE_APQ_GPIO_PINS(31);
203 DECLARE_APQ_GPIO_PINS(32);
204 DECLARE_APQ_GPIO_PINS(33);
205 DECLARE_APQ_GPIO_PINS(34);
206 DECLARE_APQ_GPIO_PINS(35);
207 DECLARE_APQ_GPIO_PINS(36);
208 DECLARE_APQ_GPIO_PINS(37);
209 DECLARE_APQ_GPIO_PINS(38);
210 DECLARE_APQ_GPIO_PINS(39);
211 DECLARE_APQ_GPIO_PINS(40);
212 DECLARE_APQ_GPIO_PINS(41);
213 DECLARE_APQ_GPIO_PINS(42);
214 DECLARE_APQ_GPIO_PINS(43);
215 DECLARE_APQ_GPIO_PINS(44);
216 DECLARE_APQ_GPIO_PINS(45);
217 DECLARE_APQ_GPIO_PINS(46);
218 DECLARE_APQ_GPIO_PINS(47);
219 DECLARE_APQ_GPIO_PINS(48);
220 DECLARE_APQ_GPIO_PINS(49);
221 DECLARE_APQ_GPIO_PINS(50);
222 DECLARE_APQ_GPIO_PINS(51);
223 DECLARE_APQ_GPIO_PINS(52);
224 DECLARE_APQ_GPIO_PINS(53);
225 DECLARE_APQ_GPIO_PINS(54);
226 DECLARE_APQ_GPIO_PINS(55);
227 DECLARE_APQ_GPIO_PINS(56);
228 DECLARE_APQ_GPIO_PINS(57);
229 DECLARE_APQ_GPIO_PINS(58);
230 DECLARE_APQ_GPIO_PINS(59);
231 DECLARE_APQ_GPIO_PINS(60);
232 DECLARE_APQ_GPIO_PINS(61);
233 DECLARE_APQ_GPIO_PINS(62);
234 DECLARE_APQ_GPIO_PINS(63);
235 DECLARE_APQ_GPIO_PINS(64);
236 DECLARE_APQ_GPIO_PINS(65);
237 DECLARE_APQ_GPIO_PINS(66);
238 DECLARE_APQ_GPIO_PINS(67);
239 DECLARE_APQ_GPIO_PINS(68);
240 DECLARE_APQ_GPIO_PINS(69);
241 DECLARE_APQ_GPIO_PINS(70);
242 DECLARE_APQ_GPIO_PINS(71);
243 DECLARE_APQ_GPIO_PINS(72);
244 DECLARE_APQ_GPIO_PINS(73);
245 DECLARE_APQ_GPIO_PINS(74);
246 DECLARE_APQ_GPIO_PINS(75);
247 DECLARE_APQ_GPIO_PINS(76);
248 DECLARE_APQ_GPIO_PINS(77);
249 DECLARE_APQ_GPIO_PINS(78);
250 DECLARE_APQ_GPIO_PINS(79);
251 DECLARE_APQ_GPIO_PINS(80);
252 DECLARE_APQ_GPIO_PINS(81);
253 DECLARE_APQ_GPIO_PINS(82);
254 DECLARE_APQ_GPIO_PINS(83);
255 DECLARE_APQ_GPIO_PINS(84);
256 DECLARE_APQ_GPIO_PINS(85);
257 DECLARE_APQ_GPIO_PINS(86);
258 DECLARE_APQ_GPIO_PINS(87);
259 DECLARE_APQ_GPIO_PINS(88);
260 DECLARE_APQ_GPIO_PINS(89);
261 DECLARE_APQ_GPIO_PINS(90);
262 DECLARE_APQ_GPIO_PINS(91);
263 DECLARE_APQ_GPIO_PINS(92);
264 DECLARE_APQ_GPIO_PINS(93);
265 DECLARE_APQ_GPIO_PINS(94);
266 DECLARE_APQ_GPIO_PINS(95);
267 DECLARE_APQ_GPIO_PINS(96);
268 DECLARE_APQ_GPIO_PINS(97);
269 DECLARE_APQ_GPIO_PINS(98);
270 DECLARE_APQ_GPIO_PINS(99);
271 DECLARE_APQ_GPIO_PINS(100);
272 DECLARE_APQ_GPIO_PINS(101);
273 DECLARE_APQ_GPIO_PINS(102);
274 DECLARE_APQ_GPIO_PINS(103);
275 DECLARE_APQ_GPIO_PINS(104);
276 DECLARE_APQ_GPIO_PINS(105);
277 DECLARE_APQ_GPIO_PINS(106);
278 DECLARE_APQ_GPIO_PINS(107);
279 DECLARE_APQ_GPIO_PINS(108);
280 DECLARE_APQ_GPIO_PINS(109);
281 DECLARE_APQ_GPIO_PINS(110);
282 DECLARE_APQ_GPIO_PINS(111);
283 DECLARE_APQ_GPIO_PINS(112);
284 DECLARE_APQ_GPIO_PINS(113);
285 DECLARE_APQ_GPIO_PINS(114);
286 DECLARE_APQ_GPIO_PINS(115);
287 DECLARE_APQ_GPIO_PINS(116);
288 DECLARE_APQ_GPIO_PINS(117);
289 DECLARE_APQ_GPIO_PINS(118);
290 DECLARE_APQ_GPIO_PINS(119);
291 DECLARE_APQ_GPIO_PINS(120);
292 DECLARE_APQ_GPIO_PINS(121);
293 DECLARE_APQ_GPIO_PINS(122);
294 DECLARE_APQ_GPIO_PINS(123);
295 DECLARE_APQ_GPIO_PINS(124);
296 DECLARE_APQ_GPIO_PINS(125);
297 DECLARE_APQ_GPIO_PINS(126);
298 DECLARE_APQ_GPIO_PINS(127);
299 DECLARE_APQ_GPIO_PINS(128);
300 DECLARE_APQ_GPIO_PINS(129);
301 DECLARE_APQ_GPIO_PINS(130);
302 DECLARE_APQ_GPIO_PINS(131);
303 DECLARE_APQ_GPIO_PINS(132);
304 DECLARE_APQ_GPIO_PINS(133);
305 DECLARE_APQ_GPIO_PINS(134);
306 DECLARE_APQ_GPIO_PINS(135);
307 DECLARE_APQ_GPIO_PINS(136);
308 DECLARE_APQ_GPIO_PINS(137);
309 DECLARE_APQ_GPIO_PINS(138);
310 DECLARE_APQ_GPIO_PINS(139);
311 DECLARE_APQ_GPIO_PINS(140);
312 DECLARE_APQ_GPIO_PINS(141);
313 DECLARE_APQ_GPIO_PINS(142);
314 DECLARE_APQ_GPIO_PINS(143);
315 DECLARE_APQ_GPIO_PINS(144);
316 DECLARE_APQ_GPIO_PINS(145);
317 DECLARE_APQ_GPIO_PINS(146);
318 
319 static const unsigned int sdc1_clk_pins[] = { 147 };
320 static const unsigned int sdc1_cmd_pins[] = { 148 };
321 static const unsigned int sdc1_data_pins[] = { 149 };
322 static const unsigned int sdc2_clk_pins[] = { 150 };
323 static const unsigned int sdc2_cmd_pins[] = { 151 };
324 static const unsigned int sdc2_data_pins[] = { 152 };
325 
326 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7)        \
327 	{						\
328 		.grp = PINCTRL_PINGROUP("gpio" #id, 	\
329 			gpio##id##_pins, 		\
330 			ARRAY_SIZE(gpio##id##_pins)),	\
331 		.funcs = (int[]){			\
332 			APQ_MUX_gpio,			\
333 			APQ_MUX_##f1,			\
334 			APQ_MUX_##f2,			\
335 			APQ_MUX_##f3,			\
336 			APQ_MUX_##f4,			\
337 			APQ_MUX_##f5,			\
338 			APQ_MUX_##f6,			\
339 			APQ_MUX_##f7			\
340 		},					\
341 		.nfuncs = 8,				\
342 		.ctl_reg = 0x1000 + 0x10 * id,		\
343 		.io_reg = 0x1004 + 0x10 * id,		\
344 		.intr_cfg_reg = 0x1008 + 0x10 * id,	\
345 		.intr_status_reg = 0x100c + 0x10 * id,	\
346 		.intr_target_reg = 0x1008 + 0x10 * id,	\
347 		.mux_bit = 2,				\
348 		.pull_bit = 0,				\
349 		.drv_bit = 6,				\
350 		.oe_bit = 9,				\
351 		.in_bit = 0,				\
352 		.out_bit = 1,				\
353 		.intr_enable_bit = 0,			\
354 		.intr_status_bit = 0,			\
355 		.intr_ack_high = 0,			\
356 		.intr_target_bit = 5,			\
357 		.intr_target_kpss_val = 3,		\
358 		.intr_raw_status_bit = 4,		\
359 		.intr_polarity_bit = 1,			\
360 		.intr_detection_bit = 2,		\
361 		.intr_detection_width = 2,		\
362 	}
363 
364 #define SDC_PINGROUP(pg_name, ctl, pull, drv)		\
365 	{						\
366 		.grp = PINCTRL_PINGROUP(#pg_name, 	\
367 			pg_name##_pins, 		\
368 			ARRAY_SIZE(pg_name##_pins)),	\
369 		.ctl_reg = ctl,                         \
370 		.io_reg = 0,                            \
371 		.intr_cfg_reg = 0,                      \
372 		.intr_status_reg = 0,                   \
373 		.intr_target_reg = 0,                   \
374 		.mux_bit = -1,                          \
375 		.pull_bit = pull,                       \
376 		.drv_bit = drv,                         \
377 		.oe_bit = -1,                           \
378 		.in_bit = -1,                           \
379 		.out_bit = -1,                          \
380 		.intr_enable_bit = -1,                  \
381 		.intr_status_bit = -1,                  \
382 		.intr_target_bit = -1,                  \
383 		.intr_target_kpss_val = -1,		\
384 		.intr_raw_status_bit = -1,              \
385 		.intr_polarity_bit = -1,                \
386 		.intr_detection_bit = -1,               \
387 		.intr_detection_width = -1,             \
388 	}
389 
390 enum apq8084_functions {
391 	APQ_MUX_adsp_ext,
392 	APQ_MUX_audio_ref,
393 	APQ_MUX_blsp_i2c1,
394 	APQ_MUX_blsp_i2c2,
395 	APQ_MUX_blsp_i2c3,
396 	APQ_MUX_blsp_i2c4,
397 	APQ_MUX_blsp_i2c5,
398 	APQ_MUX_blsp_i2c6,
399 	APQ_MUX_blsp_i2c7,
400 	APQ_MUX_blsp_i2c8,
401 	APQ_MUX_blsp_i2c9,
402 	APQ_MUX_blsp_i2c10,
403 	APQ_MUX_blsp_i2c11,
404 	APQ_MUX_blsp_i2c12,
405 	APQ_MUX_blsp_spi1,
406 	APQ_MUX_blsp_spi1_cs1,
407 	APQ_MUX_blsp_spi1_cs2,
408 	APQ_MUX_blsp_spi1_cs3,
409 	APQ_MUX_blsp_spi2,
410 	APQ_MUX_blsp_spi3,
411 	APQ_MUX_blsp_spi3_cs1,
412 	APQ_MUX_blsp_spi3_cs2,
413 	APQ_MUX_blsp_spi3_cs3,
414 	APQ_MUX_blsp_spi4,
415 	APQ_MUX_blsp_spi5,
416 	APQ_MUX_blsp_spi6,
417 	APQ_MUX_blsp_spi7,
418 	APQ_MUX_blsp_spi8,
419 	APQ_MUX_blsp_spi9,
420 	APQ_MUX_blsp_spi10,
421 	APQ_MUX_blsp_spi10_cs1,
422 	APQ_MUX_blsp_spi10_cs2,
423 	APQ_MUX_blsp_spi10_cs3,
424 	APQ_MUX_blsp_spi11,
425 	APQ_MUX_blsp_spi12,
426 	APQ_MUX_blsp_uart1,
427 	APQ_MUX_blsp_uart2,
428 	APQ_MUX_blsp_uart3,
429 	APQ_MUX_blsp_uart4,
430 	APQ_MUX_blsp_uart5,
431 	APQ_MUX_blsp_uart6,
432 	APQ_MUX_blsp_uart7,
433 	APQ_MUX_blsp_uart8,
434 	APQ_MUX_blsp_uart9,
435 	APQ_MUX_blsp_uart10,
436 	APQ_MUX_blsp_uart11,
437 	APQ_MUX_blsp_uart12,
438 	APQ_MUX_blsp_uim1,
439 	APQ_MUX_blsp_uim2,
440 	APQ_MUX_blsp_uim3,
441 	APQ_MUX_blsp_uim4,
442 	APQ_MUX_blsp_uim5,
443 	APQ_MUX_blsp_uim6,
444 	APQ_MUX_blsp_uim7,
445 	APQ_MUX_blsp_uim8,
446 	APQ_MUX_blsp_uim9,
447 	APQ_MUX_blsp_uim10,
448 	APQ_MUX_blsp_uim11,
449 	APQ_MUX_blsp_uim12,
450 	APQ_MUX_cam_mclk0,
451 	APQ_MUX_cam_mclk1,
452 	APQ_MUX_cam_mclk2,
453 	APQ_MUX_cam_mclk3,
454 	APQ_MUX_cci_async,
455 	APQ_MUX_cci_async_in0,
456 	APQ_MUX_cci_i2c0,
457 	APQ_MUX_cci_i2c1,
458 	APQ_MUX_cci_timer0,
459 	APQ_MUX_cci_timer1,
460 	APQ_MUX_cci_timer2,
461 	APQ_MUX_cci_timer3,
462 	APQ_MUX_cci_timer4,
463 	APQ_MUX_edp_hpd,
464 	APQ_MUX_gcc_gp1,
465 	APQ_MUX_gcc_gp2,
466 	APQ_MUX_gcc_gp3,
467 	APQ_MUX_gcc_obt,
468 	APQ_MUX_gcc_vtt,
469 	APQ_MUX_gp_mn,
470 	APQ_MUX_gp_pdm0,
471 	APQ_MUX_gp_pdm1,
472 	APQ_MUX_gp_pdm2,
473 	APQ_MUX_gp0_clk,
474 	APQ_MUX_gp1_clk,
475 	APQ_MUX_gpio,
476 	APQ_MUX_hdmi_cec,
477 	APQ_MUX_hdmi_ddc,
478 	APQ_MUX_hdmi_dtest,
479 	APQ_MUX_hdmi_hpd,
480 	APQ_MUX_hdmi_rcv,
481 	APQ_MUX_hsic,
482 	APQ_MUX_ldo_en,
483 	APQ_MUX_ldo_update,
484 	APQ_MUX_mdp_vsync,
485 	APQ_MUX_pci_e0,
486 	APQ_MUX_pci_e0_n,
487 	APQ_MUX_pci_e0_rst,
488 	APQ_MUX_pci_e1,
489 	APQ_MUX_pci_e1_rst,
490 	APQ_MUX_pci_e1_rst_n,
491 	APQ_MUX_pci_e1_clkreq_n,
492 	APQ_MUX_pri_mi2s,
493 	APQ_MUX_qua_mi2s,
494 	APQ_MUX_sata_act,
495 	APQ_MUX_sata_devsleep,
496 	APQ_MUX_sata_devsleep_n,
497 	APQ_MUX_sd_write,
498 	APQ_MUX_sdc_emmc_mode,
499 	APQ_MUX_sdc3,
500 	APQ_MUX_sdc4,
501 	APQ_MUX_sec_mi2s,
502 	APQ_MUX_slimbus,
503 	APQ_MUX_spdif_tx,
504 	APQ_MUX_spkr_i2s,
505 	APQ_MUX_spkr_i2s_ws,
506 	APQ_MUX_spss_geni,
507 	APQ_MUX_ter_mi2s,
508 	APQ_MUX_tsif1,
509 	APQ_MUX_tsif2,
510 	APQ_MUX_uim,
511 	APQ_MUX_uim_batt_alarm,
512 	APQ_MUX_NA,
513 };
514 
515 static const char * const gpio_groups[] = {
516 	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
517 	"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
518 	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
519 	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
520 	"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
521 	"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
522 	"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
523 	"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
524 	"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
525 	"gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
526 	"gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
527 	"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
528 	"gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
529 	"gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
530 	"gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
531 	"gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
532 	"gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
533 	"gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
534 	"gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
535 	"gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
536 	"gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
537 	"gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146"
538 };
539 
540 static const char * const adsp_ext_groups[] = {
541 	"gpio34"
542 };
543 static const char * const audio_ref_groups[] = {
544 	"gpio100"
545 };
546 static const char * const blsp_i2c1_groups[] = {
547 	"gpio2", "gpio3"
548 };
549 static const char * const blsp_i2c2_groups[] = {
550 	"gpio6", "gpio7"
551 };
552 static const char * const blsp_i2c3_groups[] = {
553 	"gpio10", "gpio11"
554 };
555 static const char * const blsp_i2c4_groups[] = {
556 	"gpio29", "gpio30"
557 };
558 static const char * const blsp_i2c5_groups[] = {
559 	"gpio41", "gpio42"
560 };
561 static const char * const blsp_i2c6_groups[] = {
562 	"gpio45", "gpio46"
563 };
564 static const char * const blsp_i2c7_groups[] = {
565 	"gpio132", "gpio133"
566 };
567 static const char * const blsp_i2c8_groups[] = {
568 	"gpio53", "gpio54"
569 };
570 static const char * const blsp_i2c9_groups[] = {
571 	"gpio57", "gpio58"
572 };
573 static const char * const blsp_i2c10_groups[] = {
574 	"gpio61", "gpio62"
575 };
576 static const char * const blsp_i2c11_groups[] = {
577 	"gpio65", "gpio66"
578 };
579 static const char * const blsp_i2c12_groups[] = {
580 	"gpio49", "gpio50"
581 };
582 static const char * const blsp_spi1_groups[] = {
583 	"gpio0", "gpio1", "gpio2", "gpio3"
584 };
585 static const char * const blsp_spi2_groups[] = {
586 	"gpio4", "gpio5", "gpio6", "gpio7"
587 };
588 static const char * const blsp_spi3_groups[] = {
589 	"gpio8", "gpio9", "gpio10", "gpio11"
590 };
591 static const char * const blsp_spi4_groups[] = {
592 	"gpio27", "gpio28", "gpio29", "gpio30"
593 };
594 static const char * const blsp_spi5_groups[] = {
595 	"gpio39", "gpio40", "gpio41", "gpio42"
596 };
597 static const char * const blsp_spi6_groups[] = {
598 	"gpio43", "gpio44", "gpio45", "gpio46"
599 };
600 static const char * const blsp_spi7_groups[] = {
601 	"gpio130", "gpio131", "gpio132", "gpio133"
602 };
603 static const char * const blsp_spi8_groups[] = {
604 	"gpio51", "gpio52", "gpio53", "gpio54"
605 };
606 static const char * const blsp_spi9_groups[] = {
607 	"gpio55", "gpio56", "gpio57", "gpio58"
608 };
609 static const char * const blsp_spi10_groups[] = {
610 	"gpio59", "gpio60", "gpio61", "gpio62"
611 };
612 static const char * const blsp_spi11_groups[] = {
613 	"gpio63", "gpio64", "gpio65", "gpio66"
614 };
615 static const char * const blsp_spi12_groups[] = {
616 	"gpio47", "gpio48", "gpio49", "gpio50"
617 };
618 static const char * const blsp_uart1_groups[] = {
619 	"gpio0", "gpio1", "gpio2", "gpio3"
620 };
621 static const char * const blsp_uart2_groups[] = {
622 	"gpio4", "gpio5", "gpio6", "gpio7"
623 };
624 static const char * const blsp_uart3_groups[] = {
625 	"gpio8"
626 };
627 static const char * const blsp_uart4_groups[] = {
628 	"gpio27", "gpio28", "gpio29", "gpio30"
629 };
630 static const char * const blsp_uart5_groups[] = {
631 	"gpio39", "gpio40", "gpio41", "gpio42"
632 };
633 static const char * const blsp_uart6_groups[] = {
634 	"gpio43", "gpio44", "gpio45", "gpio46"
635 };
636 static const char * const blsp_uart7_groups[] = {
637 	"gpio130", "gpio131", "gpio132", "gpio133"
638 };
639 static const char * const blsp_uart8_groups[] = {
640 	"gpio51", "gpio52", "gpio53", "gpio54"
641 };
642 static const char * const blsp_uart9_groups[] = {
643 	"gpio55", "gpio56", "gpio57", "gpio58"
644 };
645 static const char * const blsp_uart10_groups[] = {
646 	"gpio59", "gpio60", "gpio61", "gpio62"
647 };
648 static const char * const blsp_uart11_groups[] = {
649 	"gpio63", "gpio64", "gpio65", "gpio66"
650 };
651 static const char * const blsp_uart12_groups[] = {
652 	"gpio47", "gpio48", "gpio49", "gpio50"
653 };
654 static const char * const blsp_uim1_groups[] = {
655 	"gpio0", "gpio1"
656 };
657 static const char * const blsp_uim2_groups[] = {
658 	"gpio4", "gpio5"
659 };
660 static const char * const blsp_uim3_groups[] = {
661 	"gpio8", "gpio9"
662 };
663 static const char * const blsp_uim4_groups[] = {
664 	"gpio27", "gpio28"
665 };
666 static const char * const blsp_uim5_groups[] = {
667 	"gpio39", "gpio40"
668 };
669 static const char * const blsp_uim6_groups[] = {
670 	"gpio43", "gpio44"
671 };
672 static const char * const blsp_uim7_groups[] = {
673 	"gpio130", "gpio131"
674 };
675 static const char * const blsp_uim8_groups[] = {
676 	"gpio51", "gpio52"
677 };
678 static const char * const blsp_uim9_groups[] = {
679 	"gpio55", "gpio56"
680 };
681 static const char * const blsp_uim10_groups[] = {
682 	"gpio59", "gpio60"
683 };
684 static const char * const blsp_uim11_groups[] = {
685 	"gpio63", "gpio64"
686 };
687 static const char * const blsp_uim12_groups[] = {
688 	"gpio47", "gpio48"
689 };
690 static const char * const blsp_spi1_cs1_groups[] = {
691 	"gpio116"
692 };
693 static const char * const blsp_spi1_cs2_groups[] = {
694 	"gpio117"
695 };
696 static const char * const blsp_spi1_cs3_groups[] = {
697 	"gpio118"
698 };
699 static const char * const blsp_spi3_cs1_groups[] = {
700 	"gpio67"
701 };
702 static const char * const blsp_spi3_cs2_groups[] = {
703 	"gpio71"
704 };
705 static const char * const blsp_spi3_cs3_groups[] = {
706 	"gpio72"
707 };
708 static const char * const blsp_spi10_cs1_groups[] = {
709 	"gpio106"
710 };
711 static const char * const blsp_spi10_cs2_groups[] = {
712 	"gpio111"
713 };
714 static const char * const blsp_spi10_cs3_groups[] = {
715 	"gpio128"
716 };
717 static const char * const cam_mclk0_groups[] = {
718 	"gpio15"
719 };
720 static const char * const cam_mclk1_groups[] = {
721 	"gpio16"
722 };
723 static const char * const cam_mclk2_groups[] = {
724 	"gpio17"
725 };
726 static const char * const cam_mclk3_groups[] = {
727 	"gpio18"
728 };
729 static const char * const cci_async_groups[] = {
730 	"gpio26", "gpio119"
731 };
732 static const char * const cci_async_in0_groups[] = {
733 	"gpio120"
734 };
735 static const char * const cci_i2c0_groups[] = {
736 	"gpio19", "gpio20"
737 };
738 static const char * const cci_i2c1_groups[] = {
739 	"gpio21", "gpio22"
740 };
741 static const char * const cci_timer0_groups[] = {
742 	"gpio23"
743 };
744 static const char * const cci_timer1_groups[] = {
745 	"gpio24"
746 };
747 static const char * const cci_timer2_groups[] = {
748 	"gpio25"
749 };
750 static const char * const cci_timer3_groups[] = {
751 	"gpio26"
752 };
753 static const char * const cci_timer4_groups[] = {
754 	"gpio119"
755 };
756 static const char * const edp_hpd_groups[] = {
757 	"gpio103"
758 };
759 static const char * const gcc_gp1_groups[] = {
760 	"gpio37"
761 };
762 static const char * const gcc_gp2_groups[] = {
763 	"gpio38"
764 };
765 static const char * const gcc_gp3_groups[] = {
766 	"gpio86"
767 };
768 static const char * const gcc_obt_groups[] = {
769 	"gpio127"
770 };
771 static const char * const gcc_vtt_groups[] = {
772 	"gpio126"
773 };
774 static const char * const gp_mn_groups[] = {
775 	"gpio29"
776 };
777 static const char * const gp_pdm0_groups[] = {
778 	"gpio48", "gpio83"
779 };
780 static const char * const gp_pdm1_groups[] = {
781 	"gpio84", "gpio101"
782 };
783 static const char * const gp_pdm2_groups[] = {
784 	"gpio85", "gpio110"
785 };
786 static const char * const gp0_clk_groups[] = {
787 	"gpio25"
788 };
789 static const char * const gp1_clk_groups[] = {
790 	"gpio26"
791 };
792 static const char * const hdmi_cec_groups[] = {
793 	"gpio31"
794 };
795 static const char * const hdmi_ddc_groups[] = {
796 	"gpio32", "gpio33"
797 };
798 static const char * const hdmi_dtest_groups[] = {
799 	"gpio123"
800 };
801 static const char * const hdmi_hpd_groups[] = {
802 	"gpio34"
803 };
804 static const char * const hdmi_rcv_groups[] = {
805 	"gpio125"
806 };
807 static const char * const hsic_groups[] = {
808 	"gpio134", "gpio135"
809 };
810 static const char * const ldo_en_groups[] = {
811 	"gpio124"
812 };
813 static const char * const ldo_update_groups[] = {
814 	"gpio125"
815 };
816 static const char * const mdp_vsync_groups[] = {
817 	"gpio12", "gpio13", "gpio14"
818 };
819 static const char * const pci_e0_groups[] = {
820 	"gpio68", "gpio70"
821 };
822 static const char * const pci_e0_n_groups[] = {
823 	"gpio68", "gpio70"
824 };
825 static const char * const pci_e0_rst_groups[] = {
826 	"gpio70"
827 };
828 static const char * const pci_e1_groups[] = {
829 	"gpio140"
830 };
831 static const char * const pci_e1_rst_groups[] = {
832 	"gpio140"
833 };
834 static const char * const pci_e1_rst_n_groups[] = {
835 	"gpio140"
836 };
837 static const char * const pci_e1_clkreq_n_groups[] = {
838 	"gpio141"
839 };
840 static const char * const pri_mi2s_groups[] = {
841 	"gpio76", "gpio77", "gpio78", "gpio79", "gpio80"
842 };
843 static const char * const qua_mi2s_groups[] = {
844 	"gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97"
845 };
846 static const char * const sata_act_groups[] = {
847 	"gpio129"
848 };
849 static const char * const sata_devsleep_groups[] = {
850 	"gpio119"
851 };
852 static const char * const sata_devsleep_n_groups[] = {
853 	"gpio119"
854 };
855 static const char * const sd_write_groups[] = {
856 	"gpio75"
857 };
858 static const char * const sdc_emmc_mode_groups[] = {
859 	"gpio146"
860 };
861 static const char * const sdc3_groups[] = {
862 	"gpio67", "gpio68", "gpio69", "gpio70", "gpio71", "gpio72"
863 };
864 static const char * const sdc4_groups[] = {
865 	"gpio82", "gpio83", "gpio84", "gpio85", "gpio86",
866 	"gpio91", "gpio95", "gpio96", "gpio97", "gpio101"
867 };
868 static const char * const sec_mi2s_groups[] = {
869 	"gpio81", "gpio82", "gpio83", "gpio84", "gpio85"
870 };
871 static const char * const slimbus_groups[] = {
872 	"gpio98", "gpio99"
873 };
874 static const char * const spdif_tx_groups[] = {
875 	"gpio124", "gpio136", "gpio142"
876 };
877 static const char * const spkr_i2s_groups[] = {
878 	"gpio98", "gpio99", "gpio100"
879 };
880 static const char * const spkr_i2s_ws_groups[] = {
881 	"gpio104"
882 };
883 static const char * const spss_geni_groups[] = {
884 	"gpio8", "gpio9"
885 };
886 static const char * const ter_mi2s_groups[] = {
887 	"gpio86", "gpio87", "gpio88", "gpio89", "gpio90"
888 };
889 static const char * const tsif1_groups[] = {
890 	"gpio82", "gpio83", "gpio84", "gpio85", "gpio86"
891 };
892 static const char * const tsif2_groups[] = {
893 	"gpio91", "gpio95", "gpio96", "gpio97", "gpio101"
894 };
895 static const char * const uim_groups[] = {
896 	"gpio130", "gpio131", "gpio132", "gpio133"
897 };
898 static const char * const uim_batt_alarm_groups[] = {
899 	"gpio102"
900 };
901 static const struct pinfunction apq8084_functions[] = {
902 	APQ_PIN_FUNCTION(adsp_ext),
903 	APQ_PIN_FUNCTION(audio_ref),
904 	APQ_PIN_FUNCTION(blsp_i2c1),
905 	APQ_PIN_FUNCTION(blsp_i2c2),
906 	APQ_PIN_FUNCTION(blsp_i2c3),
907 	APQ_PIN_FUNCTION(blsp_i2c4),
908 	APQ_PIN_FUNCTION(blsp_i2c5),
909 	APQ_PIN_FUNCTION(blsp_i2c6),
910 	APQ_PIN_FUNCTION(blsp_i2c7),
911 	APQ_PIN_FUNCTION(blsp_i2c8),
912 	APQ_PIN_FUNCTION(blsp_i2c9),
913 	APQ_PIN_FUNCTION(blsp_i2c10),
914 	APQ_PIN_FUNCTION(blsp_i2c11),
915 	APQ_PIN_FUNCTION(blsp_i2c12),
916 	APQ_PIN_FUNCTION(blsp_spi1),
917 	APQ_PIN_FUNCTION(blsp_spi1_cs1),
918 	APQ_PIN_FUNCTION(blsp_spi1_cs2),
919 	APQ_PIN_FUNCTION(blsp_spi1_cs3),
920 	APQ_PIN_FUNCTION(blsp_spi2),
921 	APQ_PIN_FUNCTION(blsp_spi3),
922 	APQ_PIN_FUNCTION(blsp_spi3_cs1),
923 	APQ_PIN_FUNCTION(blsp_spi3_cs2),
924 	APQ_PIN_FUNCTION(blsp_spi3_cs3),
925 	APQ_PIN_FUNCTION(blsp_spi4),
926 	APQ_PIN_FUNCTION(blsp_spi5),
927 	APQ_PIN_FUNCTION(blsp_spi6),
928 	APQ_PIN_FUNCTION(blsp_spi7),
929 	APQ_PIN_FUNCTION(blsp_spi8),
930 	APQ_PIN_FUNCTION(blsp_spi9),
931 	APQ_PIN_FUNCTION(blsp_spi10),
932 	APQ_PIN_FUNCTION(blsp_spi10_cs1),
933 	APQ_PIN_FUNCTION(blsp_spi10_cs2),
934 	APQ_PIN_FUNCTION(blsp_spi10_cs3),
935 	APQ_PIN_FUNCTION(blsp_spi11),
936 	APQ_PIN_FUNCTION(blsp_spi12),
937 	APQ_PIN_FUNCTION(blsp_uart1),
938 	APQ_PIN_FUNCTION(blsp_uart2),
939 	APQ_PIN_FUNCTION(blsp_uart3),
940 	APQ_PIN_FUNCTION(blsp_uart4),
941 	APQ_PIN_FUNCTION(blsp_uart5),
942 	APQ_PIN_FUNCTION(blsp_uart6),
943 	APQ_PIN_FUNCTION(blsp_uart7),
944 	APQ_PIN_FUNCTION(blsp_uart8),
945 	APQ_PIN_FUNCTION(blsp_uart9),
946 	APQ_PIN_FUNCTION(blsp_uart10),
947 	APQ_PIN_FUNCTION(blsp_uart11),
948 	APQ_PIN_FUNCTION(blsp_uart12),
949 	APQ_PIN_FUNCTION(blsp_uim1),
950 	APQ_PIN_FUNCTION(blsp_uim2),
951 	APQ_PIN_FUNCTION(blsp_uim3),
952 	APQ_PIN_FUNCTION(blsp_uim4),
953 	APQ_PIN_FUNCTION(blsp_uim5),
954 	APQ_PIN_FUNCTION(blsp_uim6),
955 	APQ_PIN_FUNCTION(blsp_uim7),
956 	APQ_PIN_FUNCTION(blsp_uim8),
957 	APQ_PIN_FUNCTION(blsp_uim9),
958 	APQ_PIN_FUNCTION(blsp_uim10),
959 	APQ_PIN_FUNCTION(blsp_uim11),
960 	APQ_PIN_FUNCTION(blsp_uim12),
961 	APQ_PIN_FUNCTION(cam_mclk0),
962 	APQ_PIN_FUNCTION(cam_mclk1),
963 	APQ_PIN_FUNCTION(cam_mclk2),
964 	APQ_PIN_FUNCTION(cam_mclk3),
965 	APQ_PIN_FUNCTION(cci_async),
966 	APQ_PIN_FUNCTION(cci_async_in0),
967 	APQ_PIN_FUNCTION(cci_i2c0),
968 	APQ_PIN_FUNCTION(cci_i2c1),
969 	APQ_PIN_FUNCTION(cci_timer0),
970 	APQ_PIN_FUNCTION(cci_timer1),
971 	APQ_PIN_FUNCTION(cci_timer2),
972 	APQ_PIN_FUNCTION(cci_timer3),
973 	APQ_PIN_FUNCTION(cci_timer4),
974 	APQ_PIN_FUNCTION(edp_hpd),
975 	APQ_PIN_FUNCTION(gcc_gp1),
976 	APQ_PIN_FUNCTION(gcc_gp2),
977 	APQ_PIN_FUNCTION(gcc_gp3),
978 	APQ_PIN_FUNCTION(gcc_obt),
979 	APQ_PIN_FUNCTION(gcc_vtt),
980 	APQ_PIN_FUNCTION(gp_mn),
981 	APQ_PIN_FUNCTION(gp_pdm0),
982 	APQ_PIN_FUNCTION(gp_pdm1),
983 	APQ_PIN_FUNCTION(gp_pdm2),
984 	APQ_PIN_FUNCTION(gp0_clk),
985 	APQ_PIN_FUNCTION(gp1_clk),
986 	APQ_PIN_FUNCTION(gpio),
987 	APQ_PIN_FUNCTION(hdmi_cec),
988 	APQ_PIN_FUNCTION(hdmi_ddc),
989 	APQ_PIN_FUNCTION(hdmi_dtest),
990 	APQ_PIN_FUNCTION(hdmi_hpd),
991 	APQ_PIN_FUNCTION(hdmi_rcv),
992 	APQ_PIN_FUNCTION(hsic),
993 	APQ_PIN_FUNCTION(ldo_en),
994 	APQ_PIN_FUNCTION(ldo_update),
995 	APQ_PIN_FUNCTION(mdp_vsync),
996 	APQ_PIN_FUNCTION(pci_e0),
997 	APQ_PIN_FUNCTION(pci_e0_n),
998 	APQ_PIN_FUNCTION(pci_e0_rst),
999 	APQ_PIN_FUNCTION(pci_e1),
1000 	APQ_PIN_FUNCTION(pci_e1_rst),
1001 	APQ_PIN_FUNCTION(pci_e1_rst_n),
1002 	APQ_PIN_FUNCTION(pci_e1_clkreq_n),
1003 	APQ_PIN_FUNCTION(pri_mi2s),
1004 	APQ_PIN_FUNCTION(qua_mi2s),
1005 	APQ_PIN_FUNCTION(sata_act),
1006 	APQ_PIN_FUNCTION(sata_devsleep),
1007 	APQ_PIN_FUNCTION(sata_devsleep_n),
1008 	APQ_PIN_FUNCTION(sd_write),
1009 	APQ_PIN_FUNCTION(sdc_emmc_mode),
1010 	APQ_PIN_FUNCTION(sdc3),
1011 	APQ_PIN_FUNCTION(sdc4),
1012 	APQ_PIN_FUNCTION(sec_mi2s),
1013 	APQ_PIN_FUNCTION(slimbus),
1014 	APQ_PIN_FUNCTION(spdif_tx),
1015 	APQ_PIN_FUNCTION(spkr_i2s),
1016 	APQ_PIN_FUNCTION(spkr_i2s_ws),
1017 	APQ_PIN_FUNCTION(spss_geni),
1018 	APQ_PIN_FUNCTION(ter_mi2s),
1019 	APQ_PIN_FUNCTION(tsif1),
1020 	APQ_PIN_FUNCTION(tsif2),
1021 	APQ_PIN_FUNCTION(uim),
1022 	APQ_PIN_FUNCTION(uim_batt_alarm),
1023 };
1024 
1025 static const struct msm_pingroup apq8084_groups[] = {
1026 	PINGROUP(0,   blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA),
1027 	PINGROUP(1,   blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA),
1028 	PINGROUP(2,   blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA),
1029 	PINGROUP(3,   blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA),
1030 	PINGROUP(4,   blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA),
1031 	PINGROUP(5,   blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA),
1032 	PINGROUP(6,   blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA),
1033 	PINGROUP(7,   blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA),
1034 	PINGROUP(8,   blsp_spi3, blsp_uart3, blsp_uim3, spss_geni, NA, NA, NA),
1035 	PINGROUP(9,   blsp_spi3, blsp_uim3, blsp_uart3, spss_geni, NA, NA, NA),
1036 	PINGROUP(10,  blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA),
1037 	PINGROUP(11,  blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA),
1038 	PINGROUP(12,  mdp_vsync, NA, NA, NA, NA, NA, NA),
1039 	PINGROUP(13,  mdp_vsync, NA, NA, NA, NA, NA, NA),
1040 	PINGROUP(14,  mdp_vsync, NA, NA, NA, NA, NA, NA),
1041 	PINGROUP(15,  cam_mclk0, NA, NA, NA, NA, NA, NA),
1042 	PINGROUP(16,  cam_mclk1, NA, NA, NA, NA, NA, NA),
1043 	PINGROUP(17,  cam_mclk2, NA, NA, NA, NA, NA, NA),
1044 	PINGROUP(18,  cam_mclk3, NA, NA, NA, NA, NA, NA),
1045 	PINGROUP(19,  cci_i2c0, NA, NA, NA, NA, NA, NA),
1046 	PINGROUP(20,  cci_i2c0, NA, NA, NA, NA, NA, NA),
1047 	PINGROUP(21,  cci_i2c1, NA, NA, NA, NA, NA, NA),
1048 	PINGROUP(22,  cci_i2c1, NA, NA, NA, NA, NA, NA),
1049 	PINGROUP(23,  cci_timer0, NA, NA, NA, NA, NA, NA),
1050 	PINGROUP(24,  cci_timer1, NA, NA, NA, NA, NA, NA),
1051 	PINGROUP(25,  cci_timer2, gp0_clk, NA, NA, NA, NA, NA),
1052 	PINGROUP(26,  cci_timer3, cci_async, gp1_clk, NA, NA, NA, NA),
1053 	PINGROUP(27,  blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA, NA),
1054 	PINGROUP(28,  blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA, NA),
1055 	PINGROUP(29,  blsp_spi4, blsp_uart4, blsp_i2c4, gp_mn, NA, NA, NA),
1056 	PINGROUP(30,  blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA, NA),
1057 	PINGROUP(31,  hdmi_cec, NA, NA, NA, NA, NA, NA),
1058 	PINGROUP(32,  hdmi_ddc, NA, NA, NA, NA, NA, NA),
1059 	PINGROUP(33,  hdmi_ddc, NA, NA, NA, NA, NA, NA),
1060 	PINGROUP(34,  hdmi_hpd, NA, adsp_ext, NA, NA, NA, NA),
1061 	PINGROUP(35,  NA, NA, NA, NA, NA, NA, NA),
1062 	PINGROUP(36,  NA, NA, NA, NA, NA, NA, NA),
1063 	PINGROUP(37,  gcc_gp1, NA, NA, NA, NA, NA, NA),
1064 	PINGROUP(38,  gcc_gp2, NA, NA, NA, NA, NA, NA),
1065 	PINGROUP(39,  blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA),
1066 	PINGROUP(40,  blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA),
1067 	PINGROUP(41,  blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA),
1068 	PINGROUP(42,  blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA),
1069 	PINGROUP(43,  blsp_spi6, blsp_uart6, blsp_uim6, NA, NA, NA, NA),
1070 	PINGROUP(44,  blsp_spi6, blsp_uart6, blsp_uim6, NA, NA, NA, NA),
1071 	PINGROUP(45,  blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA),
1072 	PINGROUP(46,  blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA),
1073 	PINGROUP(47,  blsp_spi12, blsp_uart12, blsp_uim12, NA, NA, NA, NA),
1074 	PINGROUP(48,  blsp_spi12, blsp_uart12, blsp_uim12, gp_pdm0, NA, NA, NA),
1075 	PINGROUP(49,  blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA),
1076 	PINGROUP(50,  blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA),
1077 	PINGROUP(51,  blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA),
1078 	PINGROUP(52,  blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA),
1079 	PINGROUP(53,  blsp_spi8, blsp_uart8, blsp_i2c8, NA, NA, NA, NA),
1080 	PINGROUP(54,  blsp_spi8, blsp_uart8, blsp_i2c8, NA, NA, NA, NA),
1081 	PINGROUP(55,  blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA, NA),
1082 	PINGROUP(56,  blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA, NA),
1083 	PINGROUP(57,  blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA, NA),
1084 	PINGROUP(58,  blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA, NA),
1085 	PINGROUP(59,  blsp_spi10, blsp_uart10, blsp_uim10, NA, NA, NA, NA),
1086 	PINGROUP(60,  blsp_spi10, blsp_uart10, blsp_uim10, NA, NA, NA, NA),
1087 	PINGROUP(61,  blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA),
1088 	PINGROUP(62,  blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA),
1089 	PINGROUP(63,  blsp_spi11, blsp_uart11, blsp_uim11, NA, NA, NA, NA),
1090 	PINGROUP(64,  blsp_spi11, blsp_uart11, blsp_uim11, NA, NA, NA, NA),
1091 	PINGROUP(65,  blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA),
1092 	PINGROUP(66,  blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA),
1093 	PINGROUP(67,  sdc3, blsp_spi3_cs1, NA, NA, NA, NA, NA),
1094 	PINGROUP(68,  sdc3, pci_e0, NA, NA, NA, NA, NA),
1095 	PINGROUP(69,  sdc3, NA, NA, NA, NA, NA, NA),
1096 	PINGROUP(70,  sdc3, pci_e0_n, pci_e0, NA, NA, NA, NA),
1097 	PINGROUP(71,  sdc3, blsp_spi3_cs2, NA, NA, NA, NA, NA),
1098 	PINGROUP(72,  sdc3, blsp_spi3_cs3, NA, NA, NA, NA, NA),
1099 	PINGROUP(73,  NA, NA, NA, NA, NA, NA, NA),
1100 	PINGROUP(74,  NA, NA, NA, NA, NA, NA, NA),
1101 	PINGROUP(75,  sd_write, NA, NA, NA, NA, NA, NA),
1102 	PINGROUP(76,  pri_mi2s, NA, NA, NA, NA, NA, NA),
1103 	PINGROUP(77,  pri_mi2s, NA, NA, NA, NA, NA, NA),
1104 	PINGROUP(78,  pri_mi2s, NA, NA, NA, NA, NA, NA),
1105 	PINGROUP(79,  pri_mi2s, NA, NA, NA, NA, NA, NA),
1106 	PINGROUP(80,  pri_mi2s, NA, NA, NA, NA, NA, NA),
1107 	PINGROUP(81,  sec_mi2s, NA, NA, NA, NA, NA, NA),
1108 	PINGROUP(82,  sec_mi2s, sdc4, tsif1, NA, NA, NA, NA),
1109 	PINGROUP(83,  sec_mi2s, sdc4, tsif1, NA, NA, NA, gp_pdm0),
1110 	PINGROUP(84,  sec_mi2s, sdc4, tsif1, NA, NA, NA, gp_pdm1),
1111 	PINGROUP(85,  sec_mi2s, sdc4, tsif1, NA, gp_pdm2, NA, NA),
1112 	PINGROUP(86,  ter_mi2s, sdc4, tsif1, NA, NA, NA, gcc_gp3),
1113 	PINGROUP(87,  ter_mi2s, NA, NA, NA, NA, NA, NA),
1114 	PINGROUP(88,  ter_mi2s, NA, NA, NA, NA, NA, NA),
1115 	PINGROUP(89,  ter_mi2s, NA, NA, NA, NA, NA, NA),
1116 	PINGROUP(90,  ter_mi2s, NA, NA, NA, NA, NA, NA),
1117 	PINGROUP(91,  qua_mi2s, sdc4, tsif2, NA, NA, NA, NA),
1118 	PINGROUP(92,  qua_mi2s, NA, NA, NA, NA, NA, NA),
1119 	PINGROUP(93,  qua_mi2s, NA, NA, NA, NA, NA, NA),
1120 	PINGROUP(94,  qua_mi2s, NA, NA, NA, NA, NA, NA),
1121 	PINGROUP(95,  qua_mi2s, sdc4, tsif2, NA, NA, NA, gcc_gp1),
1122 	PINGROUP(96,  qua_mi2s, sdc4, tsif2, NA, NA, NA, gcc_gp2),
1123 	PINGROUP(97,  qua_mi2s, sdc4, tsif2, NA, gcc_gp3, NA, NA),
1124 	PINGROUP(98,  slimbus, spkr_i2s, NA, NA, NA, NA, NA),
1125 	PINGROUP(99,  slimbus, spkr_i2s, NA, NA, NA, NA, NA),
1126 	PINGROUP(100, audio_ref, spkr_i2s, NA, NA, NA, NA, NA),
1127 	PINGROUP(101, sdc4, tsif2, gp_pdm1, NA, NA, NA, NA),
1128 	PINGROUP(102, uim_batt_alarm, NA, NA, NA, NA, NA, NA),
1129 	PINGROUP(103, edp_hpd, NA, NA, NA, NA, NA, NA),
1130 	PINGROUP(104, spkr_i2s, NA, NA, NA, NA, NA, NA),
1131 	PINGROUP(105, NA, NA, NA, NA, NA, NA, NA),
1132 	PINGROUP(106, blsp_spi10_cs1, NA, NA, NA, NA, NA, NA),
1133 	PINGROUP(107, NA, NA, NA, NA, NA, NA, NA),
1134 	PINGROUP(108, NA, NA, NA, NA, NA, NA, NA),
1135 	PINGROUP(109, NA, NA, NA, NA, NA, NA, NA),
1136 	PINGROUP(110, gp_pdm2, NA, NA, NA, NA, NA, NA),
1137 	PINGROUP(111, blsp_spi10_cs2, NA, NA, NA, NA, NA, NA),
1138 	PINGROUP(112, NA, NA, NA, NA, NA, NA, NA),
1139 	PINGROUP(113, NA, NA, NA, NA, NA, NA, NA),
1140 	PINGROUP(114, NA, NA, NA, NA, NA, NA, NA),
1141 	PINGROUP(115, NA, NA, NA, NA, NA, NA, NA),
1142 	PINGROUP(116, blsp_spi1_cs1, NA, NA, NA, NA, NA, NA),
1143 	PINGROUP(117, blsp_spi1_cs2, NA, NA, NA, NA, NA, NA),
1144 	PINGROUP(118, blsp_spi1_cs3, NA, NA, NA, NA, NA, NA),
1145 	PINGROUP(119, cci_timer4, cci_async, sata_devsleep, sata_devsleep_n, NA, NA, NA),
1146 	PINGROUP(120, cci_async, NA, NA, NA, NA, NA, NA),
1147 	PINGROUP(121, NA, NA, NA, NA, NA, NA, NA),
1148 	PINGROUP(122, NA, NA, NA, NA, NA, NA, NA),
1149 	PINGROUP(123, hdmi_dtest, NA, NA, NA, NA, NA, NA),
1150 	PINGROUP(124, spdif_tx, ldo_en, NA, NA, NA, NA, NA),
1151 	PINGROUP(125, ldo_update, hdmi_rcv, NA, NA, NA, NA, NA),
1152 	PINGROUP(126, gcc_vtt, NA, NA, NA, NA, NA, NA),
1153 	PINGROUP(127, gcc_obt, NA, NA, NA, NA, NA, NA),
1154 	PINGROUP(128, blsp_spi10_cs3, NA, NA, NA, NA, NA, NA),
1155 	PINGROUP(129, sata_act, NA, NA, NA, NA, NA, NA),
1156 	PINGROUP(130, uim, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA),
1157 	PINGROUP(131, uim, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA),
1158 	PINGROUP(132, uim, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA),
1159 	PINGROUP(133, uim, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA),
1160 	PINGROUP(134, hsic, NA, NA, NA, NA, NA, NA),
1161 	PINGROUP(135, hsic, NA, NA, NA, NA, NA, NA),
1162 	PINGROUP(136, spdif_tx, NA, NA, NA, NA, NA, NA),
1163 	PINGROUP(137, NA, NA, NA, NA, NA, NA, NA),
1164 	PINGROUP(138, NA, NA, NA, NA, NA, NA, NA),
1165 	PINGROUP(139, NA, NA, NA, NA, NA, NA, NA),
1166 	PINGROUP(140, pci_e1_rst_n, pci_e1_rst, NA, NA, NA, NA, NA),
1167 	PINGROUP(141, pci_e1_clkreq_n, NA, NA, NA, NA, NA, NA),
1168 	PINGROUP(142, spdif_tx, NA, NA, NA, NA, NA, NA),
1169 	PINGROUP(143, NA, NA, NA, NA, NA, NA, NA),
1170 	PINGROUP(144, NA, NA, NA, NA, NA, NA, NA),
1171 	PINGROUP(145, NA, NA, NA, NA, NA, NA, NA),
1172 	PINGROUP(146, sdc_emmc_mode, NA, NA, NA, NA, NA, NA),
1173 
1174 	SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6),
1175 	SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3),
1176 	SDC_PINGROUP(sdc1_data, 0x2044, 9, 0),
1177 	SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6),
1178 	SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3),
1179 	SDC_PINGROUP(sdc2_data, 0x2048, 9, 0),
1180 };
1181 
1182 #define NUM_GPIO_PINGROUPS 147
1183 
1184 static const struct msm_pinctrl_soc_data apq8084_pinctrl = {
1185 	.pins = apq8084_pins,
1186 	.npins = ARRAY_SIZE(apq8084_pins),
1187 	.functions = apq8084_functions,
1188 	.nfunctions = ARRAY_SIZE(apq8084_functions),
1189 	.groups = apq8084_groups,
1190 	.ngroups = ARRAY_SIZE(apq8084_groups),
1191 	.ngpios = NUM_GPIO_PINGROUPS,
1192 };
1193 
1194 static int apq8084_pinctrl_probe(struct platform_device *pdev)
1195 {
1196 	return msm_pinctrl_probe(pdev, &apq8084_pinctrl);
1197 }
1198 
1199 static const struct of_device_id apq8084_pinctrl_of_match[] = {
1200 	{ .compatible = "qcom,apq8084-pinctrl", },
1201 	{ },
1202 };
1203 
1204 static struct platform_driver apq8084_pinctrl_driver = {
1205 	.driver = {
1206 		.name = "apq8084-pinctrl",
1207 		.of_match_table = apq8084_pinctrl_of_match,
1208 	},
1209 	.probe = apq8084_pinctrl_probe,
1210 	.remove = msm_pinctrl_remove,
1211 };
1212 
1213 static int __init apq8084_pinctrl_init(void)
1214 {
1215 	return platform_driver_register(&apq8084_pinctrl_driver);
1216 }
1217 arch_initcall(apq8084_pinctrl_init);
1218 
1219 static void __exit apq8084_pinctrl_exit(void)
1220 {
1221 	platform_driver_unregister(&apq8084_pinctrl_driver);
1222 }
1223 module_exit(apq8084_pinctrl_exit);
1224 
1225 MODULE_DESCRIPTION("Qualcomm APQ8084 pinctrl driver");
1226 MODULE_LICENSE("GPL v2");
1227 MODULE_DEVICE_TABLE(of, apq8084_pinctrl_of_match);
1228