1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2019, The Linux Foundation. All rights reserved. 3 4 #include <linux/module.h> 5 #include <linux/of.h> 6 #include <linux/platform_device.h> 7 #include <linux/pinctrl/pinctrl.h> 8 9 #include "pinctrl-msm.h" 10 11 static const char * const sc7180_tiles[] = { 12 "north", 13 "south", 14 "west", 15 }; 16 17 enum { 18 NORTH, 19 SOUTH, 20 WEST 21 }; 22 23 #define FUNCTION(fname) \ 24 [msm_mux_##fname] = { \ 25 .name = #fname, \ 26 .groups = fname##_groups, \ 27 .ngroups = ARRAY_SIZE(fname##_groups), \ 28 } 29 30 #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ 31 { \ 32 .name = "gpio" #id, \ 33 .pins = gpio##id##_pins, \ 34 .npins = ARRAY_SIZE(gpio##id##_pins), \ 35 .funcs = (int[]){ \ 36 msm_mux_gpio, /* gpio mode */ \ 37 msm_mux_##f1, \ 38 msm_mux_##f2, \ 39 msm_mux_##f3, \ 40 msm_mux_##f4, \ 41 msm_mux_##f5, \ 42 msm_mux_##f6, \ 43 msm_mux_##f7, \ 44 msm_mux_##f8, \ 45 msm_mux_##f9 \ 46 }, \ 47 .nfuncs = 10, \ 48 .ctl_reg = 0x1000 * id, \ 49 .io_reg = 0x1000 * id + 0x4, \ 50 .intr_cfg_reg = 0x1000 * id + 0x8, \ 51 .intr_status_reg = 0x1000 * id + 0xc, \ 52 .intr_target_reg = 0x1000 * id + 0x8, \ 53 .tile = _tile, \ 54 .mux_bit = 2, \ 55 .pull_bit = 0, \ 56 .drv_bit = 6, \ 57 .oe_bit = 9, \ 58 .in_bit = 0, \ 59 .out_bit = 1, \ 60 .intr_enable_bit = 0, \ 61 .intr_status_bit = 0, \ 62 .intr_target_bit = 5, \ 63 .intr_target_kpss_val = 3, \ 64 .intr_raw_status_bit = 4, \ 65 .intr_polarity_bit = 1, \ 66 .intr_detection_bit = 2, \ 67 .intr_detection_width = 2, \ 68 } 69 70 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ 71 { \ 72 .name = #pg_name, \ 73 .pins = pg_name##_pins, \ 74 .npins = ARRAY_SIZE(pg_name##_pins), \ 75 .ctl_reg = ctl, \ 76 .io_reg = 0, \ 77 .intr_cfg_reg = 0, \ 78 .intr_status_reg = 0, \ 79 .intr_target_reg = 0, \ 80 .mux_bit = -1, \ 81 .pull_bit = pull, \ 82 .drv_bit = drv, \ 83 .oe_bit = -1, \ 84 .in_bit = -1, \ 85 .out_bit = -1, \ 86 .intr_enable_bit = -1, \ 87 .intr_status_bit = -1, \ 88 .intr_target_bit = -1, \ 89 .intr_raw_status_bit = -1, \ 90 .intr_polarity_bit = -1, \ 91 .intr_detection_bit = -1, \ 92 .intr_detection_width = -1, \ 93 } 94 95 #define UFS_RESET(pg_name, offset) \ 96 { \ 97 .name = #pg_name, \ 98 .pins = pg_name##_pins, \ 99 .npins = ARRAY_SIZE(pg_name##_pins), \ 100 .ctl_reg = offset, \ 101 .io_reg = offset + 0x4, \ 102 .intr_cfg_reg = 0, \ 103 .intr_status_reg = 0, \ 104 .intr_target_reg = 0, \ 105 .mux_bit = -1, \ 106 .pull_bit = 3, \ 107 .drv_bit = 0, \ 108 .oe_bit = -1, \ 109 .in_bit = -1, \ 110 .out_bit = 0, \ 111 .intr_enable_bit = -1, \ 112 .intr_status_bit = -1, \ 113 .intr_target_bit = -1, \ 114 .intr_raw_status_bit = -1, \ 115 .intr_polarity_bit = -1, \ 116 .intr_detection_bit = -1, \ 117 .intr_detection_width = -1, \ 118 } 119 static const struct pinctrl_pin_desc sc7180_pins[] = { 120 PINCTRL_PIN(0, "GPIO_0"), 121 PINCTRL_PIN(1, "GPIO_1"), 122 PINCTRL_PIN(2, "GPIO_2"), 123 PINCTRL_PIN(3, "GPIO_3"), 124 PINCTRL_PIN(4, "GPIO_4"), 125 PINCTRL_PIN(5, "GPIO_5"), 126 PINCTRL_PIN(6, "GPIO_6"), 127 PINCTRL_PIN(7, "GPIO_7"), 128 PINCTRL_PIN(8, "GPIO_8"), 129 PINCTRL_PIN(9, "GPIO_9"), 130 PINCTRL_PIN(10, "GPIO_10"), 131 PINCTRL_PIN(11, "GPIO_11"), 132 PINCTRL_PIN(12, "GPIO_12"), 133 PINCTRL_PIN(13, "GPIO_13"), 134 PINCTRL_PIN(14, "GPIO_14"), 135 PINCTRL_PIN(15, "GPIO_15"), 136 PINCTRL_PIN(16, "GPIO_16"), 137 PINCTRL_PIN(17, "GPIO_17"), 138 PINCTRL_PIN(18, "GPIO_18"), 139 PINCTRL_PIN(19, "GPIO_19"), 140 PINCTRL_PIN(20, "GPIO_20"), 141 PINCTRL_PIN(21, "GPIO_21"), 142 PINCTRL_PIN(22, "GPIO_22"), 143 PINCTRL_PIN(23, "GPIO_23"), 144 PINCTRL_PIN(24, "GPIO_24"), 145 PINCTRL_PIN(25, "GPIO_25"), 146 PINCTRL_PIN(26, "GPIO_26"), 147 PINCTRL_PIN(27, "GPIO_27"), 148 PINCTRL_PIN(28, "GPIO_28"), 149 PINCTRL_PIN(29, "GPIO_29"), 150 PINCTRL_PIN(30, "GPIO_30"), 151 PINCTRL_PIN(31, "GPIO_31"), 152 PINCTRL_PIN(32, "GPIO_32"), 153 PINCTRL_PIN(33, "GPIO_33"), 154 PINCTRL_PIN(34, "GPIO_34"), 155 PINCTRL_PIN(35, "GPIO_35"), 156 PINCTRL_PIN(36, "GPIO_36"), 157 PINCTRL_PIN(37, "GPIO_37"), 158 PINCTRL_PIN(38, "GPIO_38"), 159 PINCTRL_PIN(39, "GPIO_39"), 160 PINCTRL_PIN(40, "GPIO_40"), 161 PINCTRL_PIN(41, "GPIO_41"), 162 PINCTRL_PIN(42, "GPIO_42"), 163 PINCTRL_PIN(43, "GPIO_43"), 164 PINCTRL_PIN(44, "GPIO_44"), 165 PINCTRL_PIN(45, "GPIO_45"), 166 PINCTRL_PIN(46, "GPIO_46"), 167 PINCTRL_PIN(47, "GPIO_47"), 168 PINCTRL_PIN(48, "GPIO_48"), 169 PINCTRL_PIN(49, "GPIO_49"), 170 PINCTRL_PIN(50, "GPIO_50"), 171 PINCTRL_PIN(51, "GPIO_51"), 172 PINCTRL_PIN(52, "GPIO_52"), 173 PINCTRL_PIN(53, "GPIO_53"), 174 PINCTRL_PIN(54, "GPIO_54"), 175 PINCTRL_PIN(55, "GPIO_55"), 176 PINCTRL_PIN(56, "GPIO_56"), 177 PINCTRL_PIN(57, "GPIO_57"), 178 PINCTRL_PIN(58, "GPIO_58"), 179 PINCTRL_PIN(59, "GPIO_59"), 180 PINCTRL_PIN(60, "GPIO_60"), 181 PINCTRL_PIN(61, "GPIO_61"), 182 PINCTRL_PIN(62, "GPIO_62"), 183 PINCTRL_PIN(63, "GPIO_63"), 184 PINCTRL_PIN(64, "GPIO_64"), 185 PINCTRL_PIN(65, "GPIO_65"), 186 PINCTRL_PIN(66, "GPIO_66"), 187 PINCTRL_PIN(67, "GPIO_67"), 188 PINCTRL_PIN(68, "GPIO_68"), 189 PINCTRL_PIN(69, "GPIO_69"), 190 PINCTRL_PIN(70, "GPIO_70"), 191 PINCTRL_PIN(71, "GPIO_71"), 192 PINCTRL_PIN(72, "GPIO_72"), 193 PINCTRL_PIN(73, "GPIO_73"), 194 PINCTRL_PIN(74, "GPIO_74"), 195 PINCTRL_PIN(75, "GPIO_75"), 196 PINCTRL_PIN(76, "GPIO_76"), 197 PINCTRL_PIN(77, "GPIO_77"), 198 PINCTRL_PIN(78, "GPIO_78"), 199 PINCTRL_PIN(79, "GPIO_79"), 200 PINCTRL_PIN(80, "GPIO_80"), 201 PINCTRL_PIN(81, "GPIO_81"), 202 PINCTRL_PIN(82, "GPIO_82"), 203 PINCTRL_PIN(83, "GPIO_83"), 204 PINCTRL_PIN(84, "GPIO_84"), 205 PINCTRL_PIN(85, "GPIO_85"), 206 PINCTRL_PIN(86, "GPIO_86"), 207 PINCTRL_PIN(87, "GPIO_87"), 208 PINCTRL_PIN(88, "GPIO_88"), 209 PINCTRL_PIN(89, "GPIO_89"), 210 PINCTRL_PIN(90, "GPIO_90"), 211 PINCTRL_PIN(91, "GPIO_91"), 212 PINCTRL_PIN(92, "GPIO_92"), 213 PINCTRL_PIN(93, "GPIO_93"), 214 PINCTRL_PIN(94, "GPIO_94"), 215 PINCTRL_PIN(95, "GPIO_95"), 216 PINCTRL_PIN(96, "GPIO_96"), 217 PINCTRL_PIN(97, "GPIO_97"), 218 PINCTRL_PIN(98, "GPIO_98"), 219 PINCTRL_PIN(99, "GPIO_99"), 220 PINCTRL_PIN(100, "GPIO_100"), 221 PINCTRL_PIN(101, "GPIO_101"), 222 PINCTRL_PIN(102, "GPIO_102"), 223 PINCTRL_PIN(103, "GPIO_103"), 224 PINCTRL_PIN(104, "GPIO_104"), 225 PINCTRL_PIN(105, "GPIO_105"), 226 PINCTRL_PIN(106, "GPIO_106"), 227 PINCTRL_PIN(107, "GPIO_107"), 228 PINCTRL_PIN(108, "GPIO_108"), 229 PINCTRL_PIN(109, "GPIO_109"), 230 PINCTRL_PIN(110, "GPIO_110"), 231 PINCTRL_PIN(111, "GPIO_111"), 232 PINCTRL_PIN(112, "GPIO_112"), 233 PINCTRL_PIN(113, "GPIO_113"), 234 PINCTRL_PIN(114, "GPIO_114"), 235 PINCTRL_PIN(115, "GPIO_115"), 236 PINCTRL_PIN(116, "GPIO_116"), 237 PINCTRL_PIN(117, "GPIO_117"), 238 PINCTRL_PIN(118, "GPIO_118"), 239 PINCTRL_PIN(119, "UFS_RESET"), 240 PINCTRL_PIN(120, "SDC1_RCLK"), 241 PINCTRL_PIN(121, "SDC1_CLK"), 242 PINCTRL_PIN(122, "SDC1_CMD"), 243 PINCTRL_PIN(123, "SDC1_DATA"), 244 PINCTRL_PIN(124, "SDC2_CLK"), 245 PINCTRL_PIN(125, "SDC2_CMD"), 246 PINCTRL_PIN(126, "SDC2_DATA"), 247 }; 248 249 #define DECLARE_MSM_GPIO_PINS(pin) \ 250 static const unsigned int gpio##pin##_pins[] = { pin } 251 DECLARE_MSM_GPIO_PINS(0); 252 DECLARE_MSM_GPIO_PINS(1); 253 DECLARE_MSM_GPIO_PINS(2); 254 DECLARE_MSM_GPIO_PINS(3); 255 DECLARE_MSM_GPIO_PINS(4); 256 DECLARE_MSM_GPIO_PINS(5); 257 DECLARE_MSM_GPIO_PINS(6); 258 DECLARE_MSM_GPIO_PINS(7); 259 DECLARE_MSM_GPIO_PINS(8); 260 DECLARE_MSM_GPIO_PINS(9); 261 DECLARE_MSM_GPIO_PINS(10); 262 DECLARE_MSM_GPIO_PINS(11); 263 DECLARE_MSM_GPIO_PINS(12); 264 DECLARE_MSM_GPIO_PINS(13); 265 DECLARE_MSM_GPIO_PINS(14); 266 DECLARE_MSM_GPIO_PINS(15); 267 DECLARE_MSM_GPIO_PINS(16); 268 DECLARE_MSM_GPIO_PINS(17); 269 DECLARE_MSM_GPIO_PINS(18); 270 DECLARE_MSM_GPIO_PINS(19); 271 DECLARE_MSM_GPIO_PINS(20); 272 DECLARE_MSM_GPIO_PINS(21); 273 DECLARE_MSM_GPIO_PINS(22); 274 DECLARE_MSM_GPIO_PINS(23); 275 DECLARE_MSM_GPIO_PINS(24); 276 DECLARE_MSM_GPIO_PINS(25); 277 DECLARE_MSM_GPIO_PINS(26); 278 DECLARE_MSM_GPIO_PINS(27); 279 DECLARE_MSM_GPIO_PINS(28); 280 DECLARE_MSM_GPIO_PINS(29); 281 DECLARE_MSM_GPIO_PINS(30); 282 DECLARE_MSM_GPIO_PINS(31); 283 DECLARE_MSM_GPIO_PINS(32); 284 DECLARE_MSM_GPIO_PINS(33); 285 DECLARE_MSM_GPIO_PINS(34); 286 DECLARE_MSM_GPIO_PINS(35); 287 DECLARE_MSM_GPIO_PINS(36); 288 DECLARE_MSM_GPIO_PINS(37); 289 DECLARE_MSM_GPIO_PINS(38); 290 DECLARE_MSM_GPIO_PINS(39); 291 DECLARE_MSM_GPIO_PINS(40); 292 DECLARE_MSM_GPIO_PINS(41); 293 DECLARE_MSM_GPIO_PINS(42); 294 DECLARE_MSM_GPIO_PINS(43); 295 DECLARE_MSM_GPIO_PINS(44); 296 DECLARE_MSM_GPIO_PINS(45); 297 DECLARE_MSM_GPIO_PINS(46); 298 DECLARE_MSM_GPIO_PINS(47); 299 DECLARE_MSM_GPIO_PINS(48); 300 DECLARE_MSM_GPIO_PINS(49); 301 DECLARE_MSM_GPIO_PINS(50); 302 DECLARE_MSM_GPIO_PINS(51); 303 DECLARE_MSM_GPIO_PINS(52); 304 DECLARE_MSM_GPIO_PINS(53); 305 DECLARE_MSM_GPIO_PINS(54); 306 DECLARE_MSM_GPIO_PINS(55); 307 DECLARE_MSM_GPIO_PINS(56); 308 DECLARE_MSM_GPIO_PINS(57); 309 DECLARE_MSM_GPIO_PINS(58); 310 DECLARE_MSM_GPIO_PINS(59); 311 DECLARE_MSM_GPIO_PINS(60); 312 DECLARE_MSM_GPIO_PINS(61); 313 DECLARE_MSM_GPIO_PINS(62); 314 DECLARE_MSM_GPIO_PINS(63); 315 DECLARE_MSM_GPIO_PINS(64); 316 DECLARE_MSM_GPIO_PINS(65); 317 DECLARE_MSM_GPIO_PINS(66); 318 DECLARE_MSM_GPIO_PINS(67); 319 DECLARE_MSM_GPIO_PINS(68); 320 DECLARE_MSM_GPIO_PINS(69); 321 DECLARE_MSM_GPIO_PINS(70); 322 DECLARE_MSM_GPIO_PINS(71); 323 DECLARE_MSM_GPIO_PINS(72); 324 DECLARE_MSM_GPIO_PINS(73); 325 DECLARE_MSM_GPIO_PINS(74); 326 DECLARE_MSM_GPIO_PINS(75); 327 DECLARE_MSM_GPIO_PINS(76); 328 DECLARE_MSM_GPIO_PINS(77); 329 DECLARE_MSM_GPIO_PINS(78); 330 DECLARE_MSM_GPIO_PINS(79); 331 DECLARE_MSM_GPIO_PINS(80); 332 DECLARE_MSM_GPIO_PINS(81); 333 DECLARE_MSM_GPIO_PINS(82); 334 DECLARE_MSM_GPIO_PINS(83); 335 DECLARE_MSM_GPIO_PINS(84); 336 DECLARE_MSM_GPIO_PINS(85); 337 DECLARE_MSM_GPIO_PINS(86); 338 DECLARE_MSM_GPIO_PINS(87); 339 DECLARE_MSM_GPIO_PINS(88); 340 DECLARE_MSM_GPIO_PINS(89); 341 DECLARE_MSM_GPIO_PINS(90); 342 DECLARE_MSM_GPIO_PINS(91); 343 DECLARE_MSM_GPIO_PINS(92); 344 DECLARE_MSM_GPIO_PINS(93); 345 DECLARE_MSM_GPIO_PINS(94); 346 DECLARE_MSM_GPIO_PINS(95); 347 DECLARE_MSM_GPIO_PINS(96); 348 DECLARE_MSM_GPIO_PINS(97); 349 DECLARE_MSM_GPIO_PINS(98); 350 DECLARE_MSM_GPIO_PINS(99); 351 DECLARE_MSM_GPIO_PINS(100); 352 DECLARE_MSM_GPIO_PINS(101); 353 DECLARE_MSM_GPIO_PINS(102); 354 DECLARE_MSM_GPIO_PINS(103); 355 DECLARE_MSM_GPIO_PINS(104); 356 DECLARE_MSM_GPIO_PINS(105); 357 DECLARE_MSM_GPIO_PINS(106); 358 DECLARE_MSM_GPIO_PINS(107); 359 DECLARE_MSM_GPIO_PINS(108); 360 DECLARE_MSM_GPIO_PINS(109); 361 DECLARE_MSM_GPIO_PINS(110); 362 DECLARE_MSM_GPIO_PINS(111); 363 DECLARE_MSM_GPIO_PINS(112); 364 DECLARE_MSM_GPIO_PINS(113); 365 DECLARE_MSM_GPIO_PINS(114); 366 DECLARE_MSM_GPIO_PINS(115); 367 DECLARE_MSM_GPIO_PINS(116); 368 DECLARE_MSM_GPIO_PINS(117); 369 DECLARE_MSM_GPIO_PINS(118); 370 371 static const unsigned int ufs_reset_pins[] = { 119 }; 372 static const unsigned int sdc1_rclk_pins[] = { 120 }; 373 static const unsigned int sdc1_clk_pins[] = { 121 }; 374 static const unsigned int sdc1_cmd_pins[] = { 122 }; 375 static const unsigned int sdc1_data_pins[] = { 123 }; 376 static const unsigned int sdc2_clk_pins[] = { 124 }; 377 static const unsigned int sdc2_cmd_pins[] = { 125 }; 378 static const unsigned int sdc2_data_pins[] = { 126 }; 379 380 enum sc7180_functions { 381 msm_mux_adsp_ext, 382 msm_mux_agera_pll, 383 msm_mux_aoss_cti, 384 msm_mux_atest_char, 385 msm_mux_atest_char0, 386 msm_mux_atest_char1, 387 msm_mux_atest_char2, 388 msm_mux_atest_char3, 389 msm_mux_atest_tsens, 390 msm_mux_atest_tsens2, 391 msm_mux_atest_usb1, 392 msm_mux_atest_usb2, 393 msm_mux_atest_usb10, 394 msm_mux_atest_usb11, 395 msm_mux_atest_usb12, 396 msm_mux_atest_usb13, 397 msm_mux_atest_usb20, 398 msm_mux_atest_usb21, 399 msm_mux_atest_usb22, 400 msm_mux_atest_usb23, 401 msm_mux_audio_ref, 402 msm_mux_btfm_slimbus, 403 msm_mux_cam_mclk, 404 msm_mux_cci_async, 405 msm_mux_cci_i2c, 406 msm_mux_cci_timer0, 407 msm_mux_cci_timer1, 408 msm_mux_cci_timer2, 409 msm_mux_cci_timer3, 410 msm_mux_cci_timer4, 411 msm_mux_cri_trng, 412 msm_mux_dbg_out, 413 msm_mux_ddr_bist, 414 msm_mux_ddr_pxi0, 415 msm_mux_ddr_pxi1, 416 msm_mux_ddr_pxi2, 417 msm_mux_ddr_pxi3, 418 msm_mux_dp_hot, 419 msm_mux_edp_lcd, 420 msm_mux_gcc_gp1, 421 msm_mux_gcc_gp2, 422 msm_mux_gcc_gp3, 423 msm_mux_gpio, 424 msm_mux_gp_pdm0, 425 msm_mux_gp_pdm1, 426 msm_mux_gp_pdm2, 427 msm_mux_gps_tx, 428 msm_mux_jitter_bist, 429 msm_mux_ldo_en, 430 msm_mux_ldo_update, 431 msm_mux_lpass_ext, 432 msm_mux_mdp_vsync, 433 msm_mux_mdp_vsync0, 434 msm_mux_mdp_vsync1, 435 msm_mux_mdp_vsync2, 436 msm_mux_mdp_vsync3, 437 msm_mux_mi2s_1, 438 msm_mux_mi2s_0, 439 msm_mux_mi2s_2, 440 msm_mux_mss_lte, 441 msm_mux_m_voc, 442 msm_mux_pa_indicator, 443 msm_mux_phase_flag, 444 msm_mux_PLL_BIST, 445 msm_mux_pll_bypassnl, 446 msm_mux_pll_reset, 447 msm_mux_prng_rosc, 448 msm_mux_qdss, 449 msm_mux_qdss_cti, 450 msm_mux_qlink_enable, 451 msm_mux_qlink_request, 452 msm_mux_qspi_clk, 453 msm_mux_qspi_cs, 454 msm_mux_qspi_data, 455 msm_mux_qup00, 456 msm_mux_qup01, 457 msm_mux_qup02, 458 msm_mux_qup03, 459 msm_mux_qup04, 460 msm_mux_qup05, 461 msm_mux_qup10, 462 msm_mux_qup11, 463 msm_mux_qup12, 464 msm_mux_qup13, 465 msm_mux_qup14, 466 msm_mux_qup15, 467 msm_mux_sdc1_tb, 468 msm_mux_sdc2_tb, 469 msm_mux_sd_write, 470 msm_mux_sp_cmu, 471 msm_mux_tgu_ch0, 472 msm_mux_tgu_ch1, 473 msm_mux_tgu_ch2, 474 msm_mux_tgu_ch3, 475 msm_mux_tsense_pwm1, 476 msm_mux_tsense_pwm2, 477 msm_mux_uim1, 478 msm_mux_uim2, 479 msm_mux_uim_batt, 480 msm_mux_usb_phy, 481 msm_mux_vfr_1, 482 msm_mux__V_GPIO, 483 msm_mux__V_PPS_IN, 484 msm_mux__V_PPS_OUT, 485 msm_mux_vsense_trigger, 486 msm_mux_wlan1_adc0, 487 msm_mux_wlan1_adc1, 488 msm_mux_wlan2_adc0, 489 msm_mux_wlan2_adc1, 490 msm_mux__, 491 }; 492 493 static const char * const qup01_groups[] = { 494 "gpio0", "gpio1", "gpio2", "gpio3", "gpio12", "gpio94", 495 }; 496 static const char * const gpio_groups[] = { 497 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", 498 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", 499 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", 500 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", 501 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", 502 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", 503 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", 504 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", 505 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", 506 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", 507 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", 508 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", 509 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", 510 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", 511 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", 512 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", 513 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", 514 "gpio117", "gpio118", 515 }; 516 static const char * const phase_flag_groups[] = { 517 "gpio0", "gpio1", "gpio2", "gpio8", "gpio9", 518 "gpio11", "gpio12", "gpio17", "gpio18", "gpio19", 519 "gpio20", "gpio25", "gpio26", "gpio27", "gpio28", 520 "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", 521 "gpio37", "gpio38", "gpio39", "gpio42", "gpio44", 522 "gpio56", "gpio57", "gpio58", "gpio63", "gpio64", 523 "gpio108", "gpio109", 524 }; 525 static const char * const cri_trng_groups[] = { 526 "gpio0", "gpio1", "gpio2", 527 }; 528 static const char * const sp_cmu_groups[] = { 529 "gpio3", 530 }; 531 static const char * const dbg_out_groups[] = { 532 "gpio3", 533 }; 534 static const char * const qdss_cti_groups[] = { 535 "gpio3", "gpio4", "gpio8", "gpio9", "gpio33", "gpio44", "gpio45", 536 "gpio72", 537 }; 538 static const char * const sdc1_tb_groups[] = { 539 "gpio4", 540 }; 541 static const char * const sdc2_tb_groups[] = { 542 "gpio5", 543 }; 544 static const char * const qup11_groups[] = { 545 "gpio6", "gpio7", 546 }; 547 static const char * const ddr_bist_groups[] = { 548 "gpio7", "gpio8", "gpio9", "gpio10", 549 }; 550 static const char * const gp_pdm1_groups[] = { 551 "gpio8", "gpio50", 552 }; 553 static const char * const mdp_vsync_groups[] = { 554 "gpio10", "gpio11", "gpio12", "gpio70", "gpio71", 555 }; 556 static const char * const edp_lcd_groups[] = { 557 "gpio11", 558 }; 559 static const char * const ddr_pxi2_groups[] = { 560 "gpio11", "gpio26", 561 }; 562 static const char * const m_voc_groups[] = { 563 "gpio12", 564 }; 565 static const char * const wlan2_adc0_groups[] = { 566 "gpio12", 567 }; 568 static const char * const atest_usb10_groups[] = { 569 "gpio12", 570 }; 571 static const char * const ddr_pxi3_groups[] = { 572 "gpio12", "gpio108", 573 }; 574 static const char * const cam_mclk_groups[] = { 575 "gpio13", "gpio14", "gpio15", "gpio16", "gpio23", 576 }; 577 static const char * const pll_bypassnl_groups[] = { 578 "gpio13", 579 }; 580 static const char * const qdss_groups[] = { 581 "gpio13", "gpio86", "gpio14", "gpio87", 582 "gpio15", "gpio88", "gpio16", "gpio89", 583 "gpio17", "gpio90", "gpio18", "gpio91", 584 "gpio19", "gpio21", "gpio20", "gpio22", 585 "gpio23", "gpio54", "gpio24", "gpio36", 586 "gpio25", "gpio57", "gpio26", "gpio31", 587 "gpio27", "gpio56", "gpio28", "gpio29", 588 "gpio30", "gpio35", "gpio93", "gpio104", 589 "gpio34", "gpio53", "gpio37", "gpio55", 590 }; 591 static const char * const pll_reset_groups[] = { 592 "gpio14", 593 }; 594 static const char * const qup02_groups[] = { 595 "gpio15", "gpio16", 596 }; 597 static const char * const cci_i2c_groups[] = { 598 "gpio17", "gpio18", "gpio19", "gpio20", "gpio27", "gpio28", 599 }; 600 static const char * const wlan1_adc0_groups[] = { 601 "gpio17", 602 }; 603 static const char * const atest_usb12_groups[] = { 604 "gpio17", 605 }; 606 static const char * const ddr_pxi1_groups[] = { 607 "gpio17", "gpio44", 608 }; 609 static const char * const atest_char_groups[] = { 610 "gpio17", 611 }; 612 static const char * const agera_pll_groups[] = { 613 "gpio18", 614 }; 615 static const char * const vsense_trigger_groups[] = { 616 "gpio18", 617 }; 618 static const char * const ddr_pxi0_groups[] = { 619 "gpio18", "gpio27", 620 }; 621 static const char * const atest_char3_groups[] = { 622 "gpio18", 623 }; 624 static const char * const atest_char2_groups[] = { 625 "gpio19", 626 }; 627 static const char * const atest_char1_groups[] = { 628 "gpio20", 629 }; 630 static const char * const cci_timer0_groups[] = { 631 "gpio21", 632 }; 633 static const char * const gcc_gp2_groups[] = { 634 "gpio21", 635 }; 636 static const char * const atest_char0_groups[] = { 637 "gpio21", 638 }; 639 static const char * const cci_timer1_groups[] = { 640 "gpio22", 641 }; 642 static const char * const gcc_gp3_groups[] = { 643 "gpio22", 644 }; 645 static const char * const cci_timer2_groups[] = { 646 "gpio23", 647 }; 648 static const char * const cci_timer3_groups[] = { 649 "gpio24", 650 }; 651 static const char * const cci_async_groups[] = { 652 "gpio24", "gpio25", "gpio26", 653 }; 654 static const char * const cci_timer4_groups[] = { 655 "gpio25", 656 }; 657 static const char * const qup05_groups[] = { 658 "gpio25", "gpio26", "gpio27", "gpio28", 659 }; 660 static const char * const atest_tsens_groups[] = { 661 "gpio26", 662 }; 663 static const char * const atest_usb11_groups[] = { 664 "gpio26", 665 }; 666 static const char * const PLL_BIST_groups[] = { 667 "gpio27", 668 }; 669 static const char * const sd_write_groups[] = { 670 "gpio33", 671 }; 672 static const char * const qup00_groups[] = { 673 "gpio34", "gpio35", "gpio36", "gpio37", 674 }; 675 static const char * const gp_pdm0_groups[] = { 676 "gpio37", "gpio68", 677 }; 678 static const char * const qup03_groups[] = { 679 "gpio38", "gpio39", "gpio40", "gpio41", 680 }; 681 static const char * const atest_tsens2_groups[] = { 682 "gpio39", 683 }; 684 static const char * const wlan2_adc1_groups[] = { 685 "gpio39", 686 }; 687 static const char * const atest_usb1_groups[] = { 688 "gpio39", 689 }; 690 static const char * const qup12_groups[] = { 691 "gpio42", "gpio43", "gpio44", "gpio45", 692 }; 693 static const char * const wlan1_adc1_groups[] = { 694 "gpio44", 695 }; 696 static const char * const atest_usb13_groups[] = { 697 "gpio44", 698 }; 699 static const char * const qup13_groups[] = { 700 "gpio46", "gpio47", 701 }; 702 static const char * const gcc_gp1_groups[] = { 703 "gpio48", "gpio56", 704 }; 705 static const char * const mi2s_1_groups[] = { 706 "gpio49", "gpio50", "gpio51", "gpio52", 707 }; 708 static const char * const btfm_slimbus_groups[] = { 709 "gpio49", "gpio50", "gpio51", "gpio52", 710 }; 711 static const char * const atest_usb2_groups[] = { 712 "gpio51", 713 }; 714 static const char * const atest_usb23_groups[] = { 715 "gpio52", 716 }; 717 static const char * const mi2s_0_groups[] = { 718 "gpio53", "gpio54", "gpio55", "gpio56", 719 }; 720 static const char * const qup15_groups[] = { 721 "gpio53", "gpio54", "gpio55", "gpio56", 722 }; 723 static const char * const atest_usb22_groups[] = { 724 "gpio53", 725 }; 726 static const char * const atest_usb21_groups[] = { 727 "gpio54", 728 }; 729 static const char * const atest_usb20_groups[] = { 730 "gpio55", 731 }; 732 static const char * const lpass_ext_groups[] = { 733 "gpio57", "gpio58", 734 }; 735 static const char * const audio_ref_groups[] = { 736 "gpio57", 737 }; 738 static const char * const jitter_bist_groups[] = { 739 "gpio57", 740 }; 741 static const char * const gp_pdm2_groups[] = { 742 "gpio57", 743 }; 744 static const char * const qup10_groups[] = { 745 "gpio59", "gpio60", "gpio61", "gpio62", "gpio68", "gpio72", 746 }; 747 static const char * const tgu_ch3_groups[] = { 748 "gpio62", 749 }; 750 static const char * const qspi_clk_groups[] = { 751 "gpio63", 752 }; 753 static const char * const mdp_vsync0_groups[] = { 754 "gpio63", 755 }; 756 static const char * const mi2s_2_groups[] = { 757 "gpio63", "gpio64", "gpio65", "gpio66", 758 }; 759 static const char * const mdp_vsync1_groups[] = { 760 "gpio63", 761 }; 762 static const char * const mdp_vsync2_groups[] = { 763 "gpio63", 764 }; 765 static const char * const mdp_vsync3_groups[] = { 766 "gpio63", 767 }; 768 static const char * const tgu_ch0_groups[] = { 769 "gpio63", 770 }; 771 static const char * const qspi_data_groups[] = { 772 "gpio64", "gpio65", "gpio66", "gpio67", 773 }; 774 static const char * const tgu_ch1_groups[] = { 775 "gpio64", 776 }; 777 static const char * const vfr_1_groups[] = { 778 "gpio65", 779 }; 780 static const char * const tgu_ch2_groups[] = { 781 "gpio65", 782 }; 783 static const char * const qspi_cs_groups[] = { 784 "gpio68", "gpio72", 785 }; 786 static const char * const ldo_en_groups[] = { 787 "gpio70", 788 }; 789 static const char * const ldo_update_groups[] = { 790 "gpio71", 791 }; 792 static const char * const prng_rosc_groups[] = { 793 "gpio72", 794 }; 795 static const char * const uim2_groups[] = { 796 "gpio75", "gpio76", "gpio77", "gpio78", 797 }; 798 static const char * const uim1_groups[] = { 799 "gpio79", "gpio80", "gpio81", "gpio82", 800 }; 801 static const char * const _V_GPIO_groups[] = { 802 "gpio83", "gpio84", "gpio107", 803 }; 804 static const char * const _V_PPS_IN_groups[] = { 805 "gpio83", "gpio84", "gpio107", 806 }; 807 static const char * const _V_PPS_OUT_groups[] = { 808 "gpio83", "gpio84", "gpio107", 809 }; 810 static const char * const gps_tx_groups[] = { 811 "gpio83", "gpio84", "gpio107", "gpio109", 812 }; 813 static const char * const uim_batt_groups[] = { 814 "gpio85", 815 }; 816 static const char * const dp_hot_groups[] = { 817 "gpio85", "gpio117", 818 }; 819 static const char * const aoss_cti_groups[] = { 820 "gpio85", 821 }; 822 static const char * const qup14_groups[] = { 823 "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", 824 }; 825 static const char * const adsp_ext_groups[] = { 826 "gpio87", 827 }; 828 static const char * const tsense_pwm1_groups[] = { 829 "gpio88", 830 }; 831 static const char * const tsense_pwm2_groups[] = { 832 "gpio88", 833 }; 834 static const char * const qlink_request_groups[] = { 835 "gpio96", 836 }; 837 static const char * const qlink_enable_groups[] = { 838 "gpio97", 839 }; 840 static const char * const pa_indicator_groups[] = { 841 "gpio99", 842 }; 843 static const char * const usb_phy_groups[] = { 844 "gpio104", 845 }; 846 static const char * const mss_lte_groups[] = { 847 "gpio108", "gpio109", 848 }; 849 static const char * const qup04_groups[] = { 850 "gpio115", "gpio116", 851 }; 852 853 static const struct msm_function sc7180_functions[] = { 854 FUNCTION(adsp_ext), 855 FUNCTION(agera_pll), 856 FUNCTION(aoss_cti), 857 FUNCTION(atest_char), 858 FUNCTION(atest_char0), 859 FUNCTION(atest_char1), 860 FUNCTION(atest_char2), 861 FUNCTION(atest_char3), 862 FUNCTION(atest_tsens), 863 FUNCTION(atest_tsens2), 864 FUNCTION(atest_usb1), 865 FUNCTION(atest_usb2), 866 FUNCTION(atest_usb10), 867 FUNCTION(atest_usb11), 868 FUNCTION(atest_usb12), 869 FUNCTION(atest_usb13), 870 FUNCTION(atest_usb20), 871 FUNCTION(atest_usb21), 872 FUNCTION(atest_usb22), 873 FUNCTION(atest_usb23), 874 FUNCTION(audio_ref), 875 FUNCTION(btfm_slimbus), 876 FUNCTION(cam_mclk), 877 FUNCTION(cci_async), 878 FUNCTION(cci_i2c), 879 FUNCTION(cci_timer0), 880 FUNCTION(cci_timer1), 881 FUNCTION(cci_timer2), 882 FUNCTION(cci_timer3), 883 FUNCTION(cci_timer4), 884 FUNCTION(cri_trng), 885 FUNCTION(dbg_out), 886 FUNCTION(ddr_bist), 887 FUNCTION(ddr_pxi0), 888 FUNCTION(ddr_pxi1), 889 FUNCTION(ddr_pxi2), 890 FUNCTION(ddr_pxi3), 891 FUNCTION(dp_hot), 892 FUNCTION(edp_lcd), 893 FUNCTION(gcc_gp1), 894 FUNCTION(gcc_gp2), 895 FUNCTION(gcc_gp3), 896 FUNCTION(gpio), 897 FUNCTION(gp_pdm0), 898 FUNCTION(gp_pdm1), 899 FUNCTION(gp_pdm2), 900 FUNCTION(gps_tx), 901 FUNCTION(jitter_bist), 902 FUNCTION(ldo_en), 903 FUNCTION(ldo_update), 904 FUNCTION(lpass_ext), 905 FUNCTION(mdp_vsync), 906 FUNCTION(mdp_vsync0), 907 FUNCTION(mdp_vsync1), 908 FUNCTION(mdp_vsync2), 909 FUNCTION(mdp_vsync3), 910 FUNCTION(mi2s_0), 911 FUNCTION(mi2s_1), 912 FUNCTION(mi2s_2), 913 FUNCTION(mss_lte), 914 FUNCTION(m_voc), 915 FUNCTION(pa_indicator), 916 FUNCTION(phase_flag), 917 FUNCTION(PLL_BIST), 918 FUNCTION(pll_bypassnl), 919 FUNCTION(pll_reset), 920 FUNCTION(prng_rosc), 921 FUNCTION(qdss), 922 FUNCTION(qdss_cti), 923 FUNCTION(qlink_enable), 924 FUNCTION(qlink_request), 925 FUNCTION(qspi_clk), 926 FUNCTION(qspi_cs), 927 FUNCTION(qspi_data), 928 FUNCTION(qup00), 929 FUNCTION(qup01), 930 FUNCTION(qup02), 931 FUNCTION(qup03), 932 FUNCTION(qup04), 933 FUNCTION(qup05), 934 FUNCTION(qup10), 935 FUNCTION(qup11), 936 FUNCTION(qup12), 937 FUNCTION(qup13), 938 FUNCTION(qup14), 939 FUNCTION(qup15), 940 FUNCTION(sdc1_tb), 941 FUNCTION(sdc2_tb), 942 FUNCTION(sd_write), 943 FUNCTION(sp_cmu), 944 FUNCTION(tgu_ch0), 945 FUNCTION(tgu_ch1), 946 FUNCTION(tgu_ch2), 947 FUNCTION(tgu_ch3), 948 FUNCTION(tsense_pwm1), 949 FUNCTION(tsense_pwm2), 950 FUNCTION(uim1), 951 FUNCTION(uim2), 952 FUNCTION(uim_batt), 953 FUNCTION(usb_phy), 954 FUNCTION(vfr_1), 955 FUNCTION(_V_GPIO), 956 FUNCTION(_V_PPS_IN), 957 FUNCTION(_V_PPS_OUT), 958 FUNCTION(vsense_trigger), 959 FUNCTION(wlan1_adc0), 960 FUNCTION(wlan1_adc1), 961 FUNCTION(wlan2_adc0), 962 FUNCTION(wlan2_adc1), 963 }; 964 965 /* Every pin is maintained as a single group, and missing or non-existing pin 966 * would be maintained as dummy group to synchronize pin group index with 967 * pin descriptor registered with pinctrl core. 968 * Clients would not be able to request these dummy pin groups. 969 */ 970 static const struct msm_pingroup sc7180_groups[] = { 971 [0] = PINGROUP(0, SOUTH, qup01, cri_trng, _, phase_flag, _, _, _, _, _), 972 [1] = PINGROUP(1, SOUTH, qup01, cri_trng, _, phase_flag, _, _, _, _, _), 973 [2] = PINGROUP(2, SOUTH, qup01, cri_trng, _, phase_flag, _, _, _, _, _), 974 [3] = PINGROUP(3, SOUTH, qup01, sp_cmu, dbg_out, qdss_cti, _, _, _, _, _), 975 [4] = PINGROUP(4, NORTH, sdc1_tb, _, qdss_cti, _, _, _, _, _, _), 976 [5] = PINGROUP(5, NORTH, sdc2_tb, _, _, _, _, _, _, _, _), 977 [6] = PINGROUP(6, NORTH, qup11, qup11, _, _, _, _, _, _, _), 978 [7] = PINGROUP(7, NORTH, qup11, qup11, ddr_bist, _, _, _, _, _, _), 979 [8] = PINGROUP(8, NORTH, gp_pdm1, ddr_bist, _, phase_flag, qdss_cti, _, _, _, _), 980 [9] = PINGROUP(9, NORTH, ddr_bist, _, phase_flag, qdss_cti, _, _, _, _, _), 981 [10] = PINGROUP(10, NORTH, mdp_vsync, ddr_bist, _, _, _, _, _, _, _), 982 [11] = PINGROUP(11, NORTH, mdp_vsync, edp_lcd, _, phase_flag, ddr_pxi2, _, _, _, _), 983 [12] = PINGROUP(12, SOUTH, mdp_vsync, m_voc, qup01, _, phase_flag, wlan2_adc0, atest_usb10, ddr_pxi3, _), 984 [13] = PINGROUP(13, SOUTH, cam_mclk, pll_bypassnl, qdss, _, _, _, _, _, _), 985 [14] = PINGROUP(14, SOUTH, cam_mclk, pll_reset, qdss, _, _, _, _, _, _), 986 [15] = PINGROUP(15, SOUTH, cam_mclk, qup02, qup02, qdss, _, _, _, _, _), 987 [16] = PINGROUP(16, SOUTH, cam_mclk, qup02, qup02, qdss, _, _, _, _, _), 988 [17] = PINGROUP(17, SOUTH, cci_i2c, _, phase_flag, qdss, _, wlan1_adc0, atest_usb12, ddr_pxi1, atest_char), 989 [18] = PINGROUP(18, SOUTH, cci_i2c, agera_pll, _, phase_flag, qdss, vsense_trigger, ddr_pxi0, atest_char3, _), 990 [19] = PINGROUP(19, SOUTH, cci_i2c, _, phase_flag, qdss, atest_char2, _, _, _, _), 991 [20] = PINGROUP(20, SOUTH, cci_i2c, _, phase_flag, qdss, atest_char1, _, _, _, _), 992 [21] = PINGROUP(21, NORTH, cci_timer0, gcc_gp2, _, qdss, atest_char0, _, _, _, _), 993 [22] = PINGROUP(22, NORTH, cci_timer1, gcc_gp3, _, qdss, _, _, _, _, _), 994 [23] = PINGROUP(23, SOUTH, cci_timer2, cam_mclk, qdss, _, _, _, _, _, _), 995 [24] = PINGROUP(24, SOUTH, cci_timer3, cci_async, qdss, _, _, _, _, _, _), 996 [25] = PINGROUP(25, SOUTH, cci_timer4, cci_async, qup05, _, phase_flag, qdss, _, _, _), 997 [26] = PINGROUP(26, SOUTH, cci_async, qup05, _, phase_flag, qdss, atest_tsens, atest_usb11, ddr_pxi2, _), 998 [27] = PINGROUP(27, SOUTH, cci_i2c, qup05, PLL_BIST, _, phase_flag, qdss, ddr_pxi0, _, _), 999 [28] = PINGROUP(28, SOUTH, cci_i2c, qup05, _, phase_flag, qdss, _, _, _, _), 1000 [29] = PINGROUP(29, NORTH, _, qdss, _, _, _, _, _, _, _), 1001 [30] = PINGROUP(30, SOUTH, qdss, _, _, _, _, _, _, _, _), 1002 [31] = PINGROUP(31, NORTH, _, qdss, _, _, _, _, _, _, _), 1003 [32] = PINGROUP(32, NORTH, _, phase_flag, _, _, _, _, _, _, _), 1004 [33] = PINGROUP(33, NORTH, sd_write, _, phase_flag, qdss_cti, _, _, _, _, _), 1005 [34] = PINGROUP(34, SOUTH, qup00, _, phase_flag, qdss, _, _, _, _, _), 1006 [35] = PINGROUP(35, SOUTH, qup00, _, phase_flag, qdss, _, _, _, _, _), 1007 [36] = PINGROUP(36, SOUTH, qup00, _, phase_flag, qdss, _, _, _, _, _), 1008 [37] = PINGROUP(37, SOUTH, qup00, gp_pdm0, _, phase_flag, qdss, _, _, _, _), 1009 [38] = PINGROUP(38, SOUTH, qup03, _, phase_flag, _, _, _, _, _, _), 1010 [39] = PINGROUP(39, SOUTH, qup03, _, phase_flag, atest_tsens2, wlan2_adc1, atest_usb1, _, _, _), 1011 [40] = PINGROUP(40, SOUTH, qup03, _, _, _, _, _, _, _, _), 1012 [41] = PINGROUP(41, SOUTH, qup03, _, _, _, _, _, _, _, _), 1013 [42] = PINGROUP(42, NORTH, qup12, _, phase_flag, _, _, _, _, _, _), 1014 [43] = PINGROUP(43, NORTH, qup12, _, _, _, _, _, _, _, _), 1015 [44] = PINGROUP(44, NORTH, qup12, _, phase_flag, qdss_cti, wlan1_adc1, atest_usb13, ddr_pxi1, _, _), 1016 [45] = PINGROUP(45, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _), 1017 [46] = PINGROUP(46, NORTH, qup13, qup13, _, _, _, _, _, _, _), 1018 [47] = PINGROUP(47, NORTH, qup13, qup13, _, _, _, _, _, _, _), 1019 [48] = PINGROUP(48, NORTH, gcc_gp1, _, _, _, _, _, _, _, _), 1020 [49] = PINGROUP(49, WEST, mi2s_1, btfm_slimbus, _, _, _, _, _, _, _), 1021 [50] = PINGROUP(50, WEST, mi2s_1, btfm_slimbus, gp_pdm1, _, _, _, _, _, _), 1022 [51] = PINGROUP(51, WEST, mi2s_1, btfm_slimbus, atest_usb2, _, _, _, _, _, _), 1023 [52] = PINGROUP(52, WEST, mi2s_1, btfm_slimbus, atest_usb23, _, _, _, _, _, _), 1024 [53] = PINGROUP(53, WEST, mi2s_0, qup15, qdss, atest_usb22, _, _, _, _, _), 1025 [54] = PINGROUP(54, WEST, mi2s_0, qup15, qdss, atest_usb21, _, _, _, _, _), 1026 [55] = PINGROUP(55, WEST, mi2s_0, qup15, qdss, atest_usb20, _, _, _, _, _), 1027 [56] = PINGROUP(56, WEST, mi2s_0, qup15, gcc_gp1, _, phase_flag, qdss, _, _, _), 1028 [57] = PINGROUP(57, WEST, lpass_ext, audio_ref, jitter_bist, gp_pdm2, _, phase_flag, qdss, _, _), 1029 [58] = PINGROUP(58, WEST, lpass_ext, _, phase_flag, _, _, _, _, _, _), 1030 [59] = PINGROUP(59, NORTH, qup10, _, _, _, _, _, _, _, _), 1031 [60] = PINGROUP(60, NORTH, qup10, _, _, _, _, _, _, _, _), 1032 [61] = PINGROUP(61, NORTH, qup10, _, _, _, _, _, _, _, _), 1033 [62] = PINGROUP(62, NORTH, qup10, tgu_ch3, _, _, _, _, _, _, _), 1034 [63] = PINGROUP(63, NORTH, qspi_clk, mdp_vsync0, mi2s_2, mdp_vsync1, mdp_vsync2, mdp_vsync3, tgu_ch0, _, phase_flag), 1035 [64] = PINGROUP(64, NORTH, qspi_data, mi2s_2, tgu_ch1, _, phase_flag, _, _, _, _), 1036 [65] = PINGROUP(65, NORTH, qspi_data, mi2s_2, vfr_1, tgu_ch2, _, _, _, _, _), 1037 [66] = PINGROUP(66, NORTH, qspi_data, mi2s_2, _, _, _, _, _, _, _), 1038 [67] = PINGROUP(67, NORTH, qspi_data, _, _, _, _, _, _, _, _), 1039 [68] = PINGROUP(68, NORTH, qspi_cs, qup10, gp_pdm0, _, _, _, _, _, _), 1040 [69] = PINGROUP(69, WEST, _, _, _, _, _, _, _, _, _), 1041 [70] = PINGROUP(70, NORTH, _, _, mdp_vsync, ldo_en, _, _, _, _, _), 1042 [71] = PINGROUP(71, NORTH, _, mdp_vsync, ldo_update, _, _, _, _, _, _), 1043 [72] = PINGROUP(72, NORTH, qspi_cs, qup10, prng_rosc, _, qdss_cti, _, _, _, _), 1044 [73] = PINGROUP(73, WEST, _, _, _, _, _, _, _, _, _), 1045 [74] = PINGROUP(74, WEST, _, _, _, _, _, _, _, _, _), 1046 [75] = PINGROUP(75, WEST, uim2, _, _, _, _, _, _, _, _), 1047 [76] = PINGROUP(76, WEST, uim2, _, _, _, _, _, _, _, _), 1048 [77] = PINGROUP(77, WEST, uim2, _, _, _, _, _, _, _, _), 1049 [78] = PINGROUP(78, WEST, uim2, _, _, _, _, _, _, _, _), 1050 [79] = PINGROUP(79, WEST, uim1, _, _, _, _, _, _, _, _), 1051 [80] = PINGROUP(80, WEST, uim1, _, _, _, _, _, _, _, _), 1052 [81] = PINGROUP(81, WEST, uim1, _, _, _, _, _, _, _, _), 1053 [82] = PINGROUP(82, WEST, uim1, _, _, _, _, _, _, _, _), 1054 [83] = PINGROUP(83, WEST, _, _V_GPIO, _V_PPS_IN, _V_PPS_OUT, gps_tx, _, _, _, _), 1055 [84] = PINGROUP(84, WEST, _, _V_GPIO, _V_PPS_IN, _V_PPS_OUT, gps_tx, _, _, _, _), 1056 [85] = PINGROUP(85, WEST, uim_batt, dp_hot, aoss_cti, _, _, _, _, _, _), 1057 [86] = PINGROUP(86, NORTH, qup14, qdss, _, _, _, _, _, _, _), 1058 [87] = PINGROUP(87, NORTH, qup14, adsp_ext, qdss, _, _, _, _, _, _), 1059 [88] = PINGROUP(88, NORTH, qup14, qdss, tsense_pwm1, tsense_pwm2, _, _, _, _, _), 1060 [89] = PINGROUP(89, NORTH, qup14, qdss, _, _, _, _, _, _, _), 1061 [90] = PINGROUP(90, NORTH, qup14, qdss, _, _, _, _, _, _, _), 1062 [91] = PINGROUP(91, NORTH, qup14, qdss, _, _, _, _, _, _, _), 1063 [92] = PINGROUP(92, NORTH, _, _, _, _, _, _, _, _, _), 1064 [93] = PINGROUP(93, NORTH, qdss, _, _, _, _, _, _, _, _), 1065 [94] = PINGROUP(94, SOUTH, qup01, _, _, _, _, _, _, _, _), 1066 [95] = PINGROUP(95, WEST, _, _, _, _, _, _, _, _, _), 1067 [96] = PINGROUP(96, WEST, qlink_request, _, _, _, _, _, _, _, _), 1068 [97] = PINGROUP(97, WEST, qlink_enable, _, _, _, _, _, _, _, _), 1069 [98] = PINGROUP(98, WEST, _, _, _, _, _, _, _, _, _), 1070 [99] = PINGROUP(99, WEST, _, pa_indicator, _, _, _, _, _, _, _), 1071 [100] = PINGROUP(100, WEST, _, _, _, _, _, _, _, _, _), 1072 [101] = PINGROUP(101, NORTH, _, _, _, _, _, _, _, _, _), 1073 [102] = PINGROUP(102, NORTH, _, _, _, _, _, _, _, _, _), 1074 [103] = PINGROUP(103, NORTH, _, _, _, _, _, _, _, _, _), 1075 [104] = PINGROUP(104, WEST, usb_phy, _, qdss, _, _, _, _, _, _), 1076 [105] = PINGROUP(105, NORTH, _, _, _, _, _, _, _, _, _), 1077 [106] = PINGROUP(106, NORTH, _, _, _, _, _, _, _, _, _), 1078 [107] = PINGROUP(107, WEST, _, _V_GPIO, _V_PPS_IN, _V_PPS_OUT, gps_tx, _, _, _, _), 1079 [108] = PINGROUP(108, SOUTH, mss_lte, _, phase_flag, ddr_pxi3, _, _, _, _, _), 1080 [109] = PINGROUP(109, SOUTH, mss_lte, gps_tx, _, phase_flag, _, _, _, _, _), 1081 [110] = PINGROUP(110, NORTH, _, _, _, _, _, _, _, _, _), 1082 [111] = PINGROUP(111, NORTH, _, _, _, _, _, _, _, _, _), 1083 [112] = PINGROUP(112, NORTH, _, _, _, _, _, _, _, _, _), 1084 [113] = PINGROUP(113, NORTH, _, _, _, _, _, _, _, _, _), 1085 [114] = PINGROUP(114, NORTH, _, _, _, _, _, _, _, _, _), 1086 [115] = PINGROUP(115, WEST, qup04, qup04, _, _, _, _, _, _, _), 1087 [116] = PINGROUP(116, WEST, qup04, qup04, _, _, _, _, _, _, _), 1088 [117] = PINGROUP(117, WEST, dp_hot, _, _, _, _, _, _, _, _), 1089 [118] = PINGROUP(118, WEST, _, _, _, _, _, _, _, _, _), 1090 [119] = UFS_RESET(ufs_reset, 0x97f000), 1091 [120] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x97a000, 15, 0), 1092 [121] = SDC_QDSD_PINGROUP(sdc1_clk, 0x97a000, 13, 6), 1093 [122] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x97a000, 11, 3), 1094 [123] = SDC_QDSD_PINGROUP(sdc1_data, 0x97a000, 9, 0), 1095 [124] = SDC_QDSD_PINGROUP(sdc2_clk, 0x97b000, 14, 6), 1096 [125] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x97b000, 11, 3), 1097 [126] = SDC_QDSD_PINGROUP(sdc2_data, 0x97b000, 9, 0), 1098 }; 1099 1100 static const struct msm_pinctrl_soc_data sc7180_pinctrl = { 1101 .pins = sc7180_pins, 1102 .npins = ARRAY_SIZE(sc7180_pins), 1103 .functions = sc7180_functions, 1104 .nfunctions = ARRAY_SIZE(sc7180_functions), 1105 .groups = sc7180_groups, 1106 .ngroups = ARRAY_SIZE(sc7180_groups), 1107 .ngpios = 120, 1108 .tiles = sc7180_tiles, 1109 .ntiles = ARRAY_SIZE(sc7180_tiles), 1110 }; 1111 1112 static int sc7180_pinctrl_probe(struct platform_device *pdev) 1113 { 1114 return msm_pinctrl_probe(pdev, &sc7180_pinctrl); 1115 } 1116 1117 static const struct of_device_id sc7180_pinctrl_of_match[] = { 1118 { .compatible = "qcom,sc7180-pinctrl", }, 1119 { }, 1120 }; 1121 1122 static struct platform_driver sc7180_pinctrl_driver = { 1123 .driver = { 1124 .name = "sc7180-pinctrl", 1125 .pm = &msm_pinctrl_dev_pm_ops, 1126 .of_match_table = sc7180_pinctrl_of_match, 1127 }, 1128 .probe = sc7180_pinctrl_probe, 1129 .remove = msm_pinctrl_remove, 1130 }; 1131 1132 static int __init sc7180_pinctrl_init(void) 1133 { 1134 return platform_driver_register(&sc7180_pinctrl_driver); 1135 } 1136 arch_initcall(sc7180_pinctrl_init); 1137 1138 static void __exit sc7180_pinctrl_exit(void) 1139 { 1140 platform_driver_unregister(&sc7180_pinctrl_driver); 1141 } 1142 module_exit(sc7180_pinctrl_exit); 1143 1144 MODULE_DESCRIPTION("QTI sc7180 pinctrl driver"); 1145 MODULE_LICENSE("GPL v2"); 1146 MODULE_DEVICE_TABLE(of, sc7180_pinctrl_of_match); 1147