1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/gpio/driver.h>
7 #include <linux/interrupt.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/of_irq.h>
11 #include <linux/pinctrl/pinconf-generic.h>
12 #include <linux/pinctrl/pinconf.h>
13 #include <linux/pinctrl/pinmux.h>
14 #include <linux/platform_device.h>
15 #include <linux/regmap.h>
16 #include <linux/slab.h>
17 #include <linux/types.h>
18 
19 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
20 
21 #include "../core.h"
22 #include "../pinctrl-utils.h"
23 
24 #define PMIC_GPIO_ADDRESS_RANGE			0x100
25 
26 /* type and subtype registers base address offsets */
27 #define PMIC_GPIO_REG_TYPE			0x4
28 #define PMIC_GPIO_REG_SUBTYPE			0x5
29 
30 /* GPIO peripheral type and subtype out_values */
31 #define PMIC_GPIO_TYPE				0x10
32 #define PMIC_GPIO_SUBTYPE_GPIO_4CH		0x1
33 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH		0x5
34 #define PMIC_GPIO_SUBTYPE_GPIO_8CH		0x9
35 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH		0xd
36 #define PMIC_GPIO_SUBTYPE_GPIO_LV		0x10
37 #define PMIC_GPIO_SUBTYPE_GPIO_MV		0x11
38 
39 #define PMIC_MPP_REG_RT_STS			0x10
40 #define PMIC_MPP_REG_RT_STS_VAL_MASK		0x1
41 
42 /* control register base address offsets */
43 #define PMIC_GPIO_REG_MODE_CTL			0x40
44 #define PMIC_GPIO_REG_DIG_VIN_CTL		0x41
45 #define PMIC_GPIO_REG_DIG_PULL_CTL		0x42
46 #define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL	0x44
47 #define PMIC_GPIO_REG_DIG_IN_CTL		0x43
48 #define PMIC_GPIO_REG_DIG_OUT_CTL		0x45
49 #define PMIC_GPIO_REG_EN_CTL			0x46
50 #define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL	0x4A
51 
52 /* PMIC_GPIO_REG_MODE_CTL */
53 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT		0x1
54 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT	1
55 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK	0x7
56 #define PMIC_GPIO_REG_MODE_DIR_SHIFT		4
57 #define PMIC_GPIO_REG_MODE_DIR_MASK		0x7
58 
59 #define PMIC_GPIO_MODE_DIGITAL_INPUT		0
60 #define PMIC_GPIO_MODE_DIGITAL_OUTPUT		1
61 #define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT	2
62 #define PMIC_GPIO_MODE_ANALOG_PASS_THRU		3
63 #define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK	0x3
64 
65 /* PMIC_GPIO_REG_DIG_VIN_CTL */
66 #define PMIC_GPIO_REG_VIN_SHIFT			0
67 #define PMIC_GPIO_REG_VIN_MASK			0x7
68 
69 /* PMIC_GPIO_REG_DIG_PULL_CTL */
70 #define PMIC_GPIO_REG_PULL_SHIFT		0
71 #define PMIC_GPIO_REG_PULL_MASK			0x7
72 
73 #define PMIC_GPIO_PULL_DOWN			4
74 #define PMIC_GPIO_PULL_DISABLE			5
75 
76 /* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */
77 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT		0x80
78 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT	7
79 #define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK	0xF
80 
81 /* PMIC_GPIO_REG_DIG_IN_CTL */
82 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN		0x80
83 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK	0x7
84 #define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK		0xf
85 
86 /* PMIC_GPIO_REG_DIG_OUT_CTL */
87 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT	0
88 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK		0x3
89 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT		4
90 #define PMIC_GPIO_REG_OUT_TYPE_MASK		0x3
91 
92 /*
93  * Output type - indicates pin should be configured as push-pull,
94  * open drain or open source.
95  */
96 #define PMIC_GPIO_OUT_BUF_CMOS			0
97 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS	1
98 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS	2
99 
100 /* PMIC_GPIO_REG_EN_CTL */
101 #define PMIC_GPIO_REG_MASTER_EN_SHIFT		7
102 
103 #define PMIC_GPIO_PHYSICAL_OFFSET		1
104 
105 /* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */
106 #define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK		0x3
107 
108 /* Qualcomm specific pin configurations */
109 #define PMIC_GPIO_CONF_PULL_UP			(PIN_CONFIG_END + 1)
110 #define PMIC_GPIO_CONF_STRENGTH			(PIN_CONFIG_END + 2)
111 #define PMIC_GPIO_CONF_ATEST			(PIN_CONFIG_END + 3)
112 #define PMIC_GPIO_CONF_ANALOG_PASS		(PIN_CONFIG_END + 4)
113 #define PMIC_GPIO_CONF_DTEST_BUFFER		(PIN_CONFIG_END + 5)
114 
115 /* The index of each function in pmic_gpio_functions[] array */
116 enum pmic_gpio_func_index {
117 	PMIC_GPIO_FUNC_INDEX_NORMAL,
118 	PMIC_GPIO_FUNC_INDEX_PAIRED,
119 	PMIC_GPIO_FUNC_INDEX_FUNC1,
120 	PMIC_GPIO_FUNC_INDEX_FUNC2,
121 	PMIC_GPIO_FUNC_INDEX_FUNC3,
122 	PMIC_GPIO_FUNC_INDEX_FUNC4,
123 	PMIC_GPIO_FUNC_INDEX_DTEST1,
124 	PMIC_GPIO_FUNC_INDEX_DTEST2,
125 	PMIC_GPIO_FUNC_INDEX_DTEST3,
126 	PMIC_GPIO_FUNC_INDEX_DTEST4,
127 };
128 
129 /**
130  * struct pmic_gpio_pad - keep current GPIO settings
131  * @base: Address base in SPMI device.
132  * @is_enabled: Set to false when GPIO should be put in high Z state.
133  * @out_value: Cached pin output value
134  * @have_buffer: Set to true if GPIO output could be configured in push-pull,
135  *	open-drain or open-source mode.
136  * @output_enabled: Set to true if GPIO output logic is enabled.
137  * @input_enabled: Set to true if GPIO input buffer logic is enabled.
138  * @analog_pass: Set to true if GPIO is in analog-pass-through mode.
139  * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11).
140  * @num_sources: Number of power-sources supported by this GPIO.
141  * @power_source: Current power-source used.
142  * @buffer_type: Push-pull, open-drain or open-source.
143  * @pullup: Constant current which flow trough GPIO output buffer.
144  * @strength: No, Low, Medium, High
145  * @function: See pmic_gpio_functions[]
146  * @atest: the ATEST selection for GPIO analog-pass-through mode
147  * @dtest_buffer: the DTEST buffer selection for digital input mode.
148  */
149 struct pmic_gpio_pad {
150 	u16		base;
151 	bool		is_enabled;
152 	bool		out_value;
153 	bool		have_buffer;
154 	bool		output_enabled;
155 	bool		input_enabled;
156 	bool		analog_pass;
157 	bool		lv_mv_type;
158 	unsigned int	num_sources;
159 	unsigned int	power_source;
160 	unsigned int	buffer_type;
161 	unsigned int	pullup;
162 	unsigned int	strength;
163 	unsigned int	function;
164 	unsigned int	atest;
165 	unsigned int	dtest_buffer;
166 };
167 
168 struct pmic_gpio_state {
169 	struct device	*dev;
170 	struct regmap	*map;
171 	struct pinctrl_dev *ctrl;
172 	struct gpio_chip chip;
173 };
174 
175 static const struct pinconf_generic_params pmic_gpio_bindings[] = {
176 	{"qcom,pull-up-strength",	PMIC_GPIO_CONF_PULL_UP,		0},
177 	{"qcom,drive-strength",		PMIC_GPIO_CONF_STRENGTH,	0},
178 	{"qcom,atest",			PMIC_GPIO_CONF_ATEST,		0},
179 	{"qcom,analog-pass",		PMIC_GPIO_CONF_ANALOG_PASS,	0},
180 	{"qcom,dtest-buffer",           PMIC_GPIO_CONF_DTEST_BUFFER,    0},
181 };
182 
183 #ifdef CONFIG_DEBUG_FS
184 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
185 	PCONFDUMP(PMIC_GPIO_CONF_PULL_UP,  "pull up strength", NULL, true),
186 	PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
187 	PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true),
188 	PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true),
189 	PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true),
190 };
191 #endif
192 
193 static const char *const pmic_gpio_groups[] = {
194 	"gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
195 	"gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
196 	"gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
197 	"gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
198 	"gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
199 };
200 
201 static const char *const pmic_gpio_functions[] = {
202 	[PMIC_GPIO_FUNC_INDEX_NORMAL]	= PMIC_GPIO_FUNC_NORMAL,
203 	[PMIC_GPIO_FUNC_INDEX_PAIRED]	= PMIC_GPIO_FUNC_PAIRED,
204 	[PMIC_GPIO_FUNC_INDEX_FUNC1]	= PMIC_GPIO_FUNC_FUNC1,
205 	[PMIC_GPIO_FUNC_INDEX_FUNC2]	= PMIC_GPIO_FUNC_FUNC2,
206 	[PMIC_GPIO_FUNC_INDEX_FUNC3]	= PMIC_GPIO_FUNC_FUNC3,
207 	[PMIC_GPIO_FUNC_INDEX_FUNC4]	= PMIC_GPIO_FUNC_FUNC4,
208 	[PMIC_GPIO_FUNC_INDEX_DTEST1]	= PMIC_GPIO_FUNC_DTEST1,
209 	[PMIC_GPIO_FUNC_INDEX_DTEST2]	= PMIC_GPIO_FUNC_DTEST2,
210 	[PMIC_GPIO_FUNC_INDEX_DTEST3]	= PMIC_GPIO_FUNC_DTEST3,
211 	[PMIC_GPIO_FUNC_INDEX_DTEST4]	= PMIC_GPIO_FUNC_DTEST4,
212 };
213 
214 static int pmic_gpio_read(struct pmic_gpio_state *state,
215 			  struct pmic_gpio_pad *pad, unsigned int addr)
216 {
217 	unsigned int val;
218 	int ret;
219 
220 	ret = regmap_read(state->map, pad->base + addr, &val);
221 	if (ret < 0)
222 		dev_err(state->dev, "read 0x%x failed\n", addr);
223 	else
224 		ret = val;
225 
226 	return ret;
227 }
228 
229 static int pmic_gpio_write(struct pmic_gpio_state *state,
230 			   struct pmic_gpio_pad *pad, unsigned int addr,
231 			   unsigned int val)
232 {
233 	int ret;
234 
235 	ret = regmap_write(state->map, pad->base + addr, val);
236 	if (ret < 0)
237 		dev_err(state->dev, "write 0x%x failed\n", addr);
238 
239 	return ret;
240 }
241 
242 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev)
243 {
244 	/* Every PIN is a group */
245 	return pctldev->desc->npins;
246 }
247 
248 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev,
249 					    unsigned pin)
250 {
251 	return pctldev->desc->pins[pin].name;
252 }
253 
254 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
255 				    const unsigned **pins, unsigned *num_pins)
256 {
257 	*pins = &pctldev->desc->pins[pin].number;
258 	*num_pins = 1;
259 	return 0;
260 }
261 
262 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
263 	.get_groups_count	= pmic_gpio_get_groups_count,
264 	.get_group_name		= pmic_gpio_get_group_name,
265 	.get_group_pins		= pmic_gpio_get_group_pins,
266 	.dt_node_to_map		= pinconf_generic_dt_node_to_map_group,
267 	.dt_free_map		= pinctrl_utils_free_map,
268 };
269 
270 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev)
271 {
272 	return ARRAY_SIZE(pmic_gpio_functions);
273 }
274 
275 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev,
276 					       unsigned function)
277 {
278 	return pmic_gpio_functions[function];
279 }
280 
281 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
282 					 unsigned function,
283 					 const char *const **groups,
284 					 unsigned *const num_qgroups)
285 {
286 	*groups = pmic_gpio_groups;
287 	*num_qgroups = pctldev->desc->npins;
288 	return 0;
289 }
290 
291 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
292 				unsigned pin)
293 {
294 	struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
295 	struct pmic_gpio_pad *pad;
296 	unsigned int val;
297 	int ret;
298 
299 	if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) {
300 		pr_err("function: %d is not defined\n", function);
301 		return -EINVAL;
302 	}
303 
304 	pad = pctldev->desc->pins[pin].drv_data;
305 	/*
306 	 * Non-LV/MV subtypes only support 2 special functions,
307 	 * offsetting the dtestx function values by 2
308 	 */
309 	if (!pad->lv_mv_type) {
310 		if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 ||
311 				function == PMIC_GPIO_FUNC_INDEX_FUNC4) {
312 			pr_err("LV/MV subtype doesn't have func3/func4\n");
313 			return -EINVAL;
314 		}
315 		if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1)
316 			function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 -
317 					PMIC_GPIO_FUNC_INDEX_FUNC3);
318 	}
319 
320 	pad->function = function;
321 
322 	if (pad->analog_pass)
323 		val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
324 	else if (pad->output_enabled && pad->input_enabled)
325 		val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
326 	else if (pad->output_enabled)
327 		val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
328 	else
329 		val = PMIC_GPIO_MODE_DIGITAL_INPUT;
330 
331 	if (pad->lv_mv_type) {
332 		ret = pmic_gpio_write(state, pad,
333 				PMIC_GPIO_REG_MODE_CTL, val);
334 		if (ret < 0)
335 			return ret;
336 
337 		val = pad->atest - 1;
338 		ret = pmic_gpio_write(state, pad,
339 				PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
340 		if (ret < 0)
341 			return ret;
342 
343 		val = pad->out_value
344 			<< PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
345 		val |= pad->function
346 			& PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
347 		ret = pmic_gpio_write(state, pad,
348 			PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
349 		if (ret < 0)
350 			return ret;
351 	} else {
352 		val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
353 		val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
354 		val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
355 
356 		ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
357 		if (ret < 0)
358 			return ret;
359 	}
360 
361 	val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
362 
363 	return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
364 }
365 
366 static const struct pinmux_ops pmic_gpio_pinmux_ops = {
367 	.get_functions_count	= pmic_gpio_get_functions_count,
368 	.get_function_name	= pmic_gpio_get_function_name,
369 	.get_function_groups	= pmic_gpio_get_function_groups,
370 	.set_mux		= pmic_gpio_set_mux,
371 };
372 
373 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
374 				unsigned int pin, unsigned long *config)
375 {
376 	unsigned param = pinconf_to_config_param(*config);
377 	struct pmic_gpio_pad *pad;
378 	unsigned arg;
379 
380 	pad = pctldev->desc->pins[pin].drv_data;
381 
382 	switch (param) {
383 	case PIN_CONFIG_DRIVE_PUSH_PULL:
384 		if (pad->buffer_type != PMIC_GPIO_OUT_BUF_CMOS)
385 			return -EINVAL;
386 		arg = 1;
387 		break;
388 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
389 		if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS)
390 			return -EINVAL;
391 		arg = 1;
392 		break;
393 	case PIN_CONFIG_DRIVE_OPEN_SOURCE:
394 		if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS)
395 			return -EINVAL;
396 		arg = 1;
397 		break;
398 	case PIN_CONFIG_BIAS_PULL_DOWN:
399 		if (pad->pullup != PMIC_GPIO_PULL_DOWN)
400 			return -EINVAL;
401 		arg = 1;
402 		break;
403 	case PIN_CONFIG_BIAS_DISABLE:
404 		if (pad->pullup != PMIC_GPIO_PULL_DISABLE)
405 			return -EINVAL;
406 		arg = 1;
407 		break;
408 	case PIN_CONFIG_BIAS_PULL_UP:
409 		if (pad->pullup != PMIC_GPIO_PULL_UP_30)
410 			return -EINVAL;
411 		arg = 1;
412 		break;
413 	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
414 		if (pad->is_enabled)
415 			return -EINVAL;
416 		arg = 1;
417 		break;
418 	case PIN_CONFIG_POWER_SOURCE:
419 		arg = pad->power_source;
420 		break;
421 	case PIN_CONFIG_INPUT_ENABLE:
422 		if (!pad->input_enabled)
423 			return -EINVAL;
424 		arg = 1;
425 		break;
426 	case PIN_CONFIG_OUTPUT:
427 		arg = pad->out_value;
428 		break;
429 	case PMIC_GPIO_CONF_PULL_UP:
430 		arg = pad->pullup;
431 		break;
432 	case PMIC_GPIO_CONF_STRENGTH:
433 		arg = pad->strength;
434 		break;
435 	case PMIC_GPIO_CONF_ATEST:
436 		arg = pad->atest;
437 		break;
438 	case PMIC_GPIO_CONF_ANALOG_PASS:
439 		arg = pad->analog_pass;
440 		break;
441 	case PMIC_GPIO_CONF_DTEST_BUFFER:
442 		arg = pad->dtest_buffer;
443 		break;
444 	default:
445 		return -EINVAL;
446 	}
447 
448 	*config = pinconf_to_config_packed(param, arg);
449 	return 0;
450 }
451 
452 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
453 				unsigned long *configs, unsigned nconfs)
454 {
455 	struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
456 	struct pmic_gpio_pad *pad;
457 	unsigned param, arg;
458 	unsigned int val;
459 	int i, ret;
460 
461 	pad = pctldev->desc->pins[pin].drv_data;
462 
463 	pad->is_enabled = true;
464 	for (i = 0; i < nconfs; i++) {
465 		param = pinconf_to_config_param(configs[i]);
466 		arg = pinconf_to_config_argument(configs[i]);
467 
468 		switch (param) {
469 		case PIN_CONFIG_DRIVE_PUSH_PULL:
470 			pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS;
471 			break;
472 		case PIN_CONFIG_DRIVE_OPEN_DRAIN:
473 			if (!pad->have_buffer)
474 				return -EINVAL;
475 			pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
476 			break;
477 		case PIN_CONFIG_DRIVE_OPEN_SOURCE:
478 			if (!pad->have_buffer)
479 				return -EINVAL;
480 			pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
481 			break;
482 		case PIN_CONFIG_BIAS_DISABLE:
483 			pad->pullup = PMIC_GPIO_PULL_DISABLE;
484 			break;
485 		case PIN_CONFIG_BIAS_PULL_UP:
486 			pad->pullup = PMIC_GPIO_PULL_UP_30;
487 			break;
488 		case PIN_CONFIG_BIAS_PULL_DOWN:
489 			if (arg)
490 				pad->pullup = PMIC_GPIO_PULL_DOWN;
491 			else
492 				pad->pullup = PMIC_GPIO_PULL_DISABLE;
493 			break;
494 		case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
495 			pad->is_enabled = false;
496 			break;
497 		case PIN_CONFIG_POWER_SOURCE:
498 			if (arg >= pad->num_sources)
499 				return -EINVAL;
500 			pad->power_source = arg;
501 			break;
502 		case PIN_CONFIG_INPUT_ENABLE:
503 			pad->input_enabled = arg ? true : false;
504 			break;
505 		case PIN_CONFIG_OUTPUT:
506 			pad->output_enabled = true;
507 			pad->out_value = arg;
508 			break;
509 		case PMIC_GPIO_CONF_PULL_UP:
510 			if (arg > PMIC_GPIO_PULL_UP_1P5_30)
511 				return -EINVAL;
512 			pad->pullup = arg;
513 			break;
514 		case PMIC_GPIO_CONF_STRENGTH:
515 			if (arg > PMIC_GPIO_STRENGTH_LOW)
516 				return -EINVAL;
517 			pad->strength = arg;
518 			break;
519 		case PMIC_GPIO_CONF_ATEST:
520 			if (!pad->lv_mv_type || arg > 4)
521 				return -EINVAL;
522 			pad->atest = arg;
523 			break;
524 		case PMIC_GPIO_CONF_ANALOG_PASS:
525 			if (!pad->lv_mv_type)
526 				return -EINVAL;
527 			pad->analog_pass = true;
528 			break;
529 		case PMIC_GPIO_CONF_DTEST_BUFFER:
530 			if (arg > 4)
531 				return -EINVAL;
532 			pad->dtest_buffer = arg;
533 			break;
534 		default:
535 			return -EINVAL;
536 		}
537 	}
538 
539 	val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT;
540 
541 	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val);
542 	if (ret < 0)
543 		return ret;
544 
545 	val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT;
546 
547 	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val);
548 	if (ret < 0)
549 		return ret;
550 
551 	val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT;
552 	val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
553 
554 	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val);
555 	if (ret < 0)
556 		return ret;
557 
558 	if (pad->dtest_buffer == 0) {
559 		val = 0;
560 	} else {
561 		if (pad->lv_mv_type) {
562 			val = pad->dtest_buffer - 1;
563 			val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN;
564 		} else {
565 			val = BIT(pad->dtest_buffer - 1);
566 		}
567 	}
568 	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val);
569 	if (ret < 0)
570 		return ret;
571 
572 	if (pad->analog_pass)
573 		val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
574 	else if (pad->output_enabled && pad->input_enabled)
575 		val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
576 	else if (pad->output_enabled)
577 		val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
578 	else
579 		val = PMIC_GPIO_MODE_DIGITAL_INPUT;
580 
581 	if (pad->lv_mv_type) {
582 		ret = pmic_gpio_write(state, pad,
583 				PMIC_GPIO_REG_MODE_CTL, val);
584 		if (ret < 0)
585 			return ret;
586 
587 		val = pad->atest - 1;
588 		ret = pmic_gpio_write(state, pad,
589 				PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
590 		if (ret < 0)
591 			return ret;
592 
593 		val = pad->out_value
594 			<< PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
595 		val |= pad->function
596 			& PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
597 		ret = pmic_gpio_write(state, pad,
598 			PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
599 		if (ret < 0)
600 			return ret;
601 	} else {
602 		val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
603 		val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
604 		val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
605 
606 		ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
607 		if (ret < 0)
608 			return ret;
609 	}
610 
611 	val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
612 
613 	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
614 
615 	return ret;
616 }
617 
618 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
619 				      struct seq_file *s, unsigned pin)
620 {
621 	struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
622 	struct pmic_gpio_pad *pad;
623 	int ret, val, function;
624 
625 	static const char *const biases[] = {
626 		"pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
627 		"pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
628 	};
629 	static const char *const buffer_types[] = {
630 		"push-pull", "open-drain", "open-source"
631 	};
632 	static const char *const strengths[] = {
633 		"no", "high", "medium", "low"
634 	};
635 
636 	pad = pctldev->desc->pins[pin].drv_data;
637 
638 	seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
639 
640 	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);
641 
642 	if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
643 		seq_puts(s, " ---");
644 	} else {
645 		if (pad->input_enabled) {
646 			ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
647 			if (ret < 0)
648 				return;
649 
650 			ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
651 			pad->out_value = ret;
652 		}
653 		/*
654 		 * For the non-LV/MV subtypes only 2 special functions are
655 		 * available, offsetting the dtest function values by 2.
656 		 */
657 		function = pad->function;
658 		if (!pad->lv_mv_type &&
659 				pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3)
660 			function += PMIC_GPIO_FUNC_INDEX_DTEST1 -
661 				PMIC_GPIO_FUNC_INDEX_FUNC3;
662 
663 		if (pad->analog_pass)
664 			seq_puts(s, " analog-pass");
665 		else
666 			seq_printf(s, " %-4s",
667 					pad->output_enabled ? "out" : "in");
668 		seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
669 		seq_printf(s, " %-7s", pmic_gpio_functions[function]);
670 		seq_printf(s, " vin-%d", pad->power_source);
671 		seq_printf(s, " %-27s", biases[pad->pullup]);
672 		seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
673 		seq_printf(s, " %-7s", strengths[pad->strength]);
674 		seq_printf(s, " atest-%d", pad->atest);
675 		seq_printf(s, " dtest-%d", pad->dtest_buffer);
676 	}
677 }
678 
679 static const struct pinconf_ops pmic_gpio_pinconf_ops = {
680 	.is_generic			= true,
681 	.pin_config_group_get		= pmic_gpio_config_get,
682 	.pin_config_group_set		= pmic_gpio_config_set,
683 	.pin_config_group_dbg_show	= pmic_gpio_config_dbg_show,
684 };
685 
686 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
687 {
688 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
689 	unsigned long config;
690 
691 	config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
692 
693 	return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
694 }
695 
696 static int pmic_gpio_direction_output(struct gpio_chip *chip,
697 				      unsigned pin, int val)
698 {
699 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
700 	unsigned long config;
701 
702 	config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
703 
704 	return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
705 }
706 
707 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
708 {
709 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
710 	struct pmic_gpio_pad *pad;
711 	int ret;
712 
713 	pad = state->ctrl->desc->pins[pin].drv_data;
714 
715 	if (!pad->is_enabled)
716 		return -EINVAL;
717 
718 	if (pad->input_enabled) {
719 		ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
720 		if (ret < 0)
721 			return ret;
722 
723 		pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
724 	}
725 
726 	return !!pad->out_value;
727 }
728 
729 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
730 {
731 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
732 	unsigned long config;
733 
734 	config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
735 
736 	pmic_gpio_config_set(state->ctrl, pin, &config, 1);
737 }
738 
739 static int pmic_gpio_of_xlate(struct gpio_chip *chip,
740 			      const struct of_phandle_args *gpio_desc,
741 			      u32 *flags)
742 {
743 	if (chip->of_gpio_n_cells < 2)
744 		return -EINVAL;
745 
746 	if (flags)
747 		*flags = gpio_desc->args[1];
748 
749 	return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
750 }
751 
752 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
753 {
754 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
755 	unsigned i;
756 
757 	for (i = 0; i < chip->ngpio; i++) {
758 		pmic_gpio_config_dbg_show(state->ctrl, s, i);
759 		seq_puts(s, "\n");
760 	}
761 }
762 
763 static const struct gpio_chip pmic_gpio_gpio_template = {
764 	.direction_input	= pmic_gpio_direction_input,
765 	.direction_output	= pmic_gpio_direction_output,
766 	.get			= pmic_gpio_get,
767 	.set			= pmic_gpio_set,
768 	.request		= gpiochip_generic_request,
769 	.free			= gpiochip_generic_free,
770 	.of_xlate		= pmic_gpio_of_xlate,
771 	.dbg_show		= pmic_gpio_dbg_show,
772 };
773 
774 static int pmic_gpio_populate(struct pmic_gpio_state *state,
775 			      struct pmic_gpio_pad *pad)
776 {
777 	int type, subtype, val, dir;
778 
779 	type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE);
780 	if (type < 0)
781 		return type;
782 
783 	if (type != PMIC_GPIO_TYPE) {
784 		dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
785 			type, pad->base);
786 		return -ENODEV;
787 	}
788 
789 	subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE);
790 	if (subtype < 0)
791 		return subtype;
792 
793 	switch (subtype) {
794 	case PMIC_GPIO_SUBTYPE_GPIO_4CH:
795 		pad->have_buffer = true;
796 		/* Fall through */
797 	case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
798 		pad->num_sources = 4;
799 		break;
800 	case PMIC_GPIO_SUBTYPE_GPIO_8CH:
801 		pad->have_buffer = true;
802 		/* Fall through */
803 	case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
804 		pad->num_sources = 8;
805 		break;
806 	case PMIC_GPIO_SUBTYPE_GPIO_LV:
807 		pad->num_sources = 1;
808 		pad->have_buffer = true;
809 		pad->lv_mv_type = true;
810 		break;
811 	case PMIC_GPIO_SUBTYPE_GPIO_MV:
812 		pad->num_sources = 2;
813 		pad->have_buffer = true;
814 		pad->lv_mv_type = true;
815 		break;
816 	default:
817 		dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
818 		return -ENODEV;
819 	}
820 
821 	if (pad->lv_mv_type) {
822 		val = pmic_gpio_read(state, pad,
823 				PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL);
824 		if (val < 0)
825 			return val;
826 
827 		pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT);
828 		pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
829 
830 		val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
831 		if (val < 0)
832 			return val;
833 
834 		dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK;
835 	} else {
836 		val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
837 		if (val < 0)
838 			return val;
839 
840 		pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
841 
842 		dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
843 		dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
844 		pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
845 		pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
846 	}
847 
848 	switch (dir) {
849 	case PMIC_GPIO_MODE_DIGITAL_INPUT:
850 		pad->input_enabled = true;
851 		pad->output_enabled = false;
852 		break;
853 	case PMIC_GPIO_MODE_DIGITAL_OUTPUT:
854 		pad->input_enabled = false;
855 		pad->output_enabled = true;
856 		break;
857 	case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT:
858 		pad->input_enabled = true;
859 		pad->output_enabled = true;
860 		break;
861 	case PMIC_GPIO_MODE_ANALOG_PASS_THRU:
862 		if (!pad->lv_mv_type)
863 			return -ENODEV;
864 		pad->analog_pass = true;
865 		break;
866 	default:
867 		dev_err(state->dev, "unknown GPIO direction\n");
868 		return -ENODEV;
869 	}
870 
871 	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
872 	if (val < 0)
873 		return val;
874 
875 	pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT;
876 	pad->power_source &= PMIC_GPIO_REG_VIN_MASK;
877 
878 	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL);
879 	if (val < 0)
880 		return val;
881 
882 	pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
883 	pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
884 
885 	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL);
886 	if (val < 0)
887 		return val;
888 
889 	if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN))
890 		pad->dtest_buffer =
891 			(val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1;
892 	else if (!pad->lv_mv_type)
893 		pad->dtest_buffer = ffs(val);
894 	else
895 		pad->dtest_buffer = 0;
896 
897 	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
898 	if (val < 0)
899 		return val;
900 
901 	pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
902 	pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK;
903 
904 	pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
905 	pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
906 
907 	if (pad->lv_mv_type) {
908 		val = pmic_gpio_read(state, pad,
909 				PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL);
910 		if (val < 0)
911 			return val;
912 		pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1;
913 	}
914 
915 	/* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
916 	pad->is_enabled = true;
917 	return 0;
918 }
919 
920 static struct irq_chip pmic_gpio_irq_chip = {
921 	.name = "spmi-gpio",
922 	.irq_ack = irq_chip_ack_parent,
923 	.irq_mask = irq_chip_mask_parent,
924 	.irq_unmask = irq_chip_unmask_parent,
925 	.irq_set_type = irq_chip_set_type_parent,
926 	.irq_set_wake = irq_chip_set_wake_parent,
927 	.flags = IRQCHIP_MASK_ON_SUSPEND,
928 };
929 
930 static int pmic_gpio_domain_translate(struct irq_domain *domain,
931 				      struct irq_fwspec *fwspec,
932 				      unsigned long *hwirq,
933 				      unsigned int *type)
934 {
935 	struct pmic_gpio_state *state = container_of(domain->host_data,
936 						     struct pmic_gpio_state,
937 						     chip);
938 
939 	if (fwspec->param_count != 2 ||
940 	    fwspec->param[0] < 1 || fwspec->param[0] > state->chip.ngpio)
941 		return -EINVAL;
942 
943 	*hwirq = fwspec->param[0] - PMIC_GPIO_PHYSICAL_OFFSET;
944 	*type = fwspec->param[1];
945 
946 	return 0;
947 }
948 
949 static unsigned int pmic_gpio_child_offset_to_irq(struct gpio_chip *chip,
950 						  unsigned int offset)
951 {
952 	return offset + PMIC_GPIO_PHYSICAL_OFFSET;
953 }
954 
955 static int pmic_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
956 					   unsigned int child_hwirq,
957 					   unsigned int child_type,
958 					   unsigned int *parent_hwirq,
959 					   unsigned int *parent_type)
960 {
961 	*parent_hwirq = child_hwirq + 0xc0;
962 	*parent_type = child_type;
963 
964 	return 0;
965 }
966 
967 static int pmic_gpio_probe(struct platform_device *pdev)
968 {
969 	struct irq_domain *parent_domain;
970 	struct device_node *parent_node;
971 	struct device *dev = &pdev->dev;
972 	struct pinctrl_pin_desc *pindesc;
973 	struct pinctrl_desc *pctrldesc;
974 	struct pmic_gpio_pad *pad, *pads;
975 	struct pmic_gpio_state *state;
976 	struct gpio_irq_chip *girq;
977 	int ret, npins, i;
978 	u32 reg;
979 
980 	ret = of_property_read_u32(dev->of_node, "reg", &reg);
981 	if (ret < 0) {
982 		dev_err(dev, "missing base address");
983 		return ret;
984 	}
985 
986 	npins = (uintptr_t) device_get_match_data(&pdev->dev);
987 
988 	state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
989 	if (!state)
990 		return -ENOMEM;
991 
992 	platform_set_drvdata(pdev, state);
993 
994 	state->dev = &pdev->dev;
995 	state->map = dev_get_regmap(dev->parent, NULL);
996 
997 	pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
998 	if (!pindesc)
999 		return -ENOMEM;
1000 
1001 	pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
1002 	if (!pads)
1003 		return -ENOMEM;
1004 
1005 	pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
1006 	if (!pctrldesc)
1007 		return -ENOMEM;
1008 
1009 	pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
1010 	pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
1011 	pctrldesc->confops = &pmic_gpio_pinconf_ops;
1012 	pctrldesc->owner = THIS_MODULE;
1013 	pctrldesc->name = dev_name(dev);
1014 	pctrldesc->pins = pindesc;
1015 	pctrldesc->npins = npins;
1016 	pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings);
1017 	pctrldesc->custom_params = pmic_gpio_bindings;
1018 #ifdef CONFIG_DEBUG_FS
1019 	pctrldesc->custom_conf_items = pmic_conf_items;
1020 #endif
1021 
1022 	for (i = 0; i < npins; i++, pindesc++) {
1023 		pad = &pads[i];
1024 		pindesc->drv_data = pad;
1025 		pindesc->number = i;
1026 		pindesc->name = pmic_gpio_groups[i];
1027 
1028 		pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE;
1029 
1030 		ret = pmic_gpio_populate(state, pad);
1031 		if (ret < 0)
1032 			return ret;
1033 	}
1034 
1035 	state->chip = pmic_gpio_gpio_template;
1036 	state->chip.parent = dev;
1037 	state->chip.base = -1;
1038 	state->chip.ngpio = npins;
1039 	state->chip.label = dev_name(dev);
1040 	state->chip.of_gpio_n_cells = 2;
1041 	state->chip.can_sleep = false;
1042 
1043 	state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
1044 	if (IS_ERR(state->ctrl))
1045 		return PTR_ERR(state->ctrl);
1046 
1047 	parent_node = of_irq_find_parent(state->dev->of_node);
1048 	if (!parent_node)
1049 		return -ENXIO;
1050 
1051 	parent_domain = irq_find_host(parent_node);
1052 	of_node_put(parent_node);
1053 	if (!parent_domain)
1054 		return -ENXIO;
1055 
1056 	girq = &state->chip.irq;
1057 	girq->chip = &pmic_gpio_irq_chip;
1058 	girq->default_type = IRQ_TYPE_NONE;
1059 	girq->handler = handle_level_irq;
1060 	girq->fwnode = of_node_to_fwnode(state->dev->of_node);
1061 	girq->parent_domain = parent_domain;
1062 	girq->child_to_parent_hwirq = pmic_gpio_child_to_parent_hwirq;
1063 	girq->populate_parent_fwspec = gpiochip_populate_parent_fwspec_fourcell;
1064 	girq->child_offset_to_irq = pmic_gpio_child_offset_to_irq;
1065 	girq->child_irq_domain_ops.translate = pmic_gpio_domain_translate;
1066 
1067 	ret = gpiochip_add_data(&state->chip, state);
1068 	if (ret) {
1069 		dev_err(state->dev, "can't add gpio chip\n");
1070 		return ret;
1071 	}
1072 
1073 	/*
1074 	 * For DeviceTree-supported systems, the gpio core checks the
1075 	 * pinctrl's device node for the "gpio-ranges" property.
1076 	 * If it is present, it takes care of adding the pin ranges
1077 	 * for the driver. In this case the driver can skip ahead.
1078 	 *
1079 	 * In order to remain compatible with older, existing DeviceTree
1080 	 * files which don't set the "gpio-ranges" property or systems that
1081 	 * utilize ACPI the driver has to call gpiochip_add_pin_range().
1082 	 */
1083 	if (!of_property_read_bool(dev->of_node, "gpio-ranges")) {
1084 		ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0,
1085 					     npins);
1086 		if (ret) {
1087 			dev_err(dev, "failed to add pin range\n");
1088 			goto err_range;
1089 		}
1090 	}
1091 
1092 	return 0;
1093 
1094 err_range:
1095 	gpiochip_remove(&state->chip);
1096 	return ret;
1097 }
1098 
1099 static int pmic_gpio_remove(struct platform_device *pdev)
1100 {
1101 	struct pmic_gpio_state *state = platform_get_drvdata(pdev);
1102 
1103 	gpiochip_remove(&state->chip);
1104 	return 0;
1105 }
1106 
1107 static const struct of_device_id pmic_gpio_of_match[] = {
1108 	{ .compatible = "qcom,pm8005-gpio", .data = (void *) 4 },
1109 	{ .compatible = "qcom,pm8916-gpio", .data = (void *) 4 },
1110 	{ .compatible = "qcom,pm8941-gpio", .data = (void *) 36 },
1111 	/* pm8950 has 8 GPIOs with holes on 3 */
1112 	{ .compatible = "qcom,pm8950-gpio", .data = (void *) 8 },
1113 	{ .compatible = "qcom,pmi8950-gpio", .data = (void *) 2 },
1114 	{ .compatible = "qcom,pm8994-gpio", .data = (void *) 22 },
1115 	{ .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 },
1116 	{ .compatible = "qcom,pm8998-gpio", .data = (void *) 26 },
1117 	{ .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 },
1118 	{ .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },
1119 	/* pms405 has 12 GPIOs with holes on 1, 9, and 10 */
1120 	{ .compatible = "qcom,pms405-gpio", .data = (void *) 12 },
1121 	/* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */
1122 	{ .compatible = "qcom,pm8150-gpio", .data = (void *) 10 },
1123 	/* pm8150b has 12 GPIOs with holes on 3, r and 7 */
1124 	{ .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 },
1125 	/* pm8150l has 12 GPIOs with holes on 7 */
1126 	{ .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 },
1127 	{ .compatible = "qcom,pm6150-gpio", .data = (void *) 10 },
1128 	{ .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 },
1129 	{ },
1130 };
1131 
1132 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match);
1133 
1134 static struct platform_driver pmic_gpio_driver = {
1135 	.driver = {
1136 		   .name = "qcom-spmi-gpio",
1137 		   .of_match_table = pmic_gpio_of_match,
1138 	},
1139 	.probe	= pmic_gpio_probe,
1140 	.remove = pmic_gpio_remove,
1141 };
1142 
1143 module_platform_driver(pmic_gpio_driver);
1144 
1145 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
1146 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
1147 MODULE_ALIAS("platform:qcom-spmi-gpio");
1148 MODULE_LICENSE("GPL v2");
1149