1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * R8A77951 processor support - PFC hardware block.
4  *
5  * Copyright (C) 2015-2019 Renesas Electronics Corporation
6  */
7 
8 #include <linux/errno.h>
9 #include <linux/kernel.h>
10 #include <linux/sys_soc.h>
11 
12 #include "sh_pfc.h"
13 
14 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
15 
16 #define CPU_ALL_GP(fn, sfx)						\
17 	PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),	\
18 	PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),	\
19 	PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),	\
20 	PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),	\
21 	PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),	\
22 	PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),	\
23 	PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),	\
24 	PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),	\
25 	PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),	\
26 	PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),	\
27 	PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),	\
28 	PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
29 
30 #define CPU_ALL_NOGP(fn)						\
31 	PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS),			\
32 	PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS),		\
33 	PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS),		\
34 	PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS),		\
35 	PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS),		\
36 	PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS),		\
37 	PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS),		\
38 	PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS),		\
39 	PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS),		\
40 	PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS),		\
41 	PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS),		\
42 	PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS),		\
43 	PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS),		\
44 	PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS),	\
45 	PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS),		\
46 	PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS),	\
47 	PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS),	\
48 	PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS),	\
49 	PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS),	\
50 	PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
51 	PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS),		\
52 	PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS),		\
53 	PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS),		\
54 	PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS),		\
55 	PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS),		\
56 	PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS),	\
57 	PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS),	\
58 	PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS),	\
59 	PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS),		\
60 	PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS),		\
61 	PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS),		\
62 	PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS),	\
63 	PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS),	\
64 	PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS),	\
65 	PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS),		\
66 	PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS),		\
67 	PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS),		\
68 	PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS),		\
69 	PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
70 	PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
71 	PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
72 	PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS),			\
73 	PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
74 
75 /*
76  * F_() : just information
77  * FM() : macro for FN_xxx / xxx_MARK
78  */
79 
80 /* GPSR0 */
81 #define GPSR0_15	F_(D15,			IP7_11_8)
82 #define GPSR0_14	F_(D14,			IP7_7_4)
83 #define GPSR0_13	F_(D13,			IP7_3_0)
84 #define GPSR0_12	F_(D12,			IP6_31_28)
85 #define GPSR0_11	F_(D11,			IP6_27_24)
86 #define GPSR0_10	F_(D10,			IP6_23_20)
87 #define GPSR0_9		F_(D9,			IP6_19_16)
88 #define GPSR0_8		F_(D8,			IP6_15_12)
89 #define GPSR0_7		F_(D7,			IP6_11_8)
90 #define GPSR0_6		F_(D6,			IP6_7_4)
91 #define GPSR0_5		F_(D5,			IP6_3_0)
92 #define GPSR0_4		F_(D4,			IP5_31_28)
93 #define GPSR0_3		F_(D3,			IP5_27_24)
94 #define GPSR0_2		F_(D2,			IP5_23_20)
95 #define GPSR0_1		F_(D1,			IP5_19_16)
96 #define GPSR0_0		F_(D0,			IP5_15_12)
97 
98 /* GPSR1 */
99 #define GPSR1_28	FM(CLKOUT)
100 #define GPSR1_27	F_(EX_WAIT0_A,		IP5_11_8)
101 #define GPSR1_26	F_(WE1_N,		IP5_7_4)
102 #define GPSR1_25	F_(WE0_N,		IP5_3_0)
103 #define GPSR1_24	F_(RD_WR_N,		IP4_31_28)
104 #define GPSR1_23	F_(RD_N,		IP4_27_24)
105 #define GPSR1_22	F_(BS_N,		IP4_23_20)
106 #define GPSR1_21	F_(CS1_N,		IP4_19_16)
107 #define GPSR1_20	F_(CS0_N,		IP4_15_12)
108 #define GPSR1_19	F_(A19,			IP4_11_8)
109 #define GPSR1_18	F_(A18,			IP4_7_4)
110 #define GPSR1_17	F_(A17,			IP4_3_0)
111 #define GPSR1_16	F_(A16,			IP3_31_28)
112 #define GPSR1_15	F_(A15,			IP3_27_24)
113 #define GPSR1_14	F_(A14,			IP3_23_20)
114 #define GPSR1_13	F_(A13,			IP3_19_16)
115 #define GPSR1_12	F_(A12,			IP3_15_12)
116 #define GPSR1_11	F_(A11,			IP3_11_8)
117 #define GPSR1_10	F_(A10,			IP3_7_4)
118 #define GPSR1_9		F_(A9,			IP3_3_0)
119 #define GPSR1_8		F_(A8,			IP2_31_28)
120 #define GPSR1_7		F_(A7,			IP2_27_24)
121 #define GPSR1_6		F_(A6,			IP2_23_20)
122 #define GPSR1_5		F_(A5,			IP2_19_16)
123 #define GPSR1_4		F_(A4,			IP2_15_12)
124 #define GPSR1_3		F_(A3,			IP2_11_8)
125 #define GPSR1_2		F_(A2,			IP2_7_4)
126 #define GPSR1_1		F_(A1,			IP2_3_0)
127 #define GPSR1_0		F_(A0,			IP1_31_28)
128 
129 /* GPSR2 */
130 #define GPSR2_14	F_(AVB_AVTP_CAPTURE_A,	IP0_23_20)
131 #define GPSR2_13	F_(AVB_AVTP_MATCH_A,	IP0_19_16)
132 #define GPSR2_12	F_(AVB_LINK,		IP0_15_12)
133 #define GPSR2_11	F_(AVB_PHY_INT,		IP0_11_8)
134 #define GPSR2_10	F_(AVB_MAGIC,		IP0_7_4)
135 #define GPSR2_9		F_(AVB_MDC,		IP0_3_0)
136 #define GPSR2_8		F_(PWM2_A,		IP1_27_24)
137 #define GPSR2_7		F_(PWM1_A,		IP1_23_20)
138 #define GPSR2_6		F_(PWM0,		IP1_19_16)
139 #define GPSR2_5		F_(IRQ5,		IP1_15_12)
140 #define GPSR2_4		F_(IRQ4,		IP1_11_8)
141 #define GPSR2_3		F_(IRQ3,		IP1_7_4)
142 #define GPSR2_2		F_(IRQ2,		IP1_3_0)
143 #define GPSR2_1		F_(IRQ1,		IP0_31_28)
144 #define GPSR2_0		F_(IRQ0,		IP0_27_24)
145 
146 /* GPSR3 */
147 #define GPSR3_15	F_(SD1_WP,		IP11_23_20)
148 #define GPSR3_14	F_(SD1_CD,		IP11_19_16)
149 #define GPSR3_13	F_(SD0_WP,		IP11_15_12)
150 #define GPSR3_12	F_(SD0_CD,		IP11_11_8)
151 #define GPSR3_11	F_(SD1_DAT3,		IP8_31_28)
152 #define GPSR3_10	F_(SD1_DAT2,		IP8_27_24)
153 #define GPSR3_9		F_(SD1_DAT1,		IP8_23_20)
154 #define GPSR3_8		F_(SD1_DAT0,		IP8_19_16)
155 #define GPSR3_7		F_(SD1_CMD,		IP8_15_12)
156 #define GPSR3_6		F_(SD1_CLK,		IP8_11_8)
157 #define GPSR3_5		F_(SD0_DAT3,		IP8_7_4)
158 #define GPSR3_4		F_(SD0_DAT2,		IP8_3_0)
159 #define GPSR3_3		F_(SD0_DAT1,		IP7_31_28)
160 #define GPSR3_2		F_(SD0_DAT0,		IP7_27_24)
161 #define GPSR3_1		F_(SD0_CMD,		IP7_23_20)
162 #define GPSR3_0		F_(SD0_CLK,		IP7_19_16)
163 
164 /* GPSR4 */
165 #define GPSR4_17	F_(SD3_DS,		IP11_7_4)
166 #define GPSR4_16	F_(SD3_DAT7,		IP11_3_0)
167 #define GPSR4_15	F_(SD3_DAT6,		IP10_31_28)
168 #define GPSR4_14	F_(SD3_DAT5,		IP10_27_24)
169 #define GPSR4_13	F_(SD3_DAT4,		IP10_23_20)
170 #define GPSR4_12	F_(SD3_DAT3,		IP10_19_16)
171 #define GPSR4_11	F_(SD3_DAT2,		IP10_15_12)
172 #define GPSR4_10	F_(SD3_DAT1,		IP10_11_8)
173 #define GPSR4_9		F_(SD3_DAT0,		IP10_7_4)
174 #define GPSR4_8		F_(SD3_CMD,		IP10_3_0)
175 #define GPSR4_7		F_(SD3_CLK,		IP9_31_28)
176 #define GPSR4_6		F_(SD2_DS,		IP9_27_24)
177 #define GPSR4_5		F_(SD2_DAT3,		IP9_23_20)
178 #define GPSR4_4		F_(SD2_DAT2,		IP9_19_16)
179 #define GPSR4_3		F_(SD2_DAT1,		IP9_15_12)
180 #define GPSR4_2		F_(SD2_DAT0,		IP9_11_8)
181 #define GPSR4_1		F_(SD2_CMD,		IP9_7_4)
182 #define GPSR4_0		F_(SD2_CLK,		IP9_3_0)
183 
184 /* GPSR5 */
185 #define GPSR5_25	F_(MLB_DAT,		IP14_19_16)
186 #define GPSR5_24	F_(MLB_SIG,		IP14_15_12)
187 #define GPSR5_23	F_(MLB_CLK,		IP14_11_8)
188 #define GPSR5_22	FM(MSIOF0_RXD)
189 #define GPSR5_21	F_(MSIOF0_SS2,		IP14_7_4)
190 #define GPSR5_20	FM(MSIOF0_TXD)
191 #define GPSR5_19	F_(MSIOF0_SS1,		IP14_3_0)
192 #define GPSR5_18	F_(MSIOF0_SYNC,		IP13_31_28)
193 #define GPSR5_17	FM(MSIOF0_SCK)
194 #define GPSR5_16	F_(HRTS0_N,		IP13_27_24)
195 #define GPSR5_15	F_(HCTS0_N,		IP13_23_20)
196 #define GPSR5_14	F_(HTX0,		IP13_19_16)
197 #define GPSR5_13	F_(HRX0,		IP13_15_12)
198 #define GPSR5_12	F_(HSCK0,		IP13_11_8)
199 #define GPSR5_11	F_(RX2_A,		IP13_7_4)
200 #define GPSR5_10	F_(TX2_A,		IP13_3_0)
201 #define GPSR5_9		F_(SCK2,		IP12_31_28)
202 #define GPSR5_8		F_(RTS1_N,		IP12_27_24)
203 #define GPSR5_7		F_(CTS1_N,		IP12_23_20)
204 #define GPSR5_6		F_(TX1_A,		IP12_19_16)
205 #define GPSR5_5		F_(RX1_A,		IP12_15_12)
206 #define GPSR5_4		F_(RTS0_N,		IP12_11_8)
207 #define GPSR5_3		F_(CTS0_N,		IP12_7_4)
208 #define GPSR5_2		F_(TX0,			IP12_3_0)
209 #define GPSR5_1		F_(RX0,			IP11_31_28)
210 #define GPSR5_0		F_(SCK0,		IP11_27_24)
211 
212 /* GPSR6 */
213 #define GPSR6_31	F_(USB2_CH3_OVC,	IP18_7_4)
214 #define GPSR6_30	F_(USB2_CH3_PWEN,	IP18_3_0)
215 #define GPSR6_29	F_(USB30_OVC,		IP17_31_28)
216 #define GPSR6_28	F_(USB30_PWEN,		IP17_27_24)
217 #define GPSR6_27	F_(USB1_OVC,		IP17_23_20)
218 #define GPSR6_26	F_(USB1_PWEN,		IP17_19_16)
219 #define GPSR6_25	F_(USB0_OVC,		IP17_15_12)
220 #define GPSR6_24	F_(USB0_PWEN,		IP17_11_8)
221 #define GPSR6_23	F_(AUDIO_CLKB_B,	IP17_7_4)
222 #define GPSR6_22	F_(AUDIO_CLKA_A,	IP17_3_0)
223 #define GPSR6_21	F_(SSI_SDATA9_A,	IP16_31_28)
224 #define GPSR6_20	F_(SSI_SDATA8,		IP16_27_24)
225 #define GPSR6_19	F_(SSI_SDATA7,		IP16_23_20)
226 #define GPSR6_18	F_(SSI_WS78,		IP16_19_16)
227 #define GPSR6_17	F_(SSI_SCK78,		IP16_15_12)
228 #define GPSR6_16	F_(SSI_SDATA6,		IP16_11_8)
229 #define GPSR6_15	F_(SSI_WS6,		IP16_7_4)
230 #define GPSR6_14	F_(SSI_SCK6,		IP16_3_0)
231 #define GPSR6_13	FM(SSI_SDATA5)
232 #define GPSR6_12	FM(SSI_WS5)
233 #define GPSR6_11	FM(SSI_SCK5)
234 #define GPSR6_10	F_(SSI_SDATA4,		IP15_31_28)
235 #define GPSR6_9		F_(SSI_WS4,		IP15_27_24)
236 #define GPSR6_8		F_(SSI_SCK4,		IP15_23_20)
237 #define GPSR6_7		F_(SSI_SDATA3,		IP15_19_16)
238 #define GPSR6_6		F_(SSI_WS349,		IP15_15_12)
239 #define GPSR6_5		F_(SSI_SCK349,		IP15_11_8)
240 #define GPSR6_4		F_(SSI_SDATA2_A,	IP15_7_4)
241 #define GPSR6_3		F_(SSI_SDATA1_A,	IP15_3_0)
242 #define GPSR6_2		F_(SSI_SDATA0,		IP14_31_28)
243 #define GPSR6_1		F_(SSI_WS01239,		IP14_27_24)
244 #define GPSR6_0		F_(SSI_SCK01239,	IP14_23_20)
245 
246 /* GPSR7 */
247 #define GPSR7_3		FM(GP7_03)
248 #define GPSR7_2		FM(GP7_02)
249 #define GPSR7_1		FM(AVS2)
250 #define GPSR7_0		FM(AVS1)
251 
252 
253 /* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
254 #define IP0_3_0		FM(AVB_MDC)		F_(0, 0)	FM(MSIOF2_SS2_C)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP0_7_4		FM(AVB_MAGIC)		F_(0, 0)	FM(MSIOF2_SS1_C)	FM(SCK4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP0_11_8	FM(AVB_PHY_INT)		F_(0, 0)	FM(MSIOF2_SYNC_C)	FM(RX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP0_15_12	FM(AVB_LINK)		F_(0, 0)	FM(MSIOF2_SCK_C)	FM(TX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP0_19_16	FM(AVB_AVTP_MATCH_A)	F_(0, 0)	FM(MSIOF2_RXD_C)	FM(CTS4_N_A)			F_(0, 0)	FM(FSCLKST2_N_A) F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP0_23_20	FM(AVB_AVTP_CAPTURE_A)	F_(0, 0)	FM(MSIOF2_TXD_C)	FM(RTS4_N_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP0_27_24	FM(IRQ0)		FM(QPOLB)	F_(0, 0)		FM(DU_CDE)			FM(VI4_DATA0_B) FM(CAN0_TX_B)	FM(CANFD0_TX_B)		FM(MSIOF3_SS2_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP0_31_28	FM(IRQ1)		FM(QPOLA)	F_(0, 0)		FM(DU_DISP)			FM(VI4_DATA1_B) FM(CAN0_RX_B)	FM(CANFD0_RX_B)		FM(MSIOF3_SS1_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP1_3_0		FM(IRQ2)		FM(QCPV_QDE)	F_(0, 0)		FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(VI4_DATA2_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SYNC_E) F_(0, 0)		FM(PWM3_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP1_7_4		FM(IRQ3)		FM(QSTVB_QVE)	F_(0, 0)		FM(DU_DOTCLKOUT1)		FM(VI4_DATA3_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SCK_E) F_(0, 0)		FM(PWM4_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP1_11_8	FM(IRQ4)		FM(QSTH_QHS)	F_(0, 0)		FM(DU_EXHSYNC_DU_HSYNC)		FM(VI4_DATA4_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_RXD_E) F_(0, 0)		FM(PWM5_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP1_15_12	FM(IRQ5)		FM(QSTB_QHE)	F_(0, 0)		FM(DU_EXVSYNC_DU_VSYNC)		FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0)		FM(MSIOF3_TXD_E) F_(0, 0)		FM(PWM6_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP1_19_16	FM(PWM0)		FM(AVB_AVTP_PPS)F_(0, 0)		F_(0, 0)			FM(VI4_DATA6_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IECLK_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP1_23_20	FM(PWM1_A)		F_(0, 0)	F_(0, 0)		FM(HRX3_D)			FM(VI4_DATA7_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IERX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP1_27_24	FM(PWM2_A)		F_(0, 0)	F_(0, 0)		FM(HTX3_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IETX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP1_31_28	FM(A0)			FM(LCDOUT16)	FM(MSIOF3_SYNC_B)	F_(0, 0)			FM(VI4_DATA8)	F_(0, 0)	FM(DU_DB0)		F_(0, 0)	F_(0, 0)		FM(PWM3_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP2_3_0		FM(A1)			FM(LCDOUT17)	FM(MSIOF3_TXD_B)	F_(0, 0)			FM(VI4_DATA9)	F_(0, 0)	FM(DU_DB1)		F_(0, 0)	F_(0, 0)		FM(PWM4_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP2_7_4		FM(A2)			FM(LCDOUT18)	FM(MSIOF3_SCK_B)	F_(0, 0)			FM(VI4_DATA10)	F_(0, 0)	FM(DU_DB2)		F_(0, 0)	F_(0, 0)		FM(PWM5_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP2_11_8	FM(A3)			FM(LCDOUT19)	FM(MSIOF3_RXD_B)	F_(0, 0)			FM(VI4_DATA11)	F_(0, 0)	FM(DU_DB3)		F_(0, 0)	F_(0, 0)		FM(PWM6_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 
274 /* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
275 #define IP2_15_12	FM(A4)			FM(LCDOUT20)	FM(MSIOF3_SS1_B)	F_(0, 0)			FM(VI4_DATA12)	FM(VI5_DATA12)	FM(DU_DB4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP2_19_16	FM(A5)			FM(LCDOUT21)	FM(MSIOF3_SS2_B)	FM(SCK4_B)			FM(VI4_DATA13)	FM(VI5_DATA13)	FM(DU_DB5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP2_23_20	FM(A6)			FM(LCDOUT22)	FM(MSIOF2_SS1_A)	FM(RX4_B)			FM(VI4_DATA14)	FM(VI5_DATA14)	FM(DU_DB6)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP2_27_24	FM(A7)			FM(LCDOUT23)	FM(MSIOF2_SS2_A)	FM(TX4_B)			FM(VI4_DATA15)	FM(VI5_DATA15)	FM(DU_DB7)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP2_31_28	FM(A8)			FM(RX3_B)	FM(MSIOF2_SYNC_A)	FM(HRX4_B)			F_(0, 0)	F_(0, 0)	F_(0, 0)		FM(SDA6_A)	FM(AVB_AVTP_MATCH_B)	FM(PWM1_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP3_3_0		FM(A9)			F_(0, 0)	FM(MSIOF2_SCK_A)	FM(CTS4_N_B)			F_(0, 0)	FM(VI5_VSYNC_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP3_7_4		FM(A10)			F_(0, 0)	FM(MSIOF2_RXD_A)	FM(RTS4_N_B)			F_(0, 0)	FM(VI5_HSYNC_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP3_11_8	FM(A11)			FM(TX3_B)	FM(MSIOF2_TXD_A)	FM(HTX4_B)			FM(HSCK4)	FM(VI5_FIELD)	F_(0, 0)		FM(SCL6_A)	FM(AVB_AVTP_CAPTURE_B)	FM(PWM2_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP3_15_12	FM(A12)			FM(LCDOUT12)	FM(MSIOF3_SCK_C)	F_(0, 0)			FM(HRX4_A)	FM(VI5_DATA8)	FM(DU_DG4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP3_19_16	FM(A13)			FM(LCDOUT13)	FM(MSIOF3_SYNC_C)	F_(0, 0)			FM(HTX4_A)	FM(VI5_DATA9)	FM(DU_DG5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP3_23_20	FM(A14)			FM(LCDOUT14)	FM(MSIOF3_RXD_C)	F_(0, 0)			FM(HCTS4_N)	FM(VI5_DATA10)	FM(DU_DG6)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP3_27_24	FM(A15)			FM(LCDOUT15)	FM(MSIOF3_TXD_C)	F_(0, 0)			FM(HRTS4_N)	FM(VI5_DATA11)	FM(DU_DG7)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP3_31_28	FM(A16)			FM(LCDOUT8)	F_(0, 0)		F_(0, 0)			FM(VI4_FIELD)	F_(0, 0)	FM(DU_DG0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP4_3_0		FM(A17)			FM(LCDOUT9)	F_(0, 0)		F_(0, 0)			FM(VI4_VSYNC_N)	F_(0, 0)	FM(DU_DG1)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP4_7_4		FM(A18)			FM(LCDOUT10)	F_(0, 0)		F_(0, 0)			FM(VI4_HSYNC_N)	F_(0, 0)	FM(DU_DG2)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP4_11_8	FM(A19)			FM(LCDOUT11)	F_(0, 0)		F_(0, 0)			FM(VI4_CLKENB)	F_(0, 0)	FM(DU_DG3)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP4_15_12	FM(CS0_N)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(VI5_CLKENB)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP4_19_16	FM(CS1_N)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(VI5_CLK)	F_(0, 0)		FM(EX_WAIT0_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP4_23_20	FM(BS_N)		FM(QSTVA_QVS)	FM(MSIOF3_SCK_D)	FM(SCK3)			FM(HSCK3)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN1_TX)		FM(CANFD1_TX)	FM(IETX_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP4_27_24	FM(RD_N)		F_(0, 0)	FM(MSIOF3_SYNC_D)	FM(RX3_A)			FM(HRX3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN0_TX_A)		FM(CANFD0_TX_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP4_31_28	FM(RD_WR_N)		F_(0, 0)	FM(MSIOF3_RXD_D)	FM(TX3_A)			FM(HTX3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN0_RX_A)		FM(CANFD0_RX_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP5_3_0		FM(WE0_N)		F_(0, 0)	FM(MSIOF3_TXD_D)	FM(CTS3_N)			FM(HCTS3_N)	F_(0, 0)	F_(0, 0)		FM(SCL6_B)	FM(CAN_CLK)		F_(0, 0)	FM(IECLK_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP5_7_4		FM(WE1_N)		F_(0, 0)	FM(MSIOF3_SS1_D)	FM(RTS3_N)			FM(HRTS3_N)	F_(0, 0)	F_(0, 0)		FM(SDA6_B)	FM(CAN1_RX)		FM(CANFD1_RX)	FM(IERX_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP5_11_8	FM(EX_WAIT0_A)		FM(QCLK)	F_(0, 0)		F_(0, 0)			FM(VI4_CLK)	F_(0, 0)	FM(DU_DOTCLKOUT0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP5_15_12	FM(D0)			FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)	F_(0, 0)			FM(VI4_DATA16)	FM(VI5_DATA0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP5_19_16	FM(D1)			FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)	F_(0, 0)			FM(VI4_DATA17)	FM(VI5_DATA1)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP5_23_20	FM(D2)			F_(0, 0)	FM(MSIOF3_RXD_A)	F_(0, 0)			FM(VI4_DATA18)	FM(VI5_DATA2)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP5_27_24	FM(D3)			F_(0, 0)	FM(MSIOF3_TXD_A)	F_(0, 0)			FM(VI4_DATA19)	FM(VI5_DATA3)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP5_31_28	FM(D4)			FM(MSIOF2_SCK_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA20)	FM(VI5_DATA4)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP6_3_0		FM(D5)			FM(MSIOF2_SYNC_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA21)	FM(VI5_DATA5)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP6_7_4		FM(D6)			FM(MSIOF2_RXD_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA22)	FM(VI5_DATA6)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP6_11_8	FM(D7)			FM(MSIOF2_TXD_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA23)	FM(VI5_DATA7)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP6_15_12	FM(D8)			FM(LCDOUT0)	FM(MSIOF2_SCK_D)	FM(SCK4_C)			FM(VI4_DATA0_A)	F_(0, 0)	FM(DU_DR0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP6_19_16	FM(D9)			FM(LCDOUT1)	FM(MSIOF2_SYNC_D)	F_(0, 0)			FM(VI4_DATA1_A)	F_(0, 0)	FM(DU_DR1)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP6_23_20	FM(D10)			FM(LCDOUT2)	FM(MSIOF2_RXD_D)	FM(HRX3_B)			FM(VI4_DATA2_A)	FM(CTS4_N_C)	FM(DU_DR2)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP6_27_24	FM(D11)			FM(LCDOUT3)	FM(MSIOF2_TXD_D)	FM(HTX3_B)			FM(VI4_DATA3_A)	FM(RTS4_N_C)	FM(DU_DR3)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP6_31_28	FM(D12)			FM(LCDOUT4)	FM(MSIOF2_SS1_D)	FM(RX4_C)			FM(VI4_DATA4_A)	F_(0, 0)	FM(DU_DR4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP7_3_0		FM(D13)			FM(LCDOUT5)	FM(MSIOF2_SS2_D)	FM(TX4_C)			FM(VI4_DATA5_A)	F_(0, 0)	FM(DU_DR5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP7_7_4		FM(D14)			FM(LCDOUT6)	FM(MSIOF3_SS1_A)	FM(HRX3_C)			FM(VI4_DATA6_A)	F_(0, 0)	FM(DU_DR6)		FM(SCL6_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP7_11_8	FM(D15)			FM(LCDOUT7)	FM(MSIOF3_SS2_A)	FM(HTX3_C)			FM(VI4_DATA7_A)	F_(0, 0)	FM(DU_DR7)		FM(SDA6_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP7_19_16	FM(SD0_CLK)		F_(0, 0)	FM(MSIOF1_SCK_E)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_OPWM_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 
317 /* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
318 #define IP7_23_20	FM(SD0_CMD)		F_(0, 0)	FM(MSIOF1_SYNC_E)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP7_27_24	FM(SD0_DAT0)		F_(0, 0)	FM(MSIOF1_RXD_E)	F_(0, 0)			F_(0, 0)	FM(TS_SCK0_B)	FM(STP_ISCLK_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP7_31_28	FM(SD0_DAT1)		F_(0, 0)	FM(MSIOF1_TXD_E)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP8_3_0		FM(SD0_DAT2)		F_(0, 0)	FM(MSIOF1_SS1_E)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_B)	FM(STP_ISD_0_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP8_7_4		FM(SD0_DAT3)		F_(0, 0)	FM(MSIOF1_SS2_E)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_B)	FM(STP_ISEN_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP8_11_8	FM(SD1_CLK)		F_(0, 0)	FM(MSIOF1_SCK_G)	F_(0, 0)			F_(0, 0)	FM(SIM0_CLK_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP8_15_12	FM(SD1_CMD)		F_(0, 0)	FM(MSIOF1_SYNC_G)	FM(NFCE_N_B)			F_(0, 0)	FM(SIM0_D_A)	FM(STP_IVCXO27_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP8_19_16	FM(SD1_DAT0)		FM(SD2_DAT4)	FM(MSIOF1_RXD_G)	FM(NFWP_N_B)			F_(0, 0)	FM(TS_SCK1_B)	FM(STP_ISCLK_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP8_23_20	FM(SD1_DAT1)		FM(SD2_DAT5)	FM(MSIOF1_TXD_G)	FM(NFDATA14_B)			F_(0, 0)	FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP8_27_24	FM(SD1_DAT2)		FM(SD2_DAT6)	FM(MSIOF1_SS1_G)	FM(NFDATA15_B)			F_(0, 0)	FM(TS_SDAT1_B)	FM(STP_ISD_1_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP8_31_28	FM(SD1_DAT3)		FM(SD2_DAT7)	FM(MSIOF1_SS2_G)	FM(NFRB_N_B)			F_(0, 0)	FM(TS_SDEN1_B)	FM(STP_ISEN_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP9_3_0		FM(SD2_CLK)		F_(0, 0)	FM(NFDATA8)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP9_7_4		FM(SD2_CMD)		F_(0, 0)	FM(NFDATA9)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP9_11_8	FM(SD2_DAT0)		F_(0, 0)	FM(NFDATA10)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP9_15_12	FM(SD2_DAT1)		F_(0, 0)	FM(NFDATA11)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP9_19_16	FM(SD2_DAT2)		F_(0, 0)	FM(NFDATA12)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP9_23_20	FM(SD2_DAT3)		F_(0, 0)	FM(NFDATA13)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP9_27_24	FM(SD2_DS)		F_(0, 0)	FM(NFALE)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(SATA_DEVSLP_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP9_31_28	FM(SD3_CLK)		F_(0, 0)	FM(NFWE_N)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP10_3_0	FM(SD3_CMD)		F_(0, 0)	FM(NFRE_N)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP10_7_4	FM(SD3_DAT0)		F_(0, 0)	FM(NFDATA0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP10_11_8	FM(SD3_DAT1)		F_(0, 0)	FM(NFDATA1)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP10_15_12	FM(SD3_DAT2)		F_(0, 0)	FM(NFDATA2)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP10_19_16	FM(SD3_DAT3)		F_(0, 0)	FM(NFDATA3)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP10_23_20	FM(SD3_DAT4)		FM(SD2_CD_A)	FM(NFDATA4)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP10_27_24	FM(SD3_DAT5)		FM(SD2_WP_A)	FM(NFDATA5)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP10_31_28	FM(SD3_DAT6)		FM(SD3_CD)	FM(NFDATA6)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP11_3_0	FM(SD3_DAT7)		FM(SD3_WP)	FM(NFDATA7)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP11_7_4	FM(SD3_DS)		F_(0, 0)	FM(NFCLE)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP11_11_8	FM(SD0_CD)		F_(0, 0)	FM(NFDATA14_A)		F_(0, 0)			FM(SCL2_B)	FM(SIM0_RST_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 
349 /* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
350 #define IP11_15_12	FM(SD0_WP)		F_(0, 0)	FM(NFDATA15_A)		F_(0, 0)			FM(SDA2_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP11_19_16	FM(SD1_CD)		F_(0, 0)	FM(NFRB_N_A)		F_(0, 0)			F_(0, 0)	FM(SIM0_CLK_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP11_23_20	FM(SD1_WP)		F_(0, 0)	FM(NFCE_N_A)		F_(0, 0)			F_(0, 0)	FM(SIM0_D_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP11_27_24	FM(SCK0)		FM(HSCK1_B)	FM(MSIOF1_SS2_B)	FM(AUDIO_CLKC_B)		FM(SDA2_A)	FM(SIM0_RST_B)	FM(STP_OPWM_0_C)	FM(RIF0_CLK_B)	F_(0, 0)		FM(ADICHS2)	FM(SCK5_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP11_31_28	FM(RX0)			FM(HRX1_B)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SCK0_C)	FM(STP_ISCLK_0_C)	FM(RIF0_D0_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP12_3_0	FM(TX0)			FM(HTX1_B)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)	FM(RIF0_D1_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP12_7_4	FM(CTS0_N)		FM(HCTS1_N_B)	FM(MSIOF1_SYNC_B)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)	FM(RIF1_SYNC_B)	FM(AUDIO_CLKOUT_C)	FM(ADICS_SAMP)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP12_11_8	FM(RTS0_N)		FM(HRTS1_N_B)	FM(MSIOF1_SS1_B)	FM(AUDIO_CLKA_B)		FM(SCL2_A)	F_(0, 0)	FM(STP_IVCXO27_1_C)	FM(RIF0_SYNC_B)	F_(0, 0)		FM(ADICHS1)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP12_15_12	FM(RX1_A)		FM(HRX1_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_C)	FM(STP_ISD_0_C)		FM(RIF1_CLK_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP12_19_16	FM(TX1_A)		FM(HTX1_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_C)	FM(STP_ISEN_0_C)	FM(RIF1_D0_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 #define IP12_23_20	FM(CTS1_N)		FM(HCTS1_N_A)	FM(MSIOF1_RXD_B)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN1_C)	FM(STP_ISEN_1_C)	FM(RIF1_D0_B)	F_(0, 0)		FM(ADIDATA)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361 #define IP12_27_24	FM(RTS1_N)		FM(HRTS1_N_A)	FM(MSIOF1_TXD_B)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_C)	FM(STP_ISD_1_C)		FM(RIF1_D1_B)	F_(0, 0)		FM(ADICHS0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362 #define IP12_31_28	FM(SCK2)		FM(SCIF_CLK_B)	FM(MSIOF1_SCK_B)	F_(0, 0)			F_(0, 0)	FM(TS_SCK1_C)	FM(STP_ISCLK_1_C)	FM(RIF1_CLK_B)	F_(0, 0)		FM(ADICLK)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 #define IP13_3_0	FM(TX2_A)		F_(0, 0)	F_(0, 0)		FM(SD2_CD_B)			FM(SCL1_A)	F_(0, 0)	FM(FMCLK_A)		FM(RIF1_D1_C)	F_(0, 0)		FM(FSO_CFE_0_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP13_7_4	FM(RX2_A)		F_(0, 0)	F_(0, 0)		FM(SD2_WP_B)			FM(SDA1_A)	F_(0, 0)	FM(FMIN_A)		FM(RIF1_SYNC_C)	F_(0, 0)		FM(FSO_CFE_1_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365 #define IP13_11_8	FM(HSCK0)		F_(0, 0)	FM(MSIOF1_SCK_D)	FM(AUDIO_CLKB_A)		FM(SSI_SDATA1_B)FM(TS_SCK0_D)	FM(STP_ISCLK_0_D)	FM(RIF0_CLK_C)	F_(0, 0)		F_(0, 0)	FM(RX5_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366 #define IP13_15_12	FM(HRX0)		F_(0, 0)	FM(MSIOF1_RXD_D)	F_(0, 0)			FM(SSI_SDATA2_B)FM(TS_SDEN0_D)	FM(STP_ISEN_0_D)	FM(RIF0_D0_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367 #define IP13_19_16	FM(HTX0)		F_(0, 0)	FM(MSIOF1_TXD_D)	F_(0, 0)			FM(SSI_SDATA9_B)FM(TS_SDAT0_D)	FM(STP_ISD_0_D)		FM(RIF0_D1_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368 #define IP13_23_20	FM(HCTS0_N)		FM(RX2_B)	FM(MSIOF1_SYNC_D)	F_(0, 0)			FM(SSI_SCK9_A)	FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)	FM(RIF0_SYNC_C)	FM(AUDIO_CLKOUT1_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369 #define IP13_27_24	FM(HRTS0_N)		FM(TX2_B)	FM(MSIOF1_SS1_D)	F_(0, 0)			FM(SSI_WS9_A)	F_(0, 0)	FM(STP_IVCXO27_0_D)	FM(BPFCLK_A)	FM(AUDIO_CLKOUT2_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370 #define IP13_31_28	FM(MSIOF0_SYNC)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(AUDIO_CLKOUT_A)	F_(0, 0)	FM(TX5_B)	F_(0, 0)	F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
371 #define IP14_3_0	FM(MSIOF0_SS1)		FM(RX5_A)	FM(NFWP_N_A)		FM(AUDIO_CLKA_C)		FM(SSI_SCK2_A)	F_(0, 0)	FM(STP_IVCXO27_0_C)	F_(0, 0)	FM(AUDIO_CLKOUT3_A)	F_(0, 0)	FM(TCLK1_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372 #define IP14_7_4	FM(MSIOF0_SS2)		FM(TX5_A)	FM(MSIOF1_SS2_D)	FM(AUDIO_CLKC_A)		FM(SSI_WS2_A)	F_(0, 0)	FM(STP_OPWM_0_D)	F_(0, 0)	FM(AUDIO_CLKOUT_D)	F_(0, 0)	FM(SPEEDIN_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373 #define IP14_11_8	FM(MLB_CLK)		F_(0, 0)	FM(MSIOF1_SCK_F)	F_(0, 0)			FM(SCL1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374 #define IP14_15_12	FM(MLB_SIG)		FM(RX1_B)	FM(MSIOF1_SYNC_F)	F_(0, 0)			FM(SDA1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375 #define IP14_19_16	FM(MLB_DAT)		FM(TX1_B)	FM(MSIOF1_RXD_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376 #define IP14_23_20	FM(SSI_SCK01239)	F_(0, 0)	FM(MSIOF1_TXD_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377 #define IP14_27_24	FM(SSI_WS01239)		F_(0, 0)	FM(MSIOF1_SS1_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378 
379 /* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
380 #define IP14_31_28	FM(SSI_SDATA0)		F_(0, 0)	FM(MSIOF1_SS2_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381 #define IP15_3_0	FM(SSI_SDATA1_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382 #define IP15_7_4	FM(SSI_SDATA2_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			FM(SSI_SCK1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
383 #define IP15_11_8	FM(SSI_SCK349)		F_(0, 0)	FM(MSIOF1_SS1_A)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_OPWM_0_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384 #define IP15_15_12	FM(SSI_WS349)		FM(HCTS2_N_A)	FM(MSIOF1_SS2_A)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_0_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
385 #define IP15_19_16	FM(SSI_SDATA3)		FM(HRTS2_N_A)	FM(MSIOF1_TXD_A)	F_(0, 0)			F_(0, 0)	FM(TS_SCK0_A)	FM(STP_ISCLK_0_A)	FM(RIF0_D1_A)	FM(RIF2_D0_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386 #define IP15_23_20	FM(SSI_SCK4)		FM(HRX2_A)	FM(MSIOF1_SCK_A)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_A)	FM(STP_ISD_0_A)		FM(RIF0_CLK_A)	FM(RIF2_CLK_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387 #define IP15_27_24	FM(SSI_WS4)		FM(HTX2_A)	FM(MSIOF1_SYNC_A)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_A)	FM(STP_ISEN_0_A)	FM(RIF0_SYNC_A)	FM(RIF2_SYNC_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388 #define IP15_31_28	FM(SSI_SDATA4)		FM(HSCK2_A)	FM(MSIOF1_RXD_A)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)	FM(RIF0_D0_A)	FM(RIF2_D1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389 #define IP16_3_0	FM(SSI_SCK6)		FM(USB2_PWEN)	F_(0, 0)		FM(SIM0_RST_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390 #define IP16_7_4	FM(SSI_WS6)		FM(USB2_OVC)	F_(0, 0)		FM(SIM0_D_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391 #define IP16_11_8	FM(SSI_SDATA6)		F_(0, 0)	F_(0, 0)		FM(SIM0_CLK_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(SATA_DEVSLP_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392 #define IP16_15_12	FM(SSI_SCK78)		FM(HRX2_B)	FM(MSIOF1_SCK_C)	F_(0, 0)			F_(0, 0)	FM(TS_SCK1_A)	FM(STP_ISCLK_1_A)	FM(RIF1_CLK_A)	FM(RIF3_CLK_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393 #define IP16_19_16	FM(SSI_WS78)		FM(HTX2_B)	FM(MSIOF1_SYNC_C)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_A)	FM(STP_ISD_1_A)		FM(RIF1_SYNC_A)	FM(RIF3_SYNC_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394 #define IP16_23_20	FM(SSI_SDATA7)		FM(HCTS2_N_B)	FM(MSIOF1_RXD_C)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN1_A)	FM(STP_ISEN_1_A)	FM(RIF1_D0_A)	FM(RIF3_D0_A)		F_(0, 0)	FM(TCLK2_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395 #define IP16_27_24	FM(SSI_SDATA8)		FM(HRTS2_N_B)	FM(MSIOF1_TXD_C)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)	FM(RIF1_D1_A)	FM(RIF3_D1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396 #define IP16_31_28	FM(SSI_SDATA9_A)	FM(HSCK2_B)	FM(MSIOF1_SS1_C)	FM(HSCK1_A)			FM(SSI_WS1_B)	FM(SCK1)	FM(STP_IVCXO27_1_A)	FM(SCK5_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397 #define IP17_3_0	FM(AUDIO_CLKA_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398 #define IP17_7_4	FM(AUDIO_CLKB_B)	FM(SCIF_CLK_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_1_D)	FM(REMOCON_A)	F_(0, 0)		F_(0, 0)	FM(TCLK1_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
399 #define IP17_11_8	FM(USB0_PWEN)		F_(0, 0)	F_(0, 0)		FM(SIM0_RST_C)			F_(0, 0)	FM(TS_SCK1_D)	FM(STP_ISCLK_1_D)	FM(BPFCLK_B)	FM(RIF3_CLK_B)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
400 #define IP17_15_12	FM(USB0_OVC)		F_(0, 0)	F_(0, 0)		FM(SIM0_D_C)			F_(0, 0)	FM(TS_SDAT1_D)	FM(STP_ISD_1_D)		F_(0, 0)	FM(RIF3_SYNC_B)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
401 #define IP17_19_16	FM(USB1_PWEN)		F_(0, 0)	F_(0, 0)		FM(SIM0_CLK_C)			FM(SSI_SCK1_A)	FM(TS_SCK0_E)	FM(STP_ISCLK_0_E)	FM(FMCLK_B)	FM(RIF2_CLK_B)		F_(0, 0)	FM(SPEEDIN_A)	F_(0, 0)	F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
402 #define IP17_23_20	FM(USB1_OVC)		F_(0, 0)	FM(MSIOF1_SS2_C)	F_(0, 0)			FM(SSI_WS1_A)	FM(TS_SDAT0_E)	FM(STP_ISD_0_E)		FM(FMIN_B)	FM(RIF2_SYNC_B)		F_(0, 0)	FM(REMOCON_B)	F_(0, 0)	F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
403 #define IP17_27_24	FM(USB30_PWEN)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT_B)		FM(SSI_SCK2_B)	FM(TS_SDEN1_D)	FM(STP_ISEN_1_D)	FM(STP_OPWM_0_E)FM(RIF3_D0_B)		F_(0, 0)	FM(TCLK2_B)	FM(TPU0TO0)	FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
404 #define IP17_31_28	FM(USB30_OVC)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT1_B)		FM(SSI_WS2_B)	FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)	FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)	F_(0, 0)	FM(FSO_TOE_N)	FM(TPU0TO1)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
405 #define IP18_3_0	FM(USB2_CH3_PWEN)	F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT2_B)		FM(SSI_SCK9_B)	FM(TS_SDEN0_E)	FM(STP_ISEN_0_E)	F_(0, 0)	FM(RIF2_D0_B)		F_(0, 0)	F_(0, 0)	FM(TPU0TO2)	FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
406 #define IP18_7_4	FM(USB2_CH3_OVC)	F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT3_B)		FM(SSI_WS9_B)	FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)	F_(0, 0)	FM(RIF2_D1_B)		F_(0, 0)	F_(0, 0)	FM(TPU0TO3)	FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
407 
408 #define PINMUX_GPSR	\
409 \
410 												GPSR6_31 \
411 												GPSR6_30 \
412 												GPSR6_29 \
413 		GPSR1_28									GPSR6_28 \
414 		GPSR1_27									GPSR6_27 \
415 		GPSR1_26									GPSR6_26 \
416 		GPSR1_25							GPSR5_25	GPSR6_25 \
417 		GPSR1_24							GPSR5_24	GPSR6_24 \
418 		GPSR1_23							GPSR5_23	GPSR6_23 \
419 		GPSR1_22							GPSR5_22	GPSR6_22 \
420 		GPSR1_21							GPSR5_21	GPSR6_21 \
421 		GPSR1_20							GPSR5_20	GPSR6_20 \
422 		GPSR1_19							GPSR5_19	GPSR6_19 \
423 		GPSR1_18							GPSR5_18	GPSR6_18 \
424 		GPSR1_17					GPSR4_17	GPSR5_17	GPSR6_17 \
425 		GPSR1_16					GPSR4_16	GPSR5_16	GPSR6_16 \
426 GPSR0_15	GPSR1_15			GPSR3_15	GPSR4_15	GPSR5_15	GPSR6_15 \
427 GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14	GPSR4_14	GPSR5_14	GPSR6_14 \
428 GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13	GPSR4_13	GPSR5_13	GPSR6_13 \
429 GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12	GPSR4_12	GPSR5_12	GPSR6_12 \
430 GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11	GPSR4_11	GPSR5_11	GPSR6_11 \
431 GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10	GPSR4_10	GPSR5_10	GPSR6_10 \
432 GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9		GPSR4_9		GPSR5_9		GPSR6_9 \
433 GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8		GPSR4_8		GPSR5_8		GPSR6_8 \
434 GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7		GPSR4_7		GPSR5_7		GPSR6_7 \
435 GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6		GPSR4_6		GPSR5_6		GPSR6_6 \
436 GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		GPSR4_5		GPSR5_5		GPSR6_5 \
437 GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		GPSR4_4		GPSR5_4		GPSR6_4 \
438 GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		GPSR4_3		GPSR5_3		GPSR6_3		GPSR7_3 \
439 GPSR0_2		GPSR1_2		GPSR2_2		GPSR3_2		GPSR4_2		GPSR5_2		GPSR6_2		GPSR7_2 \
440 GPSR0_1		GPSR1_1		GPSR2_1		GPSR3_1		GPSR4_1		GPSR5_1		GPSR6_1		GPSR7_1 \
441 GPSR0_0		GPSR1_0		GPSR2_0		GPSR3_0		GPSR4_0		GPSR5_0		GPSR6_0		GPSR7_0
442 
443 #define PINMUX_IPSR				\
444 \
445 FM(IP0_3_0)	IP0_3_0		FM(IP1_3_0)	IP1_3_0		FM(IP2_3_0)	IP2_3_0		FM(IP3_3_0)	IP3_3_0 \
446 FM(IP0_7_4)	IP0_7_4		FM(IP1_7_4)	IP1_7_4		FM(IP2_7_4)	IP2_7_4		FM(IP3_7_4)	IP3_7_4 \
447 FM(IP0_11_8)	IP0_11_8	FM(IP1_11_8)	IP1_11_8	FM(IP2_11_8)	IP2_11_8	FM(IP3_11_8)	IP3_11_8 \
448 FM(IP0_15_12)	IP0_15_12	FM(IP1_15_12)	IP1_15_12	FM(IP2_15_12)	IP2_15_12	FM(IP3_15_12)	IP3_15_12 \
449 FM(IP0_19_16)	IP0_19_16	FM(IP1_19_16)	IP1_19_16	FM(IP2_19_16)	IP2_19_16	FM(IP3_19_16)	IP3_19_16 \
450 FM(IP0_23_20)	IP0_23_20	FM(IP1_23_20)	IP1_23_20	FM(IP2_23_20)	IP2_23_20	FM(IP3_23_20)	IP3_23_20 \
451 FM(IP0_27_24)	IP0_27_24	FM(IP1_27_24)	IP1_27_24	FM(IP2_27_24)	IP2_27_24	FM(IP3_27_24)	IP3_27_24 \
452 FM(IP0_31_28)	IP0_31_28	FM(IP1_31_28)	IP1_31_28	FM(IP2_31_28)	IP2_31_28	FM(IP3_31_28)	IP3_31_28 \
453 \
454 FM(IP4_3_0)	IP4_3_0		FM(IP5_3_0)	IP5_3_0		FM(IP6_3_0)	IP6_3_0		FM(IP7_3_0)	IP7_3_0 \
455 FM(IP4_7_4)	IP4_7_4		FM(IP5_7_4)	IP5_7_4		FM(IP6_7_4)	IP6_7_4		FM(IP7_7_4)	IP7_7_4 \
456 FM(IP4_11_8)	IP4_11_8	FM(IP5_11_8)	IP5_11_8	FM(IP6_11_8)	IP6_11_8	FM(IP7_11_8)	IP7_11_8 \
457 FM(IP4_15_12)	IP4_15_12	FM(IP5_15_12)	IP5_15_12	FM(IP6_15_12)	IP6_15_12 \
458 FM(IP4_19_16)	IP4_19_16	FM(IP5_19_16)	IP5_19_16	FM(IP6_19_16)	IP6_19_16	FM(IP7_19_16)	IP7_19_16 \
459 FM(IP4_23_20)	IP4_23_20	FM(IP5_23_20)	IP5_23_20	FM(IP6_23_20)	IP6_23_20	FM(IP7_23_20)	IP7_23_20 \
460 FM(IP4_27_24)	IP4_27_24	FM(IP5_27_24)	IP5_27_24	FM(IP6_27_24)	IP6_27_24	FM(IP7_27_24)	IP7_27_24 \
461 FM(IP4_31_28)	IP4_31_28	FM(IP5_31_28)	IP5_31_28	FM(IP6_31_28)	IP6_31_28	FM(IP7_31_28)	IP7_31_28 \
462 \
463 FM(IP8_3_0)	IP8_3_0		FM(IP9_3_0)	IP9_3_0		FM(IP10_3_0)	IP10_3_0	FM(IP11_3_0)	IP11_3_0 \
464 FM(IP8_7_4)	IP8_7_4		FM(IP9_7_4)	IP9_7_4		FM(IP10_7_4)	IP10_7_4	FM(IP11_7_4)	IP11_7_4 \
465 FM(IP8_11_8)	IP8_11_8	FM(IP9_11_8)	IP9_11_8	FM(IP10_11_8)	IP10_11_8	FM(IP11_11_8)	IP11_11_8 \
466 FM(IP8_15_12)	IP8_15_12	FM(IP9_15_12)	IP9_15_12	FM(IP10_15_12)	IP10_15_12	FM(IP11_15_12)	IP11_15_12 \
467 FM(IP8_19_16)	IP8_19_16	FM(IP9_19_16)	IP9_19_16	FM(IP10_19_16)	IP10_19_16	FM(IP11_19_16)	IP11_19_16 \
468 FM(IP8_23_20)	IP8_23_20	FM(IP9_23_20)	IP9_23_20	FM(IP10_23_20)	IP10_23_20	FM(IP11_23_20)	IP11_23_20 \
469 FM(IP8_27_24)	IP8_27_24	FM(IP9_27_24)	IP9_27_24	FM(IP10_27_24)	IP10_27_24	FM(IP11_27_24)	IP11_27_24 \
470 FM(IP8_31_28)	IP8_31_28	FM(IP9_31_28)	IP9_31_28	FM(IP10_31_28)	IP10_31_28	FM(IP11_31_28)	IP11_31_28 \
471 \
472 FM(IP12_3_0)	IP12_3_0	FM(IP13_3_0)	IP13_3_0	FM(IP14_3_0)	IP14_3_0	FM(IP15_3_0)	IP15_3_0 \
473 FM(IP12_7_4)	IP12_7_4	FM(IP13_7_4)	IP13_7_4	FM(IP14_7_4)	IP14_7_4	FM(IP15_7_4)	IP15_7_4 \
474 FM(IP12_11_8)	IP12_11_8	FM(IP13_11_8)	IP13_11_8	FM(IP14_11_8)	IP14_11_8	FM(IP15_11_8)	IP15_11_8 \
475 FM(IP12_15_12)	IP12_15_12	FM(IP13_15_12)	IP13_15_12	FM(IP14_15_12)	IP14_15_12	FM(IP15_15_12)	IP15_15_12 \
476 FM(IP12_19_16)	IP12_19_16	FM(IP13_19_16)	IP13_19_16	FM(IP14_19_16)	IP14_19_16	FM(IP15_19_16)	IP15_19_16 \
477 FM(IP12_23_20)	IP12_23_20	FM(IP13_23_20)	IP13_23_20	FM(IP14_23_20)	IP14_23_20	FM(IP15_23_20)	IP15_23_20 \
478 FM(IP12_27_24)	IP12_27_24	FM(IP13_27_24)	IP13_27_24	FM(IP14_27_24)	IP14_27_24	FM(IP15_27_24)	IP15_27_24 \
479 FM(IP12_31_28)	IP12_31_28	FM(IP13_31_28)	IP13_31_28	FM(IP14_31_28)	IP14_31_28	FM(IP15_31_28)	IP15_31_28 \
480 \
481 FM(IP16_3_0)	IP16_3_0	FM(IP17_3_0)	IP17_3_0	FM(IP18_3_0)	IP18_3_0 \
482 FM(IP16_7_4)	IP16_7_4	FM(IP17_7_4)	IP17_7_4	FM(IP18_7_4)	IP18_7_4 \
483 FM(IP16_11_8)	IP16_11_8	FM(IP17_11_8)	IP17_11_8 \
484 FM(IP16_15_12)	IP16_15_12	FM(IP17_15_12)	IP17_15_12 \
485 FM(IP16_19_16)	IP16_19_16	FM(IP17_19_16)	IP17_19_16 \
486 FM(IP16_23_20)	IP16_23_20	FM(IP17_23_20)	IP17_23_20 \
487 FM(IP16_27_24)	IP16_27_24	FM(IP17_27_24)	IP17_27_24 \
488 FM(IP16_31_28)	IP16_31_28	FM(IP17_31_28)	IP17_31_28
489 
490 /* MOD_SEL0 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
491 #define MOD_SEL0_31_30_29	FM(SEL_MSIOF3_0)	FM(SEL_MSIOF3_1)	FM(SEL_MSIOF3_2)	FM(SEL_MSIOF3_3)	FM(SEL_MSIOF3_4)	F_(0, 0)		F_(0, 0)		F_(0, 0)
492 #define MOD_SEL0_28_27		FM(SEL_MSIOF2_0)	FM(SEL_MSIOF2_1)	FM(SEL_MSIOF2_2)	FM(SEL_MSIOF2_3)
493 #define MOD_SEL0_26_25_24	FM(SEL_MSIOF1_0)	FM(SEL_MSIOF1_1)	FM(SEL_MSIOF1_2)	FM(SEL_MSIOF1_3)	FM(SEL_MSIOF1_4)	FM(SEL_MSIOF1_5)	FM(SEL_MSIOF1_6)	F_(0, 0)
494 #define MOD_SEL0_23		FM(SEL_LBSC_0)		FM(SEL_LBSC_1)
495 #define MOD_SEL0_22		FM(SEL_IEBUS_0)		FM(SEL_IEBUS_1)
496 #define MOD_SEL0_21		FM(SEL_I2C2_0)		FM(SEL_I2C2_1)
497 #define MOD_SEL0_20		FM(SEL_I2C1_0)		FM(SEL_I2C1_1)
498 #define MOD_SEL0_19		FM(SEL_HSCIF4_0)	FM(SEL_HSCIF4_1)
499 #define MOD_SEL0_18_17		FM(SEL_HSCIF3_0)	FM(SEL_HSCIF3_1)	FM(SEL_HSCIF3_2)	FM(SEL_HSCIF3_3)
500 #define MOD_SEL0_16		FM(SEL_HSCIF1_0)	FM(SEL_HSCIF1_1)
501 #define MOD_SEL0_14_13		FM(SEL_HSCIF2_0)	FM(SEL_HSCIF2_1)	FM(SEL_HSCIF2_2)	F_(0, 0)
502 #define MOD_SEL0_12		FM(SEL_ETHERAVB_0)	FM(SEL_ETHERAVB_1)
503 #define MOD_SEL0_11		FM(SEL_DRIF3_0)		FM(SEL_DRIF3_1)
504 #define MOD_SEL0_10		FM(SEL_DRIF2_0)		FM(SEL_DRIF2_1)
505 #define MOD_SEL0_9_8		FM(SEL_DRIF1_0)		FM(SEL_DRIF1_1)		FM(SEL_DRIF1_2)		F_(0, 0)
506 #define MOD_SEL0_7_6		FM(SEL_DRIF0_0)		FM(SEL_DRIF0_1)		FM(SEL_DRIF0_2)		F_(0, 0)
507 #define MOD_SEL0_5		FM(SEL_CANFD0_0)	FM(SEL_CANFD0_1)
508 #define MOD_SEL0_4_3		FM(SEL_ADGA_0)		FM(SEL_ADGA_1)		FM(SEL_ADGA_2)		FM(SEL_ADGA_3)
509 
510 /* MOD_SEL1 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
511 #define MOD_SEL1_31_30		FM(SEL_TSIF1_0)		FM(SEL_TSIF1_1)		FM(SEL_TSIF1_2)		FM(SEL_TSIF1_3)
512 #define MOD_SEL1_29_28_27	FM(SEL_TSIF0_0)		FM(SEL_TSIF0_1)		FM(SEL_TSIF0_2)		FM(SEL_TSIF0_3)		FM(SEL_TSIF0_4)		F_(0, 0)		F_(0, 0)		F_(0, 0)
513 #define MOD_SEL1_26		FM(SEL_TIMER_TMU1_0)	FM(SEL_TIMER_TMU1_1)
514 #define MOD_SEL1_25_24		FM(SEL_SSP1_1_0)	FM(SEL_SSP1_1_1)	FM(SEL_SSP1_1_2)	FM(SEL_SSP1_1_3)
515 #define MOD_SEL1_23_22_21	FM(SEL_SSP1_0_0)	FM(SEL_SSP1_0_1)	FM(SEL_SSP1_0_2)	FM(SEL_SSP1_0_3)	FM(SEL_SSP1_0_4)	F_(0, 0)		F_(0, 0)		F_(0, 0)
516 #define MOD_SEL1_20		FM(SEL_SSI1_0)		FM(SEL_SSI1_1)
517 #define MOD_SEL1_19		FM(SEL_SPEED_PULSE_0)	FM(SEL_SPEED_PULSE_1)
518 #define MOD_SEL1_18_17		FM(SEL_SIMCARD_0)	FM(SEL_SIMCARD_1)	FM(SEL_SIMCARD_2)	FM(SEL_SIMCARD_3)
519 #define MOD_SEL1_16		FM(SEL_SDHI2_0)		FM(SEL_SDHI2_1)
520 #define MOD_SEL1_15_14		FM(SEL_SCIF4_0)		FM(SEL_SCIF4_1)		FM(SEL_SCIF4_2)		F_(0, 0)
521 #define MOD_SEL1_13		FM(SEL_SCIF3_0)		FM(SEL_SCIF3_1)
522 #define MOD_SEL1_12		FM(SEL_SCIF2_0)		FM(SEL_SCIF2_1)
523 #define MOD_SEL1_11		FM(SEL_SCIF1_0)		FM(SEL_SCIF1_1)
524 #define MOD_SEL1_10		FM(SEL_SCIF_0)		FM(SEL_SCIF_1)
525 #define MOD_SEL1_9		FM(SEL_REMOCON_0)	FM(SEL_REMOCON_1)
526 #define MOD_SEL1_6		FM(SEL_RCAN0_0)		FM(SEL_RCAN0_1)
527 #define MOD_SEL1_5		FM(SEL_PWM6_0)		FM(SEL_PWM6_1)
528 #define MOD_SEL1_4		FM(SEL_PWM5_0)		FM(SEL_PWM5_1)
529 #define MOD_SEL1_3		FM(SEL_PWM4_0)		FM(SEL_PWM4_1)
530 #define MOD_SEL1_2		FM(SEL_PWM3_0)		FM(SEL_PWM3_1)
531 #define MOD_SEL1_1		FM(SEL_PWM2_0)		FM(SEL_PWM2_1)
532 #define MOD_SEL1_0		FM(SEL_PWM1_0)		FM(SEL_PWM1_1)
533 
534 /* MOD_SEL2 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */
535 #define MOD_SEL2_31		FM(I2C_SEL_5_0)		FM(I2C_SEL_5_1)
536 #define MOD_SEL2_30		FM(I2C_SEL_3_0)		FM(I2C_SEL_3_1)
537 #define MOD_SEL2_29		FM(I2C_SEL_0_0)		FM(I2C_SEL_0_1)
538 #define MOD_SEL2_28_27		FM(SEL_FM_0)		FM(SEL_FM_1)		FM(SEL_FM_2)		FM(SEL_FM_3)
539 #define MOD_SEL2_26		FM(SEL_SCIF5_0)		FM(SEL_SCIF5_1)
540 #define MOD_SEL2_25_24_23	FM(SEL_I2C6_0)		FM(SEL_I2C6_1)		FM(SEL_I2C6_2)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)
541 #define MOD_SEL2_21		FM(SEL_SSI2_0)		FM(SEL_SSI2_1)
542 #define MOD_SEL2_20		FM(SEL_SSI9_0)		FM(SEL_SSI9_1)
543 #define MOD_SEL2_19		FM(SEL_TIMER_TMU2_0)	FM(SEL_TIMER_TMU2_1)
544 #define MOD_SEL2_18		FM(SEL_ADGB_0)		FM(SEL_ADGB_1)
545 #define MOD_SEL2_17		FM(SEL_ADGC_0)		FM(SEL_ADGC_1)
546 #define MOD_SEL2_0		FM(SEL_VIN4_0)		FM(SEL_VIN4_1)
547 
548 #define PINMUX_MOD_SELS	\
549 \
550 MOD_SEL0_31_30_29	MOD_SEL1_31_30		MOD_SEL2_31 \
551 						MOD_SEL2_30 \
552 			MOD_SEL1_29_28_27	MOD_SEL2_29 \
553 MOD_SEL0_28_27					MOD_SEL2_28_27 \
554 MOD_SEL0_26_25_24	MOD_SEL1_26		MOD_SEL2_26 \
555 			MOD_SEL1_25_24		MOD_SEL2_25_24_23 \
556 MOD_SEL0_23		MOD_SEL1_23_22_21 \
557 MOD_SEL0_22 \
558 MOD_SEL0_21					MOD_SEL2_21 \
559 MOD_SEL0_20		MOD_SEL1_20		MOD_SEL2_20 \
560 MOD_SEL0_19		MOD_SEL1_19		MOD_SEL2_19 \
561 MOD_SEL0_18_17		MOD_SEL1_18_17		MOD_SEL2_18 \
562 						MOD_SEL2_17 \
563 MOD_SEL0_16		MOD_SEL1_16 \
564 			MOD_SEL1_15_14 \
565 MOD_SEL0_14_13 \
566 			MOD_SEL1_13 \
567 MOD_SEL0_12		MOD_SEL1_12 \
568 MOD_SEL0_11		MOD_SEL1_11 \
569 MOD_SEL0_10		MOD_SEL1_10 \
570 MOD_SEL0_9_8		MOD_SEL1_9 \
571 MOD_SEL0_7_6 \
572 			MOD_SEL1_6 \
573 MOD_SEL0_5		MOD_SEL1_5 \
574 MOD_SEL0_4_3		MOD_SEL1_4 \
575 			MOD_SEL1_3 \
576 			MOD_SEL1_2 \
577 			MOD_SEL1_1 \
578 			MOD_SEL1_0		MOD_SEL2_0
579 
580 /*
581  * These pins are not able to be muxed but have other properties
582  * that can be set, such as drive-strength or pull-up/pull-down enable.
583  */
584 #define PINMUX_STATIC \
585 	FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
586 	FM(QSPI0_IO2) FM(QSPI0_IO3) \
587 	FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
588 	FM(QSPI1_IO2) FM(QSPI1_IO3) \
589 	FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
590 	FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
591 	FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
592 	FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
593 	FM(PRESETOUT) \
594 	FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
595 	FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
596 
597 #define PINMUX_PHYS \
598 	FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
599 
600 enum {
601 	PINMUX_RESERVED = 0,
602 
603 	PINMUX_DATA_BEGIN,
604 	GP_ALL(DATA),
605 	PINMUX_DATA_END,
606 
607 #define F_(x, y)
608 #define FM(x)	FN_##x,
609 	PINMUX_FUNCTION_BEGIN,
610 	GP_ALL(FN),
611 	PINMUX_GPSR
612 	PINMUX_IPSR
613 	PINMUX_MOD_SELS
614 	PINMUX_FUNCTION_END,
615 #undef F_
616 #undef FM
617 
618 #define F_(x, y)
619 #define FM(x)	x##_MARK,
620 	PINMUX_MARK_BEGIN,
621 	PINMUX_GPSR
622 	PINMUX_IPSR
623 	PINMUX_MOD_SELS
624 	PINMUX_STATIC
625 	PINMUX_PHYS
626 	PINMUX_MARK_END,
627 #undef F_
628 #undef FM
629 };
630 
631 static const u16 pinmux_data[] = {
632 	PINMUX_DATA_GP_ALL(),
633 
634 	PINMUX_SINGLE(AVS1),
635 	PINMUX_SINGLE(AVS2),
636 	PINMUX_SINGLE(CLKOUT),
637 	PINMUX_SINGLE(GP7_02),
638 	PINMUX_SINGLE(GP7_03),
639 	PINMUX_SINGLE(MSIOF0_RXD),
640 	PINMUX_SINGLE(MSIOF0_SCK),
641 	PINMUX_SINGLE(MSIOF0_TXD),
642 	PINMUX_SINGLE(SSI_SCK5),
643 	PINMUX_SINGLE(SSI_SDATA5),
644 	PINMUX_SINGLE(SSI_WS5),
645 
646 	/* IPSR0 */
647 	PINMUX_IPSR_GPSR(IP0_3_0,	AVB_MDC),
648 	PINMUX_IPSR_MSEL(IP0_3_0,	MSIOF2_SS2_C,		SEL_MSIOF2_2),
649 
650 	PINMUX_IPSR_GPSR(IP0_7_4,	AVB_MAGIC),
651 	PINMUX_IPSR_MSEL(IP0_7_4,	MSIOF2_SS1_C,		SEL_MSIOF2_2),
652 	PINMUX_IPSR_MSEL(IP0_7_4,	SCK4_A,			SEL_SCIF4_0),
653 
654 	PINMUX_IPSR_GPSR(IP0_11_8,	AVB_PHY_INT),
655 	PINMUX_IPSR_MSEL(IP0_11_8,	MSIOF2_SYNC_C,		SEL_MSIOF2_2),
656 	PINMUX_IPSR_MSEL(IP0_11_8,	RX4_A,			SEL_SCIF4_0),
657 
658 	PINMUX_IPSR_GPSR(IP0_15_12,	AVB_LINK),
659 	PINMUX_IPSR_MSEL(IP0_15_12,	MSIOF2_SCK_C,		SEL_MSIOF2_2),
660 	PINMUX_IPSR_MSEL(IP0_15_12,	TX4_A,			SEL_SCIF4_0),
661 
662 	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A,	I2C_SEL_5_0,	SEL_ETHERAVB_0),
663 	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C,		I2C_SEL_5_0,	SEL_MSIOF2_2),
664 	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A,		I2C_SEL_5_0,	SEL_SCIF4_0),
665 	PINMUX_IPSR_MSEL(IP0_19_16,	FSCLKST2_N_A,		I2C_SEL_5_0),
666 	PINMUX_IPSR_PHYS(IP0_19_16,     SCL5,                   I2C_SEL_5_1),
667 
668 	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A,	I2C_SEL_5_0,	SEL_ETHERAVB_0),
669 	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C,		I2C_SEL_5_0,	SEL_MSIOF2_2),
670 	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A,		I2C_SEL_5_0,	SEL_SCIF4_0),
671 	PINMUX_IPSR_PHYS(IP0_23_20,	SDA5,			I2C_SEL_5_1),
672 
673 	PINMUX_IPSR_GPSR(IP0_27_24,	IRQ0),
674 	PINMUX_IPSR_GPSR(IP0_27_24,	QPOLB),
675 	PINMUX_IPSR_GPSR(IP0_27_24,	DU_CDE),
676 	PINMUX_IPSR_MSEL(IP0_27_24,	VI4_DATA0_B,		SEL_VIN4_1),
677 	PINMUX_IPSR_MSEL(IP0_27_24,	CAN0_TX_B,		SEL_RCAN0_1),
678 	PINMUX_IPSR_MSEL(IP0_27_24,	CANFD0_TX_B,		SEL_CANFD0_1),
679 	PINMUX_IPSR_MSEL(IP0_27_24,	MSIOF3_SS2_E,		SEL_MSIOF3_4),
680 
681 	PINMUX_IPSR_GPSR(IP0_31_28,	IRQ1),
682 	PINMUX_IPSR_GPSR(IP0_31_28,	QPOLA),
683 	PINMUX_IPSR_GPSR(IP0_31_28,	DU_DISP),
684 	PINMUX_IPSR_MSEL(IP0_31_28,	VI4_DATA1_B,		SEL_VIN4_1),
685 	PINMUX_IPSR_MSEL(IP0_31_28,	CAN0_RX_B,		SEL_RCAN0_1),
686 	PINMUX_IPSR_MSEL(IP0_31_28,	CANFD0_RX_B,		SEL_CANFD0_1),
687 	PINMUX_IPSR_MSEL(IP0_31_28,	MSIOF3_SS1_E,		SEL_MSIOF3_4),
688 
689 	/* IPSR1 */
690 	PINMUX_IPSR_GPSR(IP1_3_0,	IRQ2),
691 	PINMUX_IPSR_GPSR(IP1_3_0,	QCPV_QDE),
692 	PINMUX_IPSR_GPSR(IP1_3_0,	DU_EXODDF_DU_ODDF_DISP_CDE),
693 	PINMUX_IPSR_MSEL(IP1_3_0,	VI4_DATA2_B,		SEL_VIN4_1),
694 	PINMUX_IPSR_MSEL(IP1_3_0,	PWM3_B,			SEL_PWM3_1),
695 	PINMUX_IPSR_MSEL(IP1_3_0,	MSIOF3_SYNC_E,		SEL_MSIOF3_4),
696 
697 	PINMUX_IPSR_GPSR(IP1_7_4,	IRQ3),
698 	PINMUX_IPSR_GPSR(IP1_7_4,	QSTVB_QVE),
699 	PINMUX_IPSR_GPSR(IP1_7_4,	DU_DOTCLKOUT1),
700 	PINMUX_IPSR_MSEL(IP1_7_4,	VI4_DATA3_B,		SEL_VIN4_1),
701 	PINMUX_IPSR_MSEL(IP1_7_4,	PWM4_B,			SEL_PWM4_1),
702 	PINMUX_IPSR_MSEL(IP1_7_4,	MSIOF3_SCK_E,		SEL_MSIOF3_4),
703 
704 	PINMUX_IPSR_GPSR(IP1_11_8,	IRQ4),
705 	PINMUX_IPSR_GPSR(IP1_11_8,	QSTH_QHS),
706 	PINMUX_IPSR_GPSR(IP1_11_8,	DU_EXHSYNC_DU_HSYNC),
707 	PINMUX_IPSR_MSEL(IP1_11_8,	VI4_DATA4_B,		SEL_VIN4_1),
708 	PINMUX_IPSR_MSEL(IP1_11_8,	PWM5_B,			SEL_PWM5_1),
709 	PINMUX_IPSR_MSEL(IP1_11_8,	MSIOF3_RXD_E,		SEL_MSIOF3_4),
710 
711 	PINMUX_IPSR_GPSR(IP1_15_12,	IRQ5),
712 	PINMUX_IPSR_GPSR(IP1_15_12,	QSTB_QHE),
713 	PINMUX_IPSR_GPSR(IP1_15_12,	DU_EXVSYNC_DU_VSYNC),
714 	PINMUX_IPSR_MSEL(IP1_15_12,	VI4_DATA5_B,		SEL_VIN4_1),
715 	PINMUX_IPSR_MSEL(IP1_15_12,	PWM6_B,			SEL_PWM6_1),
716 	PINMUX_IPSR_GPSR(IP1_15_12,	FSCLKST2_N_B),
717 	PINMUX_IPSR_MSEL(IP1_15_12,	MSIOF3_TXD_E,		SEL_MSIOF3_4),
718 
719 	PINMUX_IPSR_GPSR(IP1_19_16,	PWM0),
720 	PINMUX_IPSR_GPSR(IP1_19_16,	AVB_AVTP_PPS),
721 	PINMUX_IPSR_MSEL(IP1_19_16,	VI4_DATA6_B,		SEL_VIN4_1),
722 	PINMUX_IPSR_MSEL(IP1_19_16,	IECLK_B,		SEL_IEBUS_1),
723 
724 	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A,		I2C_SEL_3_0,	SEL_PWM1_0),
725 	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D,		I2C_SEL_3_0,	SEL_HSCIF3_3),
726 	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B,		I2C_SEL_3_0,	SEL_VIN4_1),
727 	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B,		I2C_SEL_3_0,	SEL_IEBUS_1),
728 	PINMUX_IPSR_PHYS(IP1_23_20,	SCL3,			I2C_SEL_3_1),
729 
730 	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A,		I2C_SEL_3_0,	SEL_PWM2_0),
731 	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D,		I2C_SEL_3_0,	SEL_HSCIF3_3),
732 	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B,		I2C_SEL_3_0,	SEL_IEBUS_1),
733 	PINMUX_IPSR_PHYS(IP1_27_24,	SDA3,			I2C_SEL_3_1),
734 
735 	PINMUX_IPSR_GPSR(IP1_31_28,	A0),
736 	PINMUX_IPSR_GPSR(IP1_31_28,	LCDOUT16),
737 	PINMUX_IPSR_MSEL(IP1_31_28,	MSIOF3_SYNC_B,		SEL_MSIOF3_1),
738 	PINMUX_IPSR_GPSR(IP1_31_28,	VI4_DATA8),
739 	PINMUX_IPSR_GPSR(IP1_31_28,	DU_DB0),
740 	PINMUX_IPSR_MSEL(IP1_31_28,	PWM3_A,			SEL_PWM3_0),
741 
742 	/* IPSR2 */
743 	PINMUX_IPSR_GPSR(IP2_3_0,	A1),
744 	PINMUX_IPSR_GPSR(IP2_3_0,	LCDOUT17),
745 	PINMUX_IPSR_MSEL(IP2_3_0,	MSIOF3_TXD_B,		SEL_MSIOF3_1),
746 	PINMUX_IPSR_GPSR(IP2_3_0,	VI4_DATA9),
747 	PINMUX_IPSR_GPSR(IP2_3_0,	DU_DB1),
748 	PINMUX_IPSR_MSEL(IP2_3_0,	PWM4_A,			SEL_PWM4_0),
749 
750 	PINMUX_IPSR_GPSR(IP2_7_4,	A2),
751 	PINMUX_IPSR_GPSR(IP2_7_4,	LCDOUT18),
752 	PINMUX_IPSR_MSEL(IP2_7_4,	MSIOF3_SCK_B,		SEL_MSIOF3_1),
753 	PINMUX_IPSR_GPSR(IP2_7_4,	VI4_DATA10),
754 	PINMUX_IPSR_GPSR(IP2_7_4,	DU_DB2),
755 	PINMUX_IPSR_MSEL(IP2_7_4,	PWM5_A,			SEL_PWM5_0),
756 
757 	PINMUX_IPSR_GPSR(IP2_11_8,	A3),
758 	PINMUX_IPSR_GPSR(IP2_11_8,	LCDOUT19),
759 	PINMUX_IPSR_MSEL(IP2_11_8,	MSIOF3_RXD_B,		SEL_MSIOF3_1),
760 	PINMUX_IPSR_GPSR(IP2_11_8,	VI4_DATA11),
761 	PINMUX_IPSR_GPSR(IP2_11_8,	DU_DB3),
762 	PINMUX_IPSR_MSEL(IP2_11_8,	PWM6_A,			SEL_PWM6_0),
763 
764 	PINMUX_IPSR_GPSR(IP2_15_12,	A4),
765 	PINMUX_IPSR_GPSR(IP2_15_12,	LCDOUT20),
766 	PINMUX_IPSR_MSEL(IP2_15_12,	MSIOF3_SS1_B,		SEL_MSIOF3_1),
767 	PINMUX_IPSR_GPSR(IP2_15_12,	VI4_DATA12),
768 	PINMUX_IPSR_GPSR(IP2_15_12,	VI5_DATA12),
769 	PINMUX_IPSR_GPSR(IP2_15_12,	DU_DB4),
770 
771 	PINMUX_IPSR_GPSR(IP2_19_16,	A5),
772 	PINMUX_IPSR_GPSR(IP2_19_16,	LCDOUT21),
773 	PINMUX_IPSR_MSEL(IP2_19_16,	MSIOF3_SS2_B,		SEL_MSIOF3_1),
774 	PINMUX_IPSR_MSEL(IP2_19_16,	SCK4_B,			SEL_SCIF4_1),
775 	PINMUX_IPSR_GPSR(IP2_19_16,	VI4_DATA13),
776 	PINMUX_IPSR_GPSR(IP2_19_16,	VI5_DATA13),
777 	PINMUX_IPSR_GPSR(IP2_19_16,	DU_DB5),
778 
779 	PINMUX_IPSR_GPSR(IP2_23_20,	A6),
780 	PINMUX_IPSR_GPSR(IP2_23_20,	LCDOUT22),
781 	PINMUX_IPSR_MSEL(IP2_23_20,	MSIOF2_SS1_A,		SEL_MSIOF2_0),
782 	PINMUX_IPSR_MSEL(IP2_23_20,	RX4_B,			SEL_SCIF4_1),
783 	PINMUX_IPSR_GPSR(IP2_23_20,	VI4_DATA14),
784 	PINMUX_IPSR_GPSR(IP2_23_20,	VI5_DATA14),
785 	PINMUX_IPSR_GPSR(IP2_23_20,	DU_DB6),
786 
787 	PINMUX_IPSR_GPSR(IP2_27_24,	A7),
788 	PINMUX_IPSR_GPSR(IP2_27_24,	LCDOUT23),
789 	PINMUX_IPSR_MSEL(IP2_27_24,	MSIOF2_SS2_A,		SEL_MSIOF2_0),
790 	PINMUX_IPSR_MSEL(IP2_27_24,	TX4_B,			SEL_SCIF4_1),
791 	PINMUX_IPSR_GPSR(IP2_27_24,	VI4_DATA15),
792 	PINMUX_IPSR_GPSR(IP2_27_24,	VI5_DATA15),
793 	PINMUX_IPSR_GPSR(IP2_27_24,	DU_DB7),
794 
795 	PINMUX_IPSR_GPSR(IP2_31_28,	A8),
796 	PINMUX_IPSR_MSEL(IP2_31_28,	RX3_B,			SEL_SCIF3_1),
797 	PINMUX_IPSR_MSEL(IP2_31_28,	MSIOF2_SYNC_A,		SEL_MSIOF2_0),
798 	PINMUX_IPSR_MSEL(IP2_31_28,	HRX4_B,			SEL_HSCIF4_1),
799 	PINMUX_IPSR_MSEL(IP2_31_28,	SDA6_A,			SEL_I2C6_0),
800 	PINMUX_IPSR_MSEL(IP2_31_28,	AVB_AVTP_MATCH_B,	SEL_ETHERAVB_1),
801 	PINMUX_IPSR_MSEL(IP2_31_28,	PWM1_B,			SEL_PWM1_1),
802 
803 	/* IPSR3 */
804 	PINMUX_IPSR_GPSR(IP3_3_0,	A9),
805 	PINMUX_IPSR_MSEL(IP3_3_0,	MSIOF2_SCK_A,		SEL_MSIOF2_0),
806 	PINMUX_IPSR_MSEL(IP3_3_0,	CTS4_N_B,		SEL_SCIF4_1),
807 	PINMUX_IPSR_GPSR(IP3_3_0,	VI5_VSYNC_N),
808 
809 	PINMUX_IPSR_GPSR(IP3_7_4,	A10),
810 	PINMUX_IPSR_MSEL(IP3_7_4,	MSIOF2_RXD_A,		SEL_MSIOF2_0),
811 	PINMUX_IPSR_MSEL(IP3_7_4,	RTS4_N_B,		SEL_SCIF4_1),
812 	PINMUX_IPSR_GPSR(IP3_7_4,	VI5_HSYNC_N),
813 
814 	PINMUX_IPSR_GPSR(IP3_11_8,	A11),
815 	PINMUX_IPSR_MSEL(IP3_11_8,	TX3_B,			SEL_SCIF3_1),
816 	PINMUX_IPSR_MSEL(IP3_11_8,	MSIOF2_TXD_A,		SEL_MSIOF2_0),
817 	PINMUX_IPSR_MSEL(IP3_11_8,	HTX4_B,			SEL_HSCIF4_1),
818 	PINMUX_IPSR_GPSR(IP3_11_8,	HSCK4),
819 	PINMUX_IPSR_GPSR(IP3_11_8,	VI5_FIELD),
820 	PINMUX_IPSR_MSEL(IP3_11_8,	SCL6_A,			SEL_I2C6_0),
821 	PINMUX_IPSR_MSEL(IP3_11_8,	AVB_AVTP_CAPTURE_B,	SEL_ETHERAVB_1),
822 	PINMUX_IPSR_MSEL(IP3_11_8,	PWM2_B,			SEL_PWM2_1),
823 
824 	PINMUX_IPSR_GPSR(IP3_15_12,	A12),
825 	PINMUX_IPSR_GPSR(IP3_15_12,	LCDOUT12),
826 	PINMUX_IPSR_MSEL(IP3_15_12,	MSIOF3_SCK_C,		SEL_MSIOF3_2),
827 	PINMUX_IPSR_MSEL(IP3_15_12,	HRX4_A,			SEL_HSCIF4_0),
828 	PINMUX_IPSR_GPSR(IP3_15_12,	VI5_DATA8),
829 	PINMUX_IPSR_GPSR(IP3_15_12,	DU_DG4),
830 
831 	PINMUX_IPSR_GPSR(IP3_19_16,	A13),
832 	PINMUX_IPSR_GPSR(IP3_19_16,	LCDOUT13),
833 	PINMUX_IPSR_MSEL(IP3_19_16,	MSIOF3_SYNC_C,		SEL_MSIOF3_2),
834 	PINMUX_IPSR_MSEL(IP3_19_16,	HTX4_A,			SEL_HSCIF4_0),
835 	PINMUX_IPSR_GPSR(IP3_19_16,	VI5_DATA9),
836 	PINMUX_IPSR_GPSR(IP3_19_16,	DU_DG5),
837 
838 	PINMUX_IPSR_GPSR(IP3_23_20,	A14),
839 	PINMUX_IPSR_GPSR(IP3_23_20,	LCDOUT14),
840 	PINMUX_IPSR_MSEL(IP3_23_20,	MSIOF3_RXD_C,		SEL_MSIOF3_2),
841 	PINMUX_IPSR_GPSR(IP3_23_20,	HCTS4_N),
842 	PINMUX_IPSR_GPSR(IP3_23_20,	VI5_DATA10),
843 	PINMUX_IPSR_GPSR(IP3_23_20,	DU_DG6),
844 
845 	PINMUX_IPSR_GPSR(IP3_27_24,	A15),
846 	PINMUX_IPSR_GPSR(IP3_27_24,	LCDOUT15),
847 	PINMUX_IPSR_MSEL(IP3_27_24,	MSIOF3_TXD_C,		SEL_MSIOF3_2),
848 	PINMUX_IPSR_GPSR(IP3_27_24,	HRTS4_N),
849 	PINMUX_IPSR_GPSR(IP3_27_24,	VI5_DATA11),
850 	PINMUX_IPSR_GPSR(IP3_27_24,	DU_DG7),
851 
852 	PINMUX_IPSR_GPSR(IP3_31_28,	A16),
853 	PINMUX_IPSR_GPSR(IP3_31_28,	LCDOUT8),
854 	PINMUX_IPSR_GPSR(IP3_31_28,	VI4_FIELD),
855 	PINMUX_IPSR_GPSR(IP3_31_28,	DU_DG0),
856 
857 	/* IPSR4 */
858 	PINMUX_IPSR_GPSR(IP4_3_0,	A17),
859 	PINMUX_IPSR_GPSR(IP4_3_0,	LCDOUT9),
860 	PINMUX_IPSR_GPSR(IP4_3_0,	VI4_VSYNC_N),
861 	PINMUX_IPSR_GPSR(IP4_3_0,	DU_DG1),
862 
863 	PINMUX_IPSR_GPSR(IP4_7_4,	A18),
864 	PINMUX_IPSR_GPSR(IP4_7_4,	LCDOUT10),
865 	PINMUX_IPSR_GPSR(IP4_7_4,	VI4_HSYNC_N),
866 	PINMUX_IPSR_GPSR(IP4_7_4,	DU_DG2),
867 
868 	PINMUX_IPSR_GPSR(IP4_11_8,	A19),
869 	PINMUX_IPSR_GPSR(IP4_11_8,	LCDOUT11),
870 	PINMUX_IPSR_GPSR(IP4_11_8,	VI4_CLKENB),
871 	PINMUX_IPSR_GPSR(IP4_11_8,	DU_DG3),
872 
873 	PINMUX_IPSR_GPSR(IP4_15_12,	CS0_N),
874 	PINMUX_IPSR_GPSR(IP4_15_12,	VI5_CLKENB),
875 
876 	PINMUX_IPSR_GPSR(IP4_19_16,	CS1_N),
877 	PINMUX_IPSR_GPSR(IP4_19_16,	VI5_CLK),
878 	PINMUX_IPSR_MSEL(IP4_19_16,	EX_WAIT0_B,		SEL_LBSC_1),
879 
880 	PINMUX_IPSR_GPSR(IP4_23_20,	BS_N),
881 	PINMUX_IPSR_GPSR(IP4_23_20,	QSTVA_QVS),
882 	PINMUX_IPSR_MSEL(IP4_23_20,	MSIOF3_SCK_D,		SEL_MSIOF3_3),
883 	PINMUX_IPSR_GPSR(IP4_23_20,	SCK3),
884 	PINMUX_IPSR_GPSR(IP4_23_20,	HSCK3),
885 	PINMUX_IPSR_GPSR(IP4_23_20,	CAN1_TX),
886 	PINMUX_IPSR_GPSR(IP4_23_20,	CANFD1_TX),
887 	PINMUX_IPSR_MSEL(IP4_23_20,	IETX_A,			SEL_IEBUS_0),
888 
889 	PINMUX_IPSR_GPSR(IP4_27_24,	RD_N),
890 	PINMUX_IPSR_MSEL(IP4_27_24,	MSIOF3_SYNC_D,		SEL_MSIOF3_3),
891 	PINMUX_IPSR_MSEL(IP4_27_24,	RX3_A,			SEL_SCIF3_0),
892 	PINMUX_IPSR_MSEL(IP4_27_24,	HRX3_A,			SEL_HSCIF3_0),
893 	PINMUX_IPSR_MSEL(IP4_27_24,	CAN0_TX_A,		SEL_RCAN0_0),
894 	PINMUX_IPSR_MSEL(IP4_27_24,	CANFD0_TX_A,		SEL_CANFD0_0),
895 
896 	PINMUX_IPSR_GPSR(IP4_31_28,	RD_WR_N),
897 	PINMUX_IPSR_MSEL(IP4_31_28,	MSIOF3_RXD_D,		SEL_MSIOF3_3),
898 	PINMUX_IPSR_MSEL(IP4_31_28,	TX3_A,			SEL_SCIF3_0),
899 	PINMUX_IPSR_MSEL(IP4_31_28,	HTX3_A,			SEL_HSCIF3_0),
900 	PINMUX_IPSR_MSEL(IP4_31_28,	CAN0_RX_A,		SEL_RCAN0_0),
901 	PINMUX_IPSR_MSEL(IP4_31_28,	CANFD0_RX_A,		SEL_CANFD0_0),
902 
903 	/* IPSR5 */
904 	PINMUX_IPSR_GPSR(IP5_3_0,	WE0_N),
905 	PINMUX_IPSR_MSEL(IP5_3_0,	MSIOF3_TXD_D,		SEL_MSIOF3_3),
906 	PINMUX_IPSR_GPSR(IP5_3_0,	CTS3_N),
907 	PINMUX_IPSR_GPSR(IP5_3_0,	HCTS3_N),
908 	PINMUX_IPSR_MSEL(IP5_3_0,	SCL6_B,			SEL_I2C6_1),
909 	PINMUX_IPSR_GPSR(IP5_3_0,	CAN_CLK),
910 	PINMUX_IPSR_MSEL(IP5_3_0,	IECLK_A,		SEL_IEBUS_0),
911 
912 	PINMUX_IPSR_GPSR(IP5_7_4,	WE1_N),
913 	PINMUX_IPSR_MSEL(IP5_7_4,	MSIOF3_SS1_D,		SEL_MSIOF3_3),
914 	PINMUX_IPSR_GPSR(IP5_7_4,	RTS3_N),
915 	PINMUX_IPSR_GPSR(IP5_7_4,	HRTS3_N),
916 	PINMUX_IPSR_MSEL(IP5_7_4,	SDA6_B,			SEL_I2C6_1),
917 	PINMUX_IPSR_GPSR(IP5_7_4,	CAN1_RX),
918 	PINMUX_IPSR_GPSR(IP5_7_4,	CANFD1_RX),
919 	PINMUX_IPSR_MSEL(IP5_7_4,	IERX_A,			SEL_IEBUS_0),
920 
921 	PINMUX_IPSR_MSEL(IP5_11_8,	EX_WAIT0_A,		SEL_LBSC_0),
922 	PINMUX_IPSR_GPSR(IP5_11_8,	QCLK),
923 	PINMUX_IPSR_GPSR(IP5_11_8,	VI4_CLK),
924 	PINMUX_IPSR_GPSR(IP5_11_8,	DU_DOTCLKOUT0),
925 
926 	PINMUX_IPSR_GPSR(IP5_15_12,	D0),
927 	PINMUX_IPSR_MSEL(IP5_15_12,	MSIOF2_SS1_B,		SEL_MSIOF2_1),
928 	PINMUX_IPSR_MSEL(IP5_15_12,	MSIOF3_SCK_A,		SEL_MSIOF3_0),
929 	PINMUX_IPSR_GPSR(IP5_15_12,	VI4_DATA16),
930 	PINMUX_IPSR_GPSR(IP5_15_12,	VI5_DATA0),
931 
932 	PINMUX_IPSR_GPSR(IP5_19_16,	D1),
933 	PINMUX_IPSR_MSEL(IP5_19_16,	MSIOF2_SS2_B,		SEL_MSIOF2_1),
934 	PINMUX_IPSR_MSEL(IP5_19_16,	MSIOF3_SYNC_A,		SEL_MSIOF3_0),
935 	PINMUX_IPSR_GPSR(IP5_19_16,	VI4_DATA17),
936 	PINMUX_IPSR_GPSR(IP5_19_16,	VI5_DATA1),
937 
938 	PINMUX_IPSR_GPSR(IP5_23_20,	D2),
939 	PINMUX_IPSR_MSEL(IP5_23_20,	MSIOF3_RXD_A,		SEL_MSIOF3_0),
940 	PINMUX_IPSR_GPSR(IP5_23_20,	VI4_DATA18),
941 	PINMUX_IPSR_GPSR(IP5_23_20,	VI5_DATA2),
942 
943 	PINMUX_IPSR_GPSR(IP5_27_24,	D3),
944 	PINMUX_IPSR_MSEL(IP5_27_24,	MSIOF3_TXD_A,		SEL_MSIOF3_0),
945 	PINMUX_IPSR_GPSR(IP5_27_24,	VI4_DATA19),
946 	PINMUX_IPSR_GPSR(IP5_27_24,	VI5_DATA3),
947 
948 	PINMUX_IPSR_GPSR(IP5_31_28,	D4),
949 	PINMUX_IPSR_MSEL(IP5_31_28,	MSIOF2_SCK_B,		SEL_MSIOF2_1),
950 	PINMUX_IPSR_GPSR(IP5_31_28,	VI4_DATA20),
951 	PINMUX_IPSR_GPSR(IP5_31_28,	VI5_DATA4),
952 
953 	/* IPSR6 */
954 	PINMUX_IPSR_GPSR(IP6_3_0,	D5),
955 	PINMUX_IPSR_MSEL(IP6_3_0,	MSIOF2_SYNC_B,		SEL_MSIOF2_1),
956 	PINMUX_IPSR_GPSR(IP6_3_0,	VI4_DATA21),
957 	PINMUX_IPSR_GPSR(IP6_3_0,	VI5_DATA5),
958 
959 	PINMUX_IPSR_GPSR(IP6_7_4,	D6),
960 	PINMUX_IPSR_MSEL(IP6_7_4,	MSIOF2_RXD_B,		SEL_MSIOF2_1),
961 	PINMUX_IPSR_GPSR(IP6_7_4,	VI4_DATA22),
962 	PINMUX_IPSR_GPSR(IP6_7_4,	VI5_DATA6),
963 
964 	PINMUX_IPSR_GPSR(IP6_11_8,	D7),
965 	PINMUX_IPSR_MSEL(IP6_11_8,	MSIOF2_TXD_B,		SEL_MSIOF2_1),
966 	PINMUX_IPSR_GPSR(IP6_11_8,	VI4_DATA23),
967 	PINMUX_IPSR_GPSR(IP6_11_8,	VI5_DATA7),
968 
969 	PINMUX_IPSR_GPSR(IP6_15_12,	D8),
970 	PINMUX_IPSR_GPSR(IP6_15_12,	LCDOUT0),
971 	PINMUX_IPSR_MSEL(IP6_15_12,	MSIOF2_SCK_D,		SEL_MSIOF2_3),
972 	PINMUX_IPSR_MSEL(IP6_15_12,	SCK4_C,			SEL_SCIF4_2),
973 	PINMUX_IPSR_MSEL(IP6_15_12,	VI4_DATA0_A,		SEL_VIN4_0),
974 	PINMUX_IPSR_GPSR(IP6_15_12,	DU_DR0),
975 
976 	PINMUX_IPSR_GPSR(IP6_19_16,	D9),
977 	PINMUX_IPSR_GPSR(IP6_19_16,	LCDOUT1),
978 	PINMUX_IPSR_MSEL(IP6_19_16,	MSIOF2_SYNC_D,		SEL_MSIOF2_3),
979 	PINMUX_IPSR_MSEL(IP6_19_16,	VI4_DATA1_A,		SEL_VIN4_0),
980 	PINMUX_IPSR_GPSR(IP6_19_16,	DU_DR1),
981 
982 	PINMUX_IPSR_GPSR(IP6_23_20,	D10),
983 	PINMUX_IPSR_GPSR(IP6_23_20,	LCDOUT2),
984 	PINMUX_IPSR_MSEL(IP6_23_20,	MSIOF2_RXD_D,		SEL_MSIOF2_3),
985 	PINMUX_IPSR_MSEL(IP6_23_20,	HRX3_B,			SEL_HSCIF3_1),
986 	PINMUX_IPSR_MSEL(IP6_23_20,	VI4_DATA2_A,		SEL_VIN4_0),
987 	PINMUX_IPSR_MSEL(IP6_23_20,	CTS4_N_C,		SEL_SCIF4_2),
988 	PINMUX_IPSR_GPSR(IP6_23_20,	DU_DR2),
989 
990 	PINMUX_IPSR_GPSR(IP6_27_24,	D11),
991 	PINMUX_IPSR_GPSR(IP6_27_24,	LCDOUT3),
992 	PINMUX_IPSR_MSEL(IP6_27_24,	MSIOF2_TXD_D,		SEL_MSIOF2_3),
993 	PINMUX_IPSR_MSEL(IP6_27_24,	HTX3_B,			SEL_HSCIF3_1),
994 	PINMUX_IPSR_MSEL(IP6_27_24,	VI4_DATA3_A,		SEL_VIN4_0),
995 	PINMUX_IPSR_MSEL(IP6_27_24,	RTS4_N_C,		SEL_SCIF4_2),
996 	PINMUX_IPSR_GPSR(IP6_27_24,	DU_DR3),
997 
998 	PINMUX_IPSR_GPSR(IP6_31_28,	D12),
999 	PINMUX_IPSR_GPSR(IP6_31_28,	LCDOUT4),
1000 	PINMUX_IPSR_MSEL(IP6_31_28,	MSIOF2_SS1_D,		SEL_MSIOF2_3),
1001 	PINMUX_IPSR_MSEL(IP6_31_28,	RX4_C,			SEL_SCIF4_2),
1002 	PINMUX_IPSR_MSEL(IP6_31_28,	VI4_DATA4_A,		SEL_VIN4_0),
1003 	PINMUX_IPSR_GPSR(IP6_31_28,	DU_DR4),
1004 
1005 	/* IPSR7 */
1006 	PINMUX_IPSR_GPSR(IP7_3_0,	D13),
1007 	PINMUX_IPSR_GPSR(IP7_3_0,	LCDOUT5),
1008 	PINMUX_IPSR_MSEL(IP7_3_0,	MSIOF2_SS2_D,		SEL_MSIOF2_3),
1009 	PINMUX_IPSR_MSEL(IP7_3_0,	TX4_C,			SEL_SCIF4_2),
1010 	PINMUX_IPSR_MSEL(IP7_3_0,	VI4_DATA5_A,		SEL_VIN4_0),
1011 	PINMUX_IPSR_GPSR(IP7_3_0,	DU_DR5),
1012 
1013 	PINMUX_IPSR_GPSR(IP7_7_4,	D14),
1014 	PINMUX_IPSR_GPSR(IP7_7_4,	LCDOUT6),
1015 	PINMUX_IPSR_MSEL(IP7_7_4,	MSIOF3_SS1_A,		SEL_MSIOF3_0),
1016 	PINMUX_IPSR_MSEL(IP7_7_4,	HRX3_C,			SEL_HSCIF3_2),
1017 	PINMUX_IPSR_MSEL(IP7_7_4,	VI4_DATA6_A,		SEL_VIN4_0),
1018 	PINMUX_IPSR_GPSR(IP7_7_4,	DU_DR6),
1019 	PINMUX_IPSR_MSEL(IP7_7_4,	SCL6_C,			SEL_I2C6_2),
1020 
1021 	PINMUX_IPSR_GPSR(IP7_11_8,	D15),
1022 	PINMUX_IPSR_GPSR(IP7_11_8,	LCDOUT7),
1023 	PINMUX_IPSR_MSEL(IP7_11_8,	MSIOF3_SS2_A,		SEL_MSIOF3_0),
1024 	PINMUX_IPSR_MSEL(IP7_11_8,	HTX3_C,			SEL_HSCIF3_2),
1025 	PINMUX_IPSR_MSEL(IP7_11_8,	VI4_DATA7_A,		SEL_VIN4_0),
1026 	PINMUX_IPSR_GPSR(IP7_11_8,	DU_DR7),
1027 	PINMUX_IPSR_MSEL(IP7_11_8,	SDA6_C,			SEL_I2C6_2),
1028 
1029 	PINMUX_IPSR_GPSR(IP7_19_16,	SD0_CLK),
1030 	PINMUX_IPSR_MSEL(IP7_19_16,	MSIOF1_SCK_E,		SEL_MSIOF1_4),
1031 	PINMUX_IPSR_MSEL(IP7_19_16,	STP_OPWM_0_B,		SEL_SSP1_0_1),
1032 
1033 	PINMUX_IPSR_GPSR(IP7_23_20,	SD0_CMD),
1034 	PINMUX_IPSR_MSEL(IP7_23_20,	MSIOF1_SYNC_E,		SEL_MSIOF1_4),
1035 	PINMUX_IPSR_MSEL(IP7_23_20,	STP_IVCXO27_0_B,	SEL_SSP1_0_1),
1036 
1037 	PINMUX_IPSR_GPSR(IP7_27_24,	SD0_DAT0),
1038 	PINMUX_IPSR_MSEL(IP7_27_24,	MSIOF1_RXD_E,		SEL_MSIOF1_4),
1039 	PINMUX_IPSR_MSEL(IP7_27_24,	TS_SCK0_B,		SEL_TSIF0_1),
1040 	PINMUX_IPSR_MSEL(IP7_27_24,	STP_ISCLK_0_B,		SEL_SSP1_0_1),
1041 
1042 	PINMUX_IPSR_GPSR(IP7_31_28,	SD0_DAT1),
1043 	PINMUX_IPSR_MSEL(IP7_31_28,	MSIOF1_TXD_E,		SEL_MSIOF1_4),
1044 	PINMUX_IPSR_MSEL(IP7_31_28,	TS_SPSYNC0_B,		SEL_TSIF0_1),
1045 	PINMUX_IPSR_MSEL(IP7_31_28,	STP_ISSYNC_0_B,		SEL_SSP1_0_1),
1046 
1047 	/* IPSR8 */
1048 	PINMUX_IPSR_GPSR(IP8_3_0,	SD0_DAT2),
1049 	PINMUX_IPSR_MSEL(IP8_3_0,	MSIOF1_SS1_E,		SEL_MSIOF1_4),
1050 	PINMUX_IPSR_MSEL(IP8_3_0,	TS_SDAT0_B,		SEL_TSIF0_1),
1051 	PINMUX_IPSR_MSEL(IP8_3_0,	STP_ISD_0_B,		SEL_SSP1_0_1),
1052 
1053 	PINMUX_IPSR_GPSR(IP8_7_4,	SD0_DAT3),
1054 	PINMUX_IPSR_MSEL(IP8_7_4,	MSIOF1_SS2_E,		SEL_MSIOF1_4),
1055 	PINMUX_IPSR_MSEL(IP8_7_4,	TS_SDEN0_B,		SEL_TSIF0_1),
1056 	PINMUX_IPSR_MSEL(IP8_7_4,	STP_ISEN_0_B,		SEL_SSP1_0_1),
1057 
1058 	PINMUX_IPSR_GPSR(IP8_11_8,	SD1_CLK),
1059 	PINMUX_IPSR_MSEL(IP8_11_8,	MSIOF1_SCK_G,		SEL_MSIOF1_6),
1060 	PINMUX_IPSR_MSEL(IP8_11_8,	SIM0_CLK_A,		SEL_SIMCARD_0),
1061 
1062 	PINMUX_IPSR_GPSR(IP8_15_12,	SD1_CMD),
1063 	PINMUX_IPSR_MSEL(IP8_15_12,	MSIOF1_SYNC_G,		SEL_MSIOF1_6),
1064 	PINMUX_IPSR_GPSR(IP8_15_12,	NFCE_N_B),
1065 	PINMUX_IPSR_MSEL(IP8_15_12,	SIM0_D_A,		SEL_SIMCARD_0),
1066 	PINMUX_IPSR_MSEL(IP8_15_12,	STP_IVCXO27_1_B,	SEL_SSP1_1_1),
1067 
1068 	PINMUX_IPSR_GPSR(IP8_19_16,	SD1_DAT0),
1069 	PINMUX_IPSR_GPSR(IP8_19_16,	SD2_DAT4),
1070 	PINMUX_IPSR_MSEL(IP8_19_16,	MSIOF1_RXD_G,		SEL_MSIOF1_6),
1071 	PINMUX_IPSR_GPSR(IP8_19_16,	NFWP_N_B),
1072 	PINMUX_IPSR_MSEL(IP8_19_16,	TS_SCK1_B,		SEL_TSIF1_1),
1073 	PINMUX_IPSR_MSEL(IP8_19_16,	STP_ISCLK_1_B,		SEL_SSP1_1_1),
1074 
1075 	PINMUX_IPSR_GPSR(IP8_23_20,	SD1_DAT1),
1076 	PINMUX_IPSR_GPSR(IP8_23_20,	SD2_DAT5),
1077 	PINMUX_IPSR_MSEL(IP8_23_20,	MSIOF1_TXD_G,		SEL_MSIOF1_6),
1078 	PINMUX_IPSR_GPSR(IP8_23_20,	NFDATA14_B),
1079 	PINMUX_IPSR_MSEL(IP8_23_20,	TS_SPSYNC1_B,		SEL_TSIF1_1),
1080 	PINMUX_IPSR_MSEL(IP8_23_20,	STP_ISSYNC_1_B,		SEL_SSP1_1_1),
1081 
1082 	PINMUX_IPSR_GPSR(IP8_27_24,	SD1_DAT2),
1083 	PINMUX_IPSR_GPSR(IP8_27_24,	SD2_DAT6),
1084 	PINMUX_IPSR_MSEL(IP8_27_24,	MSIOF1_SS1_G,		SEL_MSIOF1_6),
1085 	PINMUX_IPSR_GPSR(IP8_27_24,	NFDATA15_B),
1086 	PINMUX_IPSR_MSEL(IP8_27_24,	TS_SDAT1_B,		SEL_TSIF1_1),
1087 	PINMUX_IPSR_MSEL(IP8_27_24,	STP_ISD_1_B,		SEL_SSP1_1_1),
1088 
1089 	PINMUX_IPSR_GPSR(IP8_31_28,	SD1_DAT3),
1090 	PINMUX_IPSR_GPSR(IP8_31_28,	SD2_DAT7),
1091 	PINMUX_IPSR_MSEL(IP8_31_28,	MSIOF1_SS2_G,		SEL_MSIOF1_6),
1092 	PINMUX_IPSR_GPSR(IP8_31_28,	NFRB_N_B),
1093 	PINMUX_IPSR_MSEL(IP8_31_28,	TS_SDEN1_B,		SEL_TSIF1_1),
1094 	PINMUX_IPSR_MSEL(IP8_31_28,	STP_ISEN_1_B,		SEL_SSP1_1_1),
1095 
1096 	/* IPSR9 */
1097 	PINMUX_IPSR_GPSR(IP9_3_0,	SD2_CLK),
1098 	PINMUX_IPSR_GPSR(IP9_3_0,	NFDATA8),
1099 
1100 	PINMUX_IPSR_GPSR(IP9_7_4,	SD2_CMD),
1101 	PINMUX_IPSR_GPSR(IP9_7_4,	NFDATA9),
1102 
1103 	PINMUX_IPSR_GPSR(IP9_11_8,	SD2_DAT0),
1104 	PINMUX_IPSR_GPSR(IP9_11_8,	NFDATA10),
1105 
1106 	PINMUX_IPSR_GPSR(IP9_15_12,	SD2_DAT1),
1107 	PINMUX_IPSR_GPSR(IP9_15_12,	NFDATA11),
1108 
1109 	PINMUX_IPSR_GPSR(IP9_19_16,	SD2_DAT2),
1110 	PINMUX_IPSR_GPSR(IP9_19_16,	NFDATA12),
1111 
1112 	PINMUX_IPSR_GPSR(IP9_23_20,	SD2_DAT3),
1113 	PINMUX_IPSR_GPSR(IP9_23_20,	NFDATA13),
1114 
1115 	PINMUX_IPSR_GPSR(IP9_27_24,	SD2_DS),
1116 	PINMUX_IPSR_GPSR(IP9_27_24,	NFALE),
1117 	PINMUX_IPSR_GPSR(IP9_27_24,	SATA_DEVSLP_B),
1118 
1119 	PINMUX_IPSR_GPSR(IP9_31_28,	SD3_CLK),
1120 	PINMUX_IPSR_GPSR(IP9_31_28,	NFWE_N),
1121 
1122 	/* IPSR10 */
1123 	PINMUX_IPSR_GPSR(IP10_3_0,	SD3_CMD),
1124 	PINMUX_IPSR_GPSR(IP10_3_0,	NFRE_N),
1125 
1126 	PINMUX_IPSR_GPSR(IP10_7_4,	SD3_DAT0),
1127 	PINMUX_IPSR_GPSR(IP10_7_4,	NFDATA0),
1128 
1129 	PINMUX_IPSR_GPSR(IP10_11_8,	SD3_DAT1),
1130 	PINMUX_IPSR_GPSR(IP10_11_8,	NFDATA1),
1131 
1132 	PINMUX_IPSR_GPSR(IP10_15_12,	SD3_DAT2),
1133 	PINMUX_IPSR_GPSR(IP10_15_12,	NFDATA2),
1134 
1135 	PINMUX_IPSR_GPSR(IP10_19_16,	SD3_DAT3),
1136 	PINMUX_IPSR_GPSR(IP10_19_16,	NFDATA3),
1137 
1138 	PINMUX_IPSR_GPSR(IP10_23_20,	SD3_DAT4),
1139 	PINMUX_IPSR_MSEL(IP10_23_20,	SD2_CD_A,		SEL_SDHI2_0),
1140 	PINMUX_IPSR_GPSR(IP10_23_20,	NFDATA4),
1141 
1142 	PINMUX_IPSR_GPSR(IP10_27_24,	SD3_DAT5),
1143 	PINMUX_IPSR_MSEL(IP10_27_24,	SD2_WP_A,		SEL_SDHI2_0),
1144 	PINMUX_IPSR_GPSR(IP10_27_24,	NFDATA5),
1145 
1146 	PINMUX_IPSR_GPSR(IP10_31_28,	SD3_DAT6),
1147 	PINMUX_IPSR_GPSR(IP10_31_28,	SD3_CD),
1148 	PINMUX_IPSR_GPSR(IP10_31_28,	NFDATA6),
1149 
1150 	/* IPSR11 */
1151 	PINMUX_IPSR_GPSR(IP11_3_0,	SD3_DAT7),
1152 	PINMUX_IPSR_GPSR(IP11_3_0,	SD3_WP),
1153 	PINMUX_IPSR_GPSR(IP11_3_0,	NFDATA7),
1154 
1155 	PINMUX_IPSR_GPSR(IP11_7_4,	SD3_DS),
1156 	PINMUX_IPSR_GPSR(IP11_7_4,	NFCLE),
1157 
1158 	PINMUX_IPSR_GPSR(IP11_11_8,	SD0_CD),
1159 	PINMUX_IPSR_MSEL(IP11_11_8,	SCL2_B,			SEL_I2C2_1),
1160 	PINMUX_IPSR_MSEL(IP11_11_8,	SIM0_RST_A,		SEL_SIMCARD_0),
1161 
1162 	PINMUX_IPSR_GPSR(IP11_15_12,	SD0_WP),
1163 	PINMUX_IPSR_MSEL(IP11_15_12,	SDA2_B,			SEL_I2C2_1),
1164 
1165 	PINMUX_IPSR_MSEL(IP11_19_16,	SD1_CD,			I2C_SEL_0_0),
1166 	PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B,		I2C_SEL_0_0,	SEL_SIMCARD_1),
1167 	PINMUX_IPSR_PHYS(IP11_19_16,	SCL0,			I2C_SEL_0_1),
1168 
1169 	PINMUX_IPSR_MSEL(IP11_23_20,	SD1_WP,			I2C_SEL_0_0),
1170 	PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B,		I2C_SEL_0_0,	SEL_SIMCARD_1),
1171 	PINMUX_IPSR_PHYS(IP11_23_20,	SDA0,			I2C_SEL_0_1),
1172 
1173 	PINMUX_IPSR_GPSR(IP11_27_24,	SCK0),
1174 	PINMUX_IPSR_MSEL(IP11_27_24,	HSCK1_B,		SEL_HSCIF1_1),
1175 	PINMUX_IPSR_MSEL(IP11_27_24,	MSIOF1_SS2_B,		SEL_MSIOF1_1),
1176 	PINMUX_IPSR_MSEL(IP11_27_24,	AUDIO_CLKC_B,		SEL_ADGC_1),
1177 	PINMUX_IPSR_MSEL(IP11_27_24,	SDA2_A,			SEL_I2C2_0),
1178 	PINMUX_IPSR_MSEL(IP11_27_24,	SIM0_RST_B,		SEL_SIMCARD_1),
1179 	PINMUX_IPSR_MSEL(IP11_27_24,	STP_OPWM_0_C,		SEL_SSP1_0_2),
1180 	PINMUX_IPSR_MSEL(IP11_27_24,	RIF0_CLK_B,		SEL_DRIF0_1),
1181 	PINMUX_IPSR_GPSR(IP11_27_24,	ADICHS2),
1182 	PINMUX_IPSR_MSEL(IP11_27_24,	SCK5_B,			SEL_SCIF5_1),
1183 
1184 	PINMUX_IPSR_GPSR(IP11_31_28,	RX0),
1185 	PINMUX_IPSR_MSEL(IP11_31_28,	HRX1_B,			SEL_HSCIF1_1),
1186 	PINMUX_IPSR_MSEL(IP11_31_28,	TS_SCK0_C,		SEL_TSIF0_2),
1187 	PINMUX_IPSR_MSEL(IP11_31_28,	STP_ISCLK_0_C,		SEL_SSP1_0_2),
1188 	PINMUX_IPSR_MSEL(IP11_31_28,	RIF0_D0_B,		SEL_DRIF0_1),
1189 
1190 	/* IPSR12 */
1191 	PINMUX_IPSR_GPSR(IP12_3_0,	TX0),
1192 	PINMUX_IPSR_MSEL(IP12_3_0,	HTX1_B,			SEL_HSCIF1_1),
1193 	PINMUX_IPSR_MSEL(IP12_3_0,	TS_SPSYNC0_C,		SEL_TSIF0_2),
1194 	PINMUX_IPSR_MSEL(IP12_3_0,	STP_ISSYNC_0_C,		SEL_SSP1_0_2),
1195 	PINMUX_IPSR_MSEL(IP12_3_0,	RIF0_D1_B,		SEL_DRIF0_1),
1196 
1197 	PINMUX_IPSR_GPSR(IP12_7_4,	CTS0_N),
1198 	PINMUX_IPSR_MSEL(IP12_7_4,	HCTS1_N_B,		SEL_HSCIF1_1),
1199 	PINMUX_IPSR_MSEL(IP12_7_4,	MSIOF1_SYNC_B,		SEL_MSIOF1_1),
1200 	PINMUX_IPSR_MSEL(IP12_7_4,	TS_SPSYNC1_C,		SEL_TSIF1_2),
1201 	PINMUX_IPSR_MSEL(IP12_7_4,	STP_ISSYNC_1_C,		SEL_SSP1_1_2),
1202 	PINMUX_IPSR_MSEL(IP12_7_4,	RIF1_SYNC_B,		SEL_DRIF1_1),
1203 	PINMUX_IPSR_GPSR(IP12_7_4,	AUDIO_CLKOUT_C),
1204 	PINMUX_IPSR_GPSR(IP12_7_4,	ADICS_SAMP),
1205 
1206 	PINMUX_IPSR_GPSR(IP12_11_8,	RTS0_N),
1207 	PINMUX_IPSR_MSEL(IP12_11_8,	HRTS1_N_B,		SEL_HSCIF1_1),
1208 	PINMUX_IPSR_MSEL(IP12_11_8,	MSIOF1_SS1_B,		SEL_MSIOF1_1),
1209 	PINMUX_IPSR_MSEL(IP12_11_8,	AUDIO_CLKA_B,		SEL_ADGA_1),
1210 	PINMUX_IPSR_MSEL(IP12_11_8,	SCL2_A,			SEL_I2C2_0),
1211 	PINMUX_IPSR_MSEL(IP12_11_8,	STP_IVCXO27_1_C,	SEL_SSP1_1_2),
1212 	PINMUX_IPSR_MSEL(IP12_11_8,	RIF0_SYNC_B,		SEL_DRIF0_1),
1213 	PINMUX_IPSR_GPSR(IP12_11_8,	ADICHS1),
1214 
1215 	PINMUX_IPSR_MSEL(IP12_15_12,	RX1_A,			SEL_SCIF1_0),
1216 	PINMUX_IPSR_MSEL(IP12_15_12,	HRX1_A,			SEL_HSCIF1_0),
1217 	PINMUX_IPSR_MSEL(IP12_15_12,	TS_SDAT0_C,		SEL_TSIF0_2),
1218 	PINMUX_IPSR_MSEL(IP12_15_12,	STP_ISD_0_C,		SEL_SSP1_0_2),
1219 	PINMUX_IPSR_MSEL(IP12_15_12,	RIF1_CLK_C,		SEL_DRIF1_2),
1220 
1221 	PINMUX_IPSR_MSEL(IP12_19_16,	TX1_A,			SEL_SCIF1_0),
1222 	PINMUX_IPSR_MSEL(IP12_19_16,	HTX1_A,			SEL_HSCIF1_0),
1223 	PINMUX_IPSR_MSEL(IP12_19_16,	TS_SDEN0_C,		SEL_TSIF0_2),
1224 	PINMUX_IPSR_MSEL(IP12_19_16,	STP_ISEN_0_C,		SEL_SSP1_0_2),
1225 	PINMUX_IPSR_MSEL(IP12_19_16,	RIF1_D0_C,		SEL_DRIF1_2),
1226 
1227 	PINMUX_IPSR_GPSR(IP12_23_20,	CTS1_N),
1228 	PINMUX_IPSR_MSEL(IP12_23_20,	HCTS1_N_A,		SEL_HSCIF1_0),
1229 	PINMUX_IPSR_MSEL(IP12_23_20,	MSIOF1_RXD_B,		SEL_MSIOF1_1),
1230 	PINMUX_IPSR_MSEL(IP12_23_20,	TS_SDEN1_C,		SEL_TSIF1_2),
1231 	PINMUX_IPSR_MSEL(IP12_23_20,	STP_ISEN_1_C,		SEL_SSP1_1_2),
1232 	PINMUX_IPSR_MSEL(IP12_23_20,	RIF1_D0_B,		SEL_DRIF1_1),
1233 	PINMUX_IPSR_GPSR(IP12_23_20,	ADIDATA),
1234 
1235 	PINMUX_IPSR_GPSR(IP12_27_24,	RTS1_N),
1236 	PINMUX_IPSR_MSEL(IP12_27_24,	HRTS1_N_A,		SEL_HSCIF1_0),
1237 	PINMUX_IPSR_MSEL(IP12_27_24,	MSIOF1_TXD_B,		SEL_MSIOF1_1),
1238 	PINMUX_IPSR_MSEL(IP12_27_24,	TS_SDAT1_C,		SEL_TSIF1_2),
1239 	PINMUX_IPSR_MSEL(IP12_27_24,	STP_ISD_1_C,		SEL_SSP1_1_2),
1240 	PINMUX_IPSR_MSEL(IP12_27_24,	RIF1_D1_B,		SEL_DRIF1_1),
1241 	PINMUX_IPSR_GPSR(IP12_27_24,	ADICHS0),
1242 
1243 	PINMUX_IPSR_GPSR(IP12_31_28,	SCK2),
1244 	PINMUX_IPSR_MSEL(IP12_31_28,	SCIF_CLK_B,		SEL_SCIF_1),
1245 	PINMUX_IPSR_MSEL(IP12_31_28,	MSIOF1_SCK_B,		SEL_MSIOF1_1),
1246 	PINMUX_IPSR_MSEL(IP12_31_28,	TS_SCK1_C,		SEL_TSIF1_2),
1247 	PINMUX_IPSR_MSEL(IP12_31_28,	STP_ISCLK_1_C,		SEL_SSP1_1_2),
1248 	PINMUX_IPSR_MSEL(IP12_31_28,	RIF1_CLK_B,		SEL_DRIF1_1),
1249 	PINMUX_IPSR_GPSR(IP12_31_28,	ADICLK),
1250 
1251 	/* IPSR13 */
1252 	PINMUX_IPSR_MSEL(IP13_3_0,	TX2_A,			SEL_SCIF2_0),
1253 	PINMUX_IPSR_MSEL(IP13_3_0,	SD2_CD_B,		SEL_SDHI2_1),
1254 	PINMUX_IPSR_MSEL(IP13_3_0,	SCL1_A,			SEL_I2C1_0),
1255 	PINMUX_IPSR_MSEL(IP13_3_0,	FMCLK_A,		SEL_FM_0),
1256 	PINMUX_IPSR_MSEL(IP13_3_0,	RIF1_D1_C,		SEL_DRIF1_2),
1257 	PINMUX_IPSR_GPSR(IP13_3_0,	FSO_CFE_0_N),
1258 
1259 	PINMUX_IPSR_MSEL(IP13_7_4,	RX2_A,			SEL_SCIF2_0),
1260 	PINMUX_IPSR_MSEL(IP13_7_4,	SD2_WP_B,		SEL_SDHI2_1),
1261 	PINMUX_IPSR_MSEL(IP13_7_4,	SDA1_A,			SEL_I2C1_0),
1262 	PINMUX_IPSR_MSEL(IP13_7_4,	FMIN_A,			SEL_FM_0),
1263 	PINMUX_IPSR_MSEL(IP13_7_4,	RIF1_SYNC_C,		SEL_DRIF1_2),
1264 	PINMUX_IPSR_GPSR(IP13_7_4,	FSO_CFE_1_N),
1265 
1266 	PINMUX_IPSR_GPSR(IP13_11_8,	HSCK0),
1267 	PINMUX_IPSR_MSEL(IP13_11_8,	MSIOF1_SCK_D,		SEL_MSIOF1_3),
1268 	PINMUX_IPSR_MSEL(IP13_11_8,	AUDIO_CLKB_A,		SEL_ADGB_0),
1269 	PINMUX_IPSR_MSEL(IP13_11_8,	SSI_SDATA1_B,		SEL_SSI1_1),
1270 	PINMUX_IPSR_MSEL(IP13_11_8,	TS_SCK0_D,		SEL_TSIF0_3),
1271 	PINMUX_IPSR_MSEL(IP13_11_8,	STP_ISCLK_0_D,		SEL_SSP1_0_3),
1272 	PINMUX_IPSR_MSEL(IP13_11_8,	RIF0_CLK_C,		SEL_DRIF0_2),
1273 	PINMUX_IPSR_MSEL(IP13_11_8,	RX5_B,			SEL_SCIF5_1),
1274 
1275 	PINMUX_IPSR_GPSR(IP13_15_12,	HRX0),
1276 	PINMUX_IPSR_MSEL(IP13_15_12,	MSIOF1_RXD_D,		SEL_MSIOF1_3),
1277 	PINMUX_IPSR_MSEL(IP13_15_12,	SSI_SDATA2_B,		SEL_SSI2_1),
1278 	PINMUX_IPSR_MSEL(IP13_15_12,	TS_SDEN0_D,		SEL_TSIF0_3),
1279 	PINMUX_IPSR_MSEL(IP13_15_12,	STP_ISEN_0_D,		SEL_SSP1_0_3),
1280 	PINMUX_IPSR_MSEL(IP13_15_12,	RIF0_D0_C,		SEL_DRIF0_2),
1281 
1282 	PINMUX_IPSR_GPSR(IP13_19_16,	HTX0),
1283 	PINMUX_IPSR_MSEL(IP13_19_16,	MSIOF1_TXD_D,		SEL_MSIOF1_3),
1284 	PINMUX_IPSR_MSEL(IP13_19_16,	SSI_SDATA9_B,		SEL_SSI9_1),
1285 	PINMUX_IPSR_MSEL(IP13_19_16,	TS_SDAT0_D,		SEL_TSIF0_3),
1286 	PINMUX_IPSR_MSEL(IP13_19_16,	STP_ISD_0_D,		SEL_SSP1_0_3),
1287 	PINMUX_IPSR_MSEL(IP13_19_16,	RIF0_D1_C,		SEL_DRIF0_2),
1288 
1289 	PINMUX_IPSR_GPSR(IP13_23_20,	HCTS0_N),
1290 	PINMUX_IPSR_MSEL(IP13_23_20,	RX2_B,			SEL_SCIF2_1),
1291 	PINMUX_IPSR_MSEL(IP13_23_20,	MSIOF1_SYNC_D,		SEL_MSIOF1_3),
1292 	PINMUX_IPSR_MSEL(IP13_23_20,	SSI_SCK9_A,		SEL_SSI9_0),
1293 	PINMUX_IPSR_MSEL(IP13_23_20,	TS_SPSYNC0_D,		SEL_TSIF0_3),
1294 	PINMUX_IPSR_MSEL(IP13_23_20,	STP_ISSYNC_0_D,		SEL_SSP1_0_3),
1295 	PINMUX_IPSR_MSEL(IP13_23_20,	RIF0_SYNC_C,		SEL_DRIF0_2),
1296 	PINMUX_IPSR_GPSR(IP13_23_20,	AUDIO_CLKOUT1_A),
1297 
1298 	PINMUX_IPSR_GPSR(IP13_27_24,	HRTS0_N),
1299 	PINMUX_IPSR_MSEL(IP13_27_24,	TX2_B,			SEL_SCIF2_1),
1300 	PINMUX_IPSR_MSEL(IP13_27_24,	MSIOF1_SS1_D,		SEL_MSIOF1_3),
1301 	PINMUX_IPSR_MSEL(IP13_27_24,	SSI_WS9_A,		SEL_SSI9_0),
1302 	PINMUX_IPSR_MSEL(IP13_27_24,	STP_IVCXO27_0_D,	SEL_SSP1_0_3),
1303 	PINMUX_IPSR_MSEL(IP13_27_24,	BPFCLK_A,		SEL_FM_0),
1304 	PINMUX_IPSR_GPSR(IP13_27_24,	AUDIO_CLKOUT2_A),
1305 
1306 	PINMUX_IPSR_GPSR(IP13_31_28,	MSIOF0_SYNC),
1307 	PINMUX_IPSR_GPSR(IP13_31_28,	AUDIO_CLKOUT_A),
1308 	PINMUX_IPSR_MSEL(IP13_31_28,	TX5_B,			SEL_SCIF5_1),
1309 	PINMUX_IPSR_MSEL(IP13_31_28,	BPFCLK_D,		SEL_FM_3),
1310 
1311 	/* IPSR14 */
1312 	PINMUX_IPSR_GPSR(IP14_3_0,	MSIOF0_SS1),
1313 	PINMUX_IPSR_MSEL(IP14_3_0,	RX5_A,			SEL_SCIF5_0),
1314 	PINMUX_IPSR_GPSR(IP14_3_0,	NFWP_N_A),
1315 	PINMUX_IPSR_MSEL(IP14_3_0,	AUDIO_CLKA_C,		SEL_ADGA_2),
1316 	PINMUX_IPSR_MSEL(IP14_3_0,	SSI_SCK2_A,		SEL_SSI2_0),
1317 	PINMUX_IPSR_MSEL(IP14_3_0,	STP_IVCXO27_0_C,	SEL_SSP1_0_2),
1318 	PINMUX_IPSR_GPSR(IP14_3_0,	AUDIO_CLKOUT3_A),
1319 	PINMUX_IPSR_MSEL(IP14_3_0,	TCLK1_B,		SEL_TIMER_TMU1_1),
1320 
1321 	PINMUX_IPSR_GPSR(IP14_7_4,	MSIOF0_SS2),
1322 	PINMUX_IPSR_MSEL(IP14_7_4,	TX5_A,			SEL_SCIF5_0),
1323 	PINMUX_IPSR_MSEL(IP14_7_4,	MSIOF1_SS2_D,		SEL_MSIOF1_3),
1324 	PINMUX_IPSR_MSEL(IP14_7_4,	AUDIO_CLKC_A,		SEL_ADGC_0),
1325 	PINMUX_IPSR_MSEL(IP14_7_4,	SSI_WS2_A,		SEL_SSI2_0),
1326 	PINMUX_IPSR_MSEL(IP14_7_4,	STP_OPWM_0_D,		SEL_SSP1_0_3),
1327 	PINMUX_IPSR_GPSR(IP14_7_4,	AUDIO_CLKOUT_D),
1328 	PINMUX_IPSR_MSEL(IP14_7_4,	SPEEDIN_B,		SEL_SPEED_PULSE_1),
1329 
1330 	PINMUX_IPSR_GPSR(IP14_11_8,	MLB_CLK),
1331 	PINMUX_IPSR_MSEL(IP14_11_8,	MSIOF1_SCK_F,		SEL_MSIOF1_5),
1332 	PINMUX_IPSR_MSEL(IP14_11_8,	SCL1_B,			SEL_I2C1_1),
1333 
1334 	PINMUX_IPSR_GPSR(IP14_15_12,	MLB_SIG),
1335 	PINMUX_IPSR_MSEL(IP14_15_12,	RX1_B,			SEL_SCIF1_1),
1336 	PINMUX_IPSR_MSEL(IP14_15_12,	MSIOF1_SYNC_F,		SEL_MSIOF1_5),
1337 	PINMUX_IPSR_MSEL(IP14_15_12,	SDA1_B,			SEL_I2C1_1),
1338 
1339 	PINMUX_IPSR_GPSR(IP14_19_16,	MLB_DAT),
1340 	PINMUX_IPSR_MSEL(IP14_19_16,	TX1_B,			SEL_SCIF1_1),
1341 	PINMUX_IPSR_MSEL(IP14_19_16,	MSIOF1_RXD_F,		SEL_MSIOF1_5),
1342 
1343 	PINMUX_IPSR_GPSR(IP14_23_20,	SSI_SCK01239),
1344 	PINMUX_IPSR_MSEL(IP14_23_20,	MSIOF1_TXD_F,		SEL_MSIOF1_5),
1345 
1346 	PINMUX_IPSR_GPSR(IP14_27_24,	SSI_WS01239),
1347 	PINMUX_IPSR_MSEL(IP14_27_24,	MSIOF1_SS1_F,		SEL_MSIOF1_5),
1348 
1349 	PINMUX_IPSR_GPSR(IP14_31_28,	SSI_SDATA0),
1350 	PINMUX_IPSR_MSEL(IP14_31_28,	MSIOF1_SS2_F,		SEL_MSIOF1_5),
1351 
1352 	/* IPSR15 */
1353 	PINMUX_IPSR_MSEL(IP15_3_0,	SSI_SDATA1_A,		SEL_SSI1_0),
1354 
1355 	PINMUX_IPSR_MSEL(IP15_7_4,	SSI_SDATA2_A,		SEL_SSI2_0),
1356 	PINMUX_IPSR_MSEL(IP15_7_4,	SSI_SCK1_B,		SEL_SSI1_1),
1357 
1358 	PINMUX_IPSR_GPSR(IP15_11_8,	SSI_SCK349),
1359 	PINMUX_IPSR_MSEL(IP15_11_8,	MSIOF1_SS1_A,		SEL_MSIOF1_0),
1360 	PINMUX_IPSR_MSEL(IP15_11_8,	STP_OPWM_0_A,		SEL_SSP1_0_0),
1361 
1362 	PINMUX_IPSR_GPSR(IP15_15_12,	SSI_WS349),
1363 	PINMUX_IPSR_MSEL(IP15_15_12,	HCTS2_N_A,		SEL_HSCIF2_0),
1364 	PINMUX_IPSR_MSEL(IP15_15_12,	MSIOF1_SS2_A,		SEL_MSIOF1_0),
1365 	PINMUX_IPSR_MSEL(IP15_15_12,	STP_IVCXO27_0_A,	SEL_SSP1_0_0),
1366 
1367 	PINMUX_IPSR_GPSR(IP15_19_16,	SSI_SDATA3),
1368 	PINMUX_IPSR_MSEL(IP15_19_16,	HRTS2_N_A,		SEL_HSCIF2_0),
1369 	PINMUX_IPSR_MSEL(IP15_19_16,	MSIOF1_TXD_A,		SEL_MSIOF1_0),
1370 	PINMUX_IPSR_MSEL(IP15_19_16,	TS_SCK0_A,		SEL_TSIF0_0),
1371 	PINMUX_IPSR_MSEL(IP15_19_16,	STP_ISCLK_0_A,		SEL_SSP1_0_0),
1372 	PINMUX_IPSR_MSEL(IP15_19_16,	RIF0_D1_A,		SEL_DRIF0_0),
1373 	PINMUX_IPSR_MSEL(IP15_19_16,	RIF2_D0_A,		SEL_DRIF2_0),
1374 
1375 	PINMUX_IPSR_GPSR(IP15_23_20,	SSI_SCK4),
1376 	PINMUX_IPSR_MSEL(IP15_23_20,	HRX2_A,			SEL_HSCIF2_0),
1377 	PINMUX_IPSR_MSEL(IP15_23_20,	MSIOF1_SCK_A,		SEL_MSIOF1_0),
1378 	PINMUX_IPSR_MSEL(IP15_23_20,	TS_SDAT0_A,		SEL_TSIF0_0),
1379 	PINMUX_IPSR_MSEL(IP15_23_20,	STP_ISD_0_A,		SEL_SSP1_0_0),
1380 	PINMUX_IPSR_MSEL(IP15_23_20,	RIF0_CLK_A,		SEL_DRIF0_0),
1381 	PINMUX_IPSR_MSEL(IP15_23_20,	RIF2_CLK_A,		SEL_DRIF2_0),
1382 
1383 	PINMUX_IPSR_GPSR(IP15_27_24,	SSI_WS4),
1384 	PINMUX_IPSR_MSEL(IP15_27_24,	HTX2_A,			SEL_HSCIF2_0),
1385 	PINMUX_IPSR_MSEL(IP15_27_24,	MSIOF1_SYNC_A,		SEL_MSIOF1_0),
1386 	PINMUX_IPSR_MSEL(IP15_27_24,	TS_SDEN0_A,		SEL_TSIF0_0),
1387 	PINMUX_IPSR_MSEL(IP15_27_24,	STP_ISEN_0_A,		SEL_SSP1_0_0),
1388 	PINMUX_IPSR_MSEL(IP15_27_24,	RIF0_SYNC_A,		SEL_DRIF0_0),
1389 	PINMUX_IPSR_MSEL(IP15_27_24,	RIF2_SYNC_A,		SEL_DRIF2_0),
1390 
1391 	PINMUX_IPSR_GPSR(IP15_31_28,	SSI_SDATA4),
1392 	PINMUX_IPSR_MSEL(IP15_31_28,	HSCK2_A,		SEL_HSCIF2_0),
1393 	PINMUX_IPSR_MSEL(IP15_31_28,	MSIOF1_RXD_A,		SEL_MSIOF1_0),
1394 	PINMUX_IPSR_MSEL(IP15_31_28,	TS_SPSYNC0_A,		SEL_TSIF0_0),
1395 	PINMUX_IPSR_MSEL(IP15_31_28,	STP_ISSYNC_0_A,		SEL_SSP1_0_0),
1396 	PINMUX_IPSR_MSEL(IP15_31_28,	RIF0_D0_A,		SEL_DRIF0_0),
1397 	PINMUX_IPSR_MSEL(IP15_31_28,	RIF2_D1_A,		SEL_DRIF2_0),
1398 
1399 	/* IPSR16 */
1400 	PINMUX_IPSR_GPSR(IP16_3_0,	SSI_SCK6),
1401 	PINMUX_IPSR_GPSR(IP16_3_0,	USB2_PWEN),
1402 	PINMUX_IPSR_MSEL(IP16_3_0,	SIM0_RST_D,		SEL_SIMCARD_3),
1403 
1404 	PINMUX_IPSR_GPSR(IP16_7_4,	SSI_WS6),
1405 	PINMUX_IPSR_GPSR(IP16_7_4,	USB2_OVC),
1406 	PINMUX_IPSR_MSEL(IP16_7_4,	SIM0_D_D,		SEL_SIMCARD_3),
1407 
1408 	PINMUX_IPSR_GPSR(IP16_11_8,	SSI_SDATA6),
1409 	PINMUX_IPSR_MSEL(IP16_11_8,	SIM0_CLK_D,		SEL_SIMCARD_3),
1410 	PINMUX_IPSR_GPSR(IP16_11_8,	SATA_DEVSLP_A),
1411 
1412 	PINMUX_IPSR_GPSR(IP16_15_12,	SSI_SCK78),
1413 	PINMUX_IPSR_MSEL(IP16_15_12,	HRX2_B,			SEL_HSCIF2_1),
1414 	PINMUX_IPSR_MSEL(IP16_15_12,	MSIOF1_SCK_C,		SEL_MSIOF1_2),
1415 	PINMUX_IPSR_MSEL(IP16_15_12,	TS_SCK1_A,		SEL_TSIF1_0),
1416 	PINMUX_IPSR_MSEL(IP16_15_12,	STP_ISCLK_1_A,		SEL_SSP1_1_0),
1417 	PINMUX_IPSR_MSEL(IP16_15_12,	RIF1_CLK_A,		SEL_DRIF1_0),
1418 	PINMUX_IPSR_MSEL(IP16_15_12,	RIF3_CLK_A,		SEL_DRIF3_0),
1419 
1420 	PINMUX_IPSR_GPSR(IP16_19_16,	SSI_WS78),
1421 	PINMUX_IPSR_MSEL(IP16_19_16,	HTX2_B,			SEL_HSCIF2_1),
1422 	PINMUX_IPSR_MSEL(IP16_19_16,	MSIOF1_SYNC_C,		SEL_MSIOF1_2),
1423 	PINMUX_IPSR_MSEL(IP16_19_16,	TS_SDAT1_A,		SEL_TSIF1_0),
1424 	PINMUX_IPSR_MSEL(IP16_19_16,	STP_ISD_1_A,		SEL_SSP1_1_0),
1425 	PINMUX_IPSR_MSEL(IP16_19_16,	RIF1_SYNC_A,		SEL_DRIF1_0),
1426 	PINMUX_IPSR_MSEL(IP16_19_16,	RIF3_SYNC_A,		SEL_DRIF3_0),
1427 
1428 	PINMUX_IPSR_GPSR(IP16_23_20,	SSI_SDATA7),
1429 	PINMUX_IPSR_MSEL(IP16_23_20,	HCTS2_N_B,		SEL_HSCIF2_1),
1430 	PINMUX_IPSR_MSEL(IP16_23_20,	MSIOF1_RXD_C,		SEL_MSIOF1_2),
1431 	PINMUX_IPSR_MSEL(IP16_23_20,	TS_SDEN1_A,		SEL_TSIF1_0),
1432 	PINMUX_IPSR_MSEL(IP16_23_20,	STP_ISEN_1_A,		SEL_SSP1_1_0),
1433 	PINMUX_IPSR_MSEL(IP16_23_20,	RIF1_D0_A,		SEL_DRIF1_0),
1434 	PINMUX_IPSR_MSEL(IP16_23_20,	RIF3_D0_A,		SEL_DRIF3_0),
1435 	PINMUX_IPSR_MSEL(IP16_23_20,	TCLK2_A,		SEL_TIMER_TMU2_0),
1436 
1437 	PINMUX_IPSR_GPSR(IP16_27_24,	SSI_SDATA8),
1438 	PINMUX_IPSR_MSEL(IP16_27_24,	HRTS2_N_B,		SEL_HSCIF2_1),
1439 	PINMUX_IPSR_MSEL(IP16_27_24,	MSIOF1_TXD_C,		SEL_MSIOF1_2),
1440 	PINMUX_IPSR_MSEL(IP16_27_24,	TS_SPSYNC1_A,		SEL_TSIF1_0),
1441 	PINMUX_IPSR_MSEL(IP16_27_24,	STP_ISSYNC_1_A,		SEL_SSP1_1_0),
1442 	PINMUX_IPSR_MSEL(IP16_27_24,	RIF1_D1_A,		SEL_DRIF1_0),
1443 	PINMUX_IPSR_MSEL(IP16_27_24,	RIF3_D1_A,		SEL_DRIF3_0),
1444 
1445 	PINMUX_IPSR_MSEL(IP16_31_28,	SSI_SDATA9_A,		SEL_SSI9_0),
1446 	PINMUX_IPSR_MSEL(IP16_31_28,	HSCK2_B,		SEL_HSCIF2_1),
1447 	PINMUX_IPSR_MSEL(IP16_31_28,	MSIOF1_SS1_C,		SEL_MSIOF1_2),
1448 	PINMUX_IPSR_MSEL(IP16_31_28,	HSCK1_A,		SEL_HSCIF1_0),
1449 	PINMUX_IPSR_MSEL(IP16_31_28,	SSI_WS1_B,		SEL_SSI1_1),
1450 	PINMUX_IPSR_GPSR(IP16_31_28,	SCK1),
1451 	PINMUX_IPSR_MSEL(IP16_31_28,	STP_IVCXO27_1_A,	SEL_SSP1_1_0),
1452 	PINMUX_IPSR_MSEL(IP16_31_28,	SCK5_A,			SEL_SCIF5_0),
1453 
1454 	/* IPSR17 */
1455 	PINMUX_IPSR_MSEL(IP17_3_0,	AUDIO_CLKA_A,		SEL_ADGA_0),
1456 
1457 	PINMUX_IPSR_MSEL(IP17_7_4,	AUDIO_CLKB_B,		SEL_ADGB_1),
1458 	PINMUX_IPSR_MSEL(IP17_7_4,	SCIF_CLK_A,		SEL_SCIF_0),
1459 	PINMUX_IPSR_MSEL(IP17_7_4,	STP_IVCXO27_1_D,	SEL_SSP1_1_3),
1460 	PINMUX_IPSR_MSEL(IP17_7_4,	REMOCON_A,		SEL_REMOCON_0),
1461 	PINMUX_IPSR_MSEL(IP17_7_4,	TCLK1_A,		SEL_TIMER_TMU1_0),
1462 
1463 	PINMUX_IPSR_GPSR(IP17_11_8,	USB0_PWEN),
1464 	PINMUX_IPSR_MSEL(IP17_11_8,	SIM0_RST_C,		SEL_SIMCARD_2),
1465 	PINMUX_IPSR_MSEL(IP17_11_8,	TS_SCK1_D,		SEL_TSIF1_3),
1466 	PINMUX_IPSR_MSEL(IP17_11_8,	STP_ISCLK_1_D,		SEL_SSP1_1_3),
1467 	PINMUX_IPSR_MSEL(IP17_11_8,	BPFCLK_B,		SEL_FM_1),
1468 	PINMUX_IPSR_MSEL(IP17_11_8,	RIF3_CLK_B,		SEL_DRIF3_1),
1469 	PINMUX_IPSR_MSEL(IP17_11_8,	HSCK2_C,		SEL_HSCIF2_2),
1470 
1471 	PINMUX_IPSR_GPSR(IP17_15_12,	USB0_OVC),
1472 	PINMUX_IPSR_MSEL(IP17_15_12,	SIM0_D_C,		SEL_SIMCARD_2),
1473 	PINMUX_IPSR_MSEL(IP17_15_12,	TS_SDAT1_D,		SEL_TSIF1_3),
1474 	PINMUX_IPSR_MSEL(IP17_15_12,	STP_ISD_1_D,		SEL_SSP1_1_3),
1475 	PINMUX_IPSR_MSEL(IP17_15_12,	RIF3_SYNC_B,		SEL_DRIF3_1),
1476 	PINMUX_IPSR_MSEL(IP17_15_12,	HRX2_C,			SEL_HSCIF2_2),
1477 
1478 	PINMUX_IPSR_GPSR(IP17_19_16,	USB1_PWEN),
1479 	PINMUX_IPSR_MSEL(IP17_19_16,	SIM0_CLK_C,		SEL_SIMCARD_2),
1480 	PINMUX_IPSR_MSEL(IP17_19_16,	SSI_SCK1_A,		SEL_SSI1_0),
1481 	PINMUX_IPSR_MSEL(IP17_19_16,	TS_SCK0_E,		SEL_TSIF0_4),
1482 	PINMUX_IPSR_MSEL(IP17_19_16,	STP_ISCLK_0_E,		SEL_SSP1_0_4),
1483 	PINMUX_IPSR_MSEL(IP17_19_16,	FMCLK_B,		SEL_FM_1),
1484 	PINMUX_IPSR_MSEL(IP17_19_16,	RIF2_CLK_B,		SEL_DRIF2_1),
1485 	PINMUX_IPSR_MSEL(IP17_19_16,	SPEEDIN_A,		SEL_SPEED_PULSE_0),
1486 	PINMUX_IPSR_MSEL(IP17_19_16,	HTX2_C,			SEL_HSCIF2_2),
1487 
1488 	PINMUX_IPSR_GPSR(IP17_23_20,	USB1_OVC),
1489 	PINMUX_IPSR_MSEL(IP17_23_20,	MSIOF1_SS2_C,		SEL_MSIOF1_2),
1490 	PINMUX_IPSR_MSEL(IP17_23_20,	SSI_WS1_A,		SEL_SSI1_0),
1491 	PINMUX_IPSR_MSEL(IP17_23_20,	TS_SDAT0_E,		SEL_TSIF0_4),
1492 	PINMUX_IPSR_MSEL(IP17_23_20,	STP_ISD_0_E,		SEL_SSP1_0_4),
1493 	PINMUX_IPSR_MSEL(IP17_23_20,	FMIN_B,			SEL_FM_1),
1494 	PINMUX_IPSR_MSEL(IP17_23_20,	RIF2_SYNC_B,		SEL_DRIF2_1),
1495 	PINMUX_IPSR_MSEL(IP17_23_20,	REMOCON_B,		SEL_REMOCON_1),
1496 	PINMUX_IPSR_MSEL(IP17_23_20,	HCTS2_N_C,		SEL_HSCIF2_2),
1497 
1498 	PINMUX_IPSR_GPSR(IP17_27_24,	USB30_PWEN),
1499 	PINMUX_IPSR_GPSR(IP17_27_24,	AUDIO_CLKOUT_B),
1500 	PINMUX_IPSR_MSEL(IP17_27_24,	SSI_SCK2_B,		SEL_SSI2_1),
1501 	PINMUX_IPSR_MSEL(IP17_27_24,	TS_SDEN1_D,		SEL_TSIF1_3),
1502 	PINMUX_IPSR_MSEL(IP17_27_24,	STP_ISEN_1_D,		SEL_SSP1_1_3),
1503 	PINMUX_IPSR_MSEL(IP17_27_24,	STP_OPWM_0_E,		SEL_SSP1_0_4),
1504 	PINMUX_IPSR_MSEL(IP17_27_24,	RIF3_D0_B,		SEL_DRIF3_1),
1505 	PINMUX_IPSR_MSEL(IP17_27_24,	TCLK2_B,		SEL_TIMER_TMU2_1),
1506 	PINMUX_IPSR_GPSR(IP17_27_24,	TPU0TO0),
1507 	PINMUX_IPSR_MSEL(IP17_27_24,	BPFCLK_C,		SEL_FM_2),
1508 	PINMUX_IPSR_MSEL(IP17_27_24,	HRTS2_N_C,		SEL_HSCIF2_2),
1509 
1510 	PINMUX_IPSR_GPSR(IP17_31_28,	USB30_OVC),
1511 	PINMUX_IPSR_GPSR(IP17_31_28,	AUDIO_CLKOUT1_B),
1512 	PINMUX_IPSR_MSEL(IP17_31_28,	SSI_WS2_B,		SEL_SSI2_1),
1513 	PINMUX_IPSR_MSEL(IP17_31_28,	TS_SPSYNC1_D,		SEL_TSIF1_3),
1514 	PINMUX_IPSR_MSEL(IP17_31_28,	STP_ISSYNC_1_D,		SEL_SSP1_1_3),
1515 	PINMUX_IPSR_MSEL(IP17_31_28,	STP_IVCXO27_0_E,	SEL_SSP1_0_4),
1516 	PINMUX_IPSR_MSEL(IP17_31_28,	RIF3_D1_B,		SEL_DRIF3_1),
1517 	PINMUX_IPSR_GPSR(IP17_31_28,	FSO_TOE_N),
1518 	PINMUX_IPSR_GPSR(IP17_31_28,	TPU0TO1),
1519 
1520 	/* IPSR18 */
1521 	PINMUX_IPSR_GPSR(IP18_3_0,	USB2_CH3_PWEN),
1522 	PINMUX_IPSR_GPSR(IP18_3_0,	AUDIO_CLKOUT2_B),
1523 	PINMUX_IPSR_MSEL(IP18_3_0,	SSI_SCK9_B,		SEL_SSI9_1),
1524 	PINMUX_IPSR_MSEL(IP18_3_0,	TS_SDEN0_E,		SEL_TSIF0_4),
1525 	PINMUX_IPSR_MSEL(IP18_3_0,	STP_ISEN_0_E,		SEL_SSP1_0_4),
1526 	PINMUX_IPSR_MSEL(IP18_3_0,	RIF2_D0_B,		SEL_DRIF2_1),
1527 	PINMUX_IPSR_GPSR(IP18_3_0,	TPU0TO2),
1528 	PINMUX_IPSR_MSEL(IP18_3_0,	FMCLK_C,		SEL_FM_2),
1529 	PINMUX_IPSR_MSEL(IP18_3_0,	FMCLK_D,		SEL_FM_3),
1530 
1531 	PINMUX_IPSR_GPSR(IP18_7_4,	USB2_CH3_OVC),
1532 	PINMUX_IPSR_GPSR(IP18_7_4,	AUDIO_CLKOUT3_B),
1533 	PINMUX_IPSR_MSEL(IP18_7_4,	SSI_WS9_B,		SEL_SSI9_1),
1534 	PINMUX_IPSR_MSEL(IP18_7_4,	TS_SPSYNC0_E,		SEL_TSIF0_4),
1535 	PINMUX_IPSR_MSEL(IP18_7_4,	STP_ISSYNC_0_E,		SEL_SSP1_0_4),
1536 	PINMUX_IPSR_MSEL(IP18_7_4,	RIF2_D1_B,		SEL_DRIF2_1),
1537 	PINMUX_IPSR_GPSR(IP18_7_4,	TPU0TO3),
1538 	PINMUX_IPSR_MSEL(IP18_7_4,	FMIN_C,			SEL_FM_2),
1539 	PINMUX_IPSR_MSEL(IP18_7_4,	FMIN_D,			SEL_FM_3),
1540 
1541 /*
1542  * Static pins can not be muxed between different functions but
1543  * still need mark entries in the pinmux list. Add each static
1544  * pin to the list without an associated function. The sh-pfc
1545  * core will do the right thing and skip trying to mux the pin
1546  * while still applying configuration to it.
1547  */
1548 #define FM(x)	PINMUX_DATA(x##_MARK, 0),
1549 	PINMUX_STATIC
1550 #undef FM
1551 };
1552 
1553 /*
1554  * Pins not associated with a GPIO port.
1555  */
1556 enum {
1557 	GP_ASSIGN_LAST(),
1558 	NOGP_ALL(),
1559 };
1560 
1561 static const struct sh_pfc_pin pinmux_pins[] = {
1562 	PINMUX_GPIO_GP_ALL(),
1563 	PINMUX_NOGP_ALL(),
1564 };
1565 
1566 /* - AUDIO CLOCK ------------------------------------------------------------ */
1567 static const unsigned int audio_clk_a_a_pins[] = {
1568 	/* CLK A */
1569 	RCAR_GP_PIN(6, 22),
1570 };
1571 static const unsigned int audio_clk_a_a_mux[] = {
1572 	AUDIO_CLKA_A_MARK,
1573 };
1574 static const unsigned int audio_clk_a_b_pins[] = {
1575 	/* CLK A */
1576 	RCAR_GP_PIN(5, 4),
1577 };
1578 static const unsigned int audio_clk_a_b_mux[] = {
1579 	AUDIO_CLKA_B_MARK,
1580 };
1581 static const unsigned int audio_clk_a_c_pins[] = {
1582 	/* CLK A */
1583 	RCAR_GP_PIN(5, 19),
1584 };
1585 static const unsigned int audio_clk_a_c_mux[] = {
1586 	AUDIO_CLKA_C_MARK,
1587 };
1588 static const unsigned int audio_clk_b_a_pins[] = {
1589 	/* CLK B */
1590 	RCAR_GP_PIN(5, 12),
1591 };
1592 static const unsigned int audio_clk_b_a_mux[] = {
1593 	AUDIO_CLKB_A_MARK,
1594 };
1595 static const unsigned int audio_clk_b_b_pins[] = {
1596 	/* CLK B */
1597 	RCAR_GP_PIN(6, 23),
1598 };
1599 static const unsigned int audio_clk_b_b_mux[] = {
1600 	AUDIO_CLKB_B_MARK,
1601 };
1602 static const unsigned int audio_clk_c_a_pins[] = {
1603 	/* CLK C */
1604 	RCAR_GP_PIN(5, 21),
1605 };
1606 static const unsigned int audio_clk_c_a_mux[] = {
1607 	AUDIO_CLKC_A_MARK,
1608 };
1609 static const unsigned int audio_clk_c_b_pins[] = {
1610 	/* CLK C */
1611 	RCAR_GP_PIN(5, 0),
1612 };
1613 static const unsigned int audio_clk_c_b_mux[] = {
1614 	AUDIO_CLKC_B_MARK,
1615 };
1616 static const unsigned int audio_clkout_a_pins[] = {
1617 	/* CLKOUT */
1618 	RCAR_GP_PIN(5, 18),
1619 };
1620 static const unsigned int audio_clkout_a_mux[] = {
1621 	AUDIO_CLKOUT_A_MARK,
1622 };
1623 static const unsigned int audio_clkout_b_pins[] = {
1624 	/* CLKOUT */
1625 	RCAR_GP_PIN(6, 28),
1626 };
1627 static const unsigned int audio_clkout_b_mux[] = {
1628 	AUDIO_CLKOUT_B_MARK,
1629 };
1630 static const unsigned int audio_clkout_c_pins[] = {
1631 	/* CLKOUT */
1632 	RCAR_GP_PIN(5, 3),
1633 };
1634 static const unsigned int audio_clkout_c_mux[] = {
1635 	AUDIO_CLKOUT_C_MARK,
1636 };
1637 static const unsigned int audio_clkout_d_pins[] = {
1638 	/* CLKOUT */
1639 	RCAR_GP_PIN(5, 21),
1640 };
1641 static const unsigned int audio_clkout_d_mux[] = {
1642 	AUDIO_CLKOUT_D_MARK,
1643 };
1644 static const unsigned int audio_clkout1_a_pins[] = {
1645 	/* CLKOUT1 */
1646 	RCAR_GP_PIN(5, 15),
1647 };
1648 static const unsigned int audio_clkout1_a_mux[] = {
1649 	AUDIO_CLKOUT1_A_MARK,
1650 };
1651 static const unsigned int audio_clkout1_b_pins[] = {
1652 	/* CLKOUT1 */
1653 	RCAR_GP_PIN(6, 29),
1654 };
1655 static const unsigned int audio_clkout1_b_mux[] = {
1656 	AUDIO_CLKOUT1_B_MARK,
1657 };
1658 static const unsigned int audio_clkout2_a_pins[] = {
1659 	/* CLKOUT2 */
1660 	RCAR_GP_PIN(5, 16),
1661 };
1662 static const unsigned int audio_clkout2_a_mux[] = {
1663 	AUDIO_CLKOUT2_A_MARK,
1664 };
1665 static const unsigned int audio_clkout2_b_pins[] = {
1666 	/* CLKOUT2 */
1667 	RCAR_GP_PIN(6, 30),
1668 };
1669 static const unsigned int audio_clkout2_b_mux[] = {
1670 	AUDIO_CLKOUT2_B_MARK,
1671 };
1672 static const unsigned int audio_clkout3_a_pins[] = {
1673 	/* CLKOUT3 */
1674 	RCAR_GP_PIN(5, 19),
1675 };
1676 static const unsigned int audio_clkout3_a_mux[] = {
1677 	AUDIO_CLKOUT3_A_MARK,
1678 };
1679 static const unsigned int audio_clkout3_b_pins[] = {
1680 	/* CLKOUT3 */
1681 	RCAR_GP_PIN(6, 31),
1682 };
1683 static const unsigned int audio_clkout3_b_mux[] = {
1684 	AUDIO_CLKOUT3_B_MARK,
1685 };
1686 
1687 /* - EtherAVB --------------------------------------------------------------- */
1688 static const unsigned int avb_link_pins[] = {
1689 	/* AVB_LINK */
1690 	RCAR_GP_PIN(2, 12),
1691 };
1692 static const unsigned int avb_link_mux[] = {
1693 	AVB_LINK_MARK,
1694 };
1695 static const unsigned int avb_magic_pins[] = {
1696 	/* AVB_MAGIC_ */
1697 	RCAR_GP_PIN(2, 10),
1698 };
1699 static const unsigned int avb_magic_mux[] = {
1700 	AVB_MAGIC_MARK,
1701 };
1702 static const unsigned int avb_phy_int_pins[] = {
1703 	/* AVB_PHY_INT */
1704 	RCAR_GP_PIN(2, 11),
1705 };
1706 static const unsigned int avb_phy_int_mux[] = {
1707 	AVB_PHY_INT_MARK,
1708 };
1709 static const unsigned int avb_mdio_pins[] = {
1710 	/* AVB_MDC, AVB_MDIO */
1711 	RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
1712 };
1713 static const unsigned int avb_mdio_mux[] = {
1714 	AVB_MDC_MARK, AVB_MDIO_MARK,
1715 };
1716 static const unsigned int avb_mii_pins[] = {
1717 	/*
1718 	 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1719 	 * AVB_TD1, AVB_TD2, AVB_TD3,
1720 	 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1721 	 * AVB_RD1, AVB_RD2, AVB_RD3,
1722 	 * AVB_TXCREFCLK
1723 	 */
1724 	PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1725 	PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1726 	PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1727 	PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1728 	PIN_AVB_TXCREFCLK,
1729 };
1730 static const unsigned int avb_mii_mux[] = {
1731 	AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1732 	AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1733 	AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1734 	AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1735 	AVB_TXCREFCLK_MARK,
1736 };
1737 static const unsigned int avb_avtp_pps_pins[] = {
1738 	/* AVB_AVTP_PPS */
1739 	RCAR_GP_PIN(2, 6),
1740 };
1741 static const unsigned int avb_avtp_pps_mux[] = {
1742 	AVB_AVTP_PPS_MARK,
1743 };
1744 static const unsigned int avb_avtp_match_a_pins[] = {
1745 	/* AVB_AVTP_MATCH_A */
1746 	RCAR_GP_PIN(2, 13),
1747 };
1748 static const unsigned int avb_avtp_match_a_mux[] = {
1749 	AVB_AVTP_MATCH_A_MARK,
1750 };
1751 static const unsigned int avb_avtp_capture_a_pins[] = {
1752 	/* AVB_AVTP_CAPTURE_A */
1753 	RCAR_GP_PIN(2, 14),
1754 };
1755 static const unsigned int avb_avtp_capture_a_mux[] = {
1756 	AVB_AVTP_CAPTURE_A_MARK,
1757 };
1758 static const unsigned int avb_avtp_match_b_pins[] = {
1759 	/*  AVB_AVTP_MATCH_B */
1760 	RCAR_GP_PIN(1, 8),
1761 };
1762 static const unsigned int avb_avtp_match_b_mux[] = {
1763 	AVB_AVTP_MATCH_B_MARK,
1764 };
1765 static const unsigned int avb_avtp_capture_b_pins[] = {
1766 	/* AVB_AVTP_CAPTURE_B */
1767 	RCAR_GP_PIN(1, 11),
1768 };
1769 static const unsigned int avb_avtp_capture_b_mux[] = {
1770 	AVB_AVTP_CAPTURE_B_MARK,
1771 };
1772 
1773 /* - CAN ------------------------------------------------------------------ */
1774 static const unsigned int can0_data_a_pins[] = {
1775 	/* TX, RX */
1776 	RCAR_GP_PIN(1, 23),	RCAR_GP_PIN(1, 24),
1777 };
1778 static const unsigned int can0_data_a_mux[] = {
1779 	CAN0_TX_A_MARK,		CAN0_RX_A_MARK,
1780 };
1781 static const unsigned int can0_data_b_pins[] = {
1782 	/* TX, RX */
1783 	RCAR_GP_PIN(2, 0),	RCAR_GP_PIN(2, 1),
1784 };
1785 static const unsigned int can0_data_b_mux[] = {
1786 	CAN0_TX_B_MARK,		CAN0_RX_B_MARK,
1787 };
1788 static const unsigned int can1_data_pins[] = {
1789 	/* TX, RX */
1790 	RCAR_GP_PIN(1, 22),	RCAR_GP_PIN(1, 26),
1791 };
1792 static const unsigned int can1_data_mux[] = {
1793 	CAN1_TX_MARK,		CAN1_RX_MARK,
1794 };
1795 
1796 /* - CAN Clock -------------------------------------------------------------- */
1797 static const unsigned int can_clk_pins[] = {
1798 	/* CLK */
1799 	RCAR_GP_PIN(1, 25),
1800 };
1801 static const unsigned int can_clk_mux[] = {
1802 	CAN_CLK_MARK,
1803 };
1804 
1805 /* - CAN FD --------------------------------------------------------------- */
1806 static const unsigned int canfd0_data_a_pins[] = {
1807 	/* TX, RX */
1808 	RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1809 };
1810 static const unsigned int canfd0_data_a_mux[] = {
1811 	CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
1812 };
1813 static const unsigned int canfd0_data_b_pins[] = {
1814 	/* TX, RX */
1815 	RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1816 };
1817 static const unsigned int canfd0_data_b_mux[] = {
1818 	CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
1819 };
1820 static const unsigned int canfd1_data_pins[] = {
1821 	/* TX, RX */
1822 	RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1823 };
1824 static const unsigned int canfd1_data_mux[] = {
1825 	CANFD1_TX_MARK,         CANFD1_RX_MARK,
1826 };
1827 
1828 #ifdef CONFIG_PINCTRL_PFC_R8A77951
1829 /* - DRIF0 --------------------------------------------------------------- */
1830 static const unsigned int drif0_ctrl_a_pins[] = {
1831 	/* CLK, SYNC */
1832 	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1833 };
1834 static const unsigned int drif0_ctrl_a_mux[] = {
1835 	RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1836 };
1837 static const unsigned int drif0_data0_a_pins[] = {
1838 	/* D0 */
1839 	RCAR_GP_PIN(6, 10),
1840 };
1841 static const unsigned int drif0_data0_a_mux[] = {
1842 	RIF0_D0_A_MARK,
1843 };
1844 static const unsigned int drif0_data1_a_pins[] = {
1845 	/* D1 */
1846 	RCAR_GP_PIN(6, 7),
1847 };
1848 static const unsigned int drif0_data1_a_mux[] = {
1849 	RIF0_D1_A_MARK,
1850 };
1851 static const unsigned int drif0_ctrl_b_pins[] = {
1852 	/* CLK, SYNC */
1853 	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1854 };
1855 static const unsigned int drif0_ctrl_b_mux[] = {
1856 	RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1857 };
1858 static const unsigned int drif0_data0_b_pins[] = {
1859 	/* D0 */
1860 	RCAR_GP_PIN(5, 1),
1861 };
1862 static const unsigned int drif0_data0_b_mux[] = {
1863 	RIF0_D0_B_MARK,
1864 };
1865 static const unsigned int drif0_data1_b_pins[] = {
1866 	/* D1 */
1867 	RCAR_GP_PIN(5, 2),
1868 };
1869 static const unsigned int drif0_data1_b_mux[] = {
1870 	RIF0_D1_B_MARK,
1871 };
1872 static const unsigned int drif0_ctrl_c_pins[] = {
1873 	/* CLK, SYNC */
1874 	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1875 };
1876 static const unsigned int drif0_ctrl_c_mux[] = {
1877 	RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1878 };
1879 static const unsigned int drif0_data0_c_pins[] = {
1880 	/* D0 */
1881 	RCAR_GP_PIN(5, 13),
1882 };
1883 static const unsigned int drif0_data0_c_mux[] = {
1884 	RIF0_D0_C_MARK,
1885 };
1886 static const unsigned int drif0_data1_c_pins[] = {
1887 	/* D1 */
1888 	RCAR_GP_PIN(5, 14),
1889 };
1890 static const unsigned int drif0_data1_c_mux[] = {
1891 	RIF0_D1_C_MARK,
1892 };
1893 /* - DRIF1 --------------------------------------------------------------- */
1894 static const unsigned int drif1_ctrl_a_pins[] = {
1895 	/* CLK, SYNC */
1896 	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1897 };
1898 static const unsigned int drif1_ctrl_a_mux[] = {
1899 	RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1900 };
1901 static const unsigned int drif1_data0_a_pins[] = {
1902 	/* D0 */
1903 	RCAR_GP_PIN(6, 19),
1904 };
1905 static const unsigned int drif1_data0_a_mux[] = {
1906 	RIF1_D0_A_MARK,
1907 };
1908 static const unsigned int drif1_data1_a_pins[] = {
1909 	/* D1 */
1910 	RCAR_GP_PIN(6, 20),
1911 };
1912 static const unsigned int drif1_data1_a_mux[] = {
1913 	RIF1_D1_A_MARK,
1914 };
1915 static const unsigned int drif1_ctrl_b_pins[] = {
1916 	/* CLK, SYNC */
1917 	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1918 };
1919 static const unsigned int drif1_ctrl_b_mux[] = {
1920 	RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1921 };
1922 static const unsigned int drif1_data0_b_pins[] = {
1923 	/* D0 */
1924 	RCAR_GP_PIN(5, 7),
1925 };
1926 static const unsigned int drif1_data0_b_mux[] = {
1927 	RIF1_D0_B_MARK,
1928 };
1929 static const unsigned int drif1_data1_b_pins[] = {
1930 	/* D1 */
1931 	RCAR_GP_PIN(5, 8),
1932 };
1933 static const unsigned int drif1_data1_b_mux[] = {
1934 	RIF1_D1_B_MARK,
1935 };
1936 static const unsigned int drif1_ctrl_c_pins[] = {
1937 	/* CLK, SYNC */
1938 	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1939 };
1940 static const unsigned int drif1_ctrl_c_mux[] = {
1941 	RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1942 };
1943 static const unsigned int drif1_data0_c_pins[] = {
1944 	/* D0 */
1945 	RCAR_GP_PIN(5, 6),
1946 };
1947 static const unsigned int drif1_data0_c_mux[] = {
1948 	RIF1_D0_C_MARK,
1949 };
1950 static const unsigned int drif1_data1_c_pins[] = {
1951 	/* D1 */
1952 	RCAR_GP_PIN(5, 10),
1953 };
1954 static const unsigned int drif1_data1_c_mux[] = {
1955 	RIF1_D1_C_MARK,
1956 };
1957 /* - DRIF2 --------------------------------------------------------------- */
1958 static const unsigned int drif2_ctrl_a_pins[] = {
1959 	/* CLK, SYNC */
1960 	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1961 };
1962 static const unsigned int drif2_ctrl_a_mux[] = {
1963 	RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1964 };
1965 static const unsigned int drif2_data0_a_pins[] = {
1966 	/* D0 */
1967 	RCAR_GP_PIN(6, 7),
1968 };
1969 static const unsigned int drif2_data0_a_mux[] = {
1970 	RIF2_D0_A_MARK,
1971 };
1972 static const unsigned int drif2_data1_a_pins[] = {
1973 	/* D1 */
1974 	RCAR_GP_PIN(6, 10),
1975 };
1976 static const unsigned int drif2_data1_a_mux[] = {
1977 	RIF2_D1_A_MARK,
1978 };
1979 static const unsigned int drif2_ctrl_b_pins[] = {
1980 	/* CLK, SYNC */
1981 	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1982 };
1983 static const unsigned int drif2_ctrl_b_mux[] = {
1984 	RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1985 };
1986 static const unsigned int drif2_data0_b_pins[] = {
1987 	/* D0 */
1988 	RCAR_GP_PIN(6, 30),
1989 };
1990 static const unsigned int drif2_data0_b_mux[] = {
1991 	RIF2_D0_B_MARK,
1992 };
1993 static const unsigned int drif2_data1_b_pins[] = {
1994 	/* D1 */
1995 	RCAR_GP_PIN(6, 31),
1996 };
1997 static const unsigned int drif2_data1_b_mux[] = {
1998 	RIF2_D1_B_MARK,
1999 };
2000 /* - DRIF3 --------------------------------------------------------------- */
2001 static const unsigned int drif3_ctrl_a_pins[] = {
2002 	/* CLK, SYNC */
2003 	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2004 };
2005 static const unsigned int drif3_ctrl_a_mux[] = {
2006 	RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2007 };
2008 static const unsigned int drif3_data0_a_pins[] = {
2009 	/* D0 */
2010 	RCAR_GP_PIN(6, 19),
2011 };
2012 static const unsigned int drif3_data0_a_mux[] = {
2013 	RIF3_D0_A_MARK,
2014 };
2015 static const unsigned int drif3_data1_a_pins[] = {
2016 	/* D1 */
2017 	RCAR_GP_PIN(6, 20),
2018 };
2019 static const unsigned int drif3_data1_a_mux[] = {
2020 	RIF3_D1_A_MARK,
2021 };
2022 static const unsigned int drif3_ctrl_b_pins[] = {
2023 	/* CLK, SYNC */
2024 	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2025 };
2026 static const unsigned int drif3_ctrl_b_mux[] = {
2027 	RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2028 };
2029 static const unsigned int drif3_data0_b_pins[] = {
2030 	/* D0 */
2031 	RCAR_GP_PIN(6, 28),
2032 };
2033 static const unsigned int drif3_data0_b_mux[] = {
2034 	RIF3_D0_B_MARK,
2035 };
2036 static const unsigned int drif3_data1_b_pins[] = {
2037 	/* D1 */
2038 	RCAR_GP_PIN(6, 29),
2039 };
2040 static const unsigned int drif3_data1_b_mux[] = {
2041 	RIF3_D1_B_MARK,
2042 };
2043 #endif /* CONFIG_PINCTRL_PFC_R8A77951 */
2044 
2045 /* - DU --------------------------------------------------------------------- */
2046 static const unsigned int du_rgb666_pins[] = {
2047 	/* R[7:2], G[7:2], B[7:2] */
2048 	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2049 	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2050 	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2051 	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2052 	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2053 	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2054 };
2055 static const unsigned int du_rgb666_mux[] = {
2056 	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2057 	DU_DR3_MARK, DU_DR2_MARK,
2058 	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2059 	DU_DG3_MARK, DU_DG2_MARK,
2060 	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2061 	DU_DB3_MARK, DU_DB2_MARK,
2062 };
2063 static const unsigned int du_rgb888_pins[] = {
2064 	/* R[7:0], G[7:0], B[7:0] */
2065 	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2066 	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2067 	RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
2068 	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2069 	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2070 	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2071 	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2072 	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2073 	RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
2074 };
2075 static const unsigned int du_rgb888_mux[] = {
2076 	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2077 	DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2078 	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2079 	DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2080 	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2081 	DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2082 };
2083 static const unsigned int du_clk_out_0_pins[] = {
2084 	/* CLKOUT */
2085 	RCAR_GP_PIN(1, 27),
2086 };
2087 static const unsigned int du_clk_out_0_mux[] = {
2088 	DU_DOTCLKOUT0_MARK
2089 };
2090 static const unsigned int du_clk_out_1_pins[] = {
2091 	/* CLKOUT */
2092 	RCAR_GP_PIN(2, 3),
2093 };
2094 static const unsigned int du_clk_out_1_mux[] = {
2095 	DU_DOTCLKOUT1_MARK
2096 };
2097 static const unsigned int du_sync_pins[] = {
2098 	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2099 	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2100 };
2101 static const unsigned int du_sync_mux[] = {
2102 	DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2103 };
2104 static const unsigned int du_oddf_pins[] = {
2105 	/* EXDISP/EXODDF/EXCDE */
2106 	RCAR_GP_PIN(2, 2),
2107 };
2108 static const unsigned int du_oddf_mux[] = {
2109 	DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2110 };
2111 static const unsigned int du_cde_pins[] = {
2112 	/* CDE */
2113 	RCAR_GP_PIN(2, 0),
2114 };
2115 static const unsigned int du_cde_mux[] = {
2116 	DU_CDE_MARK,
2117 };
2118 static const unsigned int du_disp_pins[] = {
2119 	/* DISP */
2120 	RCAR_GP_PIN(2, 1),
2121 };
2122 static const unsigned int du_disp_mux[] = {
2123 	DU_DISP_MARK,
2124 };
2125 
2126 /* - HSCIF0 ----------------------------------------------------------------- */
2127 static const unsigned int hscif0_data_pins[] = {
2128 	/* RX, TX */
2129 	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2130 };
2131 static const unsigned int hscif0_data_mux[] = {
2132 	HRX0_MARK, HTX0_MARK,
2133 };
2134 static const unsigned int hscif0_clk_pins[] = {
2135 	/* SCK */
2136 	RCAR_GP_PIN(5, 12),
2137 };
2138 static const unsigned int hscif0_clk_mux[] = {
2139 	HSCK0_MARK,
2140 };
2141 static const unsigned int hscif0_ctrl_pins[] = {
2142 	/* RTS, CTS */
2143 	RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2144 };
2145 static const unsigned int hscif0_ctrl_mux[] = {
2146 	HRTS0_N_MARK, HCTS0_N_MARK,
2147 };
2148 /* - HSCIF1 ----------------------------------------------------------------- */
2149 static const unsigned int hscif1_data_a_pins[] = {
2150 	/* RX, TX */
2151 	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2152 };
2153 static const unsigned int hscif1_data_a_mux[] = {
2154 	HRX1_A_MARK, HTX1_A_MARK,
2155 };
2156 static const unsigned int hscif1_clk_a_pins[] = {
2157 	/* SCK */
2158 	RCAR_GP_PIN(6, 21),
2159 };
2160 static const unsigned int hscif1_clk_a_mux[] = {
2161 	HSCK1_A_MARK,
2162 };
2163 static const unsigned int hscif1_ctrl_a_pins[] = {
2164 	/* RTS, CTS */
2165 	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2166 };
2167 static const unsigned int hscif1_ctrl_a_mux[] = {
2168 	HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2169 };
2170 
2171 static const unsigned int hscif1_data_b_pins[] = {
2172 	/* RX, TX */
2173 	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2174 };
2175 static const unsigned int hscif1_data_b_mux[] = {
2176 	HRX1_B_MARK, HTX1_B_MARK,
2177 };
2178 static const unsigned int hscif1_clk_b_pins[] = {
2179 	/* SCK */
2180 	RCAR_GP_PIN(5, 0),
2181 };
2182 static const unsigned int hscif1_clk_b_mux[] = {
2183 	HSCK1_B_MARK,
2184 };
2185 static const unsigned int hscif1_ctrl_b_pins[] = {
2186 	/* RTS, CTS */
2187 	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2188 };
2189 static const unsigned int hscif1_ctrl_b_mux[] = {
2190 	HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2191 };
2192 /* - HSCIF2 ----------------------------------------------------------------- */
2193 static const unsigned int hscif2_data_a_pins[] = {
2194 	/* RX, TX */
2195 	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2196 };
2197 static const unsigned int hscif2_data_a_mux[] = {
2198 	HRX2_A_MARK, HTX2_A_MARK,
2199 };
2200 static const unsigned int hscif2_clk_a_pins[] = {
2201 	/* SCK */
2202 	RCAR_GP_PIN(6, 10),
2203 };
2204 static const unsigned int hscif2_clk_a_mux[] = {
2205 	HSCK2_A_MARK,
2206 };
2207 static const unsigned int hscif2_ctrl_a_pins[] = {
2208 	/* RTS, CTS */
2209 	RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2210 };
2211 static const unsigned int hscif2_ctrl_a_mux[] = {
2212 	HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2213 };
2214 
2215 static const unsigned int hscif2_data_b_pins[] = {
2216 	/* RX, TX */
2217 	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2218 };
2219 static const unsigned int hscif2_data_b_mux[] = {
2220 	HRX2_B_MARK, HTX2_B_MARK,
2221 };
2222 static const unsigned int hscif2_clk_b_pins[] = {
2223 	/* SCK */
2224 	RCAR_GP_PIN(6, 21),
2225 };
2226 static const unsigned int hscif2_clk_b_mux[] = {
2227 	HSCK2_B_MARK,
2228 };
2229 static const unsigned int hscif2_ctrl_b_pins[] = {
2230 	/* RTS, CTS */
2231 	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2232 };
2233 static const unsigned int hscif2_ctrl_b_mux[] = {
2234 	HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2235 };
2236 
2237 static const unsigned int hscif2_data_c_pins[] = {
2238 	/* RX, TX */
2239 	RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2240 };
2241 static const unsigned int hscif2_data_c_mux[] = {
2242 	HRX2_C_MARK, HTX2_C_MARK,
2243 };
2244 static const unsigned int hscif2_clk_c_pins[] = {
2245 	/* SCK */
2246 	RCAR_GP_PIN(6, 24),
2247 };
2248 static const unsigned int hscif2_clk_c_mux[] = {
2249 	HSCK2_C_MARK,
2250 };
2251 static const unsigned int hscif2_ctrl_c_pins[] = {
2252 	/* RTS, CTS */
2253 	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2254 };
2255 static const unsigned int hscif2_ctrl_c_mux[] = {
2256 	HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2257 };
2258 /* - HSCIF3 ----------------------------------------------------------------- */
2259 static const unsigned int hscif3_data_a_pins[] = {
2260 	/* RX, TX */
2261 	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2262 };
2263 static const unsigned int hscif3_data_a_mux[] = {
2264 	HRX3_A_MARK, HTX3_A_MARK,
2265 };
2266 static const unsigned int hscif3_clk_pins[] = {
2267 	/* SCK */
2268 	RCAR_GP_PIN(1, 22),
2269 };
2270 static const unsigned int hscif3_clk_mux[] = {
2271 	HSCK3_MARK,
2272 };
2273 static const unsigned int hscif3_ctrl_pins[] = {
2274 	/* RTS, CTS */
2275 	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2276 };
2277 static const unsigned int hscif3_ctrl_mux[] = {
2278 	HRTS3_N_MARK, HCTS3_N_MARK,
2279 };
2280 
2281 static const unsigned int hscif3_data_b_pins[] = {
2282 	/* RX, TX */
2283 	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2284 };
2285 static const unsigned int hscif3_data_b_mux[] = {
2286 	HRX3_B_MARK, HTX3_B_MARK,
2287 };
2288 static const unsigned int hscif3_data_c_pins[] = {
2289 	/* RX, TX */
2290 	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2291 };
2292 static const unsigned int hscif3_data_c_mux[] = {
2293 	HRX3_C_MARK, HTX3_C_MARK,
2294 };
2295 static const unsigned int hscif3_data_d_pins[] = {
2296 	/* RX, TX */
2297 	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2298 };
2299 static const unsigned int hscif3_data_d_mux[] = {
2300 	HRX3_D_MARK, HTX3_D_MARK,
2301 };
2302 /* - HSCIF4 ----------------------------------------------------------------- */
2303 static const unsigned int hscif4_data_a_pins[] = {
2304 	/* RX, TX */
2305 	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2306 };
2307 static const unsigned int hscif4_data_a_mux[] = {
2308 	HRX4_A_MARK, HTX4_A_MARK,
2309 };
2310 static const unsigned int hscif4_clk_pins[] = {
2311 	/* SCK */
2312 	RCAR_GP_PIN(1, 11),
2313 };
2314 static const unsigned int hscif4_clk_mux[] = {
2315 	HSCK4_MARK,
2316 };
2317 static const unsigned int hscif4_ctrl_pins[] = {
2318 	/* RTS, CTS */
2319 	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2320 };
2321 static const unsigned int hscif4_ctrl_mux[] = {
2322 	HRTS4_N_MARK, HCTS4_N_MARK,
2323 };
2324 
2325 static const unsigned int hscif4_data_b_pins[] = {
2326 	/* RX, TX */
2327 	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2328 };
2329 static const unsigned int hscif4_data_b_mux[] = {
2330 	HRX4_B_MARK, HTX4_B_MARK,
2331 };
2332 
2333 /* - I2C -------------------------------------------------------------------- */
2334 static const unsigned int i2c0_pins[] = {
2335 	/* SCL, SDA */
2336 	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2337 };
2338 
2339 static const unsigned int i2c0_mux[] = {
2340 	SCL0_MARK, SDA0_MARK,
2341 };
2342 
2343 static const unsigned int i2c1_a_pins[] = {
2344 	/* SDA, SCL */
2345 	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2346 };
2347 static const unsigned int i2c1_a_mux[] = {
2348 	SDA1_A_MARK, SCL1_A_MARK,
2349 };
2350 static const unsigned int i2c1_b_pins[] = {
2351 	/* SDA, SCL */
2352 	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2353 };
2354 static const unsigned int i2c1_b_mux[] = {
2355 	SDA1_B_MARK, SCL1_B_MARK,
2356 };
2357 static const unsigned int i2c2_a_pins[] = {
2358 	/* SDA, SCL */
2359 	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2360 };
2361 static const unsigned int i2c2_a_mux[] = {
2362 	SDA2_A_MARK, SCL2_A_MARK,
2363 };
2364 static const unsigned int i2c2_b_pins[] = {
2365 	/* SDA, SCL */
2366 	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2367 };
2368 static const unsigned int i2c2_b_mux[] = {
2369 	SDA2_B_MARK, SCL2_B_MARK,
2370 };
2371 
2372 static const unsigned int i2c3_pins[] = {
2373 	/* SCL, SDA */
2374 	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2375 };
2376 
2377 static const unsigned int i2c3_mux[] = {
2378 	SCL3_MARK, SDA3_MARK,
2379 };
2380 
2381 static const unsigned int i2c5_pins[] = {
2382 	/* SCL, SDA */
2383 	RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2384 };
2385 
2386 static const unsigned int i2c5_mux[] = {
2387 	SCL5_MARK, SDA5_MARK,
2388 };
2389 
2390 static const unsigned int i2c6_a_pins[] = {
2391 	/* SDA, SCL */
2392 	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2393 };
2394 static const unsigned int i2c6_a_mux[] = {
2395 	SDA6_A_MARK, SCL6_A_MARK,
2396 };
2397 static const unsigned int i2c6_b_pins[] = {
2398 	/* SDA, SCL */
2399 	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2400 };
2401 static const unsigned int i2c6_b_mux[] = {
2402 	SDA6_B_MARK, SCL6_B_MARK,
2403 };
2404 static const unsigned int i2c6_c_pins[] = {
2405 	/* SDA, SCL */
2406 	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2407 };
2408 static const unsigned int i2c6_c_mux[] = {
2409 	SDA6_C_MARK, SCL6_C_MARK,
2410 };
2411 
2412 /* - INTC-EX ---------------------------------------------------------------- */
2413 static const unsigned int intc_ex_irq0_pins[] = {
2414 	/* IRQ0 */
2415 	RCAR_GP_PIN(2, 0),
2416 };
2417 static const unsigned int intc_ex_irq0_mux[] = {
2418 	IRQ0_MARK,
2419 };
2420 static const unsigned int intc_ex_irq1_pins[] = {
2421 	/* IRQ1 */
2422 	RCAR_GP_PIN(2, 1),
2423 };
2424 static const unsigned int intc_ex_irq1_mux[] = {
2425 	IRQ1_MARK,
2426 };
2427 static const unsigned int intc_ex_irq2_pins[] = {
2428 	/* IRQ2 */
2429 	RCAR_GP_PIN(2, 2),
2430 };
2431 static const unsigned int intc_ex_irq2_mux[] = {
2432 	IRQ2_MARK,
2433 };
2434 static const unsigned int intc_ex_irq3_pins[] = {
2435 	/* IRQ3 */
2436 	RCAR_GP_PIN(2, 3),
2437 };
2438 static const unsigned int intc_ex_irq3_mux[] = {
2439 	IRQ3_MARK,
2440 };
2441 static const unsigned int intc_ex_irq4_pins[] = {
2442 	/* IRQ4 */
2443 	RCAR_GP_PIN(2, 4),
2444 };
2445 static const unsigned int intc_ex_irq4_mux[] = {
2446 	IRQ4_MARK,
2447 };
2448 static const unsigned int intc_ex_irq5_pins[] = {
2449 	/* IRQ5 */
2450 	RCAR_GP_PIN(2, 5),
2451 };
2452 static const unsigned int intc_ex_irq5_mux[] = {
2453 	IRQ5_MARK,
2454 };
2455 
2456 #ifdef CONFIG_PINCTRL_PFC_R8A77951
2457 /* - MLB+ ------------------------------------------------------------------- */
2458 static const unsigned int mlb_3pin_pins[] = {
2459 	RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2460 };
2461 static const unsigned int mlb_3pin_mux[] = {
2462 	MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2463 };
2464 #endif /* CONFIG_PINCTRL_PFC_R8A77951 */
2465 
2466 /* - MSIOF0 ----------------------------------------------------------------- */
2467 static const unsigned int msiof0_clk_pins[] = {
2468 	/* SCK */
2469 	RCAR_GP_PIN(5, 17),
2470 };
2471 static const unsigned int msiof0_clk_mux[] = {
2472 	MSIOF0_SCK_MARK,
2473 };
2474 static const unsigned int msiof0_sync_pins[] = {
2475 	/* SYNC */
2476 	RCAR_GP_PIN(5, 18),
2477 };
2478 static const unsigned int msiof0_sync_mux[] = {
2479 	MSIOF0_SYNC_MARK,
2480 };
2481 static const unsigned int msiof0_ss1_pins[] = {
2482 	/* SS1 */
2483 	RCAR_GP_PIN(5, 19),
2484 };
2485 static const unsigned int msiof0_ss1_mux[] = {
2486 	MSIOF0_SS1_MARK,
2487 };
2488 static const unsigned int msiof0_ss2_pins[] = {
2489 	/* SS2 */
2490 	RCAR_GP_PIN(5, 21),
2491 };
2492 static const unsigned int msiof0_ss2_mux[] = {
2493 	MSIOF0_SS2_MARK,
2494 };
2495 static const unsigned int msiof0_txd_pins[] = {
2496 	/* TXD */
2497 	RCAR_GP_PIN(5, 20),
2498 };
2499 static const unsigned int msiof0_txd_mux[] = {
2500 	MSIOF0_TXD_MARK,
2501 };
2502 static const unsigned int msiof0_rxd_pins[] = {
2503 	/* RXD */
2504 	RCAR_GP_PIN(5, 22),
2505 };
2506 static const unsigned int msiof0_rxd_mux[] = {
2507 	MSIOF0_RXD_MARK,
2508 };
2509 /* - MSIOF1 ----------------------------------------------------------------- */
2510 static const unsigned int msiof1_clk_a_pins[] = {
2511 	/* SCK */
2512 	RCAR_GP_PIN(6, 8),
2513 };
2514 static const unsigned int msiof1_clk_a_mux[] = {
2515 	MSIOF1_SCK_A_MARK,
2516 };
2517 static const unsigned int msiof1_sync_a_pins[] = {
2518 	/* SYNC */
2519 	RCAR_GP_PIN(6, 9),
2520 };
2521 static const unsigned int msiof1_sync_a_mux[] = {
2522 	MSIOF1_SYNC_A_MARK,
2523 };
2524 static const unsigned int msiof1_ss1_a_pins[] = {
2525 	/* SS1 */
2526 	RCAR_GP_PIN(6, 5),
2527 };
2528 static const unsigned int msiof1_ss1_a_mux[] = {
2529 	MSIOF1_SS1_A_MARK,
2530 };
2531 static const unsigned int msiof1_ss2_a_pins[] = {
2532 	/* SS2 */
2533 	RCAR_GP_PIN(6, 6),
2534 };
2535 static const unsigned int msiof1_ss2_a_mux[] = {
2536 	MSIOF1_SS2_A_MARK,
2537 };
2538 static const unsigned int msiof1_txd_a_pins[] = {
2539 	/* TXD */
2540 	RCAR_GP_PIN(6, 7),
2541 };
2542 static const unsigned int msiof1_txd_a_mux[] = {
2543 	MSIOF1_TXD_A_MARK,
2544 };
2545 static const unsigned int msiof1_rxd_a_pins[] = {
2546 	/* RXD */
2547 	RCAR_GP_PIN(6, 10),
2548 };
2549 static const unsigned int msiof1_rxd_a_mux[] = {
2550 	MSIOF1_RXD_A_MARK,
2551 };
2552 static const unsigned int msiof1_clk_b_pins[] = {
2553 	/* SCK */
2554 	RCAR_GP_PIN(5, 9),
2555 };
2556 static const unsigned int msiof1_clk_b_mux[] = {
2557 	MSIOF1_SCK_B_MARK,
2558 };
2559 static const unsigned int msiof1_sync_b_pins[] = {
2560 	/* SYNC */
2561 	RCAR_GP_PIN(5, 3),
2562 };
2563 static const unsigned int msiof1_sync_b_mux[] = {
2564 	MSIOF1_SYNC_B_MARK,
2565 };
2566 static const unsigned int msiof1_ss1_b_pins[] = {
2567 	/* SS1 */
2568 	RCAR_GP_PIN(5, 4),
2569 };
2570 static const unsigned int msiof1_ss1_b_mux[] = {
2571 	MSIOF1_SS1_B_MARK,
2572 };
2573 static const unsigned int msiof1_ss2_b_pins[] = {
2574 	/* SS2 */
2575 	RCAR_GP_PIN(5, 0),
2576 };
2577 static const unsigned int msiof1_ss2_b_mux[] = {
2578 	MSIOF1_SS2_B_MARK,
2579 };
2580 static const unsigned int msiof1_txd_b_pins[] = {
2581 	/* TXD */
2582 	RCAR_GP_PIN(5, 8),
2583 };
2584 static const unsigned int msiof1_txd_b_mux[] = {
2585 	MSIOF1_TXD_B_MARK,
2586 };
2587 static const unsigned int msiof1_rxd_b_pins[] = {
2588 	/* RXD */
2589 	RCAR_GP_PIN(5, 7),
2590 };
2591 static const unsigned int msiof1_rxd_b_mux[] = {
2592 	MSIOF1_RXD_B_MARK,
2593 };
2594 static const unsigned int msiof1_clk_c_pins[] = {
2595 	/* SCK */
2596 	RCAR_GP_PIN(6, 17),
2597 };
2598 static const unsigned int msiof1_clk_c_mux[] = {
2599 	MSIOF1_SCK_C_MARK,
2600 };
2601 static const unsigned int msiof1_sync_c_pins[] = {
2602 	/* SYNC */
2603 	RCAR_GP_PIN(6, 18),
2604 };
2605 static const unsigned int msiof1_sync_c_mux[] = {
2606 	MSIOF1_SYNC_C_MARK,
2607 };
2608 static const unsigned int msiof1_ss1_c_pins[] = {
2609 	/* SS1 */
2610 	RCAR_GP_PIN(6, 21),
2611 };
2612 static const unsigned int msiof1_ss1_c_mux[] = {
2613 	MSIOF1_SS1_C_MARK,
2614 };
2615 static const unsigned int msiof1_ss2_c_pins[] = {
2616 	/* SS2 */
2617 	RCAR_GP_PIN(6, 27),
2618 };
2619 static const unsigned int msiof1_ss2_c_mux[] = {
2620 	MSIOF1_SS2_C_MARK,
2621 };
2622 static const unsigned int msiof1_txd_c_pins[] = {
2623 	/* TXD */
2624 	RCAR_GP_PIN(6, 20),
2625 };
2626 static const unsigned int msiof1_txd_c_mux[] = {
2627 	MSIOF1_TXD_C_MARK,
2628 };
2629 static const unsigned int msiof1_rxd_c_pins[] = {
2630 	/* RXD */
2631 	RCAR_GP_PIN(6, 19),
2632 };
2633 static const unsigned int msiof1_rxd_c_mux[] = {
2634 	MSIOF1_RXD_C_MARK,
2635 };
2636 static const unsigned int msiof1_clk_d_pins[] = {
2637 	/* SCK */
2638 	RCAR_GP_PIN(5, 12),
2639 };
2640 static const unsigned int msiof1_clk_d_mux[] = {
2641 	MSIOF1_SCK_D_MARK,
2642 };
2643 static const unsigned int msiof1_sync_d_pins[] = {
2644 	/* SYNC */
2645 	RCAR_GP_PIN(5, 15),
2646 };
2647 static const unsigned int msiof1_sync_d_mux[] = {
2648 	MSIOF1_SYNC_D_MARK,
2649 };
2650 static const unsigned int msiof1_ss1_d_pins[] = {
2651 	/* SS1 */
2652 	RCAR_GP_PIN(5, 16),
2653 };
2654 static const unsigned int msiof1_ss1_d_mux[] = {
2655 	MSIOF1_SS1_D_MARK,
2656 };
2657 static const unsigned int msiof1_ss2_d_pins[] = {
2658 	/* SS2 */
2659 	RCAR_GP_PIN(5, 21),
2660 };
2661 static const unsigned int msiof1_ss2_d_mux[] = {
2662 	MSIOF1_SS2_D_MARK,
2663 };
2664 static const unsigned int msiof1_txd_d_pins[] = {
2665 	/* TXD */
2666 	RCAR_GP_PIN(5, 14),
2667 };
2668 static const unsigned int msiof1_txd_d_mux[] = {
2669 	MSIOF1_TXD_D_MARK,
2670 };
2671 static const unsigned int msiof1_rxd_d_pins[] = {
2672 	/* RXD */
2673 	RCAR_GP_PIN(5, 13),
2674 };
2675 static const unsigned int msiof1_rxd_d_mux[] = {
2676 	MSIOF1_RXD_D_MARK,
2677 };
2678 static const unsigned int msiof1_clk_e_pins[] = {
2679 	/* SCK */
2680 	RCAR_GP_PIN(3, 0),
2681 };
2682 static const unsigned int msiof1_clk_e_mux[] = {
2683 	MSIOF1_SCK_E_MARK,
2684 };
2685 static const unsigned int msiof1_sync_e_pins[] = {
2686 	/* SYNC */
2687 	RCAR_GP_PIN(3, 1),
2688 };
2689 static const unsigned int msiof1_sync_e_mux[] = {
2690 	MSIOF1_SYNC_E_MARK,
2691 };
2692 static const unsigned int msiof1_ss1_e_pins[] = {
2693 	/* SS1 */
2694 	RCAR_GP_PIN(3, 4),
2695 };
2696 static const unsigned int msiof1_ss1_e_mux[] = {
2697 	MSIOF1_SS1_E_MARK,
2698 };
2699 static const unsigned int msiof1_ss2_e_pins[] = {
2700 	/* SS2 */
2701 	RCAR_GP_PIN(3, 5),
2702 };
2703 static const unsigned int msiof1_ss2_e_mux[] = {
2704 	MSIOF1_SS2_E_MARK,
2705 };
2706 static const unsigned int msiof1_txd_e_pins[] = {
2707 	/* TXD */
2708 	RCAR_GP_PIN(3, 3),
2709 };
2710 static const unsigned int msiof1_txd_e_mux[] = {
2711 	MSIOF1_TXD_E_MARK,
2712 };
2713 static const unsigned int msiof1_rxd_e_pins[] = {
2714 	/* RXD */
2715 	RCAR_GP_PIN(3, 2),
2716 };
2717 static const unsigned int msiof1_rxd_e_mux[] = {
2718 	MSIOF1_RXD_E_MARK,
2719 };
2720 static const unsigned int msiof1_clk_f_pins[] = {
2721 	/* SCK */
2722 	RCAR_GP_PIN(5, 23),
2723 };
2724 static const unsigned int msiof1_clk_f_mux[] = {
2725 	MSIOF1_SCK_F_MARK,
2726 };
2727 static const unsigned int msiof1_sync_f_pins[] = {
2728 	/* SYNC */
2729 	RCAR_GP_PIN(5, 24),
2730 };
2731 static const unsigned int msiof1_sync_f_mux[] = {
2732 	MSIOF1_SYNC_F_MARK,
2733 };
2734 static const unsigned int msiof1_ss1_f_pins[] = {
2735 	/* SS1 */
2736 	RCAR_GP_PIN(6, 1),
2737 };
2738 static const unsigned int msiof1_ss1_f_mux[] = {
2739 	MSIOF1_SS1_F_MARK,
2740 };
2741 static const unsigned int msiof1_ss2_f_pins[] = {
2742 	/* SS2 */
2743 	RCAR_GP_PIN(6, 2),
2744 };
2745 static const unsigned int msiof1_ss2_f_mux[] = {
2746 	MSIOF1_SS2_F_MARK,
2747 };
2748 static const unsigned int msiof1_txd_f_pins[] = {
2749 	/* TXD */
2750 	RCAR_GP_PIN(6, 0),
2751 };
2752 static const unsigned int msiof1_txd_f_mux[] = {
2753 	MSIOF1_TXD_F_MARK,
2754 };
2755 static const unsigned int msiof1_rxd_f_pins[] = {
2756 	/* RXD */
2757 	RCAR_GP_PIN(5, 25),
2758 };
2759 static const unsigned int msiof1_rxd_f_mux[] = {
2760 	MSIOF1_RXD_F_MARK,
2761 };
2762 static const unsigned int msiof1_clk_g_pins[] = {
2763 	/* SCK */
2764 	RCAR_GP_PIN(3, 6),
2765 };
2766 static const unsigned int msiof1_clk_g_mux[] = {
2767 	MSIOF1_SCK_G_MARK,
2768 };
2769 static const unsigned int msiof1_sync_g_pins[] = {
2770 	/* SYNC */
2771 	RCAR_GP_PIN(3, 7),
2772 };
2773 static const unsigned int msiof1_sync_g_mux[] = {
2774 	MSIOF1_SYNC_G_MARK,
2775 };
2776 static const unsigned int msiof1_ss1_g_pins[] = {
2777 	/* SS1 */
2778 	RCAR_GP_PIN(3, 10),
2779 };
2780 static const unsigned int msiof1_ss1_g_mux[] = {
2781 	MSIOF1_SS1_G_MARK,
2782 };
2783 static const unsigned int msiof1_ss2_g_pins[] = {
2784 	/* SS2 */
2785 	RCAR_GP_PIN(3, 11),
2786 };
2787 static const unsigned int msiof1_ss2_g_mux[] = {
2788 	MSIOF1_SS2_G_MARK,
2789 };
2790 static const unsigned int msiof1_txd_g_pins[] = {
2791 	/* TXD */
2792 	RCAR_GP_PIN(3, 9),
2793 };
2794 static const unsigned int msiof1_txd_g_mux[] = {
2795 	MSIOF1_TXD_G_MARK,
2796 };
2797 static const unsigned int msiof1_rxd_g_pins[] = {
2798 	/* RXD */
2799 	RCAR_GP_PIN(3, 8),
2800 };
2801 static const unsigned int msiof1_rxd_g_mux[] = {
2802 	MSIOF1_RXD_G_MARK,
2803 };
2804 /* - MSIOF2 ----------------------------------------------------------------- */
2805 static const unsigned int msiof2_clk_a_pins[] = {
2806 	/* SCK */
2807 	RCAR_GP_PIN(1, 9),
2808 };
2809 static const unsigned int msiof2_clk_a_mux[] = {
2810 	MSIOF2_SCK_A_MARK,
2811 };
2812 static const unsigned int msiof2_sync_a_pins[] = {
2813 	/* SYNC */
2814 	RCAR_GP_PIN(1, 8),
2815 };
2816 static const unsigned int msiof2_sync_a_mux[] = {
2817 	MSIOF2_SYNC_A_MARK,
2818 };
2819 static const unsigned int msiof2_ss1_a_pins[] = {
2820 	/* SS1 */
2821 	RCAR_GP_PIN(1, 6),
2822 };
2823 static const unsigned int msiof2_ss1_a_mux[] = {
2824 	MSIOF2_SS1_A_MARK,
2825 };
2826 static const unsigned int msiof2_ss2_a_pins[] = {
2827 	/* SS2 */
2828 	RCAR_GP_PIN(1, 7),
2829 };
2830 static const unsigned int msiof2_ss2_a_mux[] = {
2831 	MSIOF2_SS2_A_MARK,
2832 };
2833 static const unsigned int msiof2_txd_a_pins[] = {
2834 	/* TXD */
2835 	RCAR_GP_PIN(1, 11),
2836 };
2837 static const unsigned int msiof2_txd_a_mux[] = {
2838 	MSIOF2_TXD_A_MARK,
2839 };
2840 static const unsigned int msiof2_rxd_a_pins[] = {
2841 	/* RXD */
2842 	RCAR_GP_PIN(1, 10),
2843 };
2844 static const unsigned int msiof2_rxd_a_mux[] = {
2845 	MSIOF2_RXD_A_MARK,
2846 };
2847 static const unsigned int msiof2_clk_b_pins[] = {
2848 	/* SCK */
2849 	RCAR_GP_PIN(0, 4),
2850 };
2851 static const unsigned int msiof2_clk_b_mux[] = {
2852 	MSIOF2_SCK_B_MARK,
2853 };
2854 static const unsigned int msiof2_sync_b_pins[] = {
2855 	/* SYNC */
2856 	RCAR_GP_PIN(0, 5),
2857 };
2858 static const unsigned int msiof2_sync_b_mux[] = {
2859 	MSIOF2_SYNC_B_MARK,
2860 };
2861 static const unsigned int msiof2_ss1_b_pins[] = {
2862 	/* SS1 */
2863 	RCAR_GP_PIN(0, 0),
2864 };
2865 static const unsigned int msiof2_ss1_b_mux[] = {
2866 	MSIOF2_SS1_B_MARK,
2867 };
2868 static const unsigned int msiof2_ss2_b_pins[] = {
2869 	/* SS2 */
2870 	RCAR_GP_PIN(0, 1),
2871 };
2872 static const unsigned int msiof2_ss2_b_mux[] = {
2873 	MSIOF2_SS2_B_MARK,
2874 };
2875 static const unsigned int msiof2_txd_b_pins[] = {
2876 	/* TXD */
2877 	RCAR_GP_PIN(0, 7),
2878 };
2879 static const unsigned int msiof2_txd_b_mux[] = {
2880 	MSIOF2_TXD_B_MARK,
2881 };
2882 static const unsigned int msiof2_rxd_b_pins[] = {
2883 	/* RXD */
2884 	RCAR_GP_PIN(0, 6),
2885 };
2886 static const unsigned int msiof2_rxd_b_mux[] = {
2887 	MSIOF2_RXD_B_MARK,
2888 };
2889 static const unsigned int msiof2_clk_c_pins[] = {
2890 	/* SCK */
2891 	RCAR_GP_PIN(2, 12),
2892 };
2893 static const unsigned int msiof2_clk_c_mux[] = {
2894 	MSIOF2_SCK_C_MARK,
2895 };
2896 static const unsigned int msiof2_sync_c_pins[] = {
2897 	/* SYNC */
2898 	RCAR_GP_PIN(2, 11),
2899 };
2900 static const unsigned int msiof2_sync_c_mux[] = {
2901 	MSIOF2_SYNC_C_MARK,
2902 };
2903 static const unsigned int msiof2_ss1_c_pins[] = {
2904 	/* SS1 */
2905 	RCAR_GP_PIN(2, 10),
2906 };
2907 static const unsigned int msiof2_ss1_c_mux[] = {
2908 	MSIOF2_SS1_C_MARK,
2909 };
2910 static const unsigned int msiof2_ss2_c_pins[] = {
2911 	/* SS2 */
2912 	RCAR_GP_PIN(2, 9),
2913 };
2914 static const unsigned int msiof2_ss2_c_mux[] = {
2915 	MSIOF2_SS2_C_MARK,
2916 };
2917 static const unsigned int msiof2_txd_c_pins[] = {
2918 	/* TXD */
2919 	RCAR_GP_PIN(2, 14),
2920 };
2921 static const unsigned int msiof2_txd_c_mux[] = {
2922 	MSIOF2_TXD_C_MARK,
2923 };
2924 static const unsigned int msiof2_rxd_c_pins[] = {
2925 	/* RXD */
2926 	RCAR_GP_PIN(2, 13),
2927 };
2928 static const unsigned int msiof2_rxd_c_mux[] = {
2929 	MSIOF2_RXD_C_MARK,
2930 };
2931 static const unsigned int msiof2_clk_d_pins[] = {
2932 	/* SCK */
2933 	RCAR_GP_PIN(0, 8),
2934 };
2935 static const unsigned int msiof2_clk_d_mux[] = {
2936 	MSIOF2_SCK_D_MARK,
2937 };
2938 static const unsigned int msiof2_sync_d_pins[] = {
2939 	/* SYNC */
2940 	RCAR_GP_PIN(0, 9),
2941 };
2942 static const unsigned int msiof2_sync_d_mux[] = {
2943 	MSIOF2_SYNC_D_MARK,
2944 };
2945 static const unsigned int msiof2_ss1_d_pins[] = {
2946 	/* SS1 */
2947 	RCAR_GP_PIN(0, 12),
2948 };
2949 static const unsigned int msiof2_ss1_d_mux[] = {
2950 	MSIOF2_SS1_D_MARK,
2951 };
2952 static const unsigned int msiof2_ss2_d_pins[] = {
2953 	/* SS2 */
2954 	RCAR_GP_PIN(0, 13),
2955 };
2956 static const unsigned int msiof2_ss2_d_mux[] = {
2957 	MSIOF2_SS2_D_MARK,
2958 };
2959 static const unsigned int msiof2_txd_d_pins[] = {
2960 	/* TXD */
2961 	RCAR_GP_PIN(0, 11),
2962 };
2963 static const unsigned int msiof2_txd_d_mux[] = {
2964 	MSIOF2_TXD_D_MARK,
2965 };
2966 static const unsigned int msiof2_rxd_d_pins[] = {
2967 	/* RXD */
2968 	RCAR_GP_PIN(0, 10),
2969 };
2970 static const unsigned int msiof2_rxd_d_mux[] = {
2971 	MSIOF2_RXD_D_MARK,
2972 };
2973 /* - MSIOF3 ----------------------------------------------------------------- */
2974 static const unsigned int msiof3_clk_a_pins[] = {
2975 	/* SCK */
2976 	RCAR_GP_PIN(0, 0),
2977 };
2978 static const unsigned int msiof3_clk_a_mux[] = {
2979 	MSIOF3_SCK_A_MARK,
2980 };
2981 static const unsigned int msiof3_sync_a_pins[] = {
2982 	/* SYNC */
2983 	RCAR_GP_PIN(0, 1),
2984 };
2985 static const unsigned int msiof3_sync_a_mux[] = {
2986 	MSIOF3_SYNC_A_MARK,
2987 };
2988 static const unsigned int msiof3_ss1_a_pins[] = {
2989 	/* SS1 */
2990 	RCAR_GP_PIN(0, 14),
2991 };
2992 static const unsigned int msiof3_ss1_a_mux[] = {
2993 	MSIOF3_SS1_A_MARK,
2994 };
2995 static const unsigned int msiof3_ss2_a_pins[] = {
2996 	/* SS2 */
2997 	RCAR_GP_PIN(0, 15),
2998 };
2999 static const unsigned int msiof3_ss2_a_mux[] = {
3000 	MSIOF3_SS2_A_MARK,
3001 };
3002 static const unsigned int msiof3_txd_a_pins[] = {
3003 	/* TXD */
3004 	RCAR_GP_PIN(0, 3),
3005 };
3006 static const unsigned int msiof3_txd_a_mux[] = {
3007 	MSIOF3_TXD_A_MARK,
3008 };
3009 static const unsigned int msiof3_rxd_a_pins[] = {
3010 	/* RXD */
3011 	RCAR_GP_PIN(0, 2),
3012 };
3013 static const unsigned int msiof3_rxd_a_mux[] = {
3014 	MSIOF3_RXD_A_MARK,
3015 };
3016 static const unsigned int msiof3_clk_b_pins[] = {
3017 	/* SCK */
3018 	RCAR_GP_PIN(1, 2),
3019 };
3020 static const unsigned int msiof3_clk_b_mux[] = {
3021 	MSIOF3_SCK_B_MARK,
3022 };
3023 static const unsigned int msiof3_sync_b_pins[] = {
3024 	/* SYNC */
3025 	RCAR_GP_PIN(1, 0),
3026 };
3027 static const unsigned int msiof3_sync_b_mux[] = {
3028 	MSIOF3_SYNC_B_MARK,
3029 };
3030 static const unsigned int msiof3_ss1_b_pins[] = {
3031 	/* SS1 */
3032 	RCAR_GP_PIN(1, 4),
3033 };
3034 static const unsigned int msiof3_ss1_b_mux[] = {
3035 	MSIOF3_SS1_B_MARK,
3036 };
3037 static const unsigned int msiof3_ss2_b_pins[] = {
3038 	/* SS2 */
3039 	RCAR_GP_PIN(1, 5),
3040 };
3041 static const unsigned int msiof3_ss2_b_mux[] = {
3042 	MSIOF3_SS2_B_MARK,
3043 };
3044 static const unsigned int msiof3_txd_b_pins[] = {
3045 	/* TXD */
3046 	RCAR_GP_PIN(1, 1),
3047 };
3048 static const unsigned int msiof3_txd_b_mux[] = {
3049 	MSIOF3_TXD_B_MARK,
3050 };
3051 static const unsigned int msiof3_rxd_b_pins[] = {
3052 	/* RXD */
3053 	RCAR_GP_PIN(1, 3),
3054 };
3055 static const unsigned int msiof3_rxd_b_mux[] = {
3056 	MSIOF3_RXD_B_MARK,
3057 };
3058 static const unsigned int msiof3_clk_c_pins[] = {
3059 	/* SCK */
3060 	RCAR_GP_PIN(1, 12),
3061 };
3062 static const unsigned int msiof3_clk_c_mux[] = {
3063 	MSIOF3_SCK_C_MARK,
3064 };
3065 static const unsigned int msiof3_sync_c_pins[] = {
3066 	/* SYNC */
3067 	RCAR_GP_PIN(1, 13),
3068 };
3069 static const unsigned int msiof3_sync_c_mux[] = {
3070 	MSIOF3_SYNC_C_MARK,
3071 };
3072 static const unsigned int msiof3_txd_c_pins[] = {
3073 	/* TXD */
3074 	RCAR_GP_PIN(1, 15),
3075 };
3076 static const unsigned int msiof3_txd_c_mux[] = {
3077 	MSIOF3_TXD_C_MARK,
3078 };
3079 static const unsigned int msiof3_rxd_c_pins[] = {
3080 	/* RXD */
3081 	RCAR_GP_PIN(1, 14),
3082 };
3083 static const unsigned int msiof3_rxd_c_mux[] = {
3084 	MSIOF3_RXD_C_MARK,
3085 };
3086 static const unsigned int msiof3_clk_d_pins[] = {
3087 	/* SCK */
3088 	RCAR_GP_PIN(1, 22),
3089 };
3090 static const unsigned int msiof3_clk_d_mux[] = {
3091 	MSIOF3_SCK_D_MARK,
3092 };
3093 static const unsigned int msiof3_sync_d_pins[] = {
3094 	/* SYNC */
3095 	RCAR_GP_PIN(1, 23),
3096 };
3097 static const unsigned int msiof3_sync_d_mux[] = {
3098 	MSIOF3_SYNC_D_MARK,
3099 };
3100 static const unsigned int msiof3_ss1_d_pins[] = {
3101 	/* SS1 */
3102 	RCAR_GP_PIN(1, 26),
3103 };
3104 static const unsigned int msiof3_ss1_d_mux[] = {
3105 	MSIOF3_SS1_D_MARK,
3106 };
3107 static const unsigned int msiof3_txd_d_pins[] = {
3108 	/* TXD */
3109 	RCAR_GP_PIN(1, 25),
3110 };
3111 static const unsigned int msiof3_txd_d_mux[] = {
3112 	MSIOF3_TXD_D_MARK,
3113 };
3114 static const unsigned int msiof3_rxd_d_pins[] = {
3115 	/* RXD */
3116 	RCAR_GP_PIN(1, 24),
3117 };
3118 static const unsigned int msiof3_rxd_d_mux[] = {
3119 	MSIOF3_RXD_D_MARK,
3120 };
3121 static const unsigned int msiof3_clk_e_pins[] = {
3122 	/* SCK */
3123 	RCAR_GP_PIN(2, 3),
3124 };
3125 static const unsigned int msiof3_clk_e_mux[] = {
3126 	MSIOF3_SCK_E_MARK,
3127 };
3128 static const unsigned int msiof3_sync_e_pins[] = {
3129 	/* SYNC */
3130 	RCAR_GP_PIN(2, 2),
3131 };
3132 static const unsigned int msiof3_sync_e_mux[] = {
3133 	MSIOF3_SYNC_E_MARK,
3134 };
3135 static const unsigned int msiof3_ss1_e_pins[] = {
3136 	/* SS1 */
3137 	RCAR_GP_PIN(2, 1),
3138 };
3139 static const unsigned int msiof3_ss1_e_mux[] = {
3140 	MSIOF3_SS1_E_MARK,
3141 };
3142 static const unsigned int msiof3_ss2_e_pins[] = {
3143 	/* SS2 */
3144 	RCAR_GP_PIN(2, 0),
3145 };
3146 static const unsigned int msiof3_ss2_e_mux[] = {
3147 	MSIOF3_SS2_E_MARK,
3148 };
3149 static const unsigned int msiof3_txd_e_pins[] = {
3150 	/* TXD */
3151 	RCAR_GP_PIN(2, 5),
3152 };
3153 static const unsigned int msiof3_txd_e_mux[] = {
3154 	MSIOF3_TXD_E_MARK,
3155 };
3156 static const unsigned int msiof3_rxd_e_pins[] = {
3157 	/* RXD */
3158 	RCAR_GP_PIN(2, 4),
3159 };
3160 static const unsigned int msiof3_rxd_e_mux[] = {
3161 	MSIOF3_RXD_E_MARK,
3162 };
3163 
3164 /* - PWM0 --------------------------------------------------------------------*/
3165 static const unsigned int pwm0_pins[] = {
3166 	/* PWM */
3167 	RCAR_GP_PIN(2, 6),
3168 };
3169 static const unsigned int pwm0_mux[] = {
3170 	PWM0_MARK,
3171 };
3172 /* - PWM1 --------------------------------------------------------------------*/
3173 static const unsigned int pwm1_a_pins[] = {
3174 	/* PWM */
3175 	RCAR_GP_PIN(2, 7),
3176 };
3177 static const unsigned int pwm1_a_mux[] = {
3178 	PWM1_A_MARK,
3179 };
3180 static const unsigned int pwm1_b_pins[] = {
3181 	/* PWM */
3182 	RCAR_GP_PIN(1, 8),
3183 };
3184 static const unsigned int pwm1_b_mux[] = {
3185 	PWM1_B_MARK,
3186 };
3187 /* - PWM2 --------------------------------------------------------------------*/
3188 static const unsigned int pwm2_a_pins[] = {
3189 	/* PWM */
3190 	RCAR_GP_PIN(2, 8),
3191 };
3192 static const unsigned int pwm2_a_mux[] = {
3193 	PWM2_A_MARK,
3194 };
3195 static const unsigned int pwm2_b_pins[] = {
3196 	/* PWM */
3197 	RCAR_GP_PIN(1, 11),
3198 };
3199 static const unsigned int pwm2_b_mux[] = {
3200 	PWM2_B_MARK,
3201 };
3202 /* - PWM3 --------------------------------------------------------------------*/
3203 static const unsigned int pwm3_a_pins[] = {
3204 	/* PWM */
3205 	RCAR_GP_PIN(1, 0),
3206 };
3207 static const unsigned int pwm3_a_mux[] = {
3208 	PWM3_A_MARK,
3209 };
3210 static const unsigned int pwm3_b_pins[] = {
3211 	/* PWM */
3212 	RCAR_GP_PIN(2, 2),
3213 };
3214 static const unsigned int pwm3_b_mux[] = {
3215 	PWM3_B_MARK,
3216 };
3217 /* - PWM4 --------------------------------------------------------------------*/
3218 static const unsigned int pwm4_a_pins[] = {
3219 	/* PWM */
3220 	RCAR_GP_PIN(1, 1),
3221 };
3222 static const unsigned int pwm4_a_mux[] = {
3223 	PWM4_A_MARK,
3224 };
3225 static const unsigned int pwm4_b_pins[] = {
3226 	/* PWM */
3227 	RCAR_GP_PIN(2, 3),
3228 };
3229 static const unsigned int pwm4_b_mux[] = {
3230 	PWM4_B_MARK,
3231 };
3232 /* - PWM5 --------------------------------------------------------------------*/
3233 static const unsigned int pwm5_a_pins[] = {
3234 	/* PWM */
3235 	RCAR_GP_PIN(1, 2),
3236 };
3237 static const unsigned int pwm5_a_mux[] = {
3238 	PWM5_A_MARK,
3239 };
3240 static const unsigned int pwm5_b_pins[] = {
3241 	/* PWM */
3242 	RCAR_GP_PIN(2, 4),
3243 };
3244 static const unsigned int pwm5_b_mux[] = {
3245 	PWM5_B_MARK,
3246 };
3247 /* - PWM6 --------------------------------------------------------------------*/
3248 static const unsigned int pwm6_a_pins[] = {
3249 	/* PWM */
3250 	RCAR_GP_PIN(1, 3),
3251 };
3252 static const unsigned int pwm6_a_mux[] = {
3253 	PWM6_A_MARK,
3254 };
3255 static const unsigned int pwm6_b_pins[] = {
3256 	/* PWM */
3257 	RCAR_GP_PIN(2, 5),
3258 };
3259 static const unsigned int pwm6_b_mux[] = {
3260 	PWM6_B_MARK,
3261 };
3262 
3263 /* - QSPI0 ------------------------------------------------------------------ */
3264 static const unsigned int qspi0_ctrl_pins[] = {
3265 	/* QSPI0_SPCLK, QSPI0_SSL */
3266 	PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
3267 };
3268 static const unsigned int qspi0_ctrl_mux[] = {
3269 	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3270 };
3271 static const unsigned int qspi0_data_pins[] = {
3272 	/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3273 	PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3274 	/* QSPI0_IO2, QSPI0_IO3 */
3275 	PIN_QSPI0_IO2, PIN_QSPI0_IO3,
3276 };
3277 static const unsigned int qspi0_data_mux[] = {
3278 	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3279 	QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3280 };
3281 /* - QSPI1 ------------------------------------------------------------------ */
3282 static const unsigned int qspi1_ctrl_pins[] = {
3283 	/* QSPI1_SPCLK, QSPI1_SSL */
3284 	PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
3285 };
3286 static const unsigned int qspi1_ctrl_mux[] = {
3287 	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3288 };
3289 static const unsigned int qspi1_data_pins[] = {
3290 	/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3291 	PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3292 	/* QSPI1_IO2, QSPI1_IO3 */
3293 	PIN_QSPI1_IO2, PIN_QSPI1_IO3,
3294 };
3295 static const unsigned int qspi1_data_mux[] = {
3296 	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3297 	QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3298 };
3299 
3300 /* - SATA --------------------------------------------------------------------*/
3301 static const unsigned int sata0_devslp_a_pins[] = {
3302 	/* DEVSLP */
3303 	RCAR_GP_PIN(6, 16),
3304 };
3305 static const unsigned int sata0_devslp_a_mux[] = {
3306 	SATA_DEVSLP_A_MARK,
3307 };
3308 static const unsigned int sata0_devslp_b_pins[] = {
3309 	/* DEVSLP */
3310 	RCAR_GP_PIN(4, 6),
3311 };
3312 static const unsigned int sata0_devslp_b_mux[] = {
3313 	SATA_DEVSLP_B_MARK,
3314 };
3315 
3316 /* - SCIF0 ------------------------------------------------------------------ */
3317 static const unsigned int scif0_data_pins[] = {
3318 	/* RX, TX */
3319 	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3320 };
3321 static const unsigned int scif0_data_mux[] = {
3322 	RX0_MARK, TX0_MARK,
3323 };
3324 static const unsigned int scif0_clk_pins[] = {
3325 	/* SCK */
3326 	RCAR_GP_PIN(5, 0),
3327 };
3328 static const unsigned int scif0_clk_mux[] = {
3329 	SCK0_MARK,
3330 };
3331 static const unsigned int scif0_ctrl_pins[] = {
3332 	/* RTS, CTS */
3333 	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3334 };
3335 static const unsigned int scif0_ctrl_mux[] = {
3336 	RTS0_N_MARK, CTS0_N_MARK,
3337 };
3338 /* - SCIF1 ------------------------------------------------------------------ */
3339 static const unsigned int scif1_data_a_pins[] = {
3340 	/* RX, TX */
3341 	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3342 };
3343 static const unsigned int scif1_data_a_mux[] = {
3344 	RX1_A_MARK, TX1_A_MARK,
3345 };
3346 static const unsigned int scif1_clk_pins[] = {
3347 	/* SCK */
3348 	RCAR_GP_PIN(6, 21),
3349 };
3350 static const unsigned int scif1_clk_mux[] = {
3351 	SCK1_MARK,
3352 };
3353 static const unsigned int scif1_ctrl_pins[] = {
3354 	/* RTS, CTS */
3355 	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3356 };
3357 static const unsigned int scif1_ctrl_mux[] = {
3358 	RTS1_N_MARK, CTS1_N_MARK,
3359 };
3360 
3361 static const unsigned int scif1_data_b_pins[] = {
3362 	/* RX, TX */
3363 	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3364 };
3365 static const unsigned int scif1_data_b_mux[] = {
3366 	RX1_B_MARK, TX1_B_MARK,
3367 };
3368 /* - SCIF2 ------------------------------------------------------------------ */
3369 static const unsigned int scif2_data_a_pins[] = {
3370 	/* RX, TX */
3371 	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3372 };
3373 static const unsigned int scif2_data_a_mux[] = {
3374 	RX2_A_MARK, TX2_A_MARK,
3375 };
3376 static const unsigned int scif2_clk_pins[] = {
3377 	/* SCK */
3378 	RCAR_GP_PIN(5, 9),
3379 };
3380 static const unsigned int scif2_clk_mux[] = {
3381 	SCK2_MARK,
3382 };
3383 static const unsigned int scif2_data_b_pins[] = {
3384 	/* RX, TX */
3385 	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3386 };
3387 static const unsigned int scif2_data_b_mux[] = {
3388 	RX2_B_MARK, TX2_B_MARK,
3389 };
3390 /* - SCIF3 ------------------------------------------------------------------ */
3391 static const unsigned int scif3_data_a_pins[] = {
3392 	/* RX, TX */
3393 	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3394 };
3395 static const unsigned int scif3_data_a_mux[] = {
3396 	RX3_A_MARK, TX3_A_MARK,
3397 };
3398 static const unsigned int scif3_clk_pins[] = {
3399 	/* SCK */
3400 	RCAR_GP_PIN(1, 22),
3401 };
3402 static const unsigned int scif3_clk_mux[] = {
3403 	SCK3_MARK,
3404 };
3405 static const unsigned int scif3_ctrl_pins[] = {
3406 	/* RTS, CTS */
3407 	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3408 };
3409 static const unsigned int scif3_ctrl_mux[] = {
3410 	RTS3_N_MARK, CTS3_N_MARK,
3411 };
3412 static const unsigned int scif3_data_b_pins[] = {
3413 	/* RX, TX */
3414 	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3415 };
3416 static const unsigned int scif3_data_b_mux[] = {
3417 	RX3_B_MARK, TX3_B_MARK,
3418 };
3419 /* - SCIF4 ------------------------------------------------------------------ */
3420 static const unsigned int scif4_data_a_pins[] = {
3421 	/* RX, TX */
3422 	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3423 };
3424 static const unsigned int scif4_data_a_mux[] = {
3425 	RX4_A_MARK, TX4_A_MARK,
3426 };
3427 static const unsigned int scif4_clk_a_pins[] = {
3428 	/* SCK */
3429 	RCAR_GP_PIN(2, 10),
3430 };
3431 static const unsigned int scif4_clk_a_mux[] = {
3432 	SCK4_A_MARK,
3433 };
3434 static const unsigned int scif4_ctrl_a_pins[] = {
3435 	/* RTS, CTS */
3436 	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3437 };
3438 static const unsigned int scif4_ctrl_a_mux[] = {
3439 	RTS4_N_A_MARK, CTS4_N_A_MARK,
3440 };
3441 static const unsigned int scif4_data_b_pins[] = {
3442 	/* RX, TX */
3443 	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3444 };
3445 static const unsigned int scif4_data_b_mux[] = {
3446 	RX4_B_MARK, TX4_B_MARK,
3447 };
3448 static const unsigned int scif4_clk_b_pins[] = {
3449 	/* SCK */
3450 	RCAR_GP_PIN(1, 5),
3451 };
3452 static const unsigned int scif4_clk_b_mux[] = {
3453 	SCK4_B_MARK,
3454 };
3455 static const unsigned int scif4_ctrl_b_pins[] = {
3456 	/* RTS, CTS */
3457 	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3458 };
3459 static const unsigned int scif4_ctrl_b_mux[] = {
3460 	RTS4_N_B_MARK, CTS4_N_B_MARK,
3461 };
3462 static const unsigned int scif4_data_c_pins[] = {
3463 	/* RX, TX */
3464 	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3465 };
3466 static const unsigned int scif4_data_c_mux[] = {
3467 	RX4_C_MARK, TX4_C_MARK,
3468 };
3469 static const unsigned int scif4_clk_c_pins[] = {
3470 	/* SCK */
3471 	RCAR_GP_PIN(0, 8),
3472 };
3473 static const unsigned int scif4_clk_c_mux[] = {
3474 	SCK4_C_MARK,
3475 };
3476 static const unsigned int scif4_ctrl_c_pins[] = {
3477 	/* RTS, CTS */
3478 	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3479 };
3480 static const unsigned int scif4_ctrl_c_mux[] = {
3481 	RTS4_N_C_MARK, CTS4_N_C_MARK,
3482 };
3483 /* - SCIF5 ------------------------------------------------------------------ */
3484 static const unsigned int scif5_data_a_pins[] = {
3485 	/* RX, TX */
3486 	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3487 };
3488 static const unsigned int scif5_data_a_mux[] = {
3489 	RX5_A_MARK, TX5_A_MARK,
3490 };
3491 static const unsigned int scif5_clk_a_pins[] = {
3492 	/* SCK */
3493 	RCAR_GP_PIN(6, 21),
3494 };
3495 static const unsigned int scif5_clk_a_mux[] = {
3496 	SCK5_A_MARK,
3497 };
3498 static const unsigned int scif5_data_b_pins[] = {
3499 	/* RX, TX */
3500 	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3501 };
3502 static const unsigned int scif5_data_b_mux[] = {
3503 	RX5_B_MARK, TX5_B_MARK,
3504 };
3505 static const unsigned int scif5_clk_b_pins[] = {
3506 	/* SCK */
3507 	RCAR_GP_PIN(5, 0),
3508 };
3509 static const unsigned int scif5_clk_b_mux[] = {
3510 	SCK5_B_MARK,
3511 };
3512 
3513 /* - SCIF Clock ------------------------------------------------------------- */
3514 static const unsigned int scif_clk_a_pins[] = {
3515 	/* SCIF_CLK */
3516 	RCAR_GP_PIN(6, 23),
3517 };
3518 static const unsigned int scif_clk_a_mux[] = {
3519 	SCIF_CLK_A_MARK,
3520 };
3521 static const unsigned int scif_clk_b_pins[] = {
3522 	/* SCIF_CLK */
3523 	RCAR_GP_PIN(5, 9),
3524 };
3525 static const unsigned int scif_clk_b_mux[] = {
3526 	SCIF_CLK_B_MARK,
3527 };
3528 
3529 /* - SDHI0 ------------------------------------------------------------------ */
3530 static const unsigned int sdhi0_data_pins[] = {
3531 	/* D[0:3] */
3532 	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3533 	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3534 };
3535 static const unsigned int sdhi0_data_mux[] = {
3536 	SD0_DAT0_MARK, SD0_DAT1_MARK,
3537 	SD0_DAT2_MARK, SD0_DAT3_MARK,
3538 };
3539 static const unsigned int sdhi0_ctrl_pins[] = {
3540 	/* CLK, CMD */
3541 	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3542 };
3543 static const unsigned int sdhi0_ctrl_mux[] = {
3544 	SD0_CLK_MARK, SD0_CMD_MARK,
3545 };
3546 static const unsigned int sdhi0_cd_pins[] = {
3547 	/* CD */
3548 	RCAR_GP_PIN(3, 12),
3549 };
3550 static const unsigned int sdhi0_cd_mux[] = {
3551 	SD0_CD_MARK,
3552 };
3553 static const unsigned int sdhi0_wp_pins[] = {
3554 	/* WP */
3555 	RCAR_GP_PIN(3, 13),
3556 };
3557 static const unsigned int sdhi0_wp_mux[] = {
3558 	SD0_WP_MARK,
3559 };
3560 /* - SDHI1 ------------------------------------------------------------------ */
3561 static const unsigned int sdhi1_data_pins[] = {
3562 	/* D[0:3] */
3563 	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3564 	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3565 };
3566 static const unsigned int sdhi1_data_mux[] = {
3567 	SD1_DAT0_MARK, SD1_DAT1_MARK,
3568 	SD1_DAT2_MARK, SD1_DAT3_MARK,
3569 };
3570 static const unsigned int sdhi1_ctrl_pins[] = {
3571 	/* CLK, CMD */
3572 	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3573 };
3574 static const unsigned int sdhi1_ctrl_mux[] = {
3575 	SD1_CLK_MARK, SD1_CMD_MARK,
3576 };
3577 static const unsigned int sdhi1_cd_pins[] = {
3578 	/* CD */
3579 	RCAR_GP_PIN(3, 14),
3580 };
3581 static const unsigned int sdhi1_cd_mux[] = {
3582 	SD1_CD_MARK,
3583 };
3584 static const unsigned int sdhi1_wp_pins[] = {
3585 	/* WP */
3586 	RCAR_GP_PIN(3, 15),
3587 };
3588 static const unsigned int sdhi1_wp_mux[] = {
3589 	SD1_WP_MARK,
3590 };
3591 /* - SDHI2 ------------------------------------------------------------------ */
3592 static const unsigned int sdhi2_data_pins[] = {
3593 	/* D[0:7] */
3594 	RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
3595 	RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
3596 	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3597 	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3598 };
3599 static const unsigned int sdhi2_data_mux[] = {
3600 	SD2_DAT0_MARK, SD2_DAT1_MARK,
3601 	SD2_DAT2_MARK, SD2_DAT3_MARK,
3602 	SD2_DAT4_MARK, SD2_DAT5_MARK,
3603 	SD2_DAT6_MARK, SD2_DAT7_MARK,
3604 };
3605 static const unsigned int sdhi2_ctrl_pins[] = {
3606 	/* CLK, CMD */
3607 	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3608 };
3609 static const unsigned int sdhi2_ctrl_mux[] = {
3610 	SD2_CLK_MARK, SD2_CMD_MARK,
3611 };
3612 static const unsigned int sdhi2_cd_a_pins[] = {
3613 	/* CD */
3614 	RCAR_GP_PIN(4, 13),
3615 };
3616 static const unsigned int sdhi2_cd_a_mux[] = {
3617 	SD2_CD_A_MARK,
3618 };
3619 static const unsigned int sdhi2_cd_b_pins[] = {
3620 	/* CD */
3621 	RCAR_GP_PIN(5, 10),
3622 };
3623 static const unsigned int sdhi2_cd_b_mux[] = {
3624 	SD2_CD_B_MARK,
3625 };
3626 static const unsigned int sdhi2_wp_a_pins[] = {
3627 	/* WP */
3628 	RCAR_GP_PIN(4, 14),
3629 };
3630 static const unsigned int sdhi2_wp_a_mux[] = {
3631 	SD2_WP_A_MARK,
3632 };
3633 static const unsigned int sdhi2_wp_b_pins[] = {
3634 	/* WP */
3635 	RCAR_GP_PIN(5, 11),
3636 };
3637 static const unsigned int sdhi2_wp_b_mux[] = {
3638 	SD2_WP_B_MARK,
3639 };
3640 static const unsigned int sdhi2_ds_pins[] = {
3641 	/* DS */
3642 	RCAR_GP_PIN(4, 6),
3643 };
3644 static const unsigned int sdhi2_ds_mux[] = {
3645 	SD2_DS_MARK,
3646 };
3647 /* - SDHI3 ------------------------------------------------------------------ */
3648 static const unsigned int sdhi3_data_pins[] = {
3649 	/* D[0:7] */
3650 	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3651 	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3652 	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3653 	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3654 };
3655 static const unsigned int sdhi3_data_mux[] = {
3656 	SD3_DAT0_MARK, SD3_DAT1_MARK,
3657 	SD3_DAT2_MARK, SD3_DAT3_MARK,
3658 	SD3_DAT4_MARK, SD3_DAT5_MARK,
3659 	SD3_DAT6_MARK, SD3_DAT7_MARK,
3660 };
3661 static const unsigned int sdhi3_ctrl_pins[] = {
3662 	/* CLK, CMD */
3663 	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3664 };
3665 static const unsigned int sdhi3_ctrl_mux[] = {
3666 	SD3_CLK_MARK, SD3_CMD_MARK,
3667 };
3668 static const unsigned int sdhi3_cd_pins[] = {
3669 	/* CD */
3670 	RCAR_GP_PIN(4, 15),
3671 };
3672 static const unsigned int sdhi3_cd_mux[] = {
3673 	SD3_CD_MARK,
3674 };
3675 static const unsigned int sdhi3_wp_pins[] = {
3676 	/* WP */
3677 	RCAR_GP_PIN(4, 16),
3678 };
3679 static const unsigned int sdhi3_wp_mux[] = {
3680 	SD3_WP_MARK,
3681 };
3682 static const unsigned int sdhi3_ds_pins[] = {
3683 	/* DS */
3684 	RCAR_GP_PIN(4, 17),
3685 };
3686 static const unsigned int sdhi3_ds_mux[] = {
3687 	SD3_DS_MARK,
3688 };
3689 
3690 /* - SSI -------------------------------------------------------------------- */
3691 static const unsigned int ssi0_data_pins[] = {
3692 	/* SDATA */
3693 	RCAR_GP_PIN(6, 2),
3694 };
3695 static const unsigned int ssi0_data_mux[] = {
3696 	SSI_SDATA0_MARK,
3697 };
3698 static const unsigned int ssi01239_ctrl_pins[] = {
3699 	/* SCK, WS */
3700 	RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3701 };
3702 static const unsigned int ssi01239_ctrl_mux[] = {
3703 	SSI_SCK01239_MARK, SSI_WS01239_MARK,
3704 };
3705 static const unsigned int ssi1_data_a_pins[] = {
3706 	/* SDATA */
3707 	RCAR_GP_PIN(6, 3),
3708 };
3709 static const unsigned int ssi1_data_a_mux[] = {
3710 	SSI_SDATA1_A_MARK,
3711 };
3712 static const unsigned int ssi1_data_b_pins[] = {
3713 	/* SDATA */
3714 	RCAR_GP_PIN(5, 12),
3715 };
3716 static const unsigned int ssi1_data_b_mux[] = {
3717 	SSI_SDATA1_B_MARK,
3718 };
3719 static const unsigned int ssi1_ctrl_a_pins[] = {
3720 	/* SCK, WS */
3721 	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3722 };
3723 static const unsigned int ssi1_ctrl_a_mux[] = {
3724 	SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3725 };
3726 static const unsigned int ssi1_ctrl_b_pins[] = {
3727 	/* SCK, WS */
3728 	RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3729 };
3730 static const unsigned int ssi1_ctrl_b_mux[] = {
3731 	SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3732 };
3733 static const unsigned int ssi2_data_a_pins[] = {
3734 	/* SDATA */
3735 	RCAR_GP_PIN(6, 4),
3736 };
3737 static const unsigned int ssi2_data_a_mux[] = {
3738 	SSI_SDATA2_A_MARK,
3739 };
3740 static const unsigned int ssi2_data_b_pins[] = {
3741 	/* SDATA */
3742 	RCAR_GP_PIN(5, 13),
3743 };
3744 static const unsigned int ssi2_data_b_mux[] = {
3745 	SSI_SDATA2_B_MARK,
3746 };
3747 static const unsigned int ssi2_ctrl_a_pins[] = {
3748 	/* SCK, WS */
3749 	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3750 };
3751 static const unsigned int ssi2_ctrl_a_mux[] = {
3752 	SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3753 };
3754 static const unsigned int ssi2_ctrl_b_pins[] = {
3755 	/* SCK, WS */
3756 	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3757 };
3758 static const unsigned int ssi2_ctrl_b_mux[] = {
3759 	SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3760 };
3761 static const unsigned int ssi3_data_pins[] = {
3762 	/* SDATA */
3763 	RCAR_GP_PIN(6, 7),
3764 };
3765 static const unsigned int ssi3_data_mux[] = {
3766 	SSI_SDATA3_MARK,
3767 };
3768 static const unsigned int ssi349_ctrl_pins[] = {
3769 	/* SCK, WS */
3770 	RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3771 };
3772 static const unsigned int ssi349_ctrl_mux[] = {
3773 	SSI_SCK349_MARK, SSI_WS349_MARK,
3774 };
3775 static const unsigned int ssi4_data_pins[] = {
3776 	/* SDATA */
3777 	RCAR_GP_PIN(6, 10),
3778 };
3779 static const unsigned int ssi4_data_mux[] = {
3780 	SSI_SDATA4_MARK,
3781 };
3782 static const unsigned int ssi4_ctrl_pins[] = {
3783 	/* SCK, WS */
3784 	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3785 };
3786 static const unsigned int ssi4_ctrl_mux[] = {
3787 	SSI_SCK4_MARK, SSI_WS4_MARK,
3788 };
3789 static const unsigned int ssi5_data_pins[] = {
3790 	/* SDATA */
3791 	RCAR_GP_PIN(6, 13),
3792 };
3793 static const unsigned int ssi5_data_mux[] = {
3794 	SSI_SDATA5_MARK,
3795 };
3796 static const unsigned int ssi5_ctrl_pins[] = {
3797 	/* SCK, WS */
3798 	RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3799 };
3800 static const unsigned int ssi5_ctrl_mux[] = {
3801 	SSI_SCK5_MARK, SSI_WS5_MARK,
3802 };
3803 static const unsigned int ssi6_data_pins[] = {
3804 	/* SDATA */
3805 	RCAR_GP_PIN(6, 16),
3806 };
3807 static const unsigned int ssi6_data_mux[] = {
3808 	SSI_SDATA6_MARK,
3809 };
3810 static const unsigned int ssi6_ctrl_pins[] = {
3811 	/* SCK, WS */
3812 	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3813 };
3814 static const unsigned int ssi6_ctrl_mux[] = {
3815 	SSI_SCK6_MARK, SSI_WS6_MARK,
3816 };
3817 static const unsigned int ssi7_data_pins[] = {
3818 	/* SDATA */
3819 	RCAR_GP_PIN(6, 19),
3820 };
3821 static const unsigned int ssi7_data_mux[] = {
3822 	SSI_SDATA7_MARK,
3823 };
3824 static const unsigned int ssi78_ctrl_pins[] = {
3825 	/* SCK, WS */
3826 	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3827 };
3828 static const unsigned int ssi78_ctrl_mux[] = {
3829 	SSI_SCK78_MARK, SSI_WS78_MARK,
3830 };
3831 static const unsigned int ssi8_data_pins[] = {
3832 	/* SDATA */
3833 	RCAR_GP_PIN(6, 20),
3834 };
3835 static const unsigned int ssi8_data_mux[] = {
3836 	SSI_SDATA8_MARK,
3837 };
3838 static const unsigned int ssi9_data_a_pins[] = {
3839 	/* SDATA */
3840 	RCAR_GP_PIN(6, 21),
3841 };
3842 static const unsigned int ssi9_data_a_mux[] = {
3843 	SSI_SDATA9_A_MARK,
3844 };
3845 static const unsigned int ssi9_data_b_pins[] = {
3846 	/* SDATA */
3847 	RCAR_GP_PIN(5, 14),
3848 };
3849 static const unsigned int ssi9_data_b_mux[] = {
3850 	SSI_SDATA9_B_MARK,
3851 };
3852 static const unsigned int ssi9_ctrl_a_pins[] = {
3853 	/* SCK, WS */
3854 	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3855 };
3856 static const unsigned int ssi9_ctrl_a_mux[] = {
3857 	SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3858 };
3859 static const unsigned int ssi9_ctrl_b_pins[] = {
3860 	/* SCK, WS */
3861 	RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3862 };
3863 static const unsigned int ssi9_ctrl_b_mux[] = {
3864 	SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3865 };
3866 
3867 /* - TMU -------------------------------------------------------------------- */
3868 static const unsigned int tmu_tclk1_a_pins[] = {
3869 	/* TCLK */
3870 	RCAR_GP_PIN(6, 23),
3871 };
3872 static const unsigned int tmu_tclk1_a_mux[] = {
3873 	TCLK1_A_MARK,
3874 };
3875 static const unsigned int tmu_tclk1_b_pins[] = {
3876 	/* TCLK */
3877 	RCAR_GP_PIN(5, 19),
3878 };
3879 static const unsigned int tmu_tclk1_b_mux[] = {
3880 	TCLK1_B_MARK,
3881 };
3882 static const unsigned int tmu_tclk2_a_pins[] = {
3883 	/* TCLK */
3884 	RCAR_GP_PIN(6, 19),
3885 };
3886 static const unsigned int tmu_tclk2_a_mux[] = {
3887 	TCLK2_A_MARK,
3888 };
3889 static const unsigned int tmu_tclk2_b_pins[] = {
3890 	/* TCLK */
3891 	RCAR_GP_PIN(6, 28),
3892 };
3893 static const unsigned int tmu_tclk2_b_mux[] = {
3894 	TCLK2_B_MARK,
3895 };
3896 
3897 /* - TPU ------------------------------------------------------------------- */
3898 static const unsigned int tpu_to0_pins[] = {
3899 	/* TPU0TO0 */
3900 	RCAR_GP_PIN(6, 28),
3901 };
3902 static const unsigned int tpu_to0_mux[] = {
3903 	TPU0TO0_MARK,
3904 };
3905 static const unsigned int tpu_to1_pins[] = {
3906 	/* TPU0TO1 */
3907 	RCAR_GP_PIN(6, 29),
3908 };
3909 static const unsigned int tpu_to1_mux[] = {
3910 	TPU0TO1_MARK,
3911 };
3912 static const unsigned int tpu_to2_pins[] = {
3913 	/* TPU0TO2 */
3914 	RCAR_GP_PIN(6, 30),
3915 };
3916 static const unsigned int tpu_to2_mux[] = {
3917 	TPU0TO2_MARK,
3918 };
3919 static const unsigned int tpu_to3_pins[] = {
3920 	/* TPU0TO3 */
3921 	RCAR_GP_PIN(6, 31),
3922 };
3923 static const unsigned int tpu_to3_mux[] = {
3924 	TPU0TO3_MARK,
3925 };
3926 
3927 /* - USB0 ------------------------------------------------------------------- */
3928 static const unsigned int usb0_pins[] = {
3929 	/* PWEN, OVC */
3930 	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3931 };
3932 static const unsigned int usb0_mux[] = {
3933 	USB0_PWEN_MARK, USB0_OVC_MARK,
3934 };
3935 /* - USB1 ------------------------------------------------------------------- */
3936 static const unsigned int usb1_pins[] = {
3937 	/* PWEN, OVC */
3938 	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3939 };
3940 static const unsigned int usb1_mux[] = {
3941 	USB1_PWEN_MARK, USB1_OVC_MARK,
3942 };
3943 /* - USB2 ------------------------------------------------------------------- */
3944 static const unsigned int usb2_pins[] = {
3945 	/* PWEN, OVC */
3946 	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3947 };
3948 static const unsigned int usb2_mux[] = {
3949 	USB2_PWEN_MARK, USB2_OVC_MARK,
3950 };
3951 /* - USB2_CH3 --------------------------------------------------------------- */
3952 static const unsigned int usb2_ch3_pins[] = {
3953 	/* PWEN, OVC */
3954 	RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3955 };
3956 static const unsigned int usb2_ch3_mux[] = {
3957 	USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
3958 };
3959 
3960 /* - USB30 ------------------------------------------------------------------ */
3961 static const unsigned int usb30_pins[] = {
3962 	/* PWEN, OVC */
3963 	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3964 };
3965 static const unsigned int usb30_mux[] = {
3966 	USB30_PWEN_MARK, USB30_OVC_MARK,
3967 };
3968 
3969 /* - VIN4 ------------------------------------------------------------------- */
3970 static const unsigned int vin4_data18_a_pins[] = {
3971 	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3972 	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3973 	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3974 	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3975 	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3976 	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3977 	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3978 	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3979 	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3980 };
3981 static const unsigned int vin4_data18_a_mux[] = {
3982 	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3983 	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3984 	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3985 	VI4_DATA10_MARK, VI4_DATA11_MARK,
3986 	VI4_DATA12_MARK, VI4_DATA13_MARK,
3987 	VI4_DATA14_MARK, VI4_DATA15_MARK,
3988 	VI4_DATA18_MARK, VI4_DATA19_MARK,
3989 	VI4_DATA20_MARK, VI4_DATA21_MARK,
3990 	VI4_DATA22_MARK, VI4_DATA23_MARK,
3991 };
3992 static const unsigned int vin4_data18_b_pins[] = {
3993 	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3994 	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3995 	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3996 	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3997 	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3998 	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3999 	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4000 	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4001 	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4002 };
4003 static const unsigned int vin4_data18_b_mux[] = {
4004 	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4005 	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4006 	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4007 	VI4_DATA10_MARK, VI4_DATA11_MARK,
4008 	VI4_DATA12_MARK, VI4_DATA13_MARK,
4009 	VI4_DATA14_MARK, VI4_DATA15_MARK,
4010 	VI4_DATA18_MARK, VI4_DATA19_MARK,
4011 	VI4_DATA20_MARK, VI4_DATA21_MARK,
4012 	VI4_DATA22_MARK, VI4_DATA23_MARK,
4013 };
4014 static const unsigned int vin4_data_a_pins[] = {
4015 	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4016 	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4017 	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4018 	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4019 	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4020 	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4021 	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4022 	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4023 	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4024 	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4025 	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4026 	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4027 };
4028 static const unsigned int vin4_data_a_mux[] = {
4029 	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4030 	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4031 	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4032 	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4033 	VI4_DATA8_MARK,  VI4_DATA9_MARK,
4034 	VI4_DATA10_MARK, VI4_DATA11_MARK,
4035 	VI4_DATA12_MARK, VI4_DATA13_MARK,
4036 	VI4_DATA14_MARK, VI4_DATA15_MARK,
4037 	VI4_DATA16_MARK, VI4_DATA17_MARK,
4038 	VI4_DATA18_MARK, VI4_DATA19_MARK,
4039 	VI4_DATA20_MARK, VI4_DATA21_MARK,
4040 	VI4_DATA22_MARK, VI4_DATA23_MARK,
4041 };
4042 static const unsigned int vin4_data_b_pins[] = {
4043 	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4044 	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4045 	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4046 	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4047 	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4048 	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4049 	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4050 	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4051 	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4052 	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4053 	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4054 	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4055 };
4056 static const unsigned int vin4_data_b_mux[] = {
4057 	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4058 	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4059 	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4060 	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4061 	VI4_DATA8_MARK,  VI4_DATA9_MARK,
4062 	VI4_DATA10_MARK, VI4_DATA11_MARK,
4063 	VI4_DATA12_MARK, VI4_DATA13_MARK,
4064 	VI4_DATA14_MARK, VI4_DATA15_MARK,
4065 	VI4_DATA16_MARK, VI4_DATA17_MARK,
4066 	VI4_DATA18_MARK, VI4_DATA19_MARK,
4067 	VI4_DATA20_MARK, VI4_DATA21_MARK,
4068 	VI4_DATA22_MARK, VI4_DATA23_MARK,
4069 };
4070 static const unsigned int vin4_sync_pins[] = {
4071 	/* HSYNC#, VSYNC# */
4072 	RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4073 };
4074 static const unsigned int vin4_sync_mux[] = {
4075 	VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4076 };
4077 static const unsigned int vin4_field_pins[] = {
4078 	/* FIELD */
4079 	RCAR_GP_PIN(1, 16),
4080 };
4081 static const unsigned int vin4_field_mux[] = {
4082 	VI4_FIELD_MARK,
4083 };
4084 static const unsigned int vin4_clkenb_pins[] = {
4085 	/* CLKENB */
4086 	RCAR_GP_PIN(1, 19),
4087 };
4088 static const unsigned int vin4_clkenb_mux[] = {
4089 	VI4_CLKENB_MARK,
4090 };
4091 static const unsigned int vin4_clk_pins[] = {
4092 	/* CLK */
4093 	RCAR_GP_PIN(1, 27),
4094 };
4095 static const unsigned int vin4_clk_mux[] = {
4096 	VI4_CLK_MARK,
4097 };
4098 
4099 /* - VIN5 ------------------------------------------------------------------- */
4100 static const unsigned int vin5_data_pins[] = {
4101 	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4102 	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4103 	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4104 	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4105 	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4106 	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4107 	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4108 	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4109 };
4110 static const unsigned int vin5_data_mux[] = {
4111 	VI5_DATA0_MARK, VI5_DATA1_MARK,
4112 	VI5_DATA2_MARK, VI5_DATA3_MARK,
4113 	VI5_DATA4_MARK, VI5_DATA5_MARK,
4114 	VI5_DATA6_MARK, VI5_DATA7_MARK,
4115 	VI5_DATA8_MARK,  VI5_DATA9_MARK,
4116 	VI5_DATA10_MARK, VI5_DATA11_MARK,
4117 	VI5_DATA12_MARK, VI5_DATA13_MARK,
4118 	VI5_DATA14_MARK, VI5_DATA15_MARK,
4119 };
4120 static const unsigned int vin5_sync_pins[] = {
4121 	/* HSYNC#, VSYNC# */
4122 	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4123 };
4124 static const unsigned int vin5_sync_mux[] = {
4125 	VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4126 };
4127 static const unsigned int vin5_field_pins[] = {
4128 	RCAR_GP_PIN(1, 11),
4129 };
4130 static const unsigned int vin5_field_mux[] = {
4131 	/* FIELD */
4132 	VI5_FIELD_MARK,
4133 };
4134 static const unsigned int vin5_clkenb_pins[] = {
4135 	RCAR_GP_PIN(1, 20),
4136 };
4137 static const unsigned int vin5_clkenb_mux[] = {
4138 	/* CLKENB */
4139 	VI5_CLKENB_MARK,
4140 };
4141 static const unsigned int vin5_clk_pins[] = {
4142 	RCAR_GP_PIN(1, 21),
4143 };
4144 static const unsigned int vin5_clk_mux[] = {
4145 	/* CLK */
4146 	VI5_CLK_MARK,
4147 };
4148 
4149 static const struct {
4150 	struct sh_pfc_pin_group common[328];
4151 #ifdef CONFIG_PINCTRL_PFC_R8A77951
4152 	struct sh_pfc_pin_group automotive[31];
4153 #endif
4154 } pinmux_groups = {
4155 	.common = {
4156 		SH_PFC_PIN_GROUP(audio_clk_a_a),
4157 		SH_PFC_PIN_GROUP(audio_clk_a_b),
4158 		SH_PFC_PIN_GROUP(audio_clk_a_c),
4159 		SH_PFC_PIN_GROUP(audio_clk_b_a),
4160 		SH_PFC_PIN_GROUP(audio_clk_b_b),
4161 		SH_PFC_PIN_GROUP(audio_clk_c_a),
4162 		SH_PFC_PIN_GROUP(audio_clk_c_b),
4163 		SH_PFC_PIN_GROUP(audio_clkout_a),
4164 		SH_PFC_PIN_GROUP(audio_clkout_b),
4165 		SH_PFC_PIN_GROUP(audio_clkout_c),
4166 		SH_PFC_PIN_GROUP(audio_clkout_d),
4167 		SH_PFC_PIN_GROUP(audio_clkout1_a),
4168 		SH_PFC_PIN_GROUP(audio_clkout1_b),
4169 		SH_PFC_PIN_GROUP(audio_clkout2_a),
4170 		SH_PFC_PIN_GROUP(audio_clkout2_b),
4171 		SH_PFC_PIN_GROUP(audio_clkout3_a),
4172 		SH_PFC_PIN_GROUP(audio_clkout3_b),
4173 		SH_PFC_PIN_GROUP(avb_link),
4174 		SH_PFC_PIN_GROUP(avb_magic),
4175 		SH_PFC_PIN_GROUP(avb_phy_int),
4176 		SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),	/* Deprecated */
4177 		SH_PFC_PIN_GROUP(avb_mdio),
4178 		SH_PFC_PIN_GROUP(avb_mii),
4179 		SH_PFC_PIN_GROUP(avb_avtp_pps),
4180 		SH_PFC_PIN_GROUP(avb_avtp_match_a),
4181 		SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4182 		SH_PFC_PIN_GROUP(avb_avtp_match_b),
4183 		SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4184 		SH_PFC_PIN_GROUP(can0_data_a),
4185 		SH_PFC_PIN_GROUP(can0_data_b),
4186 		SH_PFC_PIN_GROUP(can1_data),
4187 		SH_PFC_PIN_GROUP(can_clk),
4188 		SH_PFC_PIN_GROUP(canfd0_data_a),
4189 		SH_PFC_PIN_GROUP(canfd0_data_b),
4190 		SH_PFC_PIN_GROUP(canfd1_data),
4191 		SH_PFC_PIN_GROUP(du_rgb666),
4192 		SH_PFC_PIN_GROUP(du_rgb888),
4193 		SH_PFC_PIN_GROUP(du_clk_out_0),
4194 		SH_PFC_PIN_GROUP(du_clk_out_1),
4195 		SH_PFC_PIN_GROUP(du_sync),
4196 		SH_PFC_PIN_GROUP(du_oddf),
4197 		SH_PFC_PIN_GROUP(du_cde),
4198 		SH_PFC_PIN_GROUP(du_disp),
4199 		SH_PFC_PIN_GROUP(hscif0_data),
4200 		SH_PFC_PIN_GROUP(hscif0_clk),
4201 		SH_PFC_PIN_GROUP(hscif0_ctrl),
4202 		SH_PFC_PIN_GROUP(hscif1_data_a),
4203 		SH_PFC_PIN_GROUP(hscif1_clk_a),
4204 		SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4205 		SH_PFC_PIN_GROUP(hscif1_data_b),
4206 		SH_PFC_PIN_GROUP(hscif1_clk_b),
4207 		SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4208 		SH_PFC_PIN_GROUP(hscif2_data_a),
4209 		SH_PFC_PIN_GROUP(hscif2_clk_a),
4210 		SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4211 		SH_PFC_PIN_GROUP(hscif2_data_b),
4212 		SH_PFC_PIN_GROUP(hscif2_clk_b),
4213 		SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4214 		SH_PFC_PIN_GROUP(hscif2_data_c),
4215 		SH_PFC_PIN_GROUP(hscif2_clk_c),
4216 		SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4217 		SH_PFC_PIN_GROUP(hscif3_data_a),
4218 		SH_PFC_PIN_GROUP(hscif3_clk),
4219 		SH_PFC_PIN_GROUP(hscif3_ctrl),
4220 		SH_PFC_PIN_GROUP(hscif3_data_b),
4221 		SH_PFC_PIN_GROUP(hscif3_data_c),
4222 		SH_PFC_PIN_GROUP(hscif3_data_d),
4223 		SH_PFC_PIN_GROUP(hscif4_data_a),
4224 		SH_PFC_PIN_GROUP(hscif4_clk),
4225 		SH_PFC_PIN_GROUP(hscif4_ctrl),
4226 		SH_PFC_PIN_GROUP(hscif4_data_b),
4227 		SH_PFC_PIN_GROUP(i2c0),
4228 		SH_PFC_PIN_GROUP(i2c1_a),
4229 		SH_PFC_PIN_GROUP(i2c1_b),
4230 		SH_PFC_PIN_GROUP(i2c2_a),
4231 		SH_PFC_PIN_GROUP(i2c2_b),
4232 		SH_PFC_PIN_GROUP(i2c3),
4233 		SH_PFC_PIN_GROUP(i2c5),
4234 		SH_PFC_PIN_GROUP(i2c6_a),
4235 		SH_PFC_PIN_GROUP(i2c6_b),
4236 		SH_PFC_PIN_GROUP(i2c6_c),
4237 		SH_PFC_PIN_GROUP(intc_ex_irq0),
4238 		SH_PFC_PIN_GROUP(intc_ex_irq1),
4239 		SH_PFC_PIN_GROUP(intc_ex_irq2),
4240 		SH_PFC_PIN_GROUP(intc_ex_irq3),
4241 		SH_PFC_PIN_GROUP(intc_ex_irq4),
4242 		SH_PFC_PIN_GROUP(intc_ex_irq5),
4243 		SH_PFC_PIN_GROUP(msiof0_clk),
4244 		SH_PFC_PIN_GROUP(msiof0_sync),
4245 		SH_PFC_PIN_GROUP(msiof0_ss1),
4246 		SH_PFC_PIN_GROUP(msiof0_ss2),
4247 		SH_PFC_PIN_GROUP(msiof0_txd),
4248 		SH_PFC_PIN_GROUP(msiof0_rxd),
4249 		SH_PFC_PIN_GROUP(msiof1_clk_a),
4250 		SH_PFC_PIN_GROUP(msiof1_sync_a),
4251 		SH_PFC_PIN_GROUP(msiof1_ss1_a),
4252 		SH_PFC_PIN_GROUP(msiof1_ss2_a),
4253 		SH_PFC_PIN_GROUP(msiof1_txd_a),
4254 		SH_PFC_PIN_GROUP(msiof1_rxd_a),
4255 		SH_PFC_PIN_GROUP(msiof1_clk_b),
4256 		SH_PFC_PIN_GROUP(msiof1_sync_b),
4257 		SH_PFC_PIN_GROUP(msiof1_ss1_b),
4258 		SH_PFC_PIN_GROUP(msiof1_ss2_b),
4259 		SH_PFC_PIN_GROUP(msiof1_txd_b),
4260 		SH_PFC_PIN_GROUP(msiof1_rxd_b),
4261 		SH_PFC_PIN_GROUP(msiof1_clk_c),
4262 		SH_PFC_PIN_GROUP(msiof1_sync_c),
4263 		SH_PFC_PIN_GROUP(msiof1_ss1_c),
4264 		SH_PFC_PIN_GROUP(msiof1_ss2_c),
4265 		SH_PFC_PIN_GROUP(msiof1_txd_c),
4266 		SH_PFC_PIN_GROUP(msiof1_rxd_c),
4267 		SH_PFC_PIN_GROUP(msiof1_clk_d),
4268 		SH_PFC_PIN_GROUP(msiof1_sync_d),
4269 		SH_PFC_PIN_GROUP(msiof1_ss1_d),
4270 		SH_PFC_PIN_GROUP(msiof1_ss2_d),
4271 		SH_PFC_PIN_GROUP(msiof1_txd_d),
4272 		SH_PFC_PIN_GROUP(msiof1_rxd_d),
4273 		SH_PFC_PIN_GROUP(msiof1_clk_e),
4274 		SH_PFC_PIN_GROUP(msiof1_sync_e),
4275 		SH_PFC_PIN_GROUP(msiof1_ss1_e),
4276 		SH_PFC_PIN_GROUP(msiof1_ss2_e),
4277 		SH_PFC_PIN_GROUP(msiof1_txd_e),
4278 		SH_PFC_PIN_GROUP(msiof1_rxd_e),
4279 		SH_PFC_PIN_GROUP(msiof1_clk_f),
4280 		SH_PFC_PIN_GROUP(msiof1_sync_f),
4281 		SH_PFC_PIN_GROUP(msiof1_ss1_f),
4282 		SH_PFC_PIN_GROUP(msiof1_ss2_f),
4283 		SH_PFC_PIN_GROUP(msiof1_txd_f),
4284 		SH_PFC_PIN_GROUP(msiof1_rxd_f),
4285 		SH_PFC_PIN_GROUP(msiof1_clk_g),
4286 		SH_PFC_PIN_GROUP(msiof1_sync_g),
4287 		SH_PFC_PIN_GROUP(msiof1_ss1_g),
4288 		SH_PFC_PIN_GROUP(msiof1_ss2_g),
4289 		SH_PFC_PIN_GROUP(msiof1_txd_g),
4290 		SH_PFC_PIN_GROUP(msiof1_rxd_g),
4291 		SH_PFC_PIN_GROUP(msiof2_clk_a),
4292 		SH_PFC_PIN_GROUP(msiof2_sync_a),
4293 		SH_PFC_PIN_GROUP(msiof2_ss1_a),
4294 		SH_PFC_PIN_GROUP(msiof2_ss2_a),
4295 		SH_PFC_PIN_GROUP(msiof2_txd_a),
4296 		SH_PFC_PIN_GROUP(msiof2_rxd_a),
4297 		SH_PFC_PIN_GROUP(msiof2_clk_b),
4298 		SH_PFC_PIN_GROUP(msiof2_sync_b),
4299 		SH_PFC_PIN_GROUP(msiof2_ss1_b),
4300 		SH_PFC_PIN_GROUP(msiof2_ss2_b),
4301 		SH_PFC_PIN_GROUP(msiof2_txd_b),
4302 		SH_PFC_PIN_GROUP(msiof2_rxd_b),
4303 		SH_PFC_PIN_GROUP(msiof2_clk_c),
4304 		SH_PFC_PIN_GROUP(msiof2_sync_c),
4305 		SH_PFC_PIN_GROUP(msiof2_ss1_c),
4306 		SH_PFC_PIN_GROUP(msiof2_ss2_c),
4307 		SH_PFC_PIN_GROUP(msiof2_txd_c),
4308 		SH_PFC_PIN_GROUP(msiof2_rxd_c),
4309 		SH_PFC_PIN_GROUP(msiof2_clk_d),
4310 		SH_PFC_PIN_GROUP(msiof2_sync_d),
4311 		SH_PFC_PIN_GROUP(msiof2_ss1_d),
4312 		SH_PFC_PIN_GROUP(msiof2_ss2_d),
4313 		SH_PFC_PIN_GROUP(msiof2_txd_d),
4314 		SH_PFC_PIN_GROUP(msiof2_rxd_d),
4315 		SH_PFC_PIN_GROUP(msiof3_clk_a),
4316 		SH_PFC_PIN_GROUP(msiof3_sync_a),
4317 		SH_PFC_PIN_GROUP(msiof3_ss1_a),
4318 		SH_PFC_PIN_GROUP(msiof3_ss2_a),
4319 		SH_PFC_PIN_GROUP(msiof3_txd_a),
4320 		SH_PFC_PIN_GROUP(msiof3_rxd_a),
4321 		SH_PFC_PIN_GROUP(msiof3_clk_b),
4322 		SH_PFC_PIN_GROUP(msiof3_sync_b),
4323 		SH_PFC_PIN_GROUP(msiof3_ss1_b),
4324 		SH_PFC_PIN_GROUP(msiof3_ss2_b),
4325 		SH_PFC_PIN_GROUP(msiof3_txd_b),
4326 		SH_PFC_PIN_GROUP(msiof3_rxd_b),
4327 		SH_PFC_PIN_GROUP(msiof3_clk_c),
4328 		SH_PFC_PIN_GROUP(msiof3_sync_c),
4329 		SH_PFC_PIN_GROUP(msiof3_txd_c),
4330 		SH_PFC_PIN_GROUP(msiof3_rxd_c),
4331 		SH_PFC_PIN_GROUP(msiof3_clk_d),
4332 		SH_PFC_PIN_GROUP(msiof3_sync_d),
4333 		SH_PFC_PIN_GROUP(msiof3_ss1_d),
4334 		SH_PFC_PIN_GROUP(msiof3_txd_d),
4335 		SH_PFC_PIN_GROUP(msiof3_rxd_d),
4336 		SH_PFC_PIN_GROUP(msiof3_clk_e),
4337 		SH_PFC_PIN_GROUP(msiof3_sync_e),
4338 		SH_PFC_PIN_GROUP(msiof3_ss1_e),
4339 		SH_PFC_PIN_GROUP(msiof3_ss2_e),
4340 		SH_PFC_PIN_GROUP(msiof3_txd_e),
4341 		SH_PFC_PIN_GROUP(msiof3_rxd_e),
4342 		SH_PFC_PIN_GROUP(pwm0),
4343 		SH_PFC_PIN_GROUP(pwm1_a),
4344 		SH_PFC_PIN_GROUP(pwm1_b),
4345 		SH_PFC_PIN_GROUP(pwm2_a),
4346 		SH_PFC_PIN_GROUP(pwm2_b),
4347 		SH_PFC_PIN_GROUP(pwm3_a),
4348 		SH_PFC_PIN_GROUP(pwm3_b),
4349 		SH_PFC_PIN_GROUP(pwm4_a),
4350 		SH_PFC_PIN_GROUP(pwm4_b),
4351 		SH_PFC_PIN_GROUP(pwm5_a),
4352 		SH_PFC_PIN_GROUP(pwm5_b),
4353 		SH_PFC_PIN_GROUP(pwm6_a),
4354 		SH_PFC_PIN_GROUP(pwm6_b),
4355 		SH_PFC_PIN_GROUP(qspi0_ctrl),
4356 		BUS_DATA_PIN_GROUP(qspi0_data, 2),
4357 		BUS_DATA_PIN_GROUP(qspi0_data, 4),
4358 		SH_PFC_PIN_GROUP(qspi1_ctrl),
4359 		BUS_DATA_PIN_GROUP(qspi1_data, 2),
4360 		BUS_DATA_PIN_GROUP(qspi1_data, 4),
4361 		SH_PFC_PIN_GROUP(sata0_devslp_a),
4362 		SH_PFC_PIN_GROUP(sata0_devslp_b),
4363 		SH_PFC_PIN_GROUP(scif0_data),
4364 		SH_PFC_PIN_GROUP(scif0_clk),
4365 		SH_PFC_PIN_GROUP(scif0_ctrl),
4366 		SH_PFC_PIN_GROUP(scif1_data_a),
4367 		SH_PFC_PIN_GROUP(scif1_clk),
4368 		SH_PFC_PIN_GROUP(scif1_ctrl),
4369 		SH_PFC_PIN_GROUP(scif1_data_b),
4370 		SH_PFC_PIN_GROUP(scif2_data_a),
4371 		SH_PFC_PIN_GROUP(scif2_clk),
4372 		SH_PFC_PIN_GROUP(scif2_data_b),
4373 		SH_PFC_PIN_GROUP(scif3_data_a),
4374 		SH_PFC_PIN_GROUP(scif3_clk),
4375 		SH_PFC_PIN_GROUP(scif3_ctrl),
4376 		SH_PFC_PIN_GROUP(scif3_data_b),
4377 		SH_PFC_PIN_GROUP(scif4_data_a),
4378 		SH_PFC_PIN_GROUP(scif4_clk_a),
4379 		SH_PFC_PIN_GROUP(scif4_ctrl_a),
4380 		SH_PFC_PIN_GROUP(scif4_data_b),
4381 		SH_PFC_PIN_GROUP(scif4_clk_b),
4382 		SH_PFC_PIN_GROUP(scif4_ctrl_b),
4383 		SH_PFC_PIN_GROUP(scif4_data_c),
4384 		SH_PFC_PIN_GROUP(scif4_clk_c),
4385 		SH_PFC_PIN_GROUP(scif4_ctrl_c),
4386 		SH_PFC_PIN_GROUP(scif5_data_a),
4387 		SH_PFC_PIN_GROUP(scif5_clk_a),
4388 		SH_PFC_PIN_GROUP(scif5_data_b),
4389 		SH_PFC_PIN_GROUP(scif5_clk_b),
4390 		SH_PFC_PIN_GROUP(scif_clk_a),
4391 		SH_PFC_PIN_GROUP(scif_clk_b),
4392 		BUS_DATA_PIN_GROUP(sdhi0_data, 1),
4393 		BUS_DATA_PIN_GROUP(sdhi0_data, 4),
4394 		SH_PFC_PIN_GROUP(sdhi0_ctrl),
4395 		SH_PFC_PIN_GROUP(sdhi0_cd),
4396 		SH_PFC_PIN_GROUP(sdhi0_wp),
4397 		BUS_DATA_PIN_GROUP(sdhi1_data, 1),
4398 		BUS_DATA_PIN_GROUP(sdhi1_data, 4),
4399 		SH_PFC_PIN_GROUP(sdhi1_ctrl),
4400 		SH_PFC_PIN_GROUP(sdhi1_cd),
4401 		SH_PFC_PIN_GROUP(sdhi1_wp),
4402 		BUS_DATA_PIN_GROUP(sdhi2_data, 1),
4403 		BUS_DATA_PIN_GROUP(sdhi2_data, 4),
4404 		BUS_DATA_PIN_GROUP(sdhi2_data, 8),
4405 		SH_PFC_PIN_GROUP(sdhi2_ctrl),
4406 		SH_PFC_PIN_GROUP(sdhi2_cd_a),
4407 		SH_PFC_PIN_GROUP(sdhi2_wp_a),
4408 		SH_PFC_PIN_GROUP(sdhi2_cd_b),
4409 		SH_PFC_PIN_GROUP(sdhi2_wp_b),
4410 		SH_PFC_PIN_GROUP(sdhi2_ds),
4411 		BUS_DATA_PIN_GROUP(sdhi3_data, 1),
4412 		BUS_DATA_PIN_GROUP(sdhi3_data, 4),
4413 		BUS_DATA_PIN_GROUP(sdhi3_data, 8),
4414 		SH_PFC_PIN_GROUP(sdhi3_ctrl),
4415 		SH_PFC_PIN_GROUP(sdhi3_cd),
4416 		SH_PFC_PIN_GROUP(sdhi3_wp),
4417 		SH_PFC_PIN_GROUP(sdhi3_ds),
4418 		SH_PFC_PIN_GROUP(ssi0_data),
4419 		SH_PFC_PIN_GROUP(ssi01239_ctrl),
4420 		SH_PFC_PIN_GROUP(ssi1_data_a),
4421 		SH_PFC_PIN_GROUP(ssi1_data_b),
4422 		SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4423 		SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4424 		SH_PFC_PIN_GROUP(ssi2_data_a),
4425 		SH_PFC_PIN_GROUP(ssi2_data_b),
4426 		SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4427 		SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4428 		SH_PFC_PIN_GROUP(ssi3_data),
4429 		SH_PFC_PIN_GROUP(ssi349_ctrl),
4430 		SH_PFC_PIN_GROUP(ssi4_data),
4431 		SH_PFC_PIN_GROUP(ssi4_ctrl),
4432 		SH_PFC_PIN_GROUP(ssi5_data),
4433 		SH_PFC_PIN_GROUP(ssi5_ctrl),
4434 		SH_PFC_PIN_GROUP(ssi6_data),
4435 		SH_PFC_PIN_GROUP(ssi6_ctrl),
4436 		SH_PFC_PIN_GROUP(ssi7_data),
4437 		SH_PFC_PIN_GROUP(ssi78_ctrl),
4438 		SH_PFC_PIN_GROUP(ssi8_data),
4439 		SH_PFC_PIN_GROUP(ssi9_data_a),
4440 		SH_PFC_PIN_GROUP(ssi9_data_b),
4441 		SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4442 		SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4443 		SH_PFC_PIN_GROUP(tmu_tclk1_a),
4444 		SH_PFC_PIN_GROUP(tmu_tclk1_b),
4445 		SH_PFC_PIN_GROUP(tmu_tclk2_a),
4446 		SH_PFC_PIN_GROUP(tmu_tclk2_b),
4447 		SH_PFC_PIN_GROUP(tpu_to0),
4448 		SH_PFC_PIN_GROUP(tpu_to1),
4449 		SH_PFC_PIN_GROUP(tpu_to2),
4450 		SH_PFC_PIN_GROUP(tpu_to3),
4451 		SH_PFC_PIN_GROUP(usb0),
4452 		SH_PFC_PIN_GROUP(usb1),
4453 		SH_PFC_PIN_GROUP(usb2),
4454 		SH_PFC_PIN_GROUP(usb2_ch3),
4455 		SH_PFC_PIN_GROUP(usb30),
4456 		BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
4457 		BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
4458 		BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
4459 		BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
4460 		SH_PFC_PIN_GROUP(vin4_data18_a),
4461 		BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
4462 		BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
4463 		BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
4464 		BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
4465 		BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
4466 		BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
4467 		SH_PFC_PIN_GROUP(vin4_data18_b),
4468 		BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
4469 		BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
4470 		SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
4471 		SH_PFC_PIN_GROUP(vin4_sync),
4472 		SH_PFC_PIN_GROUP(vin4_field),
4473 		SH_PFC_PIN_GROUP(vin4_clkenb),
4474 		SH_PFC_PIN_GROUP(vin4_clk),
4475 		BUS_DATA_PIN_GROUP(vin5_data, 8),
4476 		BUS_DATA_PIN_GROUP(vin5_data, 10),
4477 		BUS_DATA_PIN_GROUP(vin5_data, 12),
4478 		BUS_DATA_PIN_GROUP(vin5_data, 16),
4479 		SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
4480 		SH_PFC_PIN_GROUP(vin5_sync),
4481 		SH_PFC_PIN_GROUP(vin5_field),
4482 		SH_PFC_PIN_GROUP(vin5_clkenb),
4483 		SH_PFC_PIN_GROUP(vin5_clk),
4484 	},
4485 #ifdef CONFIG_PINCTRL_PFC_R8A77951
4486 	.automotive = {
4487 		SH_PFC_PIN_GROUP(drif0_ctrl_a),
4488 		SH_PFC_PIN_GROUP(drif0_data0_a),
4489 		SH_PFC_PIN_GROUP(drif0_data1_a),
4490 		SH_PFC_PIN_GROUP(drif0_ctrl_b),
4491 		SH_PFC_PIN_GROUP(drif0_data0_b),
4492 		SH_PFC_PIN_GROUP(drif0_data1_b),
4493 		SH_PFC_PIN_GROUP(drif0_ctrl_c),
4494 		SH_PFC_PIN_GROUP(drif0_data0_c),
4495 		SH_PFC_PIN_GROUP(drif0_data1_c),
4496 		SH_PFC_PIN_GROUP(drif1_ctrl_a),
4497 		SH_PFC_PIN_GROUP(drif1_data0_a),
4498 		SH_PFC_PIN_GROUP(drif1_data1_a),
4499 		SH_PFC_PIN_GROUP(drif1_ctrl_b),
4500 		SH_PFC_PIN_GROUP(drif1_data0_b),
4501 		SH_PFC_PIN_GROUP(drif1_data1_b),
4502 		SH_PFC_PIN_GROUP(drif1_ctrl_c),
4503 		SH_PFC_PIN_GROUP(drif1_data0_c),
4504 		SH_PFC_PIN_GROUP(drif1_data1_c),
4505 		SH_PFC_PIN_GROUP(drif2_ctrl_a),
4506 		SH_PFC_PIN_GROUP(drif2_data0_a),
4507 		SH_PFC_PIN_GROUP(drif2_data1_a),
4508 		SH_PFC_PIN_GROUP(drif2_ctrl_b),
4509 		SH_PFC_PIN_GROUP(drif2_data0_b),
4510 		SH_PFC_PIN_GROUP(drif2_data1_b),
4511 		SH_PFC_PIN_GROUP(drif3_ctrl_a),
4512 		SH_PFC_PIN_GROUP(drif3_data0_a),
4513 		SH_PFC_PIN_GROUP(drif3_data1_a),
4514 		SH_PFC_PIN_GROUP(drif3_ctrl_b),
4515 		SH_PFC_PIN_GROUP(drif3_data0_b),
4516 		SH_PFC_PIN_GROUP(drif3_data1_b),
4517 		SH_PFC_PIN_GROUP(mlb_3pin),
4518 	}
4519 #endif /* CONFIG_PINCTRL_PFC_R8A77951 */
4520 };
4521 
4522 static const char * const audio_clk_groups[] = {
4523 	"audio_clk_a_a",
4524 	"audio_clk_a_b",
4525 	"audio_clk_a_c",
4526 	"audio_clk_b_a",
4527 	"audio_clk_b_b",
4528 	"audio_clk_c_a",
4529 	"audio_clk_c_b",
4530 	"audio_clkout_a",
4531 	"audio_clkout_b",
4532 	"audio_clkout_c",
4533 	"audio_clkout_d",
4534 	"audio_clkout1_a",
4535 	"audio_clkout1_b",
4536 	"audio_clkout2_a",
4537 	"audio_clkout2_b",
4538 	"audio_clkout3_a",
4539 	"audio_clkout3_b",
4540 };
4541 
4542 static const char * const avb_groups[] = {
4543 	"avb_link",
4544 	"avb_magic",
4545 	"avb_phy_int",
4546 	"avb_mdc",	/* Deprecated, please use "avb_mdio" instead */
4547 	"avb_mdio",
4548 	"avb_mii",
4549 	"avb_avtp_pps",
4550 	"avb_avtp_match_a",
4551 	"avb_avtp_capture_a",
4552 	"avb_avtp_match_b",
4553 	"avb_avtp_capture_b",
4554 };
4555 
4556 static const char * const can0_groups[] = {
4557 	"can0_data_a",
4558 	"can0_data_b",
4559 };
4560 
4561 static const char * const can1_groups[] = {
4562 	"can1_data",
4563 };
4564 
4565 static const char * const can_clk_groups[] = {
4566 	"can_clk",
4567 };
4568 
4569 static const char * const canfd0_groups[] = {
4570 	"canfd0_data_a",
4571 	"canfd0_data_b",
4572 };
4573 
4574 static const char * const canfd1_groups[] = {
4575 	"canfd1_data",
4576 };
4577 
4578 #ifdef CONFIG_PINCTRL_PFC_R8A77951
4579 static const char * const drif0_groups[] = {
4580 	"drif0_ctrl_a",
4581 	"drif0_data0_a",
4582 	"drif0_data1_a",
4583 	"drif0_ctrl_b",
4584 	"drif0_data0_b",
4585 	"drif0_data1_b",
4586 	"drif0_ctrl_c",
4587 	"drif0_data0_c",
4588 	"drif0_data1_c",
4589 };
4590 
4591 static const char * const drif1_groups[] = {
4592 	"drif1_ctrl_a",
4593 	"drif1_data0_a",
4594 	"drif1_data1_a",
4595 	"drif1_ctrl_b",
4596 	"drif1_data0_b",
4597 	"drif1_data1_b",
4598 	"drif1_ctrl_c",
4599 	"drif1_data0_c",
4600 	"drif1_data1_c",
4601 };
4602 
4603 static const char * const drif2_groups[] = {
4604 	"drif2_ctrl_a",
4605 	"drif2_data0_a",
4606 	"drif2_data1_a",
4607 	"drif2_ctrl_b",
4608 	"drif2_data0_b",
4609 	"drif2_data1_b",
4610 };
4611 
4612 static const char * const drif3_groups[] = {
4613 	"drif3_ctrl_a",
4614 	"drif3_data0_a",
4615 	"drif3_data1_a",
4616 	"drif3_ctrl_b",
4617 	"drif3_data0_b",
4618 	"drif3_data1_b",
4619 };
4620 #endif /* CONFIG_PINCTRL_PFC_R8A77951 */
4621 
4622 static const char * const du_groups[] = {
4623 	"du_rgb666",
4624 	"du_rgb888",
4625 	"du_clk_out_0",
4626 	"du_clk_out_1",
4627 	"du_sync",
4628 	"du_oddf",
4629 	"du_cde",
4630 	"du_disp",
4631 };
4632 
4633 static const char * const hscif0_groups[] = {
4634 	"hscif0_data",
4635 	"hscif0_clk",
4636 	"hscif0_ctrl",
4637 };
4638 
4639 static const char * const hscif1_groups[] = {
4640 	"hscif1_data_a",
4641 	"hscif1_clk_a",
4642 	"hscif1_ctrl_a",
4643 	"hscif1_data_b",
4644 	"hscif1_clk_b",
4645 	"hscif1_ctrl_b",
4646 };
4647 
4648 static const char * const hscif2_groups[] = {
4649 	"hscif2_data_a",
4650 	"hscif2_clk_a",
4651 	"hscif2_ctrl_a",
4652 	"hscif2_data_b",
4653 	"hscif2_clk_b",
4654 	"hscif2_ctrl_b",
4655 	"hscif2_data_c",
4656 	"hscif2_clk_c",
4657 	"hscif2_ctrl_c",
4658 };
4659 
4660 static const char * const hscif3_groups[] = {
4661 	"hscif3_data_a",
4662 	"hscif3_clk",
4663 	"hscif3_ctrl",
4664 	"hscif3_data_b",
4665 	"hscif3_data_c",
4666 	"hscif3_data_d",
4667 };
4668 
4669 static const char * const hscif4_groups[] = {
4670 	"hscif4_data_a",
4671 	"hscif4_clk",
4672 	"hscif4_ctrl",
4673 	"hscif4_data_b",
4674 };
4675 
4676 static const char * const i2c0_groups[] = {
4677 	"i2c0",
4678 };
4679 
4680 static const char * const i2c1_groups[] = {
4681 	"i2c1_a",
4682 	"i2c1_b",
4683 };
4684 
4685 static const char * const i2c2_groups[] = {
4686 	"i2c2_a",
4687 	"i2c2_b",
4688 };
4689 
4690 static const char * const i2c3_groups[] = {
4691 	"i2c3",
4692 };
4693 
4694 static const char * const i2c5_groups[] = {
4695 	"i2c5",
4696 };
4697 
4698 static const char * const i2c6_groups[] = {
4699 	"i2c6_a",
4700 	"i2c6_b",
4701 	"i2c6_c",
4702 };
4703 
4704 static const char * const intc_ex_groups[] = {
4705 	"intc_ex_irq0",
4706 	"intc_ex_irq1",
4707 	"intc_ex_irq2",
4708 	"intc_ex_irq3",
4709 	"intc_ex_irq4",
4710 	"intc_ex_irq5",
4711 };
4712 
4713 #ifdef CONFIG_PINCTRL_PFC_R8A77951
4714 static const char * const mlb_3pin_groups[] = {
4715 	"mlb_3pin",
4716 };
4717 #endif /* CONFIG_PINCTRL_PFC_R8A77951 */
4718 
4719 static const char * const msiof0_groups[] = {
4720 	"msiof0_clk",
4721 	"msiof0_sync",
4722 	"msiof0_ss1",
4723 	"msiof0_ss2",
4724 	"msiof0_txd",
4725 	"msiof0_rxd",
4726 };
4727 
4728 static const char * const msiof1_groups[] = {
4729 	"msiof1_clk_a",
4730 	"msiof1_sync_a",
4731 	"msiof1_ss1_a",
4732 	"msiof1_ss2_a",
4733 	"msiof1_txd_a",
4734 	"msiof1_rxd_a",
4735 	"msiof1_clk_b",
4736 	"msiof1_sync_b",
4737 	"msiof1_ss1_b",
4738 	"msiof1_ss2_b",
4739 	"msiof1_txd_b",
4740 	"msiof1_rxd_b",
4741 	"msiof1_clk_c",
4742 	"msiof1_sync_c",
4743 	"msiof1_ss1_c",
4744 	"msiof1_ss2_c",
4745 	"msiof1_txd_c",
4746 	"msiof1_rxd_c",
4747 	"msiof1_clk_d",
4748 	"msiof1_sync_d",
4749 	"msiof1_ss1_d",
4750 	"msiof1_ss2_d",
4751 	"msiof1_txd_d",
4752 	"msiof1_rxd_d",
4753 	"msiof1_clk_e",
4754 	"msiof1_sync_e",
4755 	"msiof1_ss1_e",
4756 	"msiof1_ss2_e",
4757 	"msiof1_txd_e",
4758 	"msiof1_rxd_e",
4759 	"msiof1_clk_f",
4760 	"msiof1_sync_f",
4761 	"msiof1_ss1_f",
4762 	"msiof1_ss2_f",
4763 	"msiof1_txd_f",
4764 	"msiof1_rxd_f",
4765 	"msiof1_clk_g",
4766 	"msiof1_sync_g",
4767 	"msiof1_ss1_g",
4768 	"msiof1_ss2_g",
4769 	"msiof1_txd_g",
4770 	"msiof1_rxd_g",
4771 };
4772 
4773 static const char * const msiof2_groups[] = {
4774 	"msiof2_clk_a",
4775 	"msiof2_sync_a",
4776 	"msiof2_ss1_a",
4777 	"msiof2_ss2_a",
4778 	"msiof2_txd_a",
4779 	"msiof2_rxd_a",
4780 	"msiof2_clk_b",
4781 	"msiof2_sync_b",
4782 	"msiof2_ss1_b",
4783 	"msiof2_ss2_b",
4784 	"msiof2_txd_b",
4785 	"msiof2_rxd_b",
4786 	"msiof2_clk_c",
4787 	"msiof2_sync_c",
4788 	"msiof2_ss1_c",
4789 	"msiof2_ss2_c",
4790 	"msiof2_txd_c",
4791 	"msiof2_rxd_c",
4792 	"msiof2_clk_d",
4793 	"msiof2_sync_d",
4794 	"msiof2_ss1_d",
4795 	"msiof2_ss2_d",
4796 	"msiof2_txd_d",
4797 	"msiof2_rxd_d",
4798 };
4799 
4800 static const char * const msiof3_groups[] = {
4801 	"msiof3_clk_a",
4802 	"msiof3_sync_a",
4803 	"msiof3_ss1_a",
4804 	"msiof3_ss2_a",
4805 	"msiof3_txd_a",
4806 	"msiof3_rxd_a",
4807 	"msiof3_clk_b",
4808 	"msiof3_sync_b",
4809 	"msiof3_ss1_b",
4810 	"msiof3_ss2_b",
4811 	"msiof3_txd_b",
4812 	"msiof3_rxd_b",
4813 	"msiof3_clk_c",
4814 	"msiof3_sync_c",
4815 	"msiof3_txd_c",
4816 	"msiof3_rxd_c",
4817 	"msiof3_clk_d",
4818 	"msiof3_sync_d",
4819 	"msiof3_ss1_d",
4820 	"msiof3_txd_d",
4821 	"msiof3_rxd_d",
4822 	"msiof3_clk_e",
4823 	"msiof3_sync_e",
4824 	"msiof3_ss1_e",
4825 	"msiof3_ss2_e",
4826 	"msiof3_txd_e",
4827 	"msiof3_rxd_e",
4828 };
4829 
4830 static const char * const pwm0_groups[] = {
4831 	"pwm0",
4832 };
4833 
4834 static const char * const pwm1_groups[] = {
4835 	"pwm1_a",
4836 	"pwm1_b",
4837 };
4838 
4839 static const char * const pwm2_groups[] = {
4840 	"pwm2_a",
4841 	"pwm2_b",
4842 };
4843 
4844 static const char * const pwm3_groups[] = {
4845 	"pwm3_a",
4846 	"pwm3_b",
4847 };
4848 
4849 static const char * const pwm4_groups[] = {
4850 	"pwm4_a",
4851 	"pwm4_b",
4852 };
4853 
4854 static const char * const pwm5_groups[] = {
4855 	"pwm5_a",
4856 	"pwm5_b",
4857 };
4858 
4859 static const char * const pwm6_groups[] = {
4860 	"pwm6_a",
4861 	"pwm6_b",
4862 };
4863 
4864 static const char * const qspi0_groups[] = {
4865 	"qspi0_ctrl",
4866 	"qspi0_data2",
4867 	"qspi0_data4",
4868 };
4869 
4870 static const char * const qspi1_groups[] = {
4871 	"qspi1_ctrl",
4872 	"qspi1_data2",
4873 	"qspi1_data4",
4874 };
4875 
4876 static const char * const sata0_groups[] = {
4877 	"sata0_devslp_a",
4878 	"sata0_devslp_b",
4879 };
4880 
4881 static const char * const scif0_groups[] = {
4882 	"scif0_data",
4883 	"scif0_clk",
4884 	"scif0_ctrl",
4885 };
4886 
4887 static const char * const scif1_groups[] = {
4888 	"scif1_data_a",
4889 	"scif1_clk",
4890 	"scif1_ctrl",
4891 	"scif1_data_b",
4892 };
4893 
4894 static const char * const scif2_groups[] = {
4895 	"scif2_data_a",
4896 	"scif2_clk",
4897 	"scif2_data_b",
4898 };
4899 
4900 static const char * const scif3_groups[] = {
4901 	"scif3_data_a",
4902 	"scif3_clk",
4903 	"scif3_ctrl",
4904 	"scif3_data_b",
4905 };
4906 
4907 static const char * const scif4_groups[] = {
4908 	"scif4_data_a",
4909 	"scif4_clk_a",
4910 	"scif4_ctrl_a",
4911 	"scif4_data_b",
4912 	"scif4_clk_b",
4913 	"scif4_ctrl_b",
4914 	"scif4_data_c",
4915 	"scif4_clk_c",
4916 	"scif4_ctrl_c",
4917 };
4918 
4919 static const char * const scif5_groups[] = {
4920 	"scif5_data_a",
4921 	"scif5_clk_a",
4922 	"scif5_data_b",
4923 	"scif5_clk_b",
4924 };
4925 
4926 static const char * const scif_clk_groups[] = {
4927 	"scif_clk_a",
4928 	"scif_clk_b",
4929 };
4930 
4931 static const char * const sdhi0_groups[] = {
4932 	"sdhi0_data1",
4933 	"sdhi0_data4",
4934 	"sdhi0_ctrl",
4935 	"sdhi0_cd",
4936 	"sdhi0_wp",
4937 };
4938 
4939 static const char * const sdhi1_groups[] = {
4940 	"sdhi1_data1",
4941 	"sdhi1_data4",
4942 	"sdhi1_ctrl",
4943 	"sdhi1_cd",
4944 	"sdhi1_wp",
4945 };
4946 
4947 static const char * const sdhi2_groups[] = {
4948 	"sdhi2_data1",
4949 	"sdhi2_data4",
4950 	"sdhi2_data8",
4951 	"sdhi2_ctrl",
4952 	"sdhi2_cd_a",
4953 	"sdhi2_wp_a",
4954 	"sdhi2_cd_b",
4955 	"sdhi2_wp_b",
4956 	"sdhi2_ds",
4957 };
4958 
4959 static const char * const sdhi3_groups[] = {
4960 	"sdhi3_data1",
4961 	"sdhi3_data4",
4962 	"sdhi3_data8",
4963 	"sdhi3_ctrl",
4964 	"sdhi3_cd",
4965 	"sdhi3_wp",
4966 	"sdhi3_ds",
4967 };
4968 
4969 static const char * const ssi_groups[] = {
4970 	"ssi0_data",
4971 	"ssi01239_ctrl",
4972 	"ssi1_data_a",
4973 	"ssi1_data_b",
4974 	"ssi1_ctrl_a",
4975 	"ssi1_ctrl_b",
4976 	"ssi2_data_a",
4977 	"ssi2_data_b",
4978 	"ssi2_ctrl_a",
4979 	"ssi2_ctrl_b",
4980 	"ssi3_data",
4981 	"ssi349_ctrl",
4982 	"ssi4_data",
4983 	"ssi4_ctrl",
4984 	"ssi5_data",
4985 	"ssi5_ctrl",
4986 	"ssi6_data",
4987 	"ssi6_ctrl",
4988 	"ssi7_data",
4989 	"ssi78_ctrl",
4990 	"ssi8_data",
4991 	"ssi9_data_a",
4992 	"ssi9_data_b",
4993 	"ssi9_ctrl_a",
4994 	"ssi9_ctrl_b",
4995 };
4996 
4997 static const char * const tmu_groups[] = {
4998 	"tmu_tclk1_a",
4999 	"tmu_tclk1_b",
5000 	"tmu_tclk2_a",
5001 	"tmu_tclk2_b",
5002 };
5003 
5004 static const char * const tpu_groups[] = {
5005 	"tpu_to0",
5006 	"tpu_to1",
5007 	"tpu_to2",
5008 	"tpu_to3",
5009 };
5010 
5011 static const char * const usb0_groups[] = {
5012 	"usb0",
5013 };
5014 
5015 static const char * const usb1_groups[] = {
5016 	"usb1",
5017 };
5018 
5019 static const char * const usb2_groups[] = {
5020 	"usb2",
5021 };
5022 
5023 static const char * const usb2_ch3_groups[] = {
5024 	"usb2_ch3",
5025 };
5026 
5027 static const char * const usb30_groups[] = {
5028 	"usb30",
5029 };
5030 
5031 static const char * const vin4_groups[] = {
5032 	"vin4_data8_a",
5033 	"vin4_data10_a",
5034 	"vin4_data12_a",
5035 	"vin4_data16_a",
5036 	"vin4_data18_a",
5037 	"vin4_data20_a",
5038 	"vin4_data24_a",
5039 	"vin4_data8_b",
5040 	"vin4_data10_b",
5041 	"vin4_data12_b",
5042 	"vin4_data16_b",
5043 	"vin4_data18_b",
5044 	"vin4_data20_b",
5045 	"vin4_data24_b",
5046 	"vin4_g8",
5047 	"vin4_sync",
5048 	"vin4_field",
5049 	"vin4_clkenb",
5050 	"vin4_clk",
5051 };
5052 
5053 static const char * const vin5_groups[] = {
5054 	"vin5_data8",
5055 	"vin5_data10",
5056 	"vin5_data12",
5057 	"vin5_data16",
5058 	"vin5_high8",
5059 	"vin5_sync",
5060 	"vin5_field",
5061 	"vin5_clkenb",
5062 	"vin5_clk",
5063 };
5064 
5065 static const struct {
5066 	struct sh_pfc_function common[55];
5067 #ifdef CONFIG_PINCTRL_PFC_R8A77951
5068 	struct sh_pfc_function automotive[5];
5069 #endif
5070 } pinmux_functions = {
5071 	.common = {
5072 		SH_PFC_FUNCTION(audio_clk),
5073 		SH_PFC_FUNCTION(avb),
5074 		SH_PFC_FUNCTION(can0),
5075 		SH_PFC_FUNCTION(can1),
5076 		SH_PFC_FUNCTION(can_clk),
5077 		SH_PFC_FUNCTION(canfd0),
5078 		SH_PFC_FUNCTION(canfd1),
5079 		SH_PFC_FUNCTION(du),
5080 		SH_PFC_FUNCTION(hscif0),
5081 		SH_PFC_FUNCTION(hscif1),
5082 		SH_PFC_FUNCTION(hscif2),
5083 		SH_PFC_FUNCTION(hscif3),
5084 		SH_PFC_FUNCTION(hscif4),
5085 		SH_PFC_FUNCTION(i2c0),
5086 		SH_PFC_FUNCTION(i2c1),
5087 		SH_PFC_FUNCTION(i2c2),
5088 		SH_PFC_FUNCTION(i2c3),
5089 		SH_PFC_FUNCTION(i2c5),
5090 		SH_PFC_FUNCTION(i2c6),
5091 		SH_PFC_FUNCTION(intc_ex),
5092 		SH_PFC_FUNCTION(msiof0),
5093 		SH_PFC_FUNCTION(msiof1),
5094 		SH_PFC_FUNCTION(msiof2),
5095 		SH_PFC_FUNCTION(msiof3),
5096 		SH_PFC_FUNCTION(pwm0),
5097 		SH_PFC_FUNCTION(pwm1),
5098 		SH_PFC_FUNCTION(pwm2),
5099 		SH_PFC_FUNCTION(pwm3),
5100 		SH_PFC_FUNCTION(pwm4),
5101 		SH_PFC_FUNCTION(pwm5),
5102 		SH_PFC_FUNCTION(pwm6),
5103 		SH_PFC_FUNCTION(qspi0),
5104 		SH_PFC_FUNCTION(qspi1),
5105 		SH_PFC_FUNCTION(sata0),
5106 		SH_PFC_FUNCTION(scif0),
5107 		SH_PFC_FUNCTION(scif1),
5108 		SH_PFC_FUNCTION(scif2),
5109 		SH_PFC_FUNCTION(scif3),
5110 		SH_PFC_FUNCTION(scif4),
5111 		SH_PFC_FUNCTION(scif5),
5112 		SH_PFC_FUNCTION(scif_clk),
5113 		SH_PFC_FUNCTION(sdhi0),
5114 		SH_PFC_FUNCTION(sdhi1),
5115 		SH_PFC_FUNCTION(sdhi2),
5116 		SH_PFC_FUNCTION(sdhi3),
5117 		SH_PFC_FUNCTION(ssi),
5118 		SH_PFC_FUNCTION(tmu),
5119 		SH_PFC_FUNCTION(tpu),
5120 		SH_PFC_FUNCTION(usb0),
5121 		SH_PFC_FUNCTION(usb1),
5122 		SH_PFC_FUNCTION(usb2),
5123 		SH_PFC_FUNCTION(usb2_ch3),
5124 		SH_PFC_FUNCTION(usb30),
5125 		SH_PFC_FUNCTION(vin4),
5126 		SH_PFC_FUNCTION(vin5),
5127 	},
5128 #ifdef CONFIG_PINCTRL_PFC_R8A77951
5129 	.automotive = {
5130 		SH_PFC_FUNCTION(drif0),
5131 		SH_PFC_FUNCTION(drif1),
5132 		SH_PFC_FUNCTION(drif2),
5133 		SH_PFC_FUNCTION(drif3),
5134 		SH_PFC_FUNCTION(mlb_3pin),
5135 	}
5136 #endif /* CONFIG_PINCTRL_PFC_R8A77951 */
5137 };
5138 
5139 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5140 #define F_(x, y)	FN_##y
5141 #define FM(x)		FN_##x
5142 	{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
5143 			     GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5144 				   1, 1, 1, 1, 1),
5145 			     GROUP(
5146 		/* GP0_31_16 RESERVED */
5147 		GP_0_15_FN,	GPSR0_15,
5148 		GP_0_14_FN,	GPSR0_14,
5149 		GP_0_13_FN,	GPSR0_13,
5150 		GP_0_12_FN,	GPSR0_12,
5151 		GP_0_11_FN,	GPSR0_11,
5152 		GP_0_10_FN,	GPSR0_10,
5153 		GP_0_9_FN,	GPSR0_9,
5154 		GP_0_8_FN,	GPSR0_8,
5155 		GP_0_7_FN,	GPSR0_7,
5156 		GP_0_6_FN,	GPSR0_6,
5157 		GP_0_5_FN,	GPSR0_5,
5158 		GP_0_4_FN,	GPSR0_4,
5159 		GP_0_3_FN,	GPSR0_3,
5160 		GP_0_2_FN,	GPSR0_2,
5161 		GP_0_1_FN,	GPSR0_1,
5162 		GP_0_0_FN,	GPSR0_0, ))
5163 	},
5164 	{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
5165 		0, 0,
5166 		0, 0,
5167 		0, 0,
5168 		GP_1_28_FN,	GPSR1_28,
5169 		GP_1_27_FN,	GPSR1_27,
5170 		GP_1_26_FN,	GPSR1_26,
5171 		GP_1_25_FN,	GPSR1_25,
5172 		GP_1_24_FN,	GPSR1_24,
5173 		GP_1_23_FN,	GPSR1_23,
5174 		GP_1_22_FN,	GPSR1_22,
5175 		GP_1_21_FN,	GPSR1_21,
5176 		GP_1_20_FN,	GPSR1_20,
5177 		GP_1_19_FN,	GPSR1_19,
5178 		GP_1_18_FN,	GPSR1_18,
5179 		GP_1_17_FN,	GPSR1_17,
5180 		GP_1_16_FN,	GPSR1_16,
5181 		GP_1_15_FN,	GPSR1_15,
5182 		GP_1_14_FN,	GPSR1_14,
5183 		GP_1_13_FN,	GPSR1_13,
5184 		GP_1_12_FN,	GPSR1_12,
5185 		GP_1_11_FN,	GPSR1_11,
5186 		GP_1_10_FN,	GPSR1_10,
5187 		GP_1_9_FN,	GPSR1_9,
5188 		GP_1_8_FN,	GPSR1_8,
5189 		GP_1_7_FN,	GPSR1_7,
5190 		GP_1_6_FN,	GPSR1_6,
5191 		GP_1_5_FN,	GPSR1_5,
5192 		GP_1_4_FN,	GPSR1_4,
5193 		GP_1_3_FN,	GPSR1_3,
5194 		GP_1_2_FN,	GPSR1_2,
5195 		GP_1_1_FN,	GPSR1_1,
5196 		GP_1_0_FN,	GPSR1_0, ))
5197 	},
5198 	{ PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
5199 			     GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5200 				   1, 1, 1, 1),
5201 			     GROUP(
5202 		/* GP2_31_15 RESERVED */
5203 		GP_2_14_FN,	GPSR2_14,
5204 		GP_2_13_FN,	GPSR2_13,
5205 		GP_2_12_FN,	GPSR2_12,
5206 		GP_2_11_FN,	GPSR2_11,
5207 		GP_2_10_FN,	GPSR2_10,
5208 		GP_2_9_FN,	GPSR2_9,
5209 		GP_2_8_FN,	GPSR2_8,
5210 		GP_2_7_FN,	GPSR2_7,
5211 		GP_2_6_FN,	GPSR2_6,
5212 		GP_2_5_FN,	GPSR2_5,
5213 		GP_2_4_FN,	GPSR2_4,
5214 		GP_2_3_FN,	GPSR2_3,
5215 		GP_2_2_FN,	GPSR2_2,
5216 		GP_2_1_FN,	GPSR2_1,
5217 		GP_2_0_FN,	GPSR2_0, ))
5218 	},
5219 	{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
5220 			     GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5221 				   1, 1, 1, 1, 1),
5222 			     GROUP(
5223 		/* GP3_31_16 RESERVED */
5224 		GP_3_15_FN,	GPSR3_15,
5225 		GP_3_14_FN,	GPSR3_14,
5226 		GP_3_13_FN,	GPSR3_13,
5227 		GP_3_12_FN,	GPSR3_12,
5228 		GP_3_11_FN,	GPSR3_11,
5229 		GP_3_10_FN,	GPSR3_10,
5230 		GP_3_9_FN,	GPSR3_9,
5231 		GP_3_8_FN,	GPSR3_8,
5232 		GP_3_7_FN,	GPSR3_7,
5233 		GP_3_6_FN,	GPSR3_6,
5234 		GP_3_5_FN,	GPSR3_5,
5235 		GP_3_4_FN,	GPSR3_4,
5236 		GP_3_3_FN,	GPSR3_3,
5237 		GP_3_2_FN,	GPSR3_2,
5238 		GP_3_1_FN,	GPSR3_1,
5239 		GP_3_0_FN,	GPSR3_0, ))
5240 	},
5241 	{ PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
5242 			     GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5243 				   1, 1, 1, 1, 1, 1, 1),
5244 			     GROUP(
5245 		/* GP4_31_18 RESERVED */
5246 		GP_4_17_FN,	GPSR4_17,
5247 		GP_4_16_FN,	GPSR4_16,
5248 		GP_4_15_FN,	GPSR4_15,
5249 		GP_4_14_FN,	GPSR4_14,
5250 		GP_4_13_FN,	GPSR4_13,
5251 		GP_4_12_FN,	GPSR4_12,
5252 		GP_4_11_FN,	GPSR4_11,
5253 		GP_4_10_FN,	GPSR4_10,
5254 		GP_4_9_FN,	GPSR4_9,
5255 		GP_4_8_FN,	GPSR4_8,
5256 		GP_4_7_FN,	GPSR4_7,
5257 		GP_4_6_FN,	GPSR4_6,
5258 		GP_4_5_FN,	GPSR4_5,
5259 		GP_4_4_FN,	GPSR4_4,
5260 		GP_4_3_FN,	GPSR4_3,
5261 		GP_4_2_FN,	GPSR4_2,
5262 		GP_4_1_FN,	GPSR4_1,
5263 		GP_4_0_FN,	GPSR4_0, ))
5264 	},
5265 	{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
5266 		0, 0,
5267 		0, 0,
5268 		0, 0,
5269 		0, 0,
5270 		0, 0,
5271 		0, 0,
5272 		GP_5_25_FN,	GPSR5_25,
5273 		GP_5_24_FN,	GPSR5_24,
5274 		GP_5_23_FN,	GPSR5_23,
5275 		GP_5_22_FN,	GPSR5_22,
5276 		GP_5_21_FN,	GPSR5_21,
5277 		GP_5_20_FN,	GPSR5_20,
5278 		GP_5_19_FN,	GPSR5_19,
5279 		GP_5_18_FN,	GPSR5_18,
5280 		GP_5_17_FN,	GPSR5_17,
5281 		GP_5_16_FN,	GPSR5_16,
5282 		GP_5_15_FN,	GPSR5_15,
5283 		GP_5_14_FN,	GPSR5_14,
5284 		GP_5_13_FN,	GPSR5_13,
5285 		GP_5_12_FN,	GPSR5_12,
5286 		GP_5_11_FN,	GPSR5_11,
5287 		GP_5_10_FN,	GPSR5_10,
5288 		GP_5_9_FN,	GPSR5_9,
5289 		GP_5_8_FN,	GPSR5_8,
5290 		GP_5_7_FN,	GPSR5_7,
5291 		GP_5_6_FN,	GPSR5_6,
5292 		GP_5_5_FN,	GPSR5_5,
5293 		GP_5_4_FN,	GPSR5_4,
5294 		GP_5_3_FN,	GPSR5_3,
5295 		GP_5_2_FN,	GPSR5_2,
5296 		GP_5_1_FN,	GPSR5_1,
5297 		GP_5_0_FN,	GPSR5_0, ))
5298 	},
5299 	{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
5300 		GP_6_31_FN,	GPSR6_31,
5301 		GP_6_30_FN,	GPSR6_30,
5302 		GP_6_29_FN,	GPSR6_29,
5303 		GP_6_28_FN,	GPSR6_28,
5304 		GP_6_27_FN,	GPSR6_27,
5305 		GP_6_26_FN,	GPSR6_26,
5306 		GP_6_25_FN,	GPSR6_25,
5307 		GP_6_24_FN,	GPSR6_24,
5308 		GP_6_23_FN,	GPSR6_23,
5309 		GP_6_22_FN,	GPSR6_22,
5310 		GP_6_21_FN,	GPSR6_21,
5311 		GP_6_20_FN,	GPSR6_20,
5312 		GP_6_19_FN,	GPSR6_19,
5313 		GP_6_18_FN,	GPSR6_18,
5314 		GP_6_17_FN,	GPSR6_17,
5315 		GP_6_16_FN,	GPSR6_16,
5316 		GP_6_15_FN,	GPSR6_15,
5317 		GP_6_14_FN,	GPSR6_14,
5318 		GP_6_13_FN,	GPSR6_13,
5319 		GP_6_12_FN,	GPSR6_12,
5320 		GP_6_11_FN,	GPSR6_11,
5321 		GP_6_10_FN,	GPSR6_10,
5322 		GP_6_9_FN,	GPSR6_9,
5323 		GP_6_8_FN,	GPSR6_8,
5324 		GP_6_7_FN,	GPSR6_7,
5325 		GP_6_6_FN,	GPSR6_6,
5326 		GP_6_5_FN,	GPSR6_5,
5327 		GP_6_4_FN,	GPSR6_4,
5328 		GP_6_3_FN,	GPSR6_3,
5329 		GP_6_2_FN,	GPSR6_2,
5330 		GP_6_1_FN,	GPSR6_1,
5331 		GP_6_0_FN,	GPSR6_0, ))
5332 	},
5333 	{ PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
5334 			     GROUP(-28, 1, 1, 1, 1),
5335 			     GROUP(
5336 		/* GP7_31_4 RESERVED */
5337 		GP_7_3_FN, GPSR7_3,
5338 		GP_7_2_FN, GPSR7_2,
5339 		GP_7_1_FN, GPSR7_1,
5340 		GP_7_0_FN, GPSR7_0, ))
5341 	},
5342 #undef F_
5343 #undef FM
5344 
5345 #define F_(x, y)	x,
5346 #define FM(x)		FN_##x,
5347 	{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5348 		IP0_31_28
5349 		IP0_27_24
5350 		IP0_23_20
5351 		IP0_19_16
5352 		IP0_15_12
5353 		IP0_11_8
5354 		IP0_7_4
5355 		IP0_3_0 ))
5356 	},
5357 	{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
5358 		IP1_31_28
5359 		IP1_27_24
5360 		IP1_23_20
5361 		IP1_19_16
5362 		IP1_15_12
5363 		IP1_11_8
5364 		IP1_7_4
5365 		IP1_3_0 ))
5366 	},
5367 	{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
5368 		IP2_31_28
5369 		IP2_27_24
5370 		IP2_23_20
5371 		IP2_19_16
5372 		IP2_15_12
5373 		IP2_11_8
5374 		IP2_7_4
5375 		IP2_3_0 ))
5376 	},
5377 	{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
5378 		IP3_31_28
5379 		IP3_27_24
5380 		IP3_23_20
5381 		IP3_19_16
5382 		IP3_15_12
5383 		IP3_11_8
5384 		IP3_7_4
5385 		IP3_3_0 ))
5386 	},
5387 	{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
5388 		IP4_31_28
5389 		IP4_27_24
5390 		IP4_23_20
5391 		IP4_19_16
5392 		IP4_15_12
5393 		IP4_11_8
5394 		IP4_7_4
5395 		IP4_3_0 ))
5396 	},
5397 	{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
5398 		IP5_31_28
5399 		IP5_27_24
5400 		IP5_23_20
5401 		IP5_19_16
5402 		IP5_15_12
5403 		IP5_11_8
5404 		IP5_7_4
5405 		IP5_3_0 ))
5406 	},
5407 	{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
5408 		IP6_31_28
5409 		IP6_27_24
5410 		IP6_23_20
5411 		IP6_19_16
5412 		IP6_15_12
5413 		IP6_11_8
5414 		IP6_7_4
5415 		IP6_3_0 ))
5416 	},
5417 	{ PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32,
5418 			     GROUP(4, 4, 4, 4, -4, 4, 4, 4),
5419 			     GROUP(
5420 		IP7_31_28
5421 		IP7_27_24
5422 		IP7_23_20
5423 		IP7_19_16
5424 		/* IP7_15_12 RESERVED */
5425 		IP7_11_8
5426 		IP7_7_4
5427 		IP7_3_0 ))
5428 	},
5429 	{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
5430 		IP8_31_28
5431 		IP8_27_24
5432 		IP8_23_20
5433 		IP8_19_16
5434 		IP8_15_12
5435 		IP8_11_8
5436 		IP8_7_4
5437 		IP8_3_0 ))
5438 	},
5439 	{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
5440 		IP9_31_28
5441 		IP9_27_24
5442 		IP9_23_20
5443 		IP9_19_16
5444 		IP9_15_12
5445 		IP9_11_8
5446 		IP9_7_4
5447 		IP9_3_0 ))
5448 	},
5449 	{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
5450 		IP10_31_28
5451 		IP10_27_24
5452 		IP10_23_20
5453 		IP10_19_16
5454 		IP10_15_12
5455 		IP10_11_8
5456 		IP10_7_4
5457 		IP10_3_0 ))
5458 	},
5459 	{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
5460 		IP11_31_28
5461 		IP11_27_24
5462 		IP11_23_20
5463 		IP11_19_16
5464 		IP11_15_12
5465 		IP11_11_8
5466 		IP11_7_4
5467 		IP11_3_0 ))
5468 	},
5469 	{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
5470 		IP12_31_28
5471 		IP12_27_24
5472 		IP12_23_20
5473 		IP12_19_16
5474 		IP12_15_12
5475 		IP12_11_8
5476 		IP12_7_4
5477 		IP12_3_0 ))
5478 	},
5479 	{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
5480 		IP13_31_28
5481 		IP13_27_24
5482 		IP13_23_20
5483 		IP13_19_16
5484 		IP13_15_12
5485 		IP13_11_8
5486 		IP13_7_4
5487 		IP13_3_0 ))
5488 	},
5489 	{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
5490 		IP14_31_28
5491 		IP14_27_24
5492 		IP14_23_20
5493 		IP14_19_16
5494 		IP14_15_12
5495 		IP14_11_8
5496 		IP14_7_4
5497 		IP14_3_0 ))
5498 	},
5499 	{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
5500 		IP15_31_28
5501 		IP15_27_24
5502 		IP15_23_20
5503 		IP15_19_16
5504 		IP15_15_12
5505 		IP15_11_8
5506 		IP15_7_4
5507 		IP15_3_0 ))
5508 	},
5509 	{ PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
5510 		IP16_31_28
5511 		IP16_27_24
5512 		IP16_23_20
5513 		IP16_19_16
5514 		IP16_15_12
5515 		IP16_11_8
5516 		IP16_7_4
5517 		IP16_3_0 ))
5518 	},
5519 	{ PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
5520 		IP17_31_28
5521 		IP17_27_24
5522 		IP17_23_20
5523 		IP17_19_16
5524 		IP17_15_12
5525 		IP17_11_8
5526 		IP17_7_4
5527 		IP17_3_0 ))
5528 	},
5529 	{ PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32,
5530 			     GROUP(-24, 4, 4),
5531 			     GROUP(
5532 		/* IP18_31_8 RESERVED */
5533 		IP18_7_4
5534 		IP18_3_0 ))
5535 	},
5536 #undef F_
5537 #undef FM
5538 
5539 #define F_(x, y)	x,
5540 #define FM(x)		FN_##x,
5541 	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5542 			     GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2,
5543 				   1, 1, 1, 2, 2, 1, 2, -3),
5544 			     GROUP(
5545 		MOD_SEL0_31_30_29
5546 		MOD_SEL0_28_27
5547 		MOD_SEL0_26_25_24
5548 		MOD_SEL0_23
5549 		MOD_SEL0_22
5550 		MOD_SEL0_21
5551 		MOD_SEL0_20
5552 		MOD_SEL0_19
5553 		MOD_SEL0_18_17
5554 		MOD_SEL0_16
5555 		/* RESERVED 15 */
5556 		MOD_SEL0_14_13
5557 		MOD_SEL0_12
5558 		MOD_SEL0_11
5559 		MOD_SEL0_10
5560 		MOD_SEL0_9_8
5561 		MOD_SEL0_7_6
5562 		MOD_SEL0_5
5563 		MOD_SEL0_4_3
5564 		/* RESERVED 2, 1, 0 */ ))
5565 	},
5566 	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5567 			     GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5568 				   1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
5569 			     GROUP(
5570 		MOD_SEL1_31_30
5571 		MOD_SEL1_29_28_27
5572 		MOD_SEL1_26
5573 		MOD_SEL1_25_24
5574 		MOD_SEL1_23_22_21
5575 		MOD_SEL1_20
5576 		MOD_SEL1_19
5577 		MOD_SEL1_18_17
5578 		MOD_SEL1_16
5579 		MOD_SEL1_15_14
5580 		MOD_SEL1_13
5581 		MOD_SEL1_12
5582 		MOD_SEL1_11
5583 		MOD_SEL1_10
5584 		MOD_SEL1_9
5585 		/* RESERVED 8, 7 */
5586 		MOD_SEL1_6
5587 		MOD_SEL1_5
5588 		MOD_SEL1_4
5589 		MOD_SEL1_3
5590 		MOD_SEL1_2
5591 		MOD_SEL1_1
5592 		MOD_SEL1_0 ))
5593 	},
5594 	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5595 			     GROUP(1, 1, 1, 2, 1, 3, -1, 1, 1, 1, 1, 1,
5596 				   -16, 1),
5597 			     GROUP(
5598 		MOD_SEL2_31
5599 		MOD_SEL2_30
5600 		MOD_SEL2_29
5601 		MOD_SEL2_28_27
5602 		MOD_SEL2_26
5603 		MOD_SEL2_25_24_23
5604 		/* RESERVED 22 */
5605 		MOD_SEL2_21
5606 		MOD_SEL2_20
5607 		MOD_SEL2_19
5608 		MOD_SEL2_18
5609 		MOD_SEL2_17
5610 		/* RESERVED 16-1 */
5611 		MOD_SEL2_0 ))
5612 	},
5613 	{ },
5614 };
5615 
5616 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5617 	{ PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5618 		{ PIN_QSPI0_SPCLK,    28, 2 },	/* QSPI0_SPCLK */
5619 		{ PIN_QSPI0_MOSI_IO0, 24, 2 },	/* QSPI0_MOSI_IO0 */
5620 		{ PIN_QSPI0_MISO_IO1, 20, 2 },	/* QSPI0_MISO_IO1 */
5621 		{ PIN_QSPI0_IO2,      16, 2 },	/* QSPI0_IO2 */
5622 		{ PIN_QSPI0_IO3,      12, 2 },	/* QSPI0_IO3 */
5623 		{ PIN_QSPI0_SSL,       8, 2 },	/* QSPI0_SSL */
5624 		{ PIN_QSPI1_SPCLK,     4, 2 },	/* QSPI1_SPCLK */
5625 		{ PIN_QSPI1_MOSI_IO0,  0, 2 },	/* QSPI1_MOSI_IO0 */
5626 	} },
5627 	{ PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5628 		{ PIN_QSPI1_MISO_IO1, 28, 2 },	/* QSPI1_MISO_IO1 */
5629 		{ PIN_QSPI1_IO2,      24, 2 },	/* QSPI1_IO2 */
5630 		{ PIN_QSPI1_IO3,      20, 2 },	/* QSPI1_IO3 */
5631 		{ PIN_QSPI1_SSL,      16, 2 },	/* QSPI1_SSL */
5632 		{ PIN_RPC_INT_N,      12, 2 },	/* RPC_INT# */
5633 		{ PIN_RPC_WP_N,        8, 2 },	/* RPC_WP# */
5634 		{ PIN_RPC_RESET_N,     4, 2 },	/* RPC_RESET# */
5635 		{ PIN_AVB_RX_CTL,      0, 3 },	/* AVB_RX_CTL */
5636 	} },
5637 	{ PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5638 		{ PIN_AVB_RXC,        28, 3 },	/* AVB_RXC */
5639 		{ PIN_AVB_RD0,        24, 3 },	/* AVB_RD0 */
5640 		{ PIN_AVB_RD1,        20, 3 },	/* AVB_RD1 */
5641 		{ PIN_AVB_RD2,        16, 3 },	/* AVB_RD2 */
5642 		{ PIN_AVB_RD3,        12, 3 },	/* AVB_RD3 */
5643 		{ PIN_AVB_TX_CTL,      8, 3 },	/* AVB_TX_CTL */
5644 		{ PIN_AVB_TXC,         4, 3 },	/* AVB_TXC */
5645 		{ PIN_AVB_TD0,         0, 3 },	/* AVB_TD0 */
5646 	} },
5647 	{ PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5648 		{ PIN_AVB_TD1,        28, 3 },	/* AVB_TD1 */
5649 		{ PIN_AVB_TD2,        24, 3 },	/* AVB_TD2 */
5650 		{ PIN_AVB_TD3,        20, 3 },	/* AVB_TD3 */
5651 		{ PIN_AVB_TXCREFCLK,  16, 3 },	/* AVB_TXCREFCLK */
5652 		{ PIN_AVB_MDIO,       12, 3 },	/* AVB_MDIO */
5653 		{ RCAR_GP_PIN(2,  9),  8, 3 },	/* AVB_MDC */
5654 		{ RCAR_GP_PIN(2, 10),  4, 3 },	/* AVB_MAGIC */
5655 		{ RCAR_GP_PIN(2, 11),  0, 3 },	/* AVB_PHY_INT */
5656 	} },
5657 	{ PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5658 		{ RCAR_GP_PIN(2, 12), 28, 3 },	/* AVB_LINK */
5659 		{ RCAR_GP_PIN(2, 13), 24, 3 },	/* AVB_AVTP_MATCH */
5660 		{ RCAR_GP_PIN(2, 14), 20, 3 },	/* AVB_AVTP_CAPTURE */
5661 		{ RCAR_GP_PIN(2,  0), 16, 3 },	/* IRQ0 */
5662 		{ RCAR_GP_PIN(2,  1), 12, 3 },	/* IRQ1 */
5663 		{ RCAR_GP_PIN(2,  2),  8, 3 },	/* IRQ2 */
5664 		{ RCAR_GP_PIN(2,  3),  4, 3 },	/* IRQ3 */
5665 		{ RCAR_GP_PIN(2,  4),  0, 3 },	/* IRQ4 */
5666 	} },
5667 	{ PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5668 		{ RCAR_GP_PIN(2,  5), 28, 3 },	/* IRQ5 */
5669 		{ RCAR_GP_PIN(2,  6), 24, 3 },	/* PWM0 */
5670 		{ RCAR_GP_PIN(2,  7), 20, 3 },	/* PWM1 */
5671 		{ RCAR_GP_PIN(2,  8), 16, 3 },	/* PWM2 */
5672 		{ RCAR_GP_PIN(1,  0), 12, 3 },	/* A0 */
5673 		{ RCAR_GP_PIN(1,  1),  8, 3 },	/* A1 */
5674 		{ RCAR_GP_PIN(1,  2),  4, 3 },	/* A2 */
5675 		{ RCAR_GP_PIN(1,  3),  0, 3 },	/* A3 */
5676 	} },
5677 	{ PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5678 		{ RCAR_GP_PIN(1,  4), 28, 3 },	/* A4 */
5679 		{ RCAR_GP_PIN(1,  5), 24, 3 },	/* A5 */
5680 		{ RCAR_GP_PIN(1,  6), 20, 3 },	/* A6 */
5681 		{ RCAR_GP_PIN(1,  7), 16, 3 },	/* A7 */
5682 		{ RCAR_GP_PIN(1,  8), 12, 3 },	/* A8 */
5683 		{ RCAR_GP_PIN(1,  9),  8, 3 },	/* A9 */
5684 		{ RCAR_GP_PIN(1, 10),  4, 3 },	/* A10 */
5685 		{ RCAR_GP_PIN(1, 11),  0, 3 },	/* A11 */
5686 	} },
5687 	{ PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5688 		{ RCAR_GP_PIN(1, 12), 28, 3 },	/* A12 */
5689 		{ RCAR_GP_PIN(1, 13), 24, 3 },	/* A13 */
5690 		{ RCAR_GP_PIN(1, 14), 20, 3 },	/* A14 */
5691 		{ RCAR_GP_PIN(1, 15), 16, 3 },	/* A15 */
5692 		{ RCAR_GP_PIN(1, 16), 12, 3 },	/* A16 */
5693 		{ RCAR_GP_PIN(1, 17),  8, 3 },	/* A17 */
5694 		{ RCAR_GP_PIN(1, 18),  4, 3 },	/* A18 */
5695 		{ RCAR_GP_PIN(1, 19),  0, 3 },	/* A19 */
5696 	} },
5697 	{ PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5698 		{ RCAR_GP_PIN(1, 28), 28, 3 },	/* CLKOUT */
5699 		{ RCAR_GP_PIN(1, 20), 24, 3 },	/* CS0 */
5700 		{ RCAR_GP_PIN(1, 21), 20, 3 },	/* CS1_A26 */
5701 		{ RCAR_GP_PIN(1, 22), 16, 3 },	/* BS */
5702 		{ RCAR_GP_PIN(1, 23), 12, 3 },	/* RD */
5703 		{ RCAR_GP_PIN(1, 24),  8, 3 },	/* RD_WR */
5704 		{ RCAR_GP_PIN(1, 25),  4, 3 },	/* WE0 */
5705 		{ RCAR_GP_PIN(1, 26),  0, 3 },	/* WE1 */
5706 	} },
5707 	{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5708 		{ RCAR_GP_PIN(1, 27), 28, 3 },	/* EX_WAIT0 */
5709 		{ PIN_PRESETOUT_N,    24, 3 },	/* PRESETOUT# */
5710 		{ RCAR_GP_PIN(0,  0), 20, 3 },	/* D0 */
5711 		{ RCAR_GP_PIN(0,  1), 16, 3 },	/* D1 */
5712 		{ RCAR_GP_PIN(0,  2), 12, 3 },	/* D2 */
5713 		{ RCAR_GP_PIN(0,  3),  8, 3 },	/* D3 */
5714 		{ RCAR_GP_PIN(0,  4),  4, 3 },	/* D4 */
5715 		{ RCAR_GP_PIN(0,  5),  0, 3 },	/* D5 */
5716 	} },
5717 	{ PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5718 		{ RCAR_GP_PIN(0,  6), 28, 3 },	/* D6 */
5719 		{ RCAR_GP_PIN(0,  7), 24, 3 },	/* D7 */
5720 		{ RCAR_GP_PIN(0,  8), 20, 3 },	/* D8 */
5721 		{ RCAR_GP_PIN(0,  9), 16, 3 },	/* D9 */
5722 		{ RCAR_GP_PIN(0, 10), 12, 3 },	/* D10 */
5723 		{ RCAR_GP_PIN(0, 11),  8, 3 },	/* D11 */
5724 		{ RCAR_GP_PIN(0, 12),  4, 3 },	/* D12 */
5725 		{ RCAR_GP_PIN(0, 13),  0, 3 },	/* D13 */
5726 	} },
5727 	{ PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5728 		{ RCAR_GP_PIN(0, 14), 28, 3 },	/* D14 */
5729 		{ RCAR_GP_PIN(0, 15), 24, 3 },	/* D15 */
5730 		{ RCAR_GP_PIN(7,  0), 20, 3 },	/* AVS1 */
5731 		{ RCAR_GP_PIN(7,  1), 16, 3 },	/* AVS2 */
5732 		{ RCAR_GP_PIN(7,  2), 12, 3 },	/* GP7_02 */
5733 		{ RCAR_GP_PIN(7,  3),  8, 3 },	/* GP7_03 */
5734 		{ PIN_DU_DOTCLKIN0,    4, 2 },	/* DU_DOTCLKIN0 */
5735 		{ PIN_DU_DOTCLKIN1,    0, 2 },	/* DU_DOTCLKIN1 */
5736 	} },
5737 	{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5738 #ifdef CONFIG_PINCTRL_PFC_R8A77951
5739 		{ PIN_DU_DOTCLKIN2,   28, 2 },	/* DU_DOTCLKIN2 */
5740 #endif
5741 		{ PIN_DU_DOTCLKIN3,   24, 2 },	/* DU_DOTCLKIN3 */
5742 		{ PIN_FSCLKST_N,      20, 2 },	/* FSCLKST# */
5743 		{ PIN_TMS,             4, 2 },	/* TMS */
5744 	} },
5745 	{ PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5746 		{ PIN_TDO,            28, 2 },	/* TDO */
5747 		{ PIN_ASEBRK,         24, 2 },	/* ASEBRK */
5748 		{ RCAR_GP_PIN(3,  0), 20, 3 },	/* SD0_CLK */
5749 		{ RCAR_GP_PIN(3,  1), 16, 3 },	/* SD0_CMD */
5750 		{ RCAR_GP_PIN(3,  2), 12, 3 },	/* SD0_DAT0 */
5751 		{ RCAR_GP_PIN(3,  3),  8, 3 },	/* SD0_DAT1 */
5752 		{ RCAR_GP_PIN(3,  4),  4, 3 },	/* SD0_DAT2 */
5753 		{ RCAR_GP_PIN(3,  5),  0, 3 },	/* SD0_DAT3 */
5754 	} },
5755 	{ PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5756 		{ RCAR_GP_PIN(3,  6), 28, 3 },	/* SD1_CLK */
5757 		{ RCAR_GP_PIN(3,  7), 24, 3 },	/* SD1_CMD */
5758 		{ RCAR_GP_PIN(3,  8), 20, 3 },	/* SD1_DAT0 */
5759 		{ RCAR_GP_PIN(3,  9), 16, 3 },	/* SD1_DAT1 */
5760 		{ RCAR_GP_PIN(3, 10), 12, 3 },	/* SD1_DAT2 */
5761 		{ RCAR_GP_PIN(3, 11),  8, 3 },	/* SD1_DAT3 */
5762 		{ RCAR_GP_PIN(4,  0),  4, 3 },	/* SD2_CLK */
5763 		{ RCAR_GP_PIN(4,  1),  0, 3 },	/* SD2_CMD */
5764 	} },
5765 	{ PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5766 		{ RCAR_GP_PIN(4,  2), 28, 3 },	/* SD2_DAT0 */
5767 		{ RCAR_GP_PIN(4,  3), 24, 3 },	/* SD2_DAT1 */
5768 		{ RCAR_GP_PIN(4,  4), 20, 3 },	/* SD2_DAT2 */
5769 		{ RCAR_GP_PIN(4,  5), 16, 3 },	/* SD2_DAT3 */
5770 		{ RCAR_GP_PIN(4,  6), 12, 3 },	/* SD2_DS */
5771 		{ RCAR_GP_PIN(4,  7),  8, 3 },	/* SD3_CLK */
5772 		{ RCAR_GP_PIN(4,  8),  4, 3 },	/* SD3_CMD */
5773 		{ RCAR_GP_PIN(4,  9),  0, 3 },	/* SD3_DAT0 */
5774 	} },
5775 	{ PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5776 		{ RCAR_GP_PIN(4, 10), 28, 3 },	/* SD3_DAT1 */
5777 		{ RCAR_GP_PIN(4, 11), 24, 3 },	/* SD3_DAT2 */
5778 		{ RCAR_GP_PIN(4, 12), 20, 3 },	/* SD3_DAT3 */
5779 		{ RCAR_GP_PIN(4, 13), 16, 3 },	/* SD3_DAT4 */
5780 		{ RCAR_GP_PIN(4, 14), 12, 3 },	/* SD3_DAT5 */
5781 		{ RCAR_GP_PIN(4, 15),  8, 3 },	/* SD3_DAT6 */
5782 		{ RCAR_GP_PIN(4, 16),  4, 3 },	/* SD3_DAT7 */
5783 		{ RCAR_GP_PIN(4, 17),  0, 3 },	/* SD3_DS */
5784 	} },
5785 	{ PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5786 		{ RCAR_GP_PIN(3, 12), 28, 3 },	/* SD0_CD */
5787 		{ RCAR_GP_PIN(3, 13), 24, 3 },	/* SD0_WP */
5788 		{ RCAR_GP_PIN(3, 14), 20, 3 },	/* SD1_CD */
5789 		{ RCAR_GP_PIN(3, 15), 16, 3 },	/* SD1_WP */
5790 		{ RCAR_GP_PIN(5,  0), 12, 3 },	/* SCK0 */
5791 		{ RCAR_GP_PIN(5,  1),  8, 3 },	/* RX0 */
5792 		{ RCAR_GP_PIN(5,  2),  4, 3 },	/* TX0 */
5793 		{ RCAR_GP_PIN(5,  3),  0, 3 },	/* CTS0 */
5794 	} },
5795 	{ PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5796 		{ RCAR_GP_PIN(5,  4), 28, 3 },	/* RTS0 */
5797 		{ RCAR_GP_PIN(5,  5), 24, 3 },	/* RX1 */
5798 		{ RCAR_GP_PIN(5,  6), 20, 3 },	/* TX1 */
5799 		{ RCAR_GP_PIN(5,  7), 16, 3 },	/* CTS1 */
5800 		{ RCAR_GP_PIN(5,  8), 12, 3 },	/* RTS1 */
5801 		{ RCAR_GP_PIN(5,  9),  8, 3 },	/* SCK2 */
5802 		{ RCAR_GP_PIN(5, 10),  4, 3 },	/* TX2 */
5803 		{ RCAR_GP_PIN(5, 11),  0, 3 },	/* RX2 */
5804 	} },
5805 	{ PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5806 		{ RCAR_GP_PIN(5, 12), 28, 3 },	/* HSCK0 */
5807 		{ RCAR_GP_PIN(5, 13), 24, 3 },	/* HRX0 */
5808 		{ RCAR_GP_PIN(5, 14), 20, 3 },	/* HTX0 */
5809 		{ RCAR_GP_PIN(5, 15), 16, 3 },	/* HCTS0 */
5810 		{ RCAR_GP_PIN(5, 16), 12, 3 },	/* HRTS0 */
5811 		{ RCAR_GP_PIN(5, 17),  8, 3 },	/* MSIOF0_SCK */
5812 		{ RCAR_GP_PIN(5, 18),  4, 3 },	/* MSIOF0_SYNC */
5813 		{ RCAR_GP_PIN(5, 19),  0, 3 },	/* MSIOF0_SS1 */
5814 	} },
5815 	{ PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5816 		{ RCAR_GP_PIN(5, 20), 28, 3 },	/* MSIOF0_TXD */
5817 		{ RCAR_GP_PIN(5, 21), 24, 3 },	/* MSIOF0_SS2 */
5818 		{ RCAR_GP_PIN(5, 22), 20, 3 },	/* MSIOF0_RXD */
5819 		{ RCAR_GP_PIN(5, 23), 16, 3 },	/* MLB_CLK */
5820 		{ RCAR_GP_PIN(5, 24), 12, 3 },	/* MLB_SIG */
5821 		{ RCAR_GP_PIN(5, 25),  8, 3 },	/* MLB_DAT */
5822 		{ PIN_MLB_REF,         4, 3 },	/* MLB_REF */
5823 		{ RCAR_GP_PIN(6,  0),  0, 3 },	/* SSI_SCK01239 */
5824 	} },
5825 	{ PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5826 		{ RCAR_GP_PIN(6,  1), 28, 3 },	/* SSI_WS01239 */
5827 		{ RCAR_GP_PIN(6,  2), 24, 3 },	/* SSI_SDATA0 */
5828 		{ RCAR_GP_PIN(6,  3), 20, 3 },	/* SSI_SDATA1 */
5829 		{ RCAR_GP_PIN(6,  4), 16, 3 },	/* SSI_SDATA2 */
5830 		{ RCAR_GP_PIN(6,  5), 12, 3 },	/* SSI_SCK349 */
5831 		{ RCAR_GP_PIN(6,  6),  8, 3 },	/* SSI_WS349 */
5832 		{ RCAR_GP_PIN(6,  7),  4, 3 },	/* SSI_SDATA3 */
5833 		{ RCAR_GP_PIN(6,  8),  0, 3 },	/* SSI_SCK4 */
5834 	} },
5835 	{ PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5836 		{ RCAR_GP_PIN(6,  9), 28, 3 },	/* SSI_WS4 */
5837 		{ RCAR_GP_PIN(6, 10), 24, 3 },	/* SSI_SDATA4 */
5838 		{ RCAR_GP_PIN(6, 11), 20, 3 },	/* SSI_SCK5 */
5839 		{ RCAR_GP_PIN(6, 12), 16, 3 },	/* SSI_WS5 */
5840 		{ RCAR_GP_PIN(6, 13), 12, 3 },	/* SSI_SDATA5 */
5841 		{ RCAR_GP_PIN(6, 14),  8, 3 },	/* SSI_SCK6 */
5842 		{ RCAR_GP_PIN(6, 15),  4, 3 },	/* SSI_WS6 */
5843 		{ RCAR_GP_PIN(6, 16),  0, 3 },	/* SSI_SDATA6 */
5844 	} },
5845 	{ PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5846 		{ RCAR_GP_PIN(6, 17), 28, 3 },	/* SSI_SCK78 */
5847 		{ RCAR_GP_PIN(6, 18), 24, 3 },	/* SSI_WS78 */
5848 		{ RCAR_GP_PIN(6, 19), 20, 3 },	/* SSI_SDATA7 */
5849 		{ RCAR_GP_PIN(6, 20), 16, 3 },	/* SSI_SDATA8 */
5850 		{ RCAR_GP_PIN(6, 21), 12, 3 },	/* SSI_SDATA9 */
5851 		{ RCAR_GP_PIN(6, 22),  8, 3 },	/* AUDIO_CLKA */
5852 		{ RCAR_GP_PIN(6, 23),  4, 3 },	/* AUDIO_CLKB */
5853 		{ RCAR_GP_PIN(6, 24),  0, 3 },	/* USB0_PWEN */
5854 	} },
5855 	{ PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5856 		{ RCAR_GP_PIN(6, 25), 28, 3 },	/* USB0_OVC */
5857 		{ RCAR_GP_PIN(6, 26), 24, 3 },	/* USB1_PWEN */
5858 		{ RCAR_GP_PIN(6, 27), 20, 3 },	/* USB1_OVC */
5859 		{ RCAR_GP_PIN(6, 28), 16, 3 },	/* USB30_PWEN */
5860 		{ RCAR_GP_PIN(6, 29), 12, 3 },	/* USB30_OVC */
5861 		{ RCAR_GP_PIN(6, 30),  8, 3 },	/* GP6_30/USB2_CH3_PWEN */
5862 		{ RCAR_GP_PIN(6, 31),  4, 3 },	/* GP6_31/USB2_CH3_OVC */
5863 	} },
5864 	{ },
5865 };
5866 
5867 enum ioctrl_regs {
5868 	POCCTRL,
5869 	TDSELCTRL,
5870 };
5871 
5872 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5873 	[POCCTRL] = { 0xe6060380, },
5874 	[TDSELCTRL] = { 0xe60603c0, },
5875 	{ /* sentinel */ },
5876 };
5877 
5878 static int r8a77951_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
5879 {
5880 	int bit = -EINVAL;
5881 
5882 	*pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5883 
5884 	if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5885 		bit = pin & 0x1f;
5886 
5887 	if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5888 		bit = (pin & 0x1f) + 12;
5889 
5890 	return bit;
5891 }
5892 
5893 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5894 	{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5895 		[ 0] = PIN_QSPI0_SPCLK,		/* QSPI0_SPCLK */
5896 		[ 1] = PIN_QSPI0_MOSI_IO0,	/* QSPI0_MOSI_IO0 */
5897 		[ 2] = PIN_QSPI0_MISO_IO1,	/* QSPI0_MISO_IO1 */
5898 		[ 3] = PIN_QSPI0_IO2,		/* QSPI0_IO2 */
5899 		[ 4] = PIN_QSPI0_IO3,		/* QSPI0_IO3 */
5900 		[ 5] = PIN_QSPI0_SSL,		/* QSPI0_SSL */
5901 		[ 6] = PIN_QSPI1_SPCLK,		/* QSPI1_SPCLK */
5902 		[ 7] = PIN_QSPI1_MOSI_IO0,	/* QSPI1_MOSI_IO0 */
5903 		[ 8] = PIN_QSPI1_MISO_IO1,	/* QSPI1_MISO_IO1 */
5904 		[ 9] = PIN_QSPI1_IO2,		/* QSPI1_IO2 */
5905 		[10] = PIN_QSPI1_IO3,		/* QSPI1_IO3 */
5906 		[11] = PIN_QSPI1_SSL,		/* QSPI1_SSL */
5907 		[12] = PIN_RPC_INT_N,		/* RPC_INT# */
5908 		[13] = PIN_RPC_WP_N,		/* RPC_WP# */
5909 		[14] = PIN_RPC_RESET_N,		/* RPC_RESET# */
5910 		[15] = PIN_AVB_RX_CTL,		/* AVB_RX_CTL */
5911 		[16] = PIN_AVB_RXC,		/* AVB_RXC */
5912 		[17] = PIN_AVB_RD0,		/* AVB_RD0 */
5913 		[18] = PIN_AVB_RD1,		/* AVB_RD1 */
5914 		[19] = PIN_AVB_RD2,		/* AVB_RD2 */
5915 		[20] = PIN_AVB_RD3,		/* AVB_RD3 */
5916 		[21] = PIN_AVB_TX_CTL,		/* AVB_TX_CTL */
5917 		[22] = PIN_AVB_TXC,		/* AVB_TXC */
5918 		[23] = PIN_AVB_TD0,		/* AVB_TD0 */
5919 		[24] = PIN_AVB_TD1,		/* AVB_TD1 */
5920 		[25] = PIN_AVB_TD2,		/* AVB_TD2 */
5921 		[26] = PIN_AVB_TD3,		/* AVB_TD3 */
5922 		[27] = PIN_AVB_TXCREFCLK,	/* AVB_TXCREFCLK */
5923 		[28] = PIN_AVB_MDIO,		/* AVB_MDIO */
5924 		[29] = RCAR_GP_PIN(2,  9),	/* AVB_MDC */
5925 		[30] = RCAR_GP_PIN(2, 10),	/* AVB_MAGIC */
5926 		[31] = RCAR_GP_PIN(2, 11),	/* AVB_PHY_INT */
5927 	} },
5928 	{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5929 		[ 0] = RCAR_GP_PIN(2, 12),	/* AVB_LINK */
5930 		[ 1] = RCAR_GP_PIN(2, 13),	/* AVB_AVTP_MATCH_A */
5931 		[ 2] = RCAR_GP_PIN(2, 14),	/* AVB_AVTP_CAPTURE_A */
5932 		[ 3] = RCAR_GP_PIN(2,  0),	/* IRQ0 */
5933 		[ 4] = RCAR_GP_PIN(2,  1),	/* IRQ1 */
5934 		[ 5] = RCAR_GP_PIN(2,  2),	/* IRQ2 */
5935 		[ 6] = RCAR_GP_PIN(2,  3),	/* IRQ3 */
5936 		[ 7] = RCAR_GP_PIN(2,  4),	/* IRQ4 */
5937 		[ 8] = RCAR_GP_PIN(2,  5),	/* IRQ5 */
5938 		[ 9] = RCAR_GP_PIN(2,  6),	/* PWM0 */
5939 		[10] = RCAR_GP_PIN(2,  7),	/* PWM1_A */
5940 		[11] = RCAR_GP_PIN(2,  8),	/* PWM2_A */
5941 		[12] = RCAR_GP_PIN(1,  0),	/* A0 */
5942 		[13] = RCAR_GP_PIN(1,  1),	/* A1 */
5943 		[14] = RCAR_GP_PIN(1,  2),	/* A2 */
5944 		[15] = RCAR_GP_PIN(1,  3),	/* A3 */
5945 		[16] = RCAR_GP_PIN(1,  4),	/* A4 */
5946 		[17] = RCAR_GP_PIN(1,  5),	/* A5 */
5947 		[18] = RCAR_GP_PIN(1,  6),	/* A6 */
5948 		[19] = RCAR_GP_PIN(1,  7),	/* A7 */
5949 		[20] = RCAR_GP_PIN(1,  8),	/* A8 */
5950 		[21] = RCAR_GP_PIN(1,  9),	/* A9 */
5951 		[22] = RCAR_GP_PIN(1, 10),	/* A10 */
5952 		[23] = RCAR_GP_PIN(1, 11),	/* A11 */
5953 		[24] = RCAR_GP_PIN(1, 12),	/* A12 */
5954 		[25] = RCAR_GP_PIN(1, 13),	/* A13 */
5955 		[26] = RCAR_GP_PIN(1, 14),	/* A14 */
5956 		[27] = RCAR_GP_PIN(1, 15),	/* A15 */
5957 		[28] = RCAR_GP_PIN(1, 16),	/* A16 */
5958 		[29] = RCAR_GP_PIN(1, 17),	/* A17 */
5959 		[30] = RCAR_GP_PIN(1, 18),	/* A18 */
5960 		[31] = RCAR_GP_PIN(1, 19),	/* A19 */
5961 	} },
5962 	{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5963 		[ 0] = RCAR_GP_PIN(1, 28),	/* CLKOUT */
5964 		[ 1] = RCAR_GP_PIN(1, 20),	/* CS0_N */
5965 		[ 2] = RCAR_GP_PIN(1, 21),	/* CS1_N */
5966 		[ 3] = RCAR_GP_PIN(1, 22),	/* BS_N */
5967 		[ 4] = RCAR_GP_PIN(1, 23),	/* RD_N */
5968 		[ 5] = RCAR_GP_PIN(1, 24),	/* RD_WR_N */
5969 		[ 6] = RCAR_GP_PIN(1, 25),	/* WE0_N */
5970 		[ 7] = RCAR_GP_PIN(1, 26),	/* WE1_N */
5971 		[ 8] = RCAR_GP_PIN(1, 27),	/* EX_WAIT0_A */
5972 		[ 9] = PIN_PRESETOUT_N,		/* PRESETOUT# */
5973 		[10] = RCAR_GP_PIN(0,  0),	/* D0 */
5974 		[11] = RCAR_GP_PIN(0,  1),	/* D1 */
5975 		[12] = RCAR_GP_PIN(0,  2),	/* D2 */
5976 		[13] = RCAR_GP_PIN(0,  3),	/* D3 */
5977 		[14] = RCAR_GP_PIN(0,  4),	/* D4 */
5978 		[15] = RCAR_GP_PIN(0,  5),	/* D5 */
5979 		[16] = RCAR_GP_PIN(0,  6),	/* D6 */
5980 		[17] = RCAR_GP_PIN(0,  7),	/* D7 */
5981 		[18] = RCAR_GP_PIN(0,  8),	/* D8 */
5982 		[19] = RCAR_GP_PIN(0,  9),	/* D9 */
5983 		[20] = RCAR_GP_PIN(0, 10),	/* D10 */
5984 		[21] = RCAR_GP_PIN(0, 11),	/* D11 */
5985 		[22] = RCAR_GP_PIN(0, 12),	/* D12 */
5986 		[23] = RCAR_GP_PIN(0, 13),	/* D13 */
5987 		[24] = RCAR_GP_PIN(0, 14),	/* D14 */
5988 		[25] = RCAR_GP_PIN(0, 15),	/* D15 */
5989 		[26] = RCAR_GP_PIN(7,  0),	/* AVS1 */
5990 		[27] = RCAR_GP_PIN(7,  1),	/* AVS2 */
5991 		[28] = RCAR_GP_PIN(7,  2),	/* GP7_02 */
5992 		[29] = RCAR_GP_PIN(7,  3),	/* GP7_03 */
5993 		[30] = PIN_DU_DOTCLKIN0,	/* DU_DOTCLKIN0 */
5994 		[31] = PIN_DU_DOTCLKIN1,	/* DU_DOTCLKIN1 */
5995 	} },
5996 	{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5997 		[ 0] = PIN_DU_DOTCLKIN2,	/* DU_DOTCLKIN2 */
5998 		[ 1] = PIN_DU_DOTCLKIN3,	/* DU_DOTCLKIN3 */
5999 		[ 2] = PIN_FSCLKST_N,		/* FSCLKST# */
6000 		[ 3] = PIN_EXTALR,		/* EXTALR*/
6001 		[ 4] = PIN_TRST_N,		/* TRST# */
6002 		[ 5] = PIN_TCK,			/* TCK */
6003 		[ 6] = PIN_TMS,			/* TMS */
6004 		[ 7] = PIN_TDI,			/* TDI */
6005 		[ 8] = SH_PFC_PIN_NONE,
6006 		[ 9] = PIN_ASEBRK,		/* ASEBRK */
6007 		[10] = RCAR_GP_PIN(3,  0),	/* SD0_CLK */
6008 		[11] = RCAR_GP_PIN(3,  1),	/* SD0_CMD */
6009 		[12] = RCAR_GP_PIN(3,  2),	/* SD0_DAT0 */
6010 		[13] = RCAR_GP_PIN(3,  3),	/* SD0_DAT1 */
6011 		[14] = RCAR_GP_PIN(3,  4),	/* SD0_DAT2 */
6012 		[15] = RCAR_GP_PIN(3,  5),	/* SD0_DAT3 */
6013 		[16] = RCAR_GP_PIN(3,  6),	/* SD1_CLK */
6014 		[17] = RCAR_GP_PIN(3,  7),	/* SD1_CMD */
6015 		[18] = RCAR_GP_PIN(3,  8),	/* SD1_DAT0 */
6016 		[19] = RCAR_GP_PIN(3,  9),	/* SD1_DAT1 */
6017 		[20] = RCAR_GP_PIN(3, 10),	/* SD1_DAT2 */
6018 		[21] = RCAR_GP_PIN(3, 11),	/* SD1_DAT3 */
6019 		[22] = RCAR_GP_PIN(4,  0),	/* SD2_CLK */
6020 		[23] = RCAR_GP_PIN(4,  1),	/* SD2_CMD */
6021 		[24] = RCAR_GP_PIN(4,  2),	/* SD2_DAT0 */
6022 		[25] = RCAR_GP_PIN(4,  3),	/* SD2_DAT1 */
6023 		[26] = RCAR_GP_PIN(4,  4),	/* SD2_DAT2 */
6024 		[27] = RCAR_GP_PIN(4,  5),	/* SD2_DAT3 */
6025 		[28] = RCAR_GP_PIN(4,  6),	/* SD2_DS */
6026 		[29] = RCAR_GP_PIN(4,  7),	/* SD3_CLK */
6027 		[30] = RCAR_GP_PIN(4,  8),	/* SD3_CMD */
6028 		[31] = RCAR_GP_PIN(4,  9),	/* SD3_DAT0 */
6029 	} },
6030 	{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6031 		[ 0] = RCAR_GP_PIN(4, 10),	/* SD3_DAT1 */
6032 		[ 1] = RCAR_GP_PIN(4, 11),	/* SD3_DAT2 */
6033 		[ 2] = RCAR_GP_PIN(4, 12),	/* SD3_DAT3 */
6034 		[ 3] = RCAR_GP_PIN(4, 13),	/* SD3_DAT4 */
6035 		[ 4] = RCAR_GP_PIN(4, 14),	/* SD3_DAT5 */
6036 		[ 5] = RCAR_GP_PIN(4, 15),	/* SD3_DAT6 */
6037 		[ 6] = RCAR_GP_PIN(4, 16),	/* SD3_DAT7 */
6038 		[ 7] = RCAR_GP_PIN(4, 17),	/* SD3_DS */
6039 		[ 8] = RCAR_GP_PIN(3, 12),	/* SD0_CD */
6040 		[ 9] = RCAR_GP_PIN(3, 13),	/* SD0_WP */
6041 		[10] = RCAR_GP_PIN(3, 14),	/* SD1_CD */
6042 		[11] = RCAR_GP_PIN(3, 15),	/* SD1_WP */
6043 		[12] = RCAR_GP_PIN(5,  0),	/* SCK0 */
6044 		[13] = RCAR_GP_PIN(5,  1),	/* RX0 */
6045 		[14] = RCAR_GP_PIN(5,  2),	/* TX0 */
6046 		[15] = RCAR_GP_PIN(5,  3),	/* CTS0_N */
6047 		[16] = RCAR_GP_PIN(5,  4),	/* RTS0_N */
6048 		[17] = RCAR_GP_PIN(5,  5),	/* RX1_A */
6049 		[18] = RCAR_GP_PIN(5,  6),	/* TX1_A */
6050 		[19] = RCAR_GP_PIN(5,  7),	/* CTS1_N */
6051 		[20] = RCAR_GP_PIN(5,  8),	/* RTS1_N */
6052 		[21] = RCAR_GP_PIN(5,  9),	/* SCK2 */
6053 		[22] = RCAR_GP_PIN(5, 10),	/* TX2_A */
6054 		[23] = RCAR_GP_PIN(5, 11),	/* RX2_A */
6055 		[24] = RCAR_GP_PIN(5, 12),	/* HSCK0 */
6056 		[25] = RCAR_GP_PIN(5, 13),	/* HRX0 */
6057 		[26] = RCAR_GP_PIN(5, 14),	/* HTX0 */
6058 		[27] = RCAR_GP_PIN(5, 15),	/* HCTS0_N */
6059 		[28] = RCAR_GP_PIN(5, 16),	/* HRTS0_N */
6060 		[29] = RCAR_GP_PIN(5, 17),	/* MSIOF0_SCK */
6061 		[30] = RCAR_GP_PIN(5, 18),	/* MSIOF0_SYNC */
6062 		[31] = RCAR_GP_PIN(5, 19),	/* MSIOF0_SS1 */
6063 	} },
6064 	{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6065 		[ 0] = RCAR_GP_PIN(5, 20),	/* MSIOF0_TXD */
6066 		[ 1] = RCAR_GP_PIN(5, 21),	/* MSIOF0_SS2 */
6067 		[ 2] = RCAR_GP_PIN(5, 22),	/* MSIOF0_RXD */
6068 		[ 3] = RCAR_GP_PIN(5, 23),	/* MLB_CLK */
6069 		[ 4] = RCAR_GP_PIN(5, 24),	/* MLB_SIG */
6070 		[ 5] = RCAR_GP_PIN(5, 25),	/* MLB_DAT */
6071 		[ 6] = PIN_MLB_REF,		/* MLB_REF */
6072 		[ 7] = RCAR_GP_PIN(6,  0),	/* SSI_SCK01239 */
6073 		[ 8] = RCAR_GP_PIN(6,  1),	/* SSI_WS01239 */
6074 		[ 9] = RCAR_GP_PIN(6,  2),	/* SSI_SDATA0 */
6075 		[10] = RCAR_GP_PIN(6,  3),	/* SSI_SDATA1_A */
6076 		[11] = RCAR_GP_PIN(6,  4),	/* SSI_SDATA2_A */
6077 		[12] = RCAR_GP_PIN(6,  5),	/* SSI_SCK349 */
6078 		[13] = RCAR_GP_PIN(6,  6),	/* SSI_WS349 */
6079 		[14] = RCAR_GP_PIN(6,  7),	/* SSI_SDATA3 */
6080 		[15] = RCAR_GP_PIN(6,  8),	/* SSI_SCK4 */
6081 		[16] = RCAR_GP_PIN(6,  9),	/* SSI_WS4 */
6082 		[17] = RCAR_GP_PIN(6, 10),	/* SSI_SDATA4 */
6083 		[18] = RCAR_GP_PIN(6, 11),	/* SSI_SCK5 */
6084 		[19] = RCAR_GP_PIN(6, 12),	/* SSI_WS5 */
6085 		[20] = RCAR_GP_PIN(6, 13),	/* SSI_SDATA5 */
6086 		[21] = RCAR_GP_PIN(6, 14),	/* SSI_SCK6 */
6087 		[22] = RCAR_GP_PIN(6, 15),	/* SSI_WS6 */
6088 		[23] = RCAR_GP_PIN(6, 16),	/* SSI_SDATA6 */
6089 		[24] = RCAR_GP_PIN(6, 17),	/* SSI_SCK78 */
6090 		[25] = RCAR_GP_PIN(6, 18),	/* SSI_WS78 */
6091 		[26] = RCAR_GP_PIN(6, 19),	/* SSI_SDATA7 */
6092 		[27] = RCAR_GP_PIN(6, 20),	/* SSI_SDATA8 */
6093 		[28] = RCAR_GP_PIN(6, 21),	/* SSI_SDATA9_A */
6094 		[29] = RCAR_GP_PIN(6, 22),	/* AUDIO_CLKA_A */
6095 		[30] = RCAR_GP_PIN(6, 23),	/* AUDIO_CLKB_B */
6096 		[31] = RCAR_GP_PIN(6, 24),	/* USB0_PWEN */
6097 	} },
6098 	{ PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6099 		[ 0] = RCAR_GP_PIN(6, 25),	/* USB0_OVC */
6100 		[ 1] = RCAR_GP_PIN(6, 26),	/* USB1_PWEN */
6101 		[ 2] = RCAR_GP_PIN(6, 27),	/* USB1_OVC */
6102 		[ 3] = RCAR_GP_PIN(6, 28),	/* USB30_PWEN */
6103 		[ 4] = RCAR_GP_PIN(6, 29),	/* USB30_OVC */
6104 		[ 5] = RCAR_GP_PIN(6, 30),	/* USB2_CH3_PWEN */
6105 		[ 6] = RCAR_GP_PIN(6, 31),	/* USB2_CH3_OVC */
6106 		[ 7] = SH_PFC_PIN_NONE,
6107 		[ 8] = SH_PFC_PIN_NONE,
6108 		[ 9] = SH_PFC_PIN_NONE,
6109 		[10] = SH_PFC_PIN_NONE,
6110 		[11] = SH_PFC_PIN_NONE,
6111 		[12] = SH_PFC_PIN_NONE,
6112 		[13] = SH_PFC_PIN_NONE,
6113 		[14] = SH_PFC_PIN_NONE,
6114 		[15] = SH_PFC_PIN_NONE,
6115 		[16] = SH_PFC_PIN_NONE,
6116 		[17] = SH_PFC_PIN_NONE,
6117 		[18] = SH_PFC_PIN_NONE,
6118 		[19] = SH_PFC_PIN_NONE,
6119 		[20] = SH_PFC_PIN_NONE,
6120 		[21] = SH_PFC_PIN_NONE,
6121 		[22] = SH_PFC_PIN_NONE,
6122 		[23] = SH_PFC_PIN_NONE,
6123 		[24] = SH_PFC_PIN_NONE,
6124 		[25] = SH_PFC_PIN_NONE,
6125 		[26] = SH_PFC_PIN_NONE,
6126 		[27] = SH_PFC_PIN_NONE,
6127 		[28] = SH_PFC_PIN_NONE,
6128 		[29] = SH_PFC_PIN_NONE,
6129 		[30] = SH_PFC_PIN_NONE,
6130 		[31] = SH_PFC_PIN_NONE,
6131 	} },
6132 	{ /* sentinel */ },
6133 };
6134 
6135 static const struct sh_pfc_soc_operations r8a77951_pfc_ops = {
6136 	.pin_to_pocctrl = r8a77951_pin_to_pocctrl,
6137 	.get_bias = rcar_pinmux_get_bias,
6138 	.set_bias = rcar_pinmux_set_bias,
6139 };
6140 
6141 #ifdef CONFIG_PINCTRL_PFC_R8A774E1
6142 const struct sh_pfc_soc_info r8a774e1_pinmux_info = {
6143 	.name = "r8a774e1_pfc",
6144 	.ops = &r8a77951_pfc_ops,
6145 	.unlock_reg = 0xe6060000, /* PMMR */
6146 
6147 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6148 
6149 	.pins = pinmux_pins,
6150 	.nr_pins = ARRAY_SIZE(pinmux_pins),
6151 	.groups = pinmux_groups.common,
6152 	.nr_groups = ARRAY_SIZE(pinmux_groups.common),
6153 	.functions = pinmux_functions.common,
6154 	.nr_functions = ARRAY_SIZE(pinmux_functions.common),
6155 
6156 	.cfg_regs = pinmux_config_regs,
6157 	.drive_regs = pinmux_drive_regs,
6158 	.bias_regs = pinmux_bias_regs,
6159 	.ioctrl_regs = pinmux_ioctrl_regs,
6160 
6161 	.pinmux_data = pinmux_data,
6162 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
6163 };
6164 #endif
6165 
6166 #ifdef CONFIG_PINCTRL_PFC_R8A77951
6167 const struct sh_pfc_soc_info r8a77951_pinmux_info = {
6168 	.name = "r8a77951_pfc",
6169 	.ops = &r8a77951_pfc_ops,
6170 	.unlock_reg = 0xe6060000, /* PMMR */
6171 
6172 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6173 
6174 	.pins = pinmux_pins,
6175 	.nr_pins = ARRAY_SIZE(pinmux_pins),
6176 	.groups = pinmux_groups.common,
6177 	.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6178 			ARRAY_SIZE(pinmux_groups.automotive),
6179 	.functions = pinmux_functions.common,
6180 	.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6181 			ARRAY_SIZE(pinmux_functions.automotive),
6182 
6183 	.cfg_regs = pinmux_config_regs,
6184 	.drive_regs = pinmux_drive_regs,
6185 	.bias_regs = pinmux_bias_regs,
6186 	.ioctrl_regs = pinmux_ioctrl_regs,
6187 
6188 	.pinmux_data = pinmux_data,
6189 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
6190 };
6191 #endif
6192