1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * R8A77970 processor support - PFC hardware block.
4  *
5  * Copyright (C) 2016 Renesas Electronics Corp.
6  * Copyright (C) 2017 Cogent Embedded, Inc. <source@cogentembedded.com>
7  *
8  * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
9  *
10  * R-Car Gen3 processor support - PFC hardware block.
11  *
12  * Copyright (C) 2015  Renesas Electronics Corporation
13  */
14 
15 #include <linux/errno.h>
16 #include <linux/io.h>
17 #include <linux/kernel.h>
18 
19 #include "sh_pfc.h"
20 
21 #define CPU_ALL_GP(fn, sfx)						\
22 	PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
23 	PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
24 	PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
25 	PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
26 	PORT_GP_CFG_6(4,  fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
27 	PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
28 
29 #define CPU_ALL_NOGP(fn)						\
30 	PIN_NOGP_CFG(DU_DOTCLKIN, "DU_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_DOWN),	\
31 	PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_DOWN),	\
32 	PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
33 	PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
34 	PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP),		\
35 	PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP),		\
36 	PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP),		\
37 	PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP),	\
38 	PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
39 
40 /*
41  * F_() : just information
42  * FM() : macro for FN_xxx / xxx_MARK
43  */
44 
45 /* GPSR0 */
46 #define GPSR0_21	F_(DU_EXODDF_DU_ODDF_DISP_CDE,	IP2_23_20)
47 #define GPSR0_20	F_(DU_EXVSYNC_DU_VSYNC,		IP2_19_16)
48 #define GPSR0_19	F_(DU_EXHSYNC_DU_HSYNC,		IP2_15_12)
49 #define GPSR0_18	F_(DU_DOTCLKOUT,		IP2_11_8)
50 #define GPSR0_17	F_(DU_DB7,			IP2_7_4)
51 #define GPSR0_16	F_(DU_DB6,			IP2_3_0)
52 #define GPSR0_15	F_(DU_DB5,			IP1_31_28)
53 #define GPSR0_14	F_(DU_DB4,			IP1_27_24)
54 #define GPSR0_13	F_(DU_DB3,			IP1_23_20)
55 #define GPSR0_12	F_(DU_DB2,			IP1_19_16)
56 #define GPSR0_11	F_(DU_DG7,			IP1_15_12)
57 #define GPSR0_10	F_(DU_DG6,			IP1_11_8)
58 #define GPSR0_9		F_(DU_DG5,			IP1_7_4)
59 #define GPSR0_8		F_(DU_DG4,			IP1_3_0)
60 #define GPSR0_7		F_(DU_DG3,			IP0_31_28)
61 #define GPSR0_6		F_(DU_DG2,			IP0_27_24)
62 #define GPSR0_5		F_(DU_DR7,			IP0_23_20)
63 #define GPSR0_4		F_(DU_DR6,			IP0_19_16)
64 #define GPSR0_3		F_(DU_DR5,			IP0_15_12)
65 #define GPSR0_2		F_(DU_DR4,			IP0_11_8)
66 #define GPSR0_1		F_(DU_DR3,			IP0_7_4)
67 #define GPSR0_0		F_(DU_DR2,			IP0_3_0)
68 
69 /* GPSR1 */
70 #define GPSR1_27	F_(DIGRF_CLKOUT,	IP8_27_24)
71 #define GPSR1_26	F_(DIGRF_CLKIN,		IP8_23_20)
72 #define GPSR1_25	F_(CANFD_CLK_A,		IP8_19_16)
73 #define GPSR1_24	F_(CANFD1_RX,		IP8_15_12)
74 #define GPSR1_23	F_(CANFD1_TX,		IP8_11_8)
75 #define GPSR1_22	F_(CANFD0_RX_A,		IP8_7_4)
76 #define GPSR1_21	F_(CANFD0_TX_A,		IP8_3_0)
77 #define GPSR1_20	F_(AVB0_AVTP_CAPTURE,	IP7_31_28)
78 #define GPSR1_19	FM(AVB0_AVTP_MATCH)
79 #define GPSR1_18	FM(AVB0_LINK)
80 #define GPSR1_17	FM(AVB0_PHY_INT)
81 #define GPSR1_16	FM(AVB0_MAGIC)
82 #define GPSR1_15	FM(AVB0_MDC)
83 #define GPSR1_14	FM(AVB0_MDIO)
84 #define GPSR1_13	FM(AVB0_TXCREFCLK)
85 #define GPSR1_12	FM(AVB0_TD3)
86 #define GPSR1_11	FM(AVB0_TD2)
87 #define GPSR1_10	FM(AVB0_TD1)
88 #define GPSR1_9		FM(AVB0_TD0)
89 #define GPSR1_8		FM(AVB0_TXC)
90 #define GPSR1_7		FM(AVB0_TX_CTL)
91 #define GPSR1_6		FM(AVB0_RD3)
92 #define GPSR1_5		FM(AVB0_RD2)
93 #define GPSR1_4		FM(AVB0_RD1)
94 #define GPSR1_3		FM(AVB0_RD0)
95 #define GPSR1_2		FM(AVB0_RXC)
96 #define GPSR1_1		FM(AVB0_RX_CTL)
97 #define GPSR1_0		F_(IRQ0,		IP2_27_24)
98 
99 /* GPSR2 */
100 #define GPSR2_16	F_(VI0_FIELD,		IP4_31_28)
101 #define GPSR2_15	F_(VI0_DATA11,		IP4_27_24)
102 #define GPSR2_14	F_(VI0_DATA10,		IP4_23_20)
103 #define GPSR2_13	F_(VI0_DATA9,		IP4_19_16)
104 #define GPSR2_12	F_(VI0_DATA8,		IP4_15_12)
105 #define GPSR2_11	F_(VI0_DATA7,		IP4_11_8)
106 #define GPSR2_10	F_(VI0_DATA6,		IP4_7_4)
107 #define GPSR2_9		F_(VI0_DATA5,		IP4_3_0)
108 #define GPSR2_8		F_(VI0_DATA4,		IP3_31_28)
109 #define GPSR2_7		F_(VI0_DATA3,		IP3_27_24)
110 #define GPSR2_6		F_(VI0_DATA2,		IP3_23_20)
111 #define GPSR2_5		F_(VI0_DATA1,		IP3_19_16)
112 #define GPSR2_4		F_(VI0_DATA0,		IP3_15_12)
113 #define GPSR2_3		F_(VI0_VSYNC_N,		IP3_11_8)
114 #define GPSR2_2		F_(VI0_HSYNC_N,		IP3_7_4)
115 #define GPSR2_1		F_(VI0_CLKENB,		IP3_3_0)
116 #define GPSR2_0		F_(VI0_CLK,		IP2_31_28)
117 
118 /* GPSR3 */
119 #define GPSR3_16	F_(VI1_FIELD,		IP7_3_0)
120 #define GPSR3_15	F_(VI1_DATA11,		IP6_31_28)
121 #define GPSR3_14	F_(VI1_DATA10,		IP6_27_24)
122 #define GPSR3_13	F_(VI1_DATA9,		IP6_23_20)
123 #define GPSR3_12	F_(VI1_DATA8,		IP6_19_16)
124 #define GPSR3_11	F_(VI1_DATA7,		IP6_15_12)
125 #define GPSR3_10	F_(VI1_DATA6,		IP6_11_8)
126 #define GPSR3_9		F_(VI1_DATA5,		IP6_7_4)
127 #define GPSR3_8		F_(VI1_DATA4,		IP6_3_0)
128 #define GPSR3_7		F_(VI1_DATA3,		IP5_31_28)
129 #define GPSR3_6		F_(VI1_DATA2,		IP5_27_24)
130 #define GPSR3_5		F_(VI1_DATA1,		IP5_23_20)
131 #define GPSR3_4		F_(VI1_DATA0,		IP5_19_16)
132 #define GPSR3_3		F_(VI1_VSYNC_N,		IP5_15_12)
133 #define GPSR3_2		F_(VI1_HSYNC_N,		IP5_11_8)
134 #define GPSR3_1		F_(VI1_CLKENB,		IP5_7_4)
135 #define GPSR3_0		F_(VI1_CLK,		IP5_3_0)
136 
137 /* GPSR4 */
138 #define GPSR4_5		F_(SDA2,		IP7_27_24)
139 #define GPSR4_4		F_(SCL2,		IP7_23_20)
140 #define GPSR4_3		F_(SDA1,		IP7_19_16)
141 #define GPSR4_2		F_(SCL1,		IP7_15_12)
142 #define GPSR4_1		F_(SDA0,		IP7_11_8)
143 #define GPSR4_0		F_(SCL0,		IP7_7_4)
144 
145 /* GPSR5 */
146 #define GPSR5_14	FM(RPC_INT_N)
147 #define GPSR5_13	FM(RPC_WP_N)
148 #define GPSR5_12	FM(RPC_RESET_N)
149 #define GPSR5_11	FM(QSPI1_SSL)
150 #define GPSR5_10	FM(QSPI1_IO3)
151 #define GPSR5_9		FM(QSPI1_IO2)
152 #define GPSR5_8		FM(QSPI1_MISO_IO1)
153 #define GPSR5_7		FM(QSPI1_MOSI_IO0)
154 #define GPSR5_6		FM(QSPI1_SPCLK)
155 #define GPSR5_5		FM(QSPI0_SSL)
156 #define GPSR5_4		FM(QSPI0_IO3)
157 #define GPSR5_3		FM(QSPI0_IO2)
158 #define GPSR5_2		FM(QSPI0_MISO_IO1)
159 #define GPSR5_1		FM(QSPI0_MOSI_IO0)
160 #define GPSR5_0		FM(QSPI0_SPCLK)
161 
162 
163 /* IPSRx */		/* 0 */				/* 1 */			/* 2 */		/* 3 */		/* 4 */			/* 5 */		/* 6 - F */
164 #define IP0_3_0		FM(DU_DR2)			FM(HSCK0)		F_(0, 0)	FM(A0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
165 #define IP0_7_4		FM(DU_DR3)			FM(HRTS0_N)		F_(0, 0)	FM(A1)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
166 #define IP0_11_8	FM(DU_DR4)			FM(HCTS0_N)		F_(0, 0)	FM(A2)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)	F_(0, 0) F_(0, 0)
167 #define IP0_15_12	FM(DU_DR5)			FM(HTX0)		F_(0, 0)	FM(A3)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
168 #define IP0_19_16	FM(DU_DR6)			FM(MSIOF3_RXD)		F_(0, 0)	FM(A4)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
169 #define IP0_23_20	FM(DU_DR7)			FM(MSIOF3_TXD)		F_(0, 0)	FM(A5)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
170 #define IP0_27_24	FM(DU_DG2)			FM(MSIOF3_SS1)		F_(0, 0)	FM(A6)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
171 #define IP0_31_28	FM(DU_DG3)			FM(MSIOF3_SS2)		F_(0, 0)	FM(A7)		FM(PWMFSW0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
172 #define IP1_3_0		FM(DU_DG4)			F_(0, 0)		F_(0, 0)	FM(A8)		FM(FSO_CFE_0_N_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
173 #define IP1_7_4		FM(DU_DG5)			F_(0, 0)		F_(0, 0)	FM(A9)		FM(FSO_CFE_1_N_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
174 #define IP1_11_8	FM(DU_DG6)			F_(0, 0)		F_(0, 0)	FM(A10)		FM(FSO_TOE_N_A) 	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
175 #define IP1_15_12	FM(DU_DG7)			F_(0, 0)		F_(0, 0)	FM(A11)		FM(IRQ1)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
176 #define IP1_19_16	FM(DU_DB2)			F_(0, 0)		F_(0, 0)	FM(A12)		FM(IRQ2)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
177 #define IP1_23_20	FM(DU_DB3)			F_(0, 0)		F_(0, 0)	FM(A13)		FM(FXR_CLKOUT1)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
178 #define IP1_27_24	FM(DU_DB4)			F_(0, 0)		F_(0, 0)	FM(A14)		FM(FXR_CLKOUT2)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
179 #define IP1_31_28	FM(DU_DB5)			F_(0, 0)		F_(0, 0)	FM(A15)		FM(FXR_TXENA_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
180 #define IP2_3_0		FM(DU_DB6)			F_(0, 0)		F_(0, 0)	FM(A16)		FM(FXR_TXENB_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
181 #define IP2_7_4		FM(DU_DB7)			F_(0, 0)		F_(0, 0)	FM(A17)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
182 #define IP2_11_8	FM(DU_DOTCLKOUT)		FM(SCIF_CLK_A)		F_(0, 0)	FM(A18)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
183 #define IP2_15_12	FM(DU_EXHSYNC_DU_HSYNC)		FM(HRX0)		F_(0, 0)	FM(A19)		FM(IRQ3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
184 #define IP2_19_16	FM(DU_EXVSYNC_DU_VSYNC)		FM(MSIOF3_SCK)		F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
185 #define IP2_23_20	FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(MSIOF3_SYNC)		F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
186 #define IP2_27_24	FM(IRQ0)			F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
187 #define IP2_31_28	FM(VI0_CLK)			FM(MSIOF2_SCK)		FM(SCK3)	F_(0, 0)	FM(HSCK3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
188 #define IP3_3_0		FM(VI0_CLKENB)			FM(MSIOF2_RXD)		FM(RX3)		FM(RD_WR_N)	FM(HCTS3_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
189 #define IP3_7_4		FM(VI0_HSYNC_N)			FM(MSIOF2_TXD)		FM(TX3)		F_(0, 0)	FM(HRTS3_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
190 #define IP3_11_8	FM(VI0_VSYNC_N)			FM(MSIOF2_SYNC)		FM(CTS3_N)	F_(0, 0)	FM(HTX3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
191 #define IP3_15_12	FM(VI0_DATA0)			FM(MSIOF2_SS1)		FM(RTS3_N)	F_(0, 0)	FM(HRX3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
192 #define IP3_19_16	FM(VI0_DATA1)			FM(MSIOF2_SS2)		FM(SCK1)	F_(0, 0)	FM(SPEEDIN_A)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
193 #define IP3_23_20	FM(VI0_DATA2)			FM(AVB0_AVTP_PPS)	FM(SDA3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
194 #define IP3_27_24	FM(VI0_DATA3)			FM(HSCK1)		FM(SCL3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
195 #define IP3_31_28	FM(VI0_DATA4)			FM(HRTS1_N)		FM(RX1_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
196 #define IP4_3_0		FM(VI0_DATA5)			FM(HCTS1_N)		FM(TX1_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
197 #define IP4_7_4		FM(VI0_DATA6)			FM(HTX1)		FM(CTS1_N)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
198 #define IP4_11_8	FM(VI0_DATA7)			FM(HRX1)		FM(RTS1_N)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
199 #define IP4_15_12	FM(VI0_DATA8)			FM(HSCK2)		FM(PWM0_A)	FM(A22)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
200 #define IP4_19_16	FM(VI0_DATA9)			FM(HCTS2_N)		FM(PWM1_A)	FM(A23)		FM(FSO_CFE_0_N_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
201 #define IP4_23_20	FM(VI0_DATA10)			FM(HRTS2_N)		FM(PWM2_A)	FM(A24)		FM(FSO_CFE_1_N_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202 #define IP4_27_24	FM(VI0_DATA11)			FM(HTX2)		FM(PWM3_A)	FM(A25)		FM(FSO_TOE_N_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
203 #define IP4_31_28	FM(VI0_FIELD)			FM(HRX2)		FM(PWM4_A)	FM(CS1_N)	FM(FSCLKST2_N_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204 #define IP5_3_0		FM(VI1_CLK)			FM(MSIOF1_RXD)		F_(0, 0)	FM(CS0_N)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205 #define IP5_7_4		FM(VI1_CLKENB)			FM(MSIOF1_TXD)		F_(0, 0)	FM(D0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206 #define IP5_11_8	FM(VI1_HSYNC_N)			FM(MSIOF1_SCK)		F_(0, 0)	FM(D1)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207 #define IP5_15_12	FM(VI1_VSYNC_N)			FM(MSIOF1_SYNC)		F_(0, 0)	FM(D2)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208 #define IP5_19_16	FM(VI1_DATA0)			FM(MSIOF1_SS1)		F_(0, 0)	FM(D3)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209 #define IP5_23_20	FM(VI1_DATA1)			FM(MSIOF1_SS2)		F_(0, 0)	FM(D4)		FM(MMC_CMD)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210 #define IP5_27_24	FM(VI1_DATA2)			FM(CANFD0_TX_B)		F_(0, 0)	FM(D5)		FM(MMC_D0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211 #define IP5_31_28	FM(VI1_DATA3)			FM(CANFD0_RX_B)		F_(0, 0)	FM(D6)		FM(MMC_D1)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212 #define IP6_3_0		FM(VI1_DATA4)			FM(CANFD_CLK_B)		F_(0, 0)	FM(D7)		FM(MMC_D2)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213 #define IP6_7_4		FM(VI1_DATA5)			F_(0, 0)		FM(SCK4)	FM(D8)		FM(MMC_D3)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP6_11_8	FM(VI1_DATA6)			F_(0, 0)		FM(RX4)		FM(D9)		FM(MMC_CLK)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP6_15_12	FM(VI1_DATA7)			F_(0, 0)		FM(TX4)		FM(D10)		FM(MMC_D4)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP6_19_16	FM(VI1_DATA8)			F_(0, 0)		FM(CTS4_N)	FM(D11)		FM(MMC_D5)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP6_23_20	FM(VI1_DATA9)			F_(0, 0)		FM(RTS4_N)	FM(D12)		FM(MMC_D6)		FM(SCL3_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP6_27_24	FM(VI1_DATA10)			F_(0, 0)		F_(0, 0)	FM(D13)		FM(MMC_D7)		FM(SDA3_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP6_31_28	FM(VI1_DATA11)			FM(SCL4)		FM(IRQ4)	FM(D14)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP7_3_0		FM(VI1_FIELD)			FM(SDA4)		FM(IRQ5)	FM(D15)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP7_7_4		FM(SCL0)			FM(DU_DR0)		FM(TPU0TO0)	FM(CLKOUT)	F_(0, 0)		FM(MSIOF0_RXD)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP7_11_8	FM(SDA0)			FM(DU_DR1)		FM(TPU0TO1)	FM(BS_N)	FM(SCK0)		FM(MSIOF0_TXD)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP7_15_12	FM(SCL1)			FM(DU_DG0)		FM(TPU0TO2)	FM(RD_N)	FM(CTS0_N)		FM(MSIOF0_SCK)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP7_19_16	FM(SDA1)			FM(DU_DG1)		FM(TPU0TO3)	FM(WE0_N)	FM(RTS0_N)		FM(MSIOF0_SYNC)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP7_23_20	FM(SCL2)			FM(DU_DB0)		FM(TCLK1_A)	FM(WE1_N)	FM(RX0)			FM(MSIOF0_SS1)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP7_27_24	FM(SDA2)			FM(DU_DB1)		FM(TCLK2_A)	FM(EX_WAIT0)	FM(TX0)			FM(MSIOF0_SS2)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP7_31_28	FM(AVB0_AVTP_CAPTURE)		F_(0, 0)		F_(0, 0)	F_(0, 0)	FM(FSCLKST2_N_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP8_3_0		FM(CANFD0_TX_A)			FM(FXR_TXDA)		FM(PWM0_B)	FM(DU_DISP)	FM(FSCLKST2_N_C)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP8_7_4		FM(CANFD0_RX_A)			FM(RXDA_EXTFXR)		FM(PWM1_B)	FM(DU_CDE)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP8_11_8	FM(CANFD1_TX)			FM(FXR_TXDB)		FM(PWM2_B)	FM(TCLK1_B)	FM(TX1_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 #define IP8_15_12	FM(CANFD1_RX)			FM(RXDB_EXTFXR)		FM(PWM3_B)	FM(TCLK2_B)	FM(RX1_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232 #define IP8_19_16	FM(CANFD_CLK_A)			FM(CLK_EXTFXR)		FM(PWM4_B)	FM(SPEEDIN_B)	FM(SCIF_CLK_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 #define IP8_23_20	FM(DIGRF_CLKIN)			FM(DIGRF_CLKEN_IN)	F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP8_27_24	FM(DIGRF_CLKOUT)		FM(DIGRF_CLKEN_OUT)	F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 
236 #define PINMUX_GPSR	\
237 \
238 		GPSR1_27 \
239 		GPSR1_26 \
240 		GPSR1_25 \
241 		GPSR1_24 \
242 		GPSR1_23 \
243 		GPSR1_22 \
244 GPSR0_21	GPSR1_21 \
245 GPSR0_20	GPSR1_20 \
246 GPSR0_19	GPSR1_19 \
247 GPSR0_18	GPSR1_18 \
248 GPSR0_17	GPSR1_17 \
249 GPSR0_16	GPSR1_16	GPSR2_16	GPSR3_16 \
250 GPSR0_15	GPSR1_15	GPSR2_15	GPSR3_15 \
251 GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14			GPSR5_14 \
252 GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13			GPSR5_13 \
253 GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12			GPSR5_12 \
254 GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11			GPSR5_11 \
255 GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10			GPSR5_10 \
256 GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9				GPSR5_9 \
257 GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8				GPSR5_8 \
258 GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7				GPSR5_7 \
259 GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6				GPSR5_6 \
260 GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		GPSR4_5		GPSR5_5 \
261 GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		GPSR4_4		GPSR5_4 \
262 GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		GPSR4_3		GPSR5_3 \
263 GPSR0_2		GPSR1_2		GPSR2_2		GPSR3_2		GPSR4_2		GPSR5_2 \
264 GPSR0_1		GPSR1_1		GPSR2_1		GPSR3_1		GPSR4_1		GPSR5_1 \
265 GPSR0_0		GPSR1_0		GPSR2_0		GPSR3_0		GPSR4_0		GPSR5_0
266 
267 #define PINMUX_IPSR	\
268 \
269 FM(IP0_3_0)	IP0_3_0		FM(IP1_3_0)	IP1_3_0		FM(IP2_3_0)	IP2_3_0		FM(IP3_3_0)	IP3_3_0 \
270 FM(IP0_7_4)	IP0_7_4		FM(IP1_7_4)	IP1_7_4		FM(IP2_7_4)	IP2_7_4		FM(IP3_7_4)	IP3_7_4 \
271 FM(IP0_11_8)	IP0_11_8	FM(IP1_11_8)	IP1_11_8	FM(IP2_11_8)	IP2_11_8	FM(IP3_11_8)	IP3_11_8 \
272 FM(IP0_15_12)	IP0_15_12	FM(IP1_15_12)	IP1_15_12	FM(IP2_15_12)	IP2_15_12	FM(IP3_15_12)	IP3_15_12 \
273 FM(IP0_19_16)	IP0_19_16	FM(IP1_19_16)	IP1_19_16	FM(IP2_19_16)	IP2_19_16	FM(IP3_19_16)	IP3_19_16 \
274 FM(IP0_23_20)	IP0_23_20	FM(IP1_23_20)	IP1_23_20	FM(IP2_23_20)	IP2_23_20	FM(IP3_23_20)	IP3_23_20 \
275 FM(IP0_27_24)	IP0_27_24	FM(IP1_27_24)	IP1_27_24	FM(IP2_27_24)	IP2_27_24	FM(IP3_27_24)	IP3_27_24 \
276 FM(IP0_31_28)	IP0_31_28	FM(IP1_31_28)	IP1_31_28	FM(IP2_31_28)	IP2_31_28	FM(IP3_31_28)	IP3_31_28 \
277 \
278 FM(IP4_3_0)	IP4_3_0		FM(IP5_3_0)	IP5_3_0		FM(IP6_3_0)	IP6_3_0		FM(IP7_3_0)	IP7_3_0 \
279 FM(IP4_7_4)	IP4_7_4		FM(IP5_7_4)	IP5_7_4		FM(IP6_7_4)	IP6_7_4		FM(IP7_7_4)	IP7_7_4 \
280 FM(IP4_11_8)	IP4_11_8	FM(IP5_11_8)	IP5_11_8	FM(IP6_11_8)	IP6_11_8	FM(IP7_11_8)	IP7_11_8 \
281 FM(IP4_15_12)	IP4_15_12	FM(IP5_15_12)	IP5_15_12	FM(IP6_15_12)	IP6_15_12	FM(IP7_15_12)	IP7_15_12 \
282 FM(IP4_19_16)	IP4_19_16	FM(IP5_19_16)	IP5_19_16	FM(IP6_19_16)	IP6_19_16	FM(IP7_19_16)	IP7_19_16 \
283 FM(IP4_23_20)	IP4_23_20	FM(IP5_23_20)	IP5_23_20	FM(IP6_23_20)	IP6_23_20	FM(IP7_23_20)	IP7_23_20 \
284 FM(IP4_27_24)	IP4_27_24	FM(IP5_27_24)	IP5_27_24	FM(IP6_27_24)	IP6_27_24	FM(IP7_27_24)	IP7_27_24 \
285 FM(IP4_31_28)	IP4_31_28	FM(IP5_31_28)	IP5_31_28	FM(IP6_31_28)	IP6_31_28	FM(IP7_31_28)	IP7_31_28 \
286 \
287 FM(IP8_3_0)	IP8_3_0 \
288 FM(IP8_7_4)	IP8_7_4 \
289 FM(IP8_11_8)	IP8_11_8 \
290 FM(IP8_15_12)	IP8_15_12 \
291 FM(IP8_19_16)	IP8_19_16 \
292 FM(IP8_23_20)	IP8_23_20 \
293 FM(IP8_27_24)	IP8_27_24
294 
295 /* MOD_SEL0 */		/* 0 */			/* 1 */
296 #define MOD_SEL0_11	FM(SEL_I2C3_0)		FM(SEL_I2C3_1)
297 #define MOD_SEL0_10	FM(SEL_HSCIF0_0)	FM(SEL_HSCIF0_1)
298 #define MOD_SEL0_9	FM(SEL_SCIF1_0)		FM(SEL_SCIF1_1)
299 #define MOD_SEL0_8	FM(SEL_CANFD0_0)	FM(SEL_CANFD0_1)
300 #define MOD_SEL0_7	FM(SEL_PWM4_0)		FM(SEL_PWM4_1)
301 #define MOD_SEL0_6	FM(SEL_PWM3_0)		FM(SEL_PWM3_1)
302 #define MOD_SEL0_5	FM(SEL_PWM2_0)		FM(SEL_PWM2_1)
303 #define MOD_SEL0_4	FM(SEL_PWM1_0)		FM(SEL_PWM1_1)
304 #define MOD_SEL0_3	FM(SEL_PWM0_0)		FM(SEL_PWM0_1)
305 #define MOD_SEL0_2	FM(SEL_RFSO_0)		FM(SEL_RFSO_1)
306 #define MOD_SEL0_1	FM(SEL_RSP_0)		FM(SEL_RSP_1)
307 #define MOD_SEL0_0	FM(SEL_TMU_0)		FM(SEL_TMU_1)
308 
309 #define PINMUX_MOD_SELS \
310 \
311 MOD_SEL0_11 \
312 MOD_SEL0_10 \
313 MOD_SEL0_9 \
314 MOD_SEL0_8 \
315 MOD_SEL0_7 \
316 MOD_SEL0_6 \
317 MOD_SEL0_5 \
318 MOD_SEL0_4 \
319 MOD_SEL0_3 \
320 MOD_SEL0_2 \
321 MOD_SEL0_1 \
322 MOD_SEL0_0
323 
324 enum {
325 	PINMUX_RESERVED = 0,
326 
327 	PINMUX_DATA_BEGIN,
328 	GP_ALL(DATA),
329 	PINMUX_DATA_END,
330 
331 #define F_(x, y)
332 #define FM(x)   FN_##x,
333 	PINMUX_FUNCTION_BEGIN,
334 	GP_ALL(FN),
335 	PINMUX_GPSR
336 	PINMUX_IPSR
337 	PINMUX_MOD_SELS
338 	PINMUX_FUNCTION_END,
339 #undef F_
340 #undef FM
341 
342 #define F_(x, y)
343 #define FM(x)	x##_MARK,
344 	PINMUX_MARK_BEGIN,
345 	PINMUX_GPSR
346 	PINMUX_IPSR
347 	PINMUX_MOD_SELS
348 	PINMUX_MARK_END,
349 #undef F_
350 #undef FM
351 };
352 
353 static const u16 pinmux_data[] = {
354 	PINMUX_DATA_GP_ALL(),
355 
356 	PINMUX_SINGLE(AVB0_RX_CTL),
357 	PINMUX_SINGLE(AVB0_RXC),
358 	PINMUX_SINGLE(AVB0_RD0),
359 	PINMUX_SINGLE(AVB0_RD1),
360 	PINMUX_SINGLE(AVB0_RD2),
361 	PINMUX_SINGLE(AVB0_RD3),
362 	PINMUX_SINGLE(AVB0_TX_CTL),
363 	PINMUX_SINGLE(AVB0_TXC),
364 	PINMUX_SINGLE(AVB0_TD0),
365 	PINMUX_SINGLE(AVB0_TD1),
366 	PINMUX_SINGLE(AVB0_TD2),
367 	PINMUX_SINGLE(AVB0_TD3),
368 	PINMUX_SINGLE(AVB0_TXCREFCLK),
369 	PINMUX_SINGLE(AVB0_MDIO),
370 	PINMUX_SINGLE(AVB0_MDC),
371 	PINMUX_SINGLE(AVB0_MAGIC),
372 	PINMUX_SINGLE(AVB0_PHY_INT),
373 	PINMUX_SINGLE(AVB0_LINK),
374 	PINMUX_SINGLE(AVB0_AVTP_MATCH),
375 
376 	PINMUX_SINGLE(QSPI0_SPCLK),
377 	PINMUX_SINGLE(QSPI0_MOSI_IO0),
378 	PINMUX_SINGLE(QSPI0_MISO_IO1),
379 	PINMUX_SINGLE(QSPI0_IO2),
380 	PINMUX_SINGLE(QSPI0_IO3),
381 	PINMUX_SINGLE(QSPI0_SSL),
382 	PINMUX_SINGLE(QSPI1_SPCLK),
383 	PINMUX_SINGLE(QSPI1_MOSI_IO0),
384 	PINMUX_SINGLE(QSPI1_MISO_IO1),
385 	PINMUX_SINGLE(QSPI1_IO2),
386 	PINMUX_SINGLE(QSPI1_IO3),
387 	PINMUX_SINGLE(QSPI1_SSL),
388 	PINMUX_SINGLE(RPC_RESET_N),
389 	PINMUX_SINGLE(RPC_WP_N),
390 	PINMUX_SINGLE(RPC_INT_N),
391 
392 	/* IPSR0 */
393 	PINMUX_IPSR_GPSR(IP0_3_0,	DU_DR2),
394 	PINMUX_IPSR_GPSR(IP0_3_0,	HSCK0),
395 	PINMUX_IPSR_GPSR(IP0_3_0,	A0),
396 
397 	PINMUX_IPSR_GPSR(IP0_7_4,	DU_DR3),
398 	PINMUX_IPSR_GPSR(IP0_7_4,	HRTS0_N),
399 	PINMUX_IPSR_GPSR(IP0_7_4,	A1),
400 
401 	PINMUX_IPSR_GPSR(IP0_11_8,	DU_DR4),
402 	PINMUX_IPSR_GPSR(IP0_11_8,	HCTS0_N),
403 	PINMUX_IPSR_GPSR(IP0_11_8,	A2),
404 
405 	PINMUX_IPSR_GPSR(IP0_15_12,	DU_DR5),
406 	PINMUX_IPSR_GPSR(IP0_15_12,	HTX0),
407 	PINMUX_IPSR_GPSR(IP0_15_12,	A3),
408 
409 	PINMUX_IPSR_GPSR(IP0_19_16,	DU_DR6),
410 	PINMUX_IPSR_GPSR(IP0_19_16,	MSIOF3_RXD),
411 	PINMUX_IPSR_GPSR(IP0_19_16,	A4),
412 
413 	PINMUX_IPSR_GPSR(IP0_23_20,	DU_DR7),
414 	PINMUX_IPSR_GPSR(IP0_23_20,	MSIOF3_TXD),
415 	PINMUX_IPSR_GPSR(IP0_23_20,	A5),
416 
417 	PINMUX_IPSR_GPSR(IP0_27_24,	DU_DG2),
418 	PINMUX_IPSR_GPSR(IP0_27_24,	MSIOF3_SS1),
419 	PINMUX_IPSR_GPSR(IP0_27_24,	A6),
420 
421 	PINMUX_IPSR_GPSR(IP0_31_28,	DU_DG3),
422 	PINMUX_IPSR_GPSR(IP0_31_28,	MSIOF3_SS2),
423 	PINMUX_IPSR_GPSR(IP0_31_28,	A7),
424 	PINMUX_IPSR_GPSR(IP0_31_28,	PWMFSW0),
425 
426 	/* IPSR1 */
427 	PINMUX_IPSR_GPSR(IP1_3_0,	DU_DG4),
428 	PINMUX_IPSR_GPSR(IP1_3_0,	A8),
429 	PINMUX_IPSR_MSEL(IP1_3_0,	FSO_CFE_0_N_A,	SEL_RFSO_0),
430 
431 	PINMUX_IPSR_GPSR(IP1_7_4,	DU_DG5),
432 	PINMUX_IPSR_GPSR(IP1_7_4,	A9),
433 	PINMUX_IPSR_MSEL(IP1_7_4,	FSO_CFE_1_N_A,	SEL_RFSO_0),
434 
435 	PINMUX_IPSR_GPSR(IP1_11_8,	DU_DG6),
436 	PINMUX_IPSR_GPSR(IP1_11_8,	A10),
437 	PINMUX_IPSR_MSEL(IP1_11_8,	FSO_TOE_N_A,	SEL_RFSO_0),
438 
439 	PINMUX_IPSR_GPSR(IP1_15_12,	DU_DG7),
440 	PINMUX_IPSR_GPSR(IP1_15_12,	A11),
441 	PINMUX_IPSR_GPSR(IP1_15_12,	IRQ1),
442 
443 	PINMUX_IPSR_GPSR(IP1_19_16,	DU_DB2),
444 	PINMUX_IPSR_GPSR(IP1_19_16,	A12),
445 	PINMUX_IPSR_GPSR(IP1_19_16,	IRQ2),
446 
447 	PINMUX_IPSR_GPSR(IP1_23_20,	DU_DB3),
448 	PINMUX_IPSR_GPSR(IP1_23_20,	A13),
449 	PINMUX_IPSR_GPSR(IP1_23_20,	FXR_CLKOUT1),
450 
451 	PINMUX_IPSR_GPSR(IP1_27_24,	DU_DB4),
452 	PINMUX_IPSR_GPSR(IP1_27_24,	A14),
453 	PINMUX_IPSR_GPSR(IP1_27_24,	FXR_CLKOUT2),
454 
455 	PINMUX_IPSR_GPSR(IP1_31_28,	DU_DB5),
456 	PINMUX_IPSR_GPSR(IP1_31_28,	A15),
457 	PINMUX_IPSR_GPSR(IP1_31_28,	FXR_TXENA_N),
458 
459 	/* IPSR2 */
460 	PINMUX_IPSR_GPSR(IP2_3_0,	DU_DB6),
461 	PINMUX_IPSR_GPSR(IP2_3_0,	A16),
462 	PINMUX_IPSR_GPSR(IP2_3_0,	FXR_TXENB_N),
463 
464 	PINMUX_IPSR_GPSR(IP2_7_4,	DU_DB7),
465 	PINMUX_IPSR_GPSR(IP2_7_4,	A17),
466 
467 	PINMUX_IPSR_GPSR(IP2_11_8,	DU_DOTCLKOUT),
468 	PINMUX_IPSR_MSEL(IP2_11_8,	SCIF_CLK_A,	SEL_HSCIF0_0),
469 	PINMUX_IPSR_GPSR(IP2_11_8,	A18),
470 
471 	PINMUX_IPSR_GPSR(IP2_15_12,	DU_EXHSYNC_DU_HSYNC),
472 	PINMUX_IPSR_GPSR(IP2_15_12,	HRX0),
473 	PINMUX_IPSR_GPSR(IP2_15_12,	A19),
474 	PINMUX_IPSR_GPSR(IP2_15_12,	IRQ3),
475 
476 	PINMUX_IPSR_GPSR(IP2_19_16,	DU_EXVSYNC_DU_VSYNC),
477 	PINMUX_IPSR_GPSR(IP2_19_16,	MSIOF3_SCK),
478 
479 	PINMUX_IPSR_GPSR(IP2_23_20,	DU_EXODDF_DU_ODDF_DISP_CDE),
480 	PINMUX_IPSR_GPSR(IP2_23_20,	MSIOF3_SYNC),
481 
482 	PINMUX_IPSR_GPSR(IP2_27_24,	IRQ0),
483 
484 	PINMUX_IPSR_GPSR(IP2_31_28,	VI0_CLK),
485 	PINMUX_IPSR_GPSR(IP2_31_28,	MSIOF2_SCK),
486 	PINMUX_IPSR_GPSR(IP2_31_28,	SCK3),
487 	PINMUX_IPSR_GPSR(IP2_31_28,	HSCK3),
488 
489 	/* IPSR3 */
490 	PINMUX_IPSR_GPSR(IP3_3_0,	VI0_CLKENB),
491 	PINMUX_IPSR_GPSR(IP3_3_0,	MSIOF2_RXD),
492 	PINMUX_IPSR_GPSR(IP3_3_0,	RX3),
493 	PINMUX_IPSR_GPSR(IP3_3_0,	RD_WR_N),
494 	PINMUX_IPSR_GPSR(IP3_3_0,	HCTS3_N),
495 
496 	PINMUX_IPSR_GPSR(IP3_7_4,	VI0_HSYNC_N),
497 	PINMUX_IPSR_GPSR(IP3_7_4,	MSIOF2_TXD),
498 	PINMUX_IPSR_GPSR(IP3_7_4,	TX3),
499 	PINMUX_IPSR_GPSR(IP3_7_4,	HRTS3_N),
500 
501 	PINMUX_IPSR_GPSR(IP3_11_8,	VI0_VSYNC_N),
502 	PINMUX_IPSR_GPSR(IP3_11_8,	MSIOF2_SYNC),
503 	PINMUX_IPSR_GPSR(IP3_11_8,	CTS3_N),
504 	PINMUX_IPSR_GPSR(IP3_11_8,	HTX3),
505 
506 	PINMUX_IPSR_GPSR(IP3_15_12,	VI0_DATA0),
507 	PINMUX_IPSR_GPSR(IP3_15_12,	MSIOF2_SS1),
508 	PINMUX_IPSR_GPSR(IP3_15_12,	RTS3_N),
509 	PINMUX_IPSR_GPSR(IP3_15_12,	HRX3),
510 
511 	PINMUX_IPSR_GPSR(IP3_19_16,	VI0_DATA1),
512 	PINMUX_IPSR_GPSR(IP3_19_16,	MSIOF2_SS2),
513 	PINMUX_IPSR_GPSR(IP3_19_16,	SCK1),
514 	PINMUX_IPSR_MSEL(IP3_19_16,	SPEEDIN_A,	SEL_RSP_0),
515 
516 	PINMUX_IPSR_GPSR(IP3_23_20,	VI0_DATA2),
517 	PINMUX_IPSR_GPSR(IP3_23_20,	AVB0_AVTP_PPS),
518 	PINMUX_IPSR_MSEL(IP3_23_20,	SDA3_A,		SEL_I2C3_0),
519 
520 	PINMUX_IPSR_GPSR(IP3_27_24,	VI0_DATA3),
521 	PINMUX_IPSR_GPSR(IP3_27_24,	HSCK1),
522 	PINMUX_IPSR_MSEL(IP3_27_24,	SCL3_A,		SEL_I2C3_0),
523 
524 	PINMUX_IPSR_GPSR(IP3_31_28,	VI0_DATA4),
525 	PINMUX_IPSR_GPSR(IP3_31_28,	HRTS1_N),
526 	PINMUX_IPSR_MSEL(IP3_31_28,	RX1_A,	SEL_SCIF1_0),
527 
528 	/* IPSR4 */
529 	PINMUX_IPSR_GPSR(IP4_3_0,	VI0_DATA5),
530 	PINMUX_IPSR_GPSR(IP4_3_0,	HCTS1_N),
531 	PINMUX_IPSR_MSEL(IP4_3_0,	TX1_A,	SEL_SCIF1_0),
532 
533 	PINMUX_IPSR_GPSR(IP4_7_4,	VI0_DATA6),
534 	PINMUX_IPSR_GPSR(IP4_7_4,	HTX1),
535 	PINMUX_IPSR_GPSR(IP4_7_4,	CTS1_N),
536 
537 	PINMUX_IPSR_GPSR(IP4_11_8,	VI0_DATA7),
538 	PINMUX_IPSR_GPSR(IP4_11_8,	HRX1),
539 	PINMUX_IPSR_GPSR(IP4_11_8,	RTS1_N),
540 
541 	PINMUX_IPSR_GPSR(IP4_15_12,	VI0_DATA8),
542 	PINMUX_IPSR_GPSR(IP4_15_12,	HSCK2),
543 	PINMUX_IPSR_MSEL(IP4_15_12,	PWM0_A,	SEL_PWM0_0),
544 
545 	PINMUX_IPSR_GPSR(IP4_19_16,	VI0_DATA9),
546 	PINMUX_IPSR_GPSR(IP4_19_16,	HCTS2_N),
547 	PINMUX_IPSR_MSEL(IP4_19_16,	PWM1_A,	SEL_PWM1_0),
548 	PINMUX_IPSR_MSEL(IP4_19_16,	FSO_CFE_0_N_B,	SEL_RFSO_1),
549 
550 	PINMUX_IPSR_GPSR(IP4_23_20,	VI0_DATA10),
551 	PINMUX_IPSR_GPSR(IP4_23_20,	HRTS2_N),
552 	PINMUX_IPSR_MSEL(IP4_23_20,	PWM2_A,	SEL_PWM2_0),
553 	PINMUX_IPSR_MSEL(IP4_23_20,	FSO_CFE_1_N_B,	SEL_RFSO_1),
554 
555 	PINMUX_IPSR_GPSR(IP4_27_24,	VI0_DATA11),
556 	PINMUX_IPSR_GPSR(IP4_27_24,	HTX2),
557 	PINMUX_IPSR_MSEL(IP4_27_24,	PWM3_A,	SEL_PWM3_0),
558 	PINMUX_IPSR_MSEL(IP4_27_24,	FSO_TOE_N_B,	SEL_RFSO_1),
559 
560 	PINMUX_IPSR_GPSR(IP4_31_28,	VI0_FIELD),
561 	PINMUX_IPSR_GPSR(IP4_31_28,	HRX2),
562 	PINMUX_IPSR_MSEL(IP4_31_28,	PWM4_A,	SEL_PWM4_0),
563 	PINMUX_IPSR_GPSR(IP4_31_28,	CS1_N),
564 	PINMUX_IPSR_GPSR(IP4_31_28,	FSCLKST2_N_A),
565 
566 	/* IPSR5 */
567 	PINMUX_IPSR_GPSR(IP5_3_0,	VI1_CLK),
568 	PINMUX_IPSR_GPSR(IP5_3_0,	MSIOF1_RXD),
569 	PINMUX_IPSR_GPSR(IP5_3_0,	CS0_N),
570 
571 	PINMUX_IPSR_GPSR(IP5_7_4,	VI1_CLKENB),
572 	PINMUX_IPSR_GPSR(IP5_7_4,	MSIOF1_TXD),
573 	PINMUX_IPSR_GPSR(IP5_7_4,	D0),
574 
575 	PINMUX_IPSR_GPSR(IP5_11_8,	VI1_HSYNC_N),
576 	PINMUX_IPSR_GPSR(IP5_11_8,	MSIOF1_SCK),
577 	PINMUX_IPSR_GPSR(IP5_11_8,	D1),
578 
579 	PINMUX_IPSR_GPSR(IP5_15_12,	VI1_VSYNC_N),
580 	PINMUX_IPSR_GPSR(IP5_15_12,	MSIOF1_SYNC),
581 	PINMUX_IPSR_GPSR(IP5_15_12,	D2),
582 
583 	PINMUX_IPSR_GPSR(IP5_19_16,	VI1_DATA0),
584 	PINMUX_IPSR_GPSR(IP5_19_16,	MSIOF1_SS1),
585 	PINMUX_IPSR_GPSR(IP5_19_16,	D3),
586 
587 	PINMUX_IPSR_GPSR(IP5_23_20,	VI1_DATA1),
588 	PINMUX_IPSR_GPSR(IP5_23_20,	MSIOF1_SS2),
589 	PINMUX_IPSR_GPSR(IP5_23_20,	D4),
590 	PINMUX_IPSR_GPSR(IP5_23_20,	MMC_CMD),
591 
592 	PINMUX_IPSR_GPSR(IP5_27_24,	VI1_DATA2),
593 	PINMUX_IPSR_MSEL(IP5_27_24,	CANFD0_TX_B,	SEL_CANFD0_1),
594 	PINMUX_IPSR_GPSR(IP5_27_24,	D5),
595 	PINMUX_IPSR_GPSR(IP5_27_24,	MMC_D0),
596 
597 	PINMUX_IPSR_GPSR(IP5_31_28,	VI1_DATA3),
598 	PINMUX_IPSR_MSEL(IP5_31_28,	CANFD0_RX_B,	SEL_CANFD0_1),
599 	PINMUX_IPSR_GPSR(IP5_31_28,	D6),
600 	PINMUX_IPSR_GPSR(IP5_31_28,	MMC_D1),
601 
602 	/* IPSR6 */
603 	PINMUX_IPSR_GPSR(IP6_3_0,	VI1_DATA4),
604 	PINMUX_IPSR_MSEL(IP6_3_0,	CANFD_CLK_B,	SEL_CANFD0_1),
605 	PINMUX_IPSR_GPSR(IP6_3_0,	D7),
606 	PINMUX_IPSR_GPSR(IP6_3_0,	MMC_D2),
607 
608 	PINMUX_IPSR_GPSR(IP6_7_4,	VI1_DATA5),
609 	PINMUX_IPSR_GPSR(IP6_7_4,	SCK4),
610 	PINMUX_IPSR_GPSR(IP6_7_4,	D8),
611 	PINMUX_IPSR_GPSR(IP6_7_4,	MMC_D3),
612 
613 	PINMUX_IPSR_GPSR(IP6_11_8,	VI1_DATA6),
614 	PINMUX_IPSR_GPSR(IP6_11_8,	RX4),
615 	PINMUX_IPSR_GPSR(IP6_11_8,	D9),
616 	PINMUX_IPSR_GPSR(IP6_11_8,	MMC_CLK),
617 
618 	PINMUX_IPSR_GPSR(IP6_15_12,	VI1_DATA7),
619 	PINMUX_IPSR_GPSR(IP6_15_12,	TX4),
620 	PINMUX_IPSR_GPSR(IP6_15_12,	D10),
621 	PINMUX_IPSR_GPSR(IP6_15_12,	MMC_D4),
622 
623 	PINMUX_IPSR_GPSR(IP6_19_16,	VI1_DATA8),
624 	PINMUX_IPSR_GPSR(IP6_19_16,	CTS4_N),
625 	PINMUX_IPSR_GPSR(IP6_19_16,	D11),
626 	PINMUX_IPSR_GPSR(IP6_19_16,	MMC_D5),
627 
628 	PINMUX_IPSR_GPSR(IP6_23_20,	VI1_DATA9),
629 	PINMUX_IPSR_GPSR(IP6_23_20,	RTS4_N),
630 	PINMUX_IPSR_GPSR(IP6_23_20,	D12),
631 	PINMUX_IPSR_GPSR(IP6_23_20,	MMC_D6),
632 	PINMUX_IPSR_MSEL(IP6_23_20,	SCL3_B,	SEL_I2C3_1),
633 
634 	PINMUX_IPSR_GPSR(IP6_27_24,	VI1_DATA10),
635 	PINMUX_IPSR_GPSR(IP6_27_24,	D13),
636 	PINMUX_IPSR_GPSR(IP6_27_24,	MMC_D7),
637 	PINMUX_IPSR_MSEL(IP6_27_24,	SDA3_B,	SEL_I2C3_1),
638 
639 	PINMUX_IPSR_GPSR(IP6_31_28,	VI1_DATA11),
640 	PINMUX_IPSR_GPSR(IP6_31_28,	SCL4),
641 	PINMUX_IPSR_GPSR(IP6_31_28,	IRQ4),
642 	PINMUX_IPSR_GPSR(IP6_31_28,	D14),
643 
644 	/* IPSR7 */
645 	PINMUX_IPSR_GPSR(IP7_3_0,	VI1_FIELD),
646 	PINMUX_IPSR_GPSR(IP7_3_0,	SDA4),
647 	PINMUX_IPSR_GPSR(IP7_3_0,	IRQ5),
648 	PINMUX_IPSR_GPSR(IP7_3_0,	D15),
649 
650 	PINMUX_IPSR_GPSR(IP7_7_4,	SCL0),
651 	PINMUX_IPSR_GPSR(IP7_7_4,	DU_DR0),
652 	PINMUX_IPSR_GPSR(IP7_7_4,	TPU0TO0),
653 	PINMUX_IPSR_GPSR(IP7_7_4,	CLKOUT),
654 	PINMUX_IPSR_GPSR(IP7_7_4,	MSIOF0_RXD),
655 
656 	PINMUX_IPSR_GPSR(IP7_11_8,	SDA0),
657 	PINMUX_IPSR_GPSR(IP7_11_8,	DU_DR1),
658 	PINMUX_IPSR_GPSR(IP7_11_8,	TPU0TO1),
659 	PINMUX_IPSR_GPSR(IP7_11_8,	BS_N),
660 	PINMUX_IPSR_GPSR(IP7_11_8,	SCK0),
661 	PINMUX_IPSR_GPSR(IP7_11_8,	MSIOF0_TXD),
662 
663 	PINMUX_IPSR_GPSR(IP7_15_12,	SCL1),
664 	PINMUX_IPSR_GPSR(IP7_15_12,	DU_DG0),
665 	PINMUX_IPSR_GPSR(IP7_15_12,	TPU0TO2),
666 	PINMUX_IPSR_GPSR(IP7_15_12,	RD_N),
667 	PINMUX_IPSR_GPSR(IP7_15_12,	CTS0_N),
668 	PINMUX_IPSR_GPSR(IP7_15_12,	MSIOF0_SCK),
669 
670 	PINMUX_IPSR_GPSR(IP7_19_16,	SDA1),
671 	PINMUX_IPSR_GPSR(IP7_19_16,	DU_DG1),
672 	PINMUX_IPSR_GPSR(IP7_19_16,	TPU0TO3),
673 	PINMUX_IPSR_GPSR(IP7_19_16,	WE0_N),
674 	PINMUX_IPSR_GPSR(IP7_19_16,	RTS0_N),
675 	PINMUX_IPSR_GPSR(IP7_19_16,	MSIOF0_SYNC),
676 
677 	PINMUX_IPSR_GPSR(IP7_23_20,	SCL2),
678 	PINMUX_IPSR_GPSR(IP7_23_20,	DU_DB0),
679 	PINMUX_IPSR_MSEL(IP7_23_20,	TCLK1_A,	SEL_TMU_0),
680 	PINMUX_IPSR_GPSR(IP7_23_20,	WE1_N),
681 	PINMUX_IPSR_GPSR(IP7_23_20,	RX0),
682 	PINMUX_IPSR_GPSR(IP7_23_20,	MSIOF0_SS1),
683 
684 	PINMUX_IPSR_GPSR(IP7_27_24,	SDA2),
685 	PINMUX_IPSR_GPSR(IP7_27_24,	DU_DB1),
686 	PINMUX_IPSR_MSEL(IP7_27_24,	TCLK2_A,	SEL_TMU_0),
687 	PINMUX_IPSR_GPSR(IP7_27_24,	EX_WAIT0),
688 	PINMUX_IPSR_GPSR(IP7_27_24,	TX0),
689 	PINMUX_IPSR_GPSR(IP7_27_24,	MSIOF0_SS2),
690 
691 	PINMUX_IPSR_GPSR(IP7_31_28,	AVB0_AVTP_CAPTURE),
692 	PINMUX_IPSR_GPSR(IP7_31_28,	FSCLKST2_N_B),
693 
694 	/* IPSR8 */
695 	PINMUX_IPSR_MSEL(IP8_3_0,	CANFD0_TX_A,	SEL_CANFD0_0),
696 	PINMUX_IPSR_GPSR(IP8_3_0,	FXR_TXDA),
697 	PINMUX_IPSR_MSEL(IP8_3_0,	PWM0_B,		SEL_PWM0_1),
698 	PINMUX_IPSR_GPSR(IP8_3_0,	DU_DISP),
699 	PINMUX_IPSR_GPSR(IP8_3_0,	FSCLKST2_N_C),
700 
701 	PINMUX_IPSR_MSEL(IP8_7_4,	CANFD0_RX_A,	SEL_CANFD0_0),
702 	PINMUX_IPSR_GPSR(IP8_7_4,	RXDA_EXTFXR),
703 	PINMUX_IPSR_MSEL(IP8_7_4,	PWM1_B,		SEL_PWM1_1),
704 	PINMUX_IPSR_GPSR(IP8_7_4,	DU_CDE),
705 
706 	PINMUX_IPSR_GPSR(IP8_11_8,	CANFD1_TX),
707 	PINMUX_IPSR_GPSR(IP8_11_8,	FXR_TXDB),
708 	PINMUX_IPSR_MSEL(IP8_11_8,	PWM2_B,		SEL_PWM2_1),
709 	PINMUX_IPSR_MSEL(IP8_11_8,	TCLK1_B,	SEL_TMU_1),
710 	PINMUX_IPSR_MSEL(IP8_11_8,	TX1_B,		SEL_SCIF1_1),
711 
712 	PINMUX_IPSR_GPSR(IP8_15_12,	CANFD1_RX),
713 	PINMUX_IPSR_GPSR(IP8_15_12,	RXDB_EXTFXR),
714 	PINMUX_IPSR_MSEL(IP8_15_12,	PWM3_B,		SEL_PWM3_1),
715 	PINMUX_IPSR_MSEL(IP8_15_12,	TCLK2_B,	SEL_TMU_1),
716 	PINMUX_IPSR_MSEL(IP8_15_12,	RX1_B,		SEL_SCIF1_1),
717 
718 	PINMUX_IPSR_MSEL(IP8_19_16,	CANFD_CLK_A,	SEL_CANFD0_0),
719 	PINMUX_IPSR_GPSR(IP8_19_16,	CLK_EXTFXR),
720 	PINMUX_IPSR_MSEL(IP8_19_16,	PWM4_B,		SEL_PWM4_1),
721 	PINMUX_IPSR_MSEL(IP8_19_16,	SPEEDIN_B,	SEL_RSP_1),
722 	PINMUX_IPSR_MSEL(IP8_19_16,	SCIF_CLK_B,	SEL_HSCIF0_1),
723 
724 	PINMUX_IPSR_GPSR(IP8_23_20,	DIGRF_CLKIN),
725 	PINMUX_IPSR_GPSR(IP8_23_20,	DIGRF_CLKEN_IN),
726 
727 	PINMUX_IPSR_GPSR(IP8_27_24,	DIGRF_CLKOUT),
728 	PINMUX_IPSR_GPSR(IP8_27_24,	DIGRF_CLKEN_OUT),
729 };
730 
731 /*
732  * Pins not associated with a GPIO port.
733  */
734 enum {
735 	GP_ASSIGN_LAST(),
736 	NOGP_ALL(),
737 };
738 
739 static const struct sh_pfc_pin pinmux_pins[] = {
740 	PINMUX_GPIO_GP_ALL(),
741 	PINMUX_NOGP_ALL(),
742 };
743 
744 /* - AVB0 ------------------------------------------------------------------- */
745 static const unsigned int avb0_link_pins[] = {
746 	/* AVB0_LINK */
747 	RCAR_GP_PIN(1, 18),
748 };
749 static const unsigned int avb0_link_mux[] = {
750 	AVB0_LINK_MARK,
751 };
752 static const unsigned int avb0_magic_pins[] = {
753 	/* AVB0_MAGIC */
754 	RCAR_GP_PIN(1, 16),
755 };
756 static const unsigned int avb0_magic_mux[] = {
757 	AVB0_MAGIC_MARK,
758 };
759 static const unsigned int avb0_phy_int_pins[] = {
760 	/* AVB0_PHY_INT */
761 	RCAR_GP_PIN(1, 17),
762 };
763 static const unsigned int avb0_phy_int_mux[] = {
764 	AVB0_PHY_INT_MARK,
765 };
766 static const unsigned int avb0_mdio_pins[] = {
767 	/* AVB0_MDC, AVB0_MDIO */
768 	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
769 };
770 static const unsigned int avb0_mdio_mux[] = {
771 	AVB0_MDC_MARK, AVB0_MDIO_MARK,
772 };
773 static const unsigned int avb0_rgmii_pins[] = {
774 	/*
775 	 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
776 	 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3
777 	 */
778 	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
779 	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
780 	RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
781 	RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
782 	RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
783 	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
784 };
785 static const unsigned int avb0_rgmii_mux[] = {
786 	AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
787 	AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
788 	AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
789 	AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
790 };
791 static const unsigned int avb0_txcrefclk_pins[] = {
792 	/* AVB0_TXCREFCLK */
793 	RCAR_GP_PIN(1, 13),
794 };
795 static const unsigned int avb0_txcrefclk_mux[] = {
796 	AVB0_TXCREFCLK_MARK,
797 };
798 static const unsigned int avb0_avtp_pps_pins[] = {
799 	/* AVB0_AVTP_PPS */
800 	RCAR_GP_PIN(2, 6),
801 };
802 static const unsigned int avb0_avtp_pps_mux[] = {
803 	AVB0_AVTP_PPS_MARK,
804 };
805 static const unsigned int avb0_avtp_capture_pins[] = {
806 	/* AVB0_AVTP_CAPTURE */
807 	RCAR_GP_PIN(1, 20),
808 };
809 static const unsigned int avb0_avtp_capture_mux[] = {
810 	AVB0_AVTP_CAPTURE_MARK,
811 };
812 static const unsigned int avb0_avtp_match_pins[] = {
813 	/* AVB0_AVTP_MATCH */
814 	RCAR_GP_PIN(1, 19),
815 };
816 static const unsigned int avb0_avtp_match_mux[] = {
817 	AVB0_AVTP_MATCH_MARK,
818 };
819 
820 /* - CANFD Clock ------------------------------------------------------------ */
821 static const unsigned int canfd_clk_a_pins[] = {
822 	/* CANFD_CLK */
823 	RCAR_GP_PIN(1, 25),
824 };
825 static const unsigned int canfd_clk_a_mux[] = {
826 	CANFD_CLK_A_MARK,
827 };
828 static const unsigned int canfd_clk_b_pins[] = {
829 	/* CANFD_CLK */
830 	RCAR_GP_PIN(3, 8),
831 };
832 static const unsigned int canfd_clk_b_mux[] = {
833 	CANFD_CLK_B_MARK,
834 };
835 
836 /* - CANFD0 ----------------------------------------------------------------- */
837 static const unsigned int canfd0_data_a_pins[] = {
838 	/* TX, RX */
839 	RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
840 };
841 static const unsigned int canfd0_data_a_mux[] = {
842 	CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
843 };
844 static const unsigned int canfd0_data_b_pins[] = {
845 	/* TX, RX */
846 	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
847 };
848 static const unsigned int canfd0_data_b_mux[] = {
849 	CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
850 };
851 
852 /* - CANFD1 ----------------------------------------------------------------- */
853 static const unsigned int canfd1_data_pins[] = {
854 	/* TX, RX */
855 	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
856 };
857 static const unsigned int canfd1_data_mux[] = {
858 	CANFD1_TX_MARK, CANFD1_RX_MARK,
859 };
860 
861 /* - DU --------------------------------------------------------------------- */
862 static const unsigned int du_rgb666_pins[] = {
863 	/* R[7:2], G[7:2], B[7:2] */
864 	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
865 	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
866 	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
867 	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
868 	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
869 	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
870 };
871 static const unsigned int du_rgb666_mux[] = {
872 	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
873 	DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
874 	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
875 	DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
876 	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
877 	DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
878 };
879 static const unsigned int du_clk_out_pins[] = {
880 	/* DOTCLKOUT */
881 	RCAR_GP_PIN(0, 18),
882 };
883 static const unsigned int du_clk_out_mux[] = {
884 	DU_DOTCLKOUT_MARK,
885 };
886 static const unsigned int du_sync_pins[] = {
887 	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
888 	RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
889 };
890 static const unsigned int du_sync_mux[] = {
891 	DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
892 };
893 static const unsigned int du_oddf_pins[] = {
894 	/* EXODDF/ODDF/DISP/CDE */
895 	RCAR_GP_PIN(0, 21),
896 };
897 static const unsigned int du_oddf_mux[] = {
898 	DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
899 };
900 static const unsigned int du_cde_pins[] = {
901 	/* CDE */
902 	RCAR_GP_PIN(1, 22),
903 };
904 static const unsigned int du_cde_mux[] = {
905 	DU_CDE_MARK,
906 };
907 static const unsigned int du_disp_pins[] = {
908 	/* DISP */
909 	RCAR_GP_PIN(1, 21),
910 };
911 static const unsigned int du_disp_mux[] = {
912 	DU_DISP_MARK,
913 };
914 
915 /* - HSCIF0 ----------------------------------------------------------------- */
916 static const unsigned int hscif0_data_pins[] = {
917 	/* HRX, HTX */
918 	RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 3),
919 };
920 static const unsigned int hscif0_data_mux[] = {
921 	HRX0_MARK, HTX0_MARK,
922 };
923 static const unsigned int hscif0_clk_pins[] = {
924 	/* HSCK */
925 	RCAR_GP_PIN(0, 0),
926 };
927 static const unsigned int hscif0_clk_mux[] = {
928 	HSCK0_MARK,
929 };
930 static const unsigned int hscif0_ctrl_pins[] = {
931 	/* HRTS#, HCTS# */
932 	RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
933 };
934 static const unsigned int hscif0_ctrl_mux[] = {
935 	HRTS0_N_MARK, HCTS0_N_MARK,
936 };
937 
938 /* - HSCIF1 ----------------------------------------------------------------- */
939 static const unsigned int hscif1_data_pins[] = {
940 	/* HRX, HTX */
941 	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
942 };
943 static const unsigned int hscif1_data_mux[] = {
944 	HRX1_MARK, HTX1_MARK,
945 };
946 static const unsigned int hscif1_clk_pins[] = {
947 	/* HSCK */
948 	RCAR_GP_PIN(2, 7),
949 };
950 static const unsigned int hscif1_clk_mux[] = {
951 	HSCK1_MARK,
952 };
953 static const unsigned int hscif1_ctrl_pins[] = {
954 	/* HRTS#, HCTS# */
955 	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
956 };
957 static const unsigned int hscif1_ctrl_mux[] = {
958 	HRTS1_N_MARK, HCTS1_N_MARK,
959 };
960 
961 /* - HSCIF2 ----------------------------------------------------------------- */
962 static const unsigned int hscif2_data_pins[] = {
963 	/* HRX, HTX */
964 	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
965 };
966 static const unsigned int hscif2_data_mux[] = {
967 	HRX2_MARK, HTX2_MARK,
968 };
969 static const unsigned int hscif2_clk_pins[] = {
970 	/* HSCK */
971 	RCAR_GP_PIN(2, 12),
972 };
973 static const unsigned int hscif2_clk_mux[] = {
974 	HSCK2_MARK,
975 };
976 static const unsigned int hscif2_ctrl_pins[] = {
977 	/* HRTS#, HCTS# */
978 	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
979 };
980 static const unsigned int hscif2_ctrl_mux[] = {
981 	HRTS2_N_MARK, HCTS2_N_MARK,
982 };
983 
984 /* - HSCIF3 ----------------------------------------------------------------- */
985 static const unsigned int hscif3_data_pins[] = {
986 	/* HRX, HTX */
987 	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
988 };
989 static const unsigned int hscif3_data_mux[] = {
990 	HRX3_MARK, HTX3_MARK,
991 };
992 static const unsigned int hscif3_clk_pins[] = {
993 	/* HSCK */
994 	RCAR_GP_PIN(2, 0),
995 };
996 static const unsigned int hscif3_clk_mux[] = {
997 	HSCK3_MARK,
998 };
999 static const unsigned int hscif3_ctrl_pins[] = {
1000 	/* HRTS#, HCTS# */
1001 	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
1002 };
1003 static const unsigned int hscif3_ctrl_mux[] = {
1004 	HRTS3_N_MARK, HCTS3_N_MARK,
1005 };
1006 
1007 /* - I2C0 ------------------------------------------------------------------- */
1008 static const unsigned int i2c0_pins[] = {
1009 	/* SDA, SCL */
1010 	RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
1011 };
1012 static const unsigned int i2c0_mux[] = {
1013 	SDA0_MARK, SCL0_MARK,
1014 };
1015 
1016 /* - I2C1 ------------------------------------------------------------------- */
1017 static const unsigned int i2c1_pins[] = {
1018 	/* SDA, SCL */
1019 	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1020 };
1021 static const unsigned int i2c1_mux[] = {
1022 	SDA1_MARK, SCL1_MARK,
1023 };
1024 
1025 /* - I2C2 ------------------------------------------------------------------- */
1026 static const unsigned int i2c2_pins[] = {
1027 	/* SDA, SCL */
1028 	RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1029 };
1030 static const unsigned int i2c2_mux[] = {
1031 	SDA2_MARK, SCL2_MARK,
1032 };
1033 
1034 /* - I2C3 ------------------------------------------------------------------- */
1035 static const unsigned int i2c3_a_pins[] = {
1036 	/* SDA, SCL */
1037 	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1038 };
1039 static const unsigned int i2c3_a_mux[] = {
1040 	SDA3_A_MARK, SCL3_A_MARK,
1041 };
1042 static const unsigned int i2c3_b_pins[] = {
1043 	/* SDA, SCL */
1044 	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1045 };
1046 static const unsigned int i2c3_b_mux[] = {
1047 	SDA3_B_MARK, SCL3_B_MARK,
1048 };
1049 
1050 /* - I2C4 ------------------------------------------------------------------- */
1051 static const unsigned int i2c4_pins[] = {
1052 	/* SDA, SCL */
1053 	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
1054 };
1055 static const unsigned int i2c4_mux[] = {
1056 	SDA4_MARK, SCL4_MARK,
1057 };
1058 
1059 /* - INTC-EX ---------------------------------------------------------------- */
1060 static const unsigned int intc_ex_irq0_pins[] = {
1061 	/* IRQ0 */
1062 	RCAR_GP_PIN(1, 0),
1063 };
1064 static const unsigned int intc_ex_irq0_mux[] = {
1065 	IRQ0_MARK,
1066 };
1067 static const unsigned int intc_ex_irq1_pins[] = {
1068 	/* IRQ1 */
1069 	RCAR_GP_PIN(0, 11),
1070 };
1071 static const unsigned int intc_ex_irq1_mux[] = {
1072 	IRQ1_MARK,
1073 };
1074 static const unsigned int intc_ex_irq2_pins[] = {
1075 	/* IRQ2 */
1076 	RCAR_GP_PIN(0, 12),
1077 };
1078 static const unsigned int intc_ex_irq2_mux[] = {
1079 	IRQ2_MARK,
1080 };
1081 static const unsigned int intc_ex_irq3_pins[] = {
1082 	/* IRQ3 */
1083 	RCAR_GP_PIN(0, 19),
1084 };
1085 static const unsigned int intc_ex_irq3_mux[] = {
1086 	IRQ3_MARK,
1087 };
1088 static const unsigned int intc_ex_irq4_pins[] = {
1089 	/* IRQ4 */
1090 	RCAR_GP_PIN(3, 15),
1091 };
1092 static const unsigned int intc_ex_irq4_mux[] = {
1093 	IRQ4_MARK,
1094 };
1095 static const unsigned int intc_ex_irq5_pins[] = {
1096 	/* IRQ5 */
1097 	RCAR_GP_PIN(3, 16),
1098 };
1099 static const unsigned int intc_ex_irq5_mux[] = {
1100 	IRQ5_MARK,
1101 };
1102 
1103 /* - MMC -------------------------------------------------------------------- */
1104 static const unsigned int mmc_data_pins[] = {
1105 	/* D[0:7] */
1106 	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1107 	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1108 	RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1109 	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1110 };
1111 static const unsigned int mmc_data_mux[] = {
1112 	MMC_D0_MARK, MMC_D1_MARK,
1113 	MMC_D2_MARK, MMC_D3_MARK,
1114 	MMC_D4_MARK, MMC_D5_MARK,
1115 	MMC_D6_MARK, MMC_D7_MARK,
1116 };
1117 static const unsigned int mmc_ctrl_pins[] = {
1118 	/* CLK, CMD */
1119 	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 5),
1120 };
1121 static const unsigned int mmc_ctrl_mux[] = {
1122 	MMC_CLK_MARK, MMC_CMD_MARK,
1123 };
1124 
1125 /* - MSIOF0 ----------------------------------------------------------------- */
1126 static const unsigned int msiof0_clk_pins[] = {
1127 	/* SCK */
1128 	RCAR_GP_PIN(4, 2),
1129 };
1130 static const unsigned int msiof0_clk_mux[] = {
1131 	MSIOF0_SCK_MARK,
1132 };
1133 static const unsigned int msiof0_sync_pins[] = {
1134 	/* SYNC */
1135 	RCAR_GP_PIN(4, 3),
1136 };
1137 static const unsigned int msiof0_sync_mux[] = {
1138 	MSIOF0_SYNC_MARK,
1139 };
1140 static const unsigned int msiof0_ss1_pins[] = {
1141 	/* SS1 */
1142 	RCAR_GP_PIN(4, 4),
1143 };
1144 static const unsigned int msiof0_ss1_mux[] = {
1145 	MSIOF0_SS1_MARK,
1146 };
1147 static const unsigned int msiof0_ss2_pins[] = {
1148 	/* SS2 */
1149 	RCAR_GP_PIN(4, 5),
1150 };
1151 static const unsigned int msiof0_ss2_mux[] = {
1152 	MSIOF0_SS2_MARK,
1153 };
1154 static const unsigned int msiof0_txd_pins[] = {
1155 	/* TXD */
1156 	RCAR_GP_PIN(4, 1),
1157 };
1158 static const unsigned int msiof0_txd_mux[] = {
1159 	MSIOF0_TXD_MARK,
1160 };
1161 static const unsigned int msiof0_rxd_pins[] = {
1162 	/* RXD */
1163 	RCAR_GP_PIN(4, 0),
1164 };
1165 static const unsigned int msiof0_rxd_mux[] = {
1166 	MSIOF0_RXD_MARK,
1167 };
1168 
1169 /* - MSIOF1 ----------------------------------------------------------------- */
1170 static const unsigned int msiof1_clk_pins[] = {
1171 	/* SCK */
1172 	RCAR_GP_PIN(3, 2),
1173 };
1174 static const unsigned int msiof1_clk_mux[] = {
1175 	MSIOF1_SCK_MARK,
1176 };
1177 static const unsigned int msiof1_sync_pins[] = {
1178 	/* SYNC */
1179 	RCAR_GP_PIN(3, 3),
1180 };
1181 static const unsigned int msiof1_sync_mux[] = {
1182 	MSIOF1_SYNC_MARK,
1183 };
1184 static const unsigned int msiof1_ss1_pins[] = {
1185 	/* SS1 */
1186 	RCAR_GP_PIN(3, 4),
1187 };
1188 static const unsigned int msiof1_ss1_mux[] = {
1189 	MSIOF1_SS1_MARK,
1190 };
1191 static const unsigned int msiof1_ss2_pins[] = {
1192 	/* SS2 */
1193 	RCAR_GP_PIN(3, 5),
1194 };
1195 static const unsigned int msiof1_ss2_mux[] = {
1196 	MSIOF1_SS2_MARK,
1197 };
1198 static const unsigned int msiof1_txd_pins[] = {
1199 	/* TXD */
1200 	RCAR_GP_PIN(3, 1),
1201 };
1202 static const unsigned int msiof1_txd_mux[] = {
1203 	MSIOF1_TXD_MARK,
1204 };
1205 static const unsigned int msiof1_rxd_pins[] = {
1206 	/* RXD */
1207 	RCAR_GP_PIN(3, 0),
1208 };
1209 static const unsigned int msiof1_rxd_mux[] = {
1210 	MSIOF1_RXD_MARK,
1211 };
1212 
1213 /* - MSIOF2 ----------------------------------------------------------------- */
1214 static const unsigned int msiof2_clk_pins[] = {
1215 	/* SCK */
1216 	RCAR_GP_PIN(2, 0),
1217 };
1218 static const unsigned int msiof2_clk_mux[] = {
1219 	MSIOF2_SCK_MARK,
1220 };
1221 static const unsigned int msiof2_sync_pins[] = {
1222 	/* SYNC */
1223 	RCAR_GP_PIN(2, 3),
1224 };
1225 static const unsigned int msiof2_sync_mux[] = {
1226 	MSIOF2_SYNC_MARK,
1227 };
1228 static const unsigned int msiof2_ss1_pins[] = {
1229 	/* SS1 */
1230 	RCAR_GP_PIN(2, 4),
1231 };
1232 static const unsigned int msiof2_ss1_mux[] = {
1233 	MSIOF2_SS1_MARK,
1234 };
1235 static const unsigned int msiof2_ss2_pins[] = {
1236 	/* SS2 */
1237 	RCAR_GP_PIN(2, 5),
1238 };
1239 static const unsigned int msiof2_ss2_mux[] = {
1240 	MSIOF2_SS2_MARK,
1241 };
1242 static const unsigned int msiof2_txd_pins[] = {
1243 	/* TXD */
1244 	RCAR_GP_PIN(2, 2),
1245 };
1246 static const unsigned int msiof2_txd_mux[] = {
1247 	MSIOF2_TXD_MARK,
1248 };
1249 static const unsigned int msiof2_rxd_pins[] = {
1250 	/* RXD */
1251 	RCAR_GP_PIN(2, 1),
1252 };
1253 static const unsigned int msiof2_rxd_mux[] = {
1254 	MSIOF2_RXD_MARK,
1255 };
1256 
1257 /* - MSIOF3 ----------------------------------------------------------------- */
1258 static const unsigned int msiof3_clk_pins[] = {
1259 	/* SCK */
1260 	RCAR_GP_PIN(0, 20),
1261 };
1262 static const unsigned int msiof3_clk_mux[] = {
1263 	MSIOF3_SCK_MARK,
1264 };
1265 static const unsigned int msiof3_sync_pins[] = {
1266 	/* SYNC */
1267 	RCAR_GP_PIN(0, 21),
1268 };
1269 static const unsigned int msiof3_sync_mux[] = {
1270 	MSIOF3_SYNC_MARK,
1271 };
1272 static const unsigned int msiof3_ss1_pins[] = {
1273 	/* SS1 */
1274 	RCAR_GP_PIN(0, 6),
1275 };
1276 static const unsigned int msiof3_ss1_mux[] = {
1277 	MSIOF3_SS1_MARK,
1278 };
1279 static const unsigned int msiof3_ss2_pins[] = {
1280 	/* SS2 */
1281 	RCAR_GP_PIN(0, 7),
1282 };
1283 static const unsigned int msiof3_ss2_mux[] = {
1284 	MSIOF3_SS2_MARK,
1285 };
1286 static const unsigned int msiof3_txd_pins[] = {
1287 	/* TXD */
1288 	RCAR_GP_PIN(0, 5),
1289 };
1290 static const unsigned int msiof3_txd_mux[] = {
1291 	MSIOF3_TXD_MARK,
1292 };
1293 static const unsigned int msiof3_rxd_pins[] = {
1294 	/* RXD */
1295 	RCAR_GP_PIN(0, 4),
1296 };
1297 static const unsigned int msiof3_rxd_mux[] = {
1298 	MSIOF3_RXD_MARK,
1299 };
1300 
1301 /* - PWM0 ------------------------------------------------------------------- */
1302 static const unsigned int pwm0_a_pins[] = {
1303 	RCAR_GP_PIN(2, 12),
1304 };
1305 static const unsigned int pwm0_a_mux[] = {
1306 	PWM0_A_MARK,
1307 };
1308 static const unsigned int pwm0_b_pins[] = {
1309 	RCAR_GP_PIN(1, 21),
1310 };
1311 static const unsigned int pwm0_b_mux[] = {
1312 	PWM0_B_MARK,
1313 };
1314 
1315 /* - PWM1 ------------------------------------------------------------------- */
1316 static const unsigned int pwm1_a_pins[] = {
1317 	RCAR_GP_PIN(2, 13),
1318 };
1319 static const unsigned int pwm1_a_mux[] = {
1320 	PWM1_A_MARK,
1321 };
1322 static const unsigned int pwm1_b_pins[] = {
1323 	RCAR_GP_PIN(1, 22),
1324 };
1325 static const unsigned int pwm1_b_mux[] = {
1326 	PWM1_B_MARK,
1327 };
1328 
1329 /* - PWM2 ------------------------------------------------------------------- */
1330 static const unsigned int pwm2_a_pins[] = {
1331 	RCAR_GP_PIN(2, 14),
1332 };
1333 static const unsigned int pwm2_a_mux[] = {
1334 	PWM2_A_MARK,
1335 };
1336 static const unsigned int pwm2_b_pins[] = {
1337 	RCAR_GP_PIN(1, 23),
1338 };
1339 static const unsigned int pwm2_b_mux[] = {
1340 	PWM2_B_MARK,
1341 };
1342 
1343 /* - PWM3 ------------------------------------------------------------------- */
1344 static const unsigned int pwm3_a_pins[] = {
1345 	RCAR_GP_PIN(2, 15),
1346 };
1347 static const unsigned int pwm3_a_mux[] = {
1348 	PWM3_A_MARK,
1349 };
1350 static const unsigned int pwm3_b_pins[] = {
1351 	RCAR_GP_PIN(1, 24),
1352 };
1353 static const unsigned int pwm3_b_mux[] = {
1354 	PWM3_B_MARK,
1355 };
1356 
1357 /* - PWM4 ------------------------------------------------------------------- */
1358 static const unsigned int pwm4_a_pins[] = {
1359 	RCAR_GP_PIN(2, 16),
1360 };
1361 static const unsigned int pwm4_a_mux[] = {
1362 	PWM4_A_MARK,
1363 };
1364 static const unsigned int pwm4_b_pins[] = {
1365 	RCAR_GP_PIN(1, 25),
1366 };
1367 static const unsigned int pwm4_b_mux[] = {
1368 	PWM4_B_MARK,
1369 };
1370 
1371 /* - QSPI0 ------------------------------------------------------------------ */
1372 static const unsigned int qspi0_ctrl_pins[] = {
1373 	/* SPCLK, SSL */
1374 	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
1375 };
1376 static const unsigned int qspi0_ctrl_mux[] = {
1377 	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
1378 };
1379 
1380 /* - QSPI1 ------------------------------------------------------------------ */
1381 static const unsigned int qspi1_ctrl_pins[] = {
1382 	/* SPCLK, SSL */
1383 	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
1384 };
1385 static const unsigned int qspi1_ctrl_mux[] = {
1386 	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
1387 };
1388 
1389 /* - RPC -------------------------------------------------------------------- */
1390 static const unsigned int rpc_clk_pins[] = {
1391 	/* Octal-SPI flash: C/SCLK */
1392 	/* HyperFlash: CK, CK# */
1393 	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
1394 };
1395 static const unsigned int rpc_clk_mux[] = {
1396 	QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
1397 };
1398 static const unsigned int rpc_ctrl_pins[] = {
1399 	/* Octal-SPI flash: S#/CS, DQS */
1400 	/* HyperFlash: CS#, RDS */
1401 	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1402 };
1403 static const unsigned int rpc_ctrl_mux[] = {
1404 	QSPI0_SSL_MARK, QSPI1_SSL_MARK,
1405 };
1406 static const unsigned int rpc_data_pins[] = {
1407 	/* DQ[0:7] */
1408 	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1409 	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
1410 	RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1411 	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1412 };
1413 static const unsigned int rpc_data_mux[] = {
1414 	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1415 	QSPI0_IO2_MARK, QSPI0_IO3_MARK,
1416 	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1417 	QSPI1_IO2_MARK, QSPI1_IO3_MARK,
1418 };
1419 static const unsigned int rpc_reset_pins[] = {
1420 	/* RPC_RESET# */
1421 	RCAR_GP_PIN(5, 12),
1422 };
1423 static const unsigned int rpc_reset_mux[] = {
1424 	RPC_RESET_N_MARK,
1425 };
1426 static const unsigned int rpc_int_pins[] = {
1427 	/* RPC_INT# */
1428 	RCAR_GP_PIN(5, 14),
1429 };
1430 static const unsigned int rpc_int_mux[] = {
1431 	RPC_INT_N_MARK,
1432 };
1433 static const unsigned int rpc_wp_pins[] = {
1434 	/* RPC_WP# */
1435 	RCAR_GP_PIN(5, 13),
1436 };
1437 static const unsigned int rpc_wp_mux[] = {
1438 	RPC_WP_N_MARK,
1439 };
1440 
1441 /* - SCIF Clock ------------------------------------------------------------- */
1442 static const unsigned int scif_clk_a_pins[] = {
1443 	/* SCIF_CLK */
1444 	RCAR_GP_PIN(0, 18),
1445 };
1446 static const unsigned int scif_clk_a_mux[] = {
1447 	SCIF_CLK_A_MARK,
1448 };
1449 static const unsigned int scif_clk_b_pins[] = {
1450 	/* SCIF_CLK */
1451 	RCAR_GP_PIN(1, 25),
1452 };
1453 static const unsigned int scif_clk_b_mux[] = {
1454 	SCIF_CLK_B_MARK,
1455 };
1456 
1457 /* - SCIF0 ------------------------------------------------------------------ */
1458 static const unsigned int scif0_data_pins[] = {
1459 	/* RX, TX */
1460 	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1461 };
1462 static const unsigned int scif0_data_mux[] = {
1463 	RX0_MARK, TX0_MARK,
1464 };
1465 static const unsigned int scif0_clk_pins[] = {
1466 	/* SCK */
1467 	RCAR_GP_PIN(4, 1),
1468 };
1469 static const unsigned int scif0_clk_mux[] = {
1470 	SCK0_MARK,
1471 };
1472 static const unsigned int scif0_ctrl_pins[] = {
1473 	/* RTS#, CTS# */
1474 	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1475 };
1476 static const unsigned int scif0_ctrl_mux[] = {
1477 	RTS0_N_MARK, CTS0_N_MARK,
1478 };
1479 
1480 /* - SCIF1 ------------------------------------------------------------------ */
1481 static const unsigned int scif1_data_a_pins[] = {
1482 	/* RX, TX */
1483 	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1484 };
1485 static const unsigned int scif1_data_a_mux[] = {
1486 	RX1_A_MARK, TX1_A_MARK,
1487 };
1488 static const unsigned int scif1_clk_pins[] = {
1489 	/* SCK */
1490 	RCAR_GP_PIN(2, 5),
1491 };
1492 static const unsigned int scif1_clk_mux[] = {
1493 	SCK1_MARK,
1494 };
1495 static const unsigned int scif1_ctrl_pins[] = {
1496 	/* RTS#, CTS# */
1497 	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1498 };
1499 static const unsigned int scif1_ctrl_mux[] = {
1500 	RTS1_N_MARK, CTS1_N_MARK,
1501 };
1502 static const unsigned int scif1_data_b_pins[] = {
1503 	/* RX, TX */
1504 	RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1505 };
1506 static const unsigned int scif1_data_b_mux[] = {
1507 	RX1_B_MARK, TX1_B_MARK,
1508 };
1509 
1510 /* - SCIF3 ------------------------------------------------------------------ */
1511 static const unsigned int scif3_data_pins[] = {
1512 	/* RX, TX */
1513 	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
1514 };
1515 static const unsigned int scif3_data_mux[] = {
1516 	RX3_MARK, TX3_MARK,
1517 };
1518 static const unsigned int scif3_clk_pins[] = {
1519 	/* SCK */
1520 	RCAR_GP_PIN(2, 0),
1521 };
1522 static const unsigned int scif3_clk_mux[] = {
1523 	SCK3_MARK,
1524 };
1525 static const unsigned int scif3_ctrl_pins[] = {
1526 	/* RTS#, CTS# */
1527 	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1528 };
1529 static const unsigned int scif3_ctrl_mux[] = {
1530 	RTS3_N_MARK, CTS3_N_MARK,
1531 };
1532 
1533 /* - SCIF4 ------------------------------------------------------------------ */
1534 static const unsigned int scif4_data_pins[] = {
1535 	/* RX, TX */
1536 	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1537 };
1538 static const unsigned int scif4_data_mux[] = {
1539 	RX4_MARK, TX4_MARK,
1540 };
1541 static const unsigned int scif4_clk_pins[] = {
1542 	/* SCK */
1543 	RCAR_GP_PIN(3, 9),
1544 };
1545 static const unsigned int scif4_clk_mux[] = {
1546 	SCK4_MARK,
1547 };
1548 static const unsigned int scif4_ctrl_pins[] = {
1549 	/* RTS#, CTS# */
1550 	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
1551 };
1552 static const unsigned int scif4_ctrl_mux[] = {
1553 	RTS4_N_MARK, CTS4_N_MARK,
1554 };
1555 
1556 /* - TMU -------------------------------------------------------------------- */
1557 static const unsigned int tmu_tclk1_a_pins[] = {
1558 	/* TCLK1 */
1559 	RCAR_GP_PIN(4, 4),
1560 };
1561 static const unsigned int tmu_tclk1_a_mux[] = {
1562 	TCLK1_A_MARK,
1563 };
1564 static const unsigned int tmu_tclk1_b_pins[] = {
1565 	/* TCLK1 */
1566 	RCAR_GP_PIN(1, 23),
1567 };
1568 static const unsigned int tmu_tclk1_b_mux[] = {
1569 	TCLK1_B_MARK,
1570 };
1571 static const unsigned int tmu_tclk2_a_pins[] = {
1572 	/* TCLK2 */
1573 	RCAR_GP_PIN(4, 5),
1574 };
1575 static const unsigned int tmu_tclk2_a_mux[] = {
1576 	TCLK2_A_MARK,
1577 };
1578 static const unsigned int tmu_tclk2_b_pins[] = {
1579 	/* TCLK2 */
1580 	RCAR_GP_PIN(1, 24),
1581 };
1582 static const unsigned int tmu_tclk2_b_mux[] = {
1583 	TCLK2_B_MARK,
1584 };
1585 
1586 /* - VIN0 ------------------------------------------------------------------- */
1587 static const unsigned int vin0_data_pins[] = {
1588 	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1589 	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1590 	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1591 	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1592 	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1593 	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1594 };
1595 static const unsigned int vin0_data_mux[] = {
1596 	VI0_DATA0_MARK, VI0_DATA1_MARK,
1597 	VI0_DATA2_MARK, VI0_DATA3_MARK,
1598 	VI0_DATA4_MARK, VI0_DATA5_MARK,
1599 	VI0_DATA6_MARK, VI0_DATA7_MARK,
1600 	VI0_DATA8_MARK,  VI0_DATA9_MARK,
1601 	VI0_DATA10_MARK, VI0_DATA11_MARK,
1602 };
1603 static const unsigned int vin0_sync_pins[] = {
1604 	/* HSYNC#, VSYNC# */
1605 	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1606 };
1607 static const unsigned int vin0_sync_mux[] = {
1608 	VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
1609 };
1610 static const unsigned int vin0_field_pins[] = {
1611 	/* FIELD */
1612 	RCAR_GP_PIN(2, 16),
1613 };
1614 static const unsigned int vin0_field_mux[] = {
1615 	VI0_FIELD_MARK,
1616 };
1617 static const unsigned int vin0_clkenb_pins[] = {
1618 	/* CLKENB */
1619 	RCAR_GP_PIN(2, 1),
1620 };
1621 static const unsigned int vin0_clkenb_mux[] = {
1622 	VI0_CLKENB_MARK,
1623 };
1624 static const unsigned int vin0_clk_pins[] = {
1625 	/* CLK */
1626 	RCAR_GP_PIN(2, 0),
1627 };
1628 static const unsigned int vin0_clk_mux[] = {
1629 	VI0_CLK_MARK,
1630 };
1631 
1632 /* - VIN1 ------------------------------------------------------------------- */
1633 static const unsigned int vin1_data_pins[] = {
1634 	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1635 	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1636 	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1637 	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1638 	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1639 	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
1640 };
1641 static const unsigned int vin1_data_mux[] = {
1642 	VI1_DATA0_MARK, VI1_DATA1_MARK,
1643 	VI1_DATA2_MARK, VI1_DATA3_MARK,
1644 	VI1_DATA4_MARK, VI1_DATA5_MARK,
1645 	VI1_DATA6_MARK, VI1_DATA7_MARK,
1646 	VI1_DATA8_MARK,  VI1_DATA9_MARK,
1647 	VI1_DATA10_MARK, VI1_DATA11_MARK,
1648 };
1649 static const unsigned int vin1_sync_pins[] = {
1650 	/* HSYNC#, VSYNC# */
1651 	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1652 };
1653 static const unsigned int vin1_sync_mux[] = {
1654 	VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
1655 };
1656 static const unsigned int vin1_field_pins[] = {
1657 	RCAR_GP_PIN(3, 16),
1658 };
1659 static const unsigned int vin1_field_mux[] = {
1660 	/* FIELD */
1661 	VI1_FIELD_MARK,
1662 };
1663 static const unsigned int vin1_clkenb_pins[] = {
1664 	RCAR_GP_PIN(3, 1),
1665 };
1666 static const unsigned int vin1_clkenb_mux[] = {
1667 	/* CLKENB */
1668 	VI1_CLKENB_MARK,
1669 };
1670 static const unsigned int vin1_clk_pins[] = {
1671 	RCAR_GP_PIN(3, 0),
1672 };
1673 static const unsigned int vin1_clk_mux[] = {
1674 	/* CLK */
1675 	VI1_CLK_MARK,
1676 };
1677 
1678 static const struct sh_pfc_pin_group pinmux_groups[] = {
1679 	SH_PFC_PIN_GROUP(avb0_link),
1680 	SH_PFC_PIN_GROUP(avb0_magic),
1681 	SH_PFC_PIN_GROUP(avb0_phy_int),
1682 	SH_PFC_PIN_GROUP(avb0_mdio),
1683 	SH_PFC_PIN_GROUP(avb0_rgmii),
1684 	SH_PFC_PIN_GROUP(avb0_txcrefclk),
1685 	SH_PFC_PIN_GROUP(avb0_avtp_pps),
1686 	SH_PFC_PIN_GROUP(avb0_avtp_capture),
1687 	SH_PFC_PIN_GROUP(avb0_avtp_match),
1688 	SH_PFC_PIN_GROUP(canfd_clk_a),
1689 	SH_PFC_PIN_GROUP(canfd_clk_b),
1690 	SH_PFC_PIN_GROUP(canfd0_data_a),
1691 	SH_PFC_PIN_GROUP(canfd0_data_b),
1692 	SH_PFC_PIN_GROUP(canfd1_data),
1693 	SH_PFC_PIN_GROUP(du_rgb666),
1694 	SH_PFC_PIN_GROUP(du_clk_out),
1695 	SH_PFC_PIN_GROUP(du_sync),
1696 	SH_PFC_PIN_GROUP(du_oddf),
1697 	SH_PFC_PIN_GROUP(du_cde),
1698 	SH_PFC_PIN_GROUP(du_disp),
1699 	SH_PFC_PIN_GROUP(hscif0_data),
1700 	SH_PFC_PIN_GROUP(hscif0_clk),
1701 	SH_PFC_PIN_GROUP(hscif0_ctrl),
1702 	SH_PFC_PIN_GROUP(hscif1_data),
1703 	SH_PFC_PIN_GROUP(hscif1_clk),
1704 	SH_PFC_PIN_GROUP(hscif1_ctrl),
1705 	SH_PFC_PIN_GROUP(hscif2_data),
1706 	SH_PFC_PIN_GROUP(hscif2_clk),
1707 	SH_PFC_PIN_GROUP(hscif2_ctrl),
1708 	SH_PFC_PIN_GROUP(hscif3_data),
1709 	SH_PFC_PIN_GROUP(hscif3_clk),
1710 	SH_PFC_PIN_GROUP(hscif3_ctrl),
1711 	SH_PFC_PIN_GROUP(i2c0),
1712 	SH_PFC_PIN_GROUP(i2c1),
1713 	SH_PFC_PIN_GROUP(i2c2),
1714 	SH_PFC_PIN_GROUP(i2c3_a),
1715 	SH_PFC_PIN_GROUP(i2c3_b),
1716 	SH_PFC_PIN_GROUP(i2c4),
1717 	SH_PFC_PIN_GROUP(intc_ex_irq0),
1718 	SH_PFC_PIN_GROUP(intc_ex_irq1),
1719 	SH_PFC_PIN_GROUP(intc_ex_irq2),
1720 	SH_PFC_PIN_GROUP(intc_ex_irq3),
1721 	SH_PFC_PIN_GROUP(intc_ex_irq4),
1722 	SH_PFC_PIN_GROUP(intc_ex_irq5),
1723 	BUS_DATA_PIN_GROUP(mmc_data, 1),
1724 	BUS_DATA_PIN_GROUP(mmc_data, 4),
1725 	BUS_DATA_PIN_GROUP(mmc_data, 8),
1726 	SH_PFC_PIN_GROUP(mmc_ctrl),
1727 	SH_PFC_PIN_GROUP(msiof0_clk),
1728 	SH_PFC_PIN_GROUP(msiof0_sync),
1729 	SH_PFC_PIN_GROUP(msiof0_ss1),
1730 	SH_PFC_PIN_GROUP(msiof0_ss2),
1731 	SH_PFC_PIN_GROUP(msiof0_txd),
1732 	SH_PFC_PIN_GROUP(msiof0_rxd),
1733 	SH_PFC_PIN_GROUP(msiof1_clk),
1734 	SH_PFC_PIN_GROUP(msiof1_sync),
1735 	SH_PFC_PIN_GROUP(msiof1_ss1),
1736 	SH_PFC_PIN_GROUP(msiof1_ss2),
1737 	SH_PFC_PIN_GROUP(msiof1_txd),
1738 	SH_PFC_PIN_GROUP(msiof1_rxd),
1739 	SH_PFC_PIN_GROUP(msiof2_clk),
1740 	SH_PFC_PIN_GROUP(msiof2_sync),
1741 	SH_PFC_PIN_GROUP(msiof2_ss1),
1742 	SH_PFC_PIN_GROUP(msiof2_ss2),
1743 	SH_PFC_PIN_GROUP(msiof2_txd),
1744 	SH_PFC_PIN_GROUP(msiof2_rxd),
1745 	SH_PFC_PIN_GROUP(msiof3_clk),
1746 	SH_PFC_PIN_GROUP(msiof3_sync),
1747 	SH_PFC_PIN_GROUP(msiof3_ss1),
1748 	SH_PFC_PIN_GROUP(msiof3_ss2),
1749 	SH_PFC_PIN_GROUP(msiof3_txd),
1750 	SH_PFC_PIN_GROUP(msiof3_rxd),
1751 	SH_PFC_PIN_GROUP(pwm0_a),
1752 	SH_PFC_PIN_GROUP(pwm0_b),
1753 	SH_PFC_PIN_GROUP(pwm1_a),
1754 	SH_PFC_PIN_GROUP(pwm1_b),
1755 	SH_PFC_PIN_GROUP(pwm2_a),
1756 	SH_PFC_PIN_GROUP(pwm2_b),
1757 	SH_PFC_PIN_GROUP(pwm3_a),
1758 	SH_PFC_PIN_GROUP(pwm3_b),
1759 	SH_PFC_PIN_GROUP(pwm4_a),
1760 	SH_PFC_PIN_GROUP(pwm4_b),
1761 	SH_PFC_PIN_GROUP(qspi0_ctrl),
1762 	SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
1763 	SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
1764 	SH_PFC_PIN_GROUP(qspi1_ctrl),
1765 	SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2),
1766 	SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4),
1767 	BUS_DATA_PIN_GROUP(rpc_clk, 1),
1768 	BUS_DATA_PIN_GROUP(rpc_clk, 2),
1769 	SH_PFC_PIN_GROUP(rpc_ctrl),
1770 	SH_PFC_PIN_GROUP(rpc_data),
1771 	SH_PFC_PIN_GROUP(rpc_reset),
1772 	SH_PFC_PIN_GROUP(rpc_int),
1773 	SH_PFC_PIN_GROUP(rpc_wp),
1774 	SH_PFC_PIN_GROUP(scif_clk_a),
1775 	SH_PFC_PIN_GROUP(scif_clk_b),
1776 	SH_PFC_PIN_GROUP(scif0_data),
1777 	SH_PFC_PIN_GROUP(scif0_clk),
1778 	SH_PFC_PIN_GROUP(scif0_ctrl),
1779 	SH_PFC_PIN_GROUP(scif1_data_a),
1780 	SH_PFC_PIN_GROUP(scif1_clk),
1781 	SH_PFC_PIN_GROUP(scif1_ctrl),
1782 	SH_PFC_PIN_GROUP(scif1_data_b),
1783 	SH_PFC_PIN_GROUP(scif3_data),
1784 	SH_PFC_PIN_GROUP(scif3_clk),
1785 	SH_PFC_PIN_GROUP(scif3_ctrl),
1786 	SH_PFC_PIN_GROUP(scif4_data),
1787 	SH_PFC_PIN_GROUP(scif4_clk),
1788 	SH_PFC_PIN_GROUP(scif4_ctrl),
1789 	SH_PFC_PIN_GROUP(tmu_tclk1_a),
1790 	SH_PFC_PIN_GROUP(tmu_tclk1_b),
1791 	SH_PFC_PIN_GROUP(tmu_tclk2_a),
1792 	SH_PFC_PIN_GROUP(tmu_tclk2_b),
1793 	BUS_DATA_PIN_GROUP(vin0_data, 8),
1794 	BUS_DATA_PIN_GROUP(vin0_data, 10),
1795 	BUS_DATA_PIN_GROUP(vin0_data, 12),
1796 	SH_PFC_PIN_GROUP(vin0_sync),
1797 	SH_PFC_PIN_GROUP(vin0_field),
1798 	SH_PFC_PIN_GROUP(vin0_clkenb),
1799 	SH_PFC_PIN_GROUP(vin0_clk),
1800 	BUS_DATA_PIN_GROUP(vin1_data, 8),
1801 	BUS_DATA_PIN_GROUP(vin1_data, 10),
1802 	BUS_DATA_PIN_GROUP(vin1_data, 12),
1803 	SH_PFC_PIN_GROUP(vin1_sync),
1804 	SH_PFC_PIN_GROUP(vin1_field),
1805 	SH_PFC_PIN_GROUP(vin1_clkenb),
1806 	SH_PFC_PIN_GROUP(vin1_clk),
1807 };
1808 
1809 static const char * const avb0_groups[] = {
1810 	"avb0_link",
1811 	"avb0_magic",
1812 	"avb0_phy_int",
1813 	"avb0_mdio",
1814 	"avb0_rgmii",
1815 	"avb0_txcrefclk",
1816 	"avb0_avtp_pps",
1817 	"avb0_avtp_capture",
1818 	"avb0_avtp_match",
1819 };
1820 
1821 static const char * const canfd_clk_groups[] = {
1822 	"canfd_clk_a",
1823 	"canfd_clk_b",
1824 };
1825 
1826 static const char * const canfd0_groups[] = {
1827 	"canfd0_data_a",
1828 	"canfd0_data_b",
1829 };
1830 
1831 static const char * const canfd1_groups[] = {
1832 	"canfd1_data",
1833 };
1834 
1835 static const char * const du_groups[] = {
1836 	"du_rgb666",
1837 	"du_clk_out",
1838 	"du_sync",
1839 	"du_oddf",
1840 	"du_cde",
1841 	"du_disp",
1842 };
1843 
1844 static const char * const hscif0_groups[] = {
1845 	"hscif0_data",
1846 	"hscif0_clk",
1847 	"hscif0_ctrl",
1848 };
1849 
1850 static const char * const hscif1_groups[] = {
1851 	"hscif1_data",
1852 	"hscif1_clk",
1853 	"hscif1_ctrl",
1854 };
1855 
1856 static const char * const hscif2_groups[] = {
1857 	"hscif2_data",
1858 	"hscif2_clk",
1859 	"hscif2_ctrl",
1860 };
1861 
1862 static const char * const hscif3_groups[] = {
1863 	"hscif3_data",
1864 	"hscif3_clk",
1865 	"hscif3_ctrl",
1866 };
1867 
1868 static const char * const i2c0_groups[] = {
1869 	"i2c0",
1870 };
1871 
1872 static const char * const i2c1_groups[] = {
1873 	"i2c1",
1874 };
1875 
1876 static const char * const i2c2_groups[] = {
1877 	"i2c2",
1878 };
1879 
1880 static const char * const i2c3_groups[] = {
1881 	"i2c3_a",
1882 	"i2c3_b",
1883 };
1884 
1885 static const char * const i2c4_groups[] = {
1886 	"i2c4",
1887 };
1888 
1889 static const char * const intc_ex_groups[] = {
1890 	"intc_ex_irq0",
1891 	"intc_ex_irq1",
1892 	"intc_ex_irq2",
1893 	"intc_ex_irq3",
1894 	"intc_ex_irq4",
1895 	"intc_ex_irq5",
1896 };
1897 
1898 static const char * const mmc_groups[] = {
1899 	"mmc_data1",
1900 	"mmc_data4",
1901 	"mmc_data8",
1902 	"mmc_ctrl",
1903 };
1904 
1905 static const char * const msiof0_groups[] = {
1906 	"msiof0_clk",
1907 	"msiof0_sync",
1908 	"msiof0_ss1",
1909 	"msiof0_ss2",
1910 	"msiof0_txd",
1911 	"msiof0_rxd",
1912 };
1913 
1914 static const char * const msiof1_groups[] = {
1915 	"msiof1_clk",
1916 	"msiof1_sync",
1917 	"msiof1_ss1",
1918 	"msiof1_ss2",
1919 	"msiof1_txd",
1920 	"msiof1_rxd",
1921 };
1922 
1923 static const char * const msiof2_groups[] = {
1924 	"msiof2_clk",
1925 	"msiof2_sync",
1926 	"msiof2_ss1",
1927 	"msiof2_ss2",
1928 	"msiof2_txd",
1929 	"msiof2_rxd",
1930 };
1931 
1932 static const char * const msiof3_groups[] = {
1933 	"msiof3_clk",
1934 	"msiof3_sync",
1935 	"msiof3_ss1",
1936 	"msiof3_ss2",
1937 	"msiof3_txd",
1938 	"msiof3_rxd",
1939 };
1940 
1941 static const char * const pwm0_groups[] = {
1942 	"pwm0_a",
1943 	"pwm0_b",
1944 };
1945 
1946 static const char * const pwm1_groups[] = {
1947 	"pwm1_a",
1948 	"pwm1_b",
1949 };
1950 
1951 static const char * const pwm2_groups[] = {
1952 	"pwm2_a",
1953 	"pwm2_b",
1954 };
1955 
1956 static const char * const pwm3_groups[] = {
1957 	"pwm3_a",
1958 	"pwm3_b",
1959 };
1960 
1961 static const char * const pwm4_groups[] = {
1962 	"pwm4_a",
1963 	"pwm4_b",
1964 };
1965 
1966 static const char * const qspi0_groups[] = {
1967 	"qspi0_ctrl",
1968 	"qspi0_data2",
1969 	"qspi0_data4",
1970 };
1971 
1972 static const char * const qspi1_groups[] = {
1973 	"qspi1_ctrl",
1974 	"qspi1_data2",
1975 	"qspi1_data4",
1976 };
1977 
1978 static const char * const rpc_groups[] = {
1979 	"rpc_clk1",
1980 	"rpc_clk2",
1981 	"rpc_ctrl",
1982 	"rpc_data",
1983 	"rpc_reset",
1984 	"rpc_int",
1985 	"rpc_wp",
1986 };
1987 
1988 static const char * const scif_clk_groups[] = {
1989 	"scif_clk_a",
1990 	"scif_clk_b",
1991 };
1992 
1993 static const char * const scif0_groups[] = {
1994 	"scif0_data",
1995 	"scif0_clk",
1996 	"scif0_ctrl",
1997 };
1998 
1999 static const char * const scif1_groups[] = {
2000 	"scif1_data_a",
2001 	"scif1_clk",
2002 	"scif1_ctrl",
2003 	"scif1_data_b",
2004 };
2005 
2006 static const char * const scif3_groups[] = {
2007 	"scif3_data",
2008 	"scif3_clk",
2009 	"scif3_ctrl",
2010 };
2011 
2012 static const char * const scif4_groups[] = {
2013 	"scif4_data",
2014 	"scif4_clk",
2015 	"scif4_ctrl",
2016 };
2017 
2018 static const char * const tmu_groups[] = {
2019 	"tmu_tclk1_a",
2020 	"tmu_tclk1_b",
2021 	"tmu_tclk2_a",
2022 	"tmu_tclk2_b",
2023 };
2024 
2025 static const char * const vin0_groups[] = {
2026 	"vin0_data8",
2027 	"vin0_data10",
2028 	"vin0_data12",
2029 	"vin0_sync",
2030 	"vin0_field",
2031 	"vin0_clkenb",
2032 	"vin0_clk",
2033 };
2034 
2035 static const char * const vin1_groups[] = {
2036 	"vin1_data8",
2037 	"vin1_data10",
2038 	"vin1_data12",
2039 	"vin1_sync",
2040 	"vin1_field",
2041 	"vin1_clkenb",
2042 	"vin1_clk",
2043 };
2044 
2045 static const struct sh_pfc_function pinmux_functions[] = {
2046 	SH_PFC_FUNCTION(avb0),
2047 	SH_PFC_FUNCTION(canfd_clk),
2048 	SH_PFC_FUNCTION(canfd0),
2049 	SH_PFC_FUNCTION(canfd1),
2050 	SH_PFC_FUNCTION(du),
2051 	SH_PFC_FUNCTION(hscif0),
2052 	SH_PFC_FUNCTION(hscif1),
2053 	SH_PFC_FUNCTION(hscif2),
2054 	SH_PFC_FUNCTION(hscif3),
2055 	SH_PFC_FUNCTION(i2c0),
2056 	SH_PFC_FUNCTION(i2c1),
2057 	SH_PFC_FUNCTION(i2c2),
2058 	SH_PFC_FUNCTION(i2c3),
2059 	SH_PFC_FUNCTION(i2c4),
2060 	SH_PFC_FUNCTION(intc_ex),
2061 	SH_PFC_FUNCTION(mmc),
2062 	SH_PFC_FUNCTION(msiof0),
2063 	SH_PFC_FUNCTION(msiof1),
2064 	SH_PFC_FUNCTION(msiof2),
2065 	SH_PFC_FUNCTION(msiof3),
2066 	SH_PFC_FUNCTION(pwm0),
2067 	SH_PFC_FUNCTION(pwm1),
2068 	SH_PFC_FUNCTION(pwm2),
2069 	SH_PFC_FUNCTION(pwm3),
2070 	SH_PFC_FUNCTION(pwm4),
2071 	SH_PFC_FUNCTION(qspi0),
2072 	SH_PFC_FUNCTION(qspi1),
2073 	SH_PFC_FUNCTION(rpc),
2074 	SH_PFC_FUNCTION(scif_clk),
2075 	SH_PFC_FUNCTION(scif0),
2076 	SH_PFC_FUNCTION(scif1),
2077 	SH_PFC_FUNCTION(scif3),
2078 	SH_PFC_FUNCTION(scif4),
2079 	SH_PFC_FUNCTION(tmu),
2080 	SH_PFC_FUNCTION(vin0),
2081 	SH_PFC_FUNCTION(vin1),
2082 };
2083 
2084 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2085 #define F_(x, y)	FN_##y
2086 #define FM(x)		FN_##x
2087 	{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
2088 			     GROUP(-10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2089 				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2090 			     GROUP(
2091 		/* GP0_31_22 RESERVED */
2092 		GP_0_21_FN,	GPSR0_21,
2093 		GP_0_20_FN,	GPSR0_20,
2094 		GP_0_19_FN,	GPSR0_19,
2095 		GP_0_18_FN,	GPSR0_18,
2096 		GP_0_17_FN,	GPSR0_17,
2097 		GP_0_16_FN,	GPSR0_16,
2098 		GP_0_15_FN,	GPSR0_15,
2099 		GP_0_14_FN,	GPSR0_14,
2100 		GP_0_13_FN,	GPSR0_13,
2101 		GP_0_12_FN,	GPSR0_12,
2102 		GP_0_11_FN,	GPSR0_11,
2103 		GP_0_10_FN,	GPSR0_10,
2104 		GP_0_9_FN,	GPSR0_9,
2105 		GP_0_8_FN,	GPSR0_8,
2106 		GP_0_7_FN,	GPSR0_7,
2107 		GP_0_6_FN,	GPSR0_6,
2108 		GP_0_5_FN,	GPSR0_5,
2109 		GP_0_4_FN,	GPSR0_4,
2110 		GP_0_3_FN,	GPSR0_3,
2111 		GP_0_2_FN,	GPSR0_2,
2112 		GP_0_1_FN,	GPSR0_1,
2113 		GP_0_0_FN,	GPSR0_0, ))
2114 	},
2115 	{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
2116 		0, 0,
2117 		0, 0,
2118 		0, 0,
2119 		0, 0,
2120 		GP_1_27_FN,	GPSR1_27,
2121 		GP_1_26_FN,	GPSR1_26,
2122 		GP_1_25_FN,	GPSR1_25,
2123 		GP_1_24_FN,	GPSR1_24,
2124 		GP_1_23_FN,	GPSR1_23,
2125 		GP_1_22_FN,	GPSR1_22,
2126 		GP_1_21_FN,	GPSR1_21,
2127 		GP_1_20_FN,	GPSR1_20,
2128 		GP_1_19_FN,	GPSR1_19,
2129 		GP_1_18_FN,	GPSR1_18,
2130 		GP_1_17_FN,	GPSR1_17,
2131 		GP_1_16_FN,	GPSR1_16,
2132 		GP_1_15_FN,	GPSR1_15,
2133 		GP_1_14_FN,	GPSR1_14,
2134 		GP_1_13_FN,	GPSR1_13,
2135 		GP_1_12_FN,	GPSR1_12,
2136 		GP_1_11_FN,	GPSR1_11,
2137 		GP_1_10_FN,	GPSR1_10,
2138 		GP_1_9_FN,	GPSR1_9,
2139 		GP_1_8_FN,	GPSR1_8,
2140 		GP_1_7_FN,	GPSR1_7,
2141 		GP_1_6_FN,	GPSR1_6,
2142 		GP_1_5_FN,	GPSR1_5,
2143 		GP_1_4_FN,	GPSR1_4,
2144 		GP_1_3_FN,	GPSR1_3,
2145 		GP_1_2_FN,	GPSR1_2,
2146 		GP_1_1_FN,	GPSR1_1,
2147 		GP_1_0_FN,	GPSR1_0, ))
2148 	},
2149 	{ PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
2150 			     GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2151 				   1, 1, 1, 1, 1, 1),
2152 			     GROUP(
2153 		/* GP2_31_17 RESERVED */
2154 		GP_2_16_FN,	GPSR2_16,
2155 		GP_2_15_FN,	GPSR2_15,
2156 		GP_2_14_FN,	GPSR2_14,
2157 		GP_2_13_FN,	GPSR2_13,
2158 		GP_2_12_FN,	GPSR2_12,
2159 		GP_2_11_FN,	GPSR2_11,
2160 		GP_2_10_FN,	GPSR2_10,
2161 		GP_2_9_FN,	GPSR2_9,
2162 		GP_2_8_FN,	GPSR2_8,
2163 		GP_2_7_FN,	GPSR2_7,
2164 		GP_2_6_FN,	GPSR2_6,
2165 		GP_2_5_FN,	GPSR2_5,
2166 		GP_2_4_FN,	GPSR2_4,
2167 		GP_2_3_FN,	GPSR2_3,
2168 		GP_2_2_FN,	GPSR2_2,
2169 		GP_2_1_FN,	GPSR2_1,
2170 		GP_2_0_FN,	GPSR2_0, ))
2171 	},
2172 	{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
2173 			     GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2174 				   1, 1, 1, 1, 1, 1),
2175 			     GROUP(
2176 		/* GP3_31_17 RESERVED */
2177 		GP_3_16_FN,	GPSR3_16,
2178 		GP_3_15_FN,	GPSR3_15,
2179 		GP_3_14_FN,	GPSR3_14,
2180 		GP_3_13_FN,	GPSR3_13,
2181 		GP_3_12_FN,	GPSR3_12,
2182 		GP_3_11_FN,	GPSR3_11,
2183 		GP_3_10_FN,	GPSR3_10,
2184 		GP_3_9_FN,	GPSR3_9,
2185 		GP_3_8_FN,	GPSR3_8,
2186 		GP_3_7_FN,	GPSR3_7,
2187 		GP_3_6_FN,	GPSR3_6,
2188 		GP_3_5_FN,	GPSR3_5,
2189 		GP_3_4_FN,	GPSR3_4,
2190 		GP_3_3_FN,	GPSR3_3,
2191 		GP_3_2_FN,	GPSR3_2,
2192 		GP_3_1_FN,	GPSR3_1,
2193 		GP_3_0_FN,	GPSR3_0, ))
2194 	},
2195 	{ PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
2196 			     GROUP(-26, 1, 1, 1, 1, 1, 1),
2197 			     GROUP(
2198 		/* GP4_31_6 RESERVED */
2199 		GP_4_5_FN,	GPSR4_5,
2200 		GP_4_4_FN,	GPSR4_4,
2201 		GP_4_3_FN,	GPSR4_3,
2202 		GP_4_2_FN,	GPSR4_2,
2203 		GP_4_1_FN,	GPSR4_1,
2204 		GP_4_0_FN,	GPSR4_0, ))
2205 	},
2206 	{ PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
2207 			     GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2208 				   1, 1, 1, 1),
2209 			     GROUP(
2210 		/* GP5_31_15 RESERVED */
2211 		GP_5_14_FN,	GPSR5_14,
2212 		GP_5_13_FN,	GPSR5_13,
2213 		GP_5_12_FN,	GPSR5_12,
2214 		GP_5_11_FN,	GPSR5_11,
2215 		GP_5_10_FN,	GPSR5_10,
2216 		GP_5_9_FN,	GPSR5_9,
2217 		GP_5_8_FN,	GPSR5_8,
2218 		GP_5_7_FN,	GPSR5_7,
2219 		GP_5_6_FN,	GPSR5_6,
2220 		GP_5_5_FN,	GPSR5_5,
2221 		GP_5_4_FN,	GPSR5_4,
2222 		GP_5_3_FN,	GPSR5_3,
2223 		GP_5_2_FN,	GPSR5_2,
2224 		GP_5_1_FN,	GPSR5_1,
2225 		GP_5_0_FN,	GPSR5_0, ))
2226 	},
2227 #undef F_
2228 #undef FM
2229 
2230 #define F_(x, y)	x,
2231 #define FM(x)		FN_##x,
2232 	{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
2233 		IP0_31_28
2234 		IP0_27_24
2235 		IP0_23_20
2236 		IP0_19_16
2237 		IP0_15_12
2238 		IP0_11_8
2239 		IP0_7_4
2240 		IP0_3_0 ))
2241 	},
2242 	{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
2243 		IP1_31_28
2244 		IP1_27_24
2245 		IP1_23_20
2246 		IP1_19_16
2247 		IP1_15_12
2248 		IP1_11_8
2249 		IP1_7_4
2250 		IP1_3_0 ))
2251 	},
2252 	{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
2253 		IP2_31_28
2254 		IP2_27_24
2255 		IP2_23_20
2256 		IP2_19_16
2257 		IP2_15_12
2258 		IP2_11_8
2259 		IP2_7_4
2260 		IP2_3_0 ))
2261 	},
2262 	{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
2263 		IP3_31_28
2264 		IP3_27_24
2265 		IP3_23_20
2266 		IP3_19_16
2267 		IP3_15_12
2268 		IP3_11_8
2269 		IP3_7_4
2270 		IP3_3_0 ))
2271 	},
2272 	{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
2273 		IP4_31_28
2274 		IP4_27_24
2275 		IP4_23_20
2276 		IP4_19_16
2277 		IP4_15_12
2278 		IP4_11_8
2279 		IP4_7_4
2280 		IP4_3_0 ))
2281 	},
2282 	{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
2283 		IP5_31_28
2284 		IP5_27_24
2285 		IP5_23_20
2286 		IP5_19_16
2287 		IP5_15_12
2288 		IP5_11_8
2289 		IP5_7_4
2290 		IP5_3_0 ))
2291 	},
2292 	{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
2293 		IP6_31_28
2294 		IP6_27_24
2295 		IP6_23_20
2296 		IP6_19_16
2297 		IP6_15_12
2298 		IP6_11_8
2299 		IP6_7_4
2300 		IP6_3_0 ))
2301 	},
2302 	{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
2303 		IP7_31_28
2304 		IP7_27_24
2305 		IP7_23_20
2306 		IP7_19_16
2307 		IP7_15_12
2308 		IP7_11_8
2309 		IP7_7_4
2310 		IP7_3_0 ))
2311 	},
2312 	{ PINMUX_CFG_REG_VAR("IPSR8", 0xe6060220, 32,
2313 			      GROUP(-4, 4, 4, 4, 4, 4, 4, 4),
2314 			      GROUP(
2315 		/* IP8_31_28 RESERVED */
2316 		IP8_27_24
2317 		IP8_23_20
2318 		IP8_19_16
2319 		IP8_15_12
2320 		IP8_11_8
2321 		IP8_7_4
2322 		IP8_3_0 ))
2323 	},
2324 #undef F_
2325 #undef FM
2326 
2327 #define F_(x, y)	x,
2328 #define FM(x)		FN_##x,
2329 	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2330 			     GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2331 			     GROUP(
2332 		/* RESERVED 31-12 */
2333 		MOD_SEL0_11
2334 		MOD_SEL0_10
2335 		MOD_SEL0_9
2336 		MOD_SEL0_8
2337 		MOD_SEL0_7
2338 		MOD_SEL0_6
2339 		MOD_SEL0_5
2340 		MOD_SEL0_4
2341 		MOD_SEL0_3
2342 		MOD_SEL0_2
2343 		MOD_SEL0_1
2344 		MOD_SEL0_0 ))
2345 	},
2346 	{ /* sentinel */ }
2347 };
2348 
2349 enum ioctrl_regs {
2350 	POCCTRL0,
2351 	POCCTRL1,
2352 	POCCTRL2,
2353 	TDSELCTRL,
2354 };
2355 
2356 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
2357 	[POCCTRL0] = { 0xe6060380 },
2358 	[POCCTRL1] = { 0xe6060384 },
2359 	[POCCTRL2] = { 0xe6060388 },
2360 	[TDSELCTRL] = { 0xe60603c0, },
2361 	{ /* sentinel */ }
2362 };
2363 
2364 static int r8a77970_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
2365 {
2366 	int bit = pin & 0x1f;
2367 
2368 	switch (pin) {
2369 	case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 21):
2370 		*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
2371 		return bit;
2372 
2373 	case RCAR_GP_PIN(2, 0) ... RCAR_GP_PIN(2, 9):
2374 		*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
2375 		return bit + 22;
2376 
2377 	case RCAR_GP_PIN(2, 10) ... RCAR_GP_PIN(2, 16):
2378 		*pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
2379 		return bit - 10;
2380 
2381 	case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 16):
2382 		*pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
2383 		return bit + 7;
2384 
2385 	case PIN_VDDQ_AVB0:
2386 		*pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
2387 		return 0;
2388 
2389 	default:
2390 		return -EINVAL;
2391 	}
2392 }
2393 
2394 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
2395 	{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
2396 		[ 0] = RCAR_GP_PIN(0, 0),	/* DU_DR2 */
2397 		[ 1] = RCAR_GP_PIN(0, 1),	/* DU_DR3 */
2398 		[ 2] = RCAR_GP_PIN(0, 2),	/* DU_DR4 */
2399 		[ 3] = RCAR_GP_PIN(0, 3),	/* DU_DR5 */
2400 		[ 4] = RCAR_GP_PIN(0, 4),	/* DU_DR6 */
2401 		[ 5] = RCAR_GP_PIN(0, 5),	/* DU_DR7 */
2402 		[ 6] = RCAR_GP_PIN(0, 6),	/* DU_DG2 */
2403 		[ 7] = RCAR_GP_PIN(0, 7),	/* DU_DG3 */
2404 		[ 8] = RCAR_GP_PIN(0, 8),	/* DU_DG4 */
2405 		[ 9] = RCAR_GP_PIN(0, 9),	/* DU_DG5 */
2406 		[10] = RCAR_GP_PIN(0, 10),	/* DU_DG6 */
2407 		[11] = RCAR_GP_PIN(0, 11),	/* DU_DG7 */
2408 		[12] = RCAR_GP_PIN(0, 12),	/* DU_DB2 */
2409 		[13] = RCAR_GP_PIN(0, 13),	/* DU_DB3 */
2410 		[14] = RCAR_GP_PIN(0, 14),	/* DU_DB4 */
2411 		[15] = RCAR_GP_PIN(0, 15),	/* DU_DB5 */
2412 		[16] = RCAR_GP_PIN(0, 16),	/* DU_DB6 */
2413 		[17] = RCAR_GP_PIN(0, 17),	/* DU_DB7 */
2414 		[18] = RCAR_GP_PIN(0, 18),	/* DU_DOTCLKOUT */
2415 		[19] = RCAR_GP_PIN(0, 19),	/* DU_EXHSYNC/DU_HSYNC */
2416 		[20] = RCAR_GP_PIN(0, 20),	/* DU_EXVSYNC/DU_VSYNC */
2417 		[21] = RCAR_GP_PIN(0, 21),	/* DU_EXODDF/DU_ODDF/DISP/CDE */
2418 		[22] = PIN_DU_DOTCLKIN,		/* DU_DOTCLKIN */
2419 		[23] = PIN_PRESETOUT_N,		/* PRESETOUT# */
2420 		[24] = PIN_EXTALR,		/* EXTALR */
2421 		[25] = PIN_FSCLKST_N,		/* FSCLKST# */
2422 		[26] = RCAR_GP_PIN(1, 0),	/* IRQ0 */
2423 		[27] = PIN_TRST_N,		/* TRST# */
2424 		[28] = PIN_TCK,			/* TCK */
2425 		[29] = PIN_TMS,			/* TMS */
2426 		[30] = PIN_TDI,			/* TDI */
2427 		[31] = RCAR_GP_PIN(2, 0),	/* VI0_CLK */
2428 	} },
2429 	{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
2430 		[ 0] = RCAR_GP_PIN(2, 1),	/* VI0_CLKENB */
2431 		[ 1] = RCAR_GP_PIN(2, 2),	/* VI0_HSYNC# */
2432 		[ 2] = RCAR_GP_PIN(2, 3),	/* VI0_VSYNC# */
2433 		[ 3] = RCAR_GP_PIN(2, 4),	/* VI0_DATA0 */
2434 		[ 4] = RCAR_GP_PIN(2, 5),	/* VI0_DATA1 */
2435 		[ 5] = RCAR_GP_PIN(2, 6),	/* VI0_DATA2 */
2436 		[ 6] = RCAR_GP_PIN(2, 7),	/* VI0_DATA3 */
2437 		[ 7] = RCAR_GP_PIN(2, 8),	/* VI0_DATA4 */
2438 		[ 8] = RCAR_GP_PIN(2, 9),	/* VI0_DATA5 */
2439 		[ 9] = RCAR_GP_PIN(2, 10),	/* VI0_DATA6 */
2440 		[10] = RCAR_GP_PIN(2, 11),	/* VI0_DATA7 */
2441 		[11] = RCAR_GP_PIN(2, 12),	/* VI0_DATA8 */
2442 		[12] = RCAR_GP_PIN(2, 13),	/* VI0_DATA9 */
2443 		[13] = RCAR_GP_PIN(2, 14),	/* VI0_DATA10 */
2444 		[14] = RCAR_GP_PIN(2, 15),	/* VI0_DATA11 */
2445 		[15] = RCAR_GP_PIN(2, 16),	/* VI0_FIELD */
2446 		[16] = RCAR_GP_PIN(3, 0),	/* VI1_CLK */
2447 		[17] = RCAR_GP_PIN(3, 1),	/* VI1_CLKENB */
2448 		[18] = RCAR_GP_PIN(3, 2),	/* VI1_HSYNC# */
2449 		[19] = RCAR_GP_PIN(3, 3),	/* VI1_VSYNC# */
2450 		[20] = RCAR_GP_PIN(3, 4),	/* VI1_DATA0 */
2451 		[21] = RCAR_GP_PIN(3, 5),	/* VI1_DATA1 */
2452 		[22] = RCAR_GP_PIN(3, 6),	/* VI1_DATA2 */
2453 		[23] = RCAR_GP_PIN(3, 7),	/* VI1_DATA3 */
2454 		[24] = RCAR_GP_PIN(3, 8),	/* VI1_DATA4 */
2455 		[25] = RCAR_GP_PIN(3, 9),	/* VI1_DATA5 */
2456 		[26] = RCAR_GP_PIN(3, 10),	/* VI1_DATA6 */
2457 		[27] = RCAR_GP_PIN(3, 11),	/* VI1_DATA7 */
2458 		[28] = RCAR_GP_PIN(3, 12),	/* VI1_DATA8 */
2459 		[29] = RCAR_GP_PIN(3, 13),	/* VI1_DATA9 */
2460 		[30] = RCAR_GP_PIN(3, 14),	/* VI1_DATA10 */
2461 		[31] = RCAR_GP_PIN(3, 15),	/* VI1_DATA11 */
2462 	} },
2463 	{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
2464 		[ 0] = RCAR_GP_PIN(3, 16),	/* VI1_FIELD */
2465 		[ 1] = RCAR_GP_PIN(4, 0),	/* SCL0 */
2466 		[ 2] = RCAR_GP_PIN(4, 1),	/* SDA0 */
2467 		[ 3] = RCAR_GP_PIN(4, 2),	/* SCL1 */
2468 		[ 4] = RCAR_GP_PIN(4, 3),	/* SDA1 */
2469 		[ 5] = RCAR_GP_PIN(4, 4),	/* SCL2 */
2470 		[ 6] = RCAR_GP_PIN(4, 5),	/* SDA2 */
2471 		[ 7] = RCAR_GP_PIN(1, 1),	/* AVB0_RX_CTL */
2472 		[ 8] = RCAR_GP_PIN(1, 2),	/* AVB0_RXC */
2473 		[ 9] = RCAR_GP_PIN(1, 3),	/* AVB0_RD0 */
2474 		[10] = RCAR_GP_PIN(1, 4),	/* AVB0_RD1 */
2475 		[11] = RCAR_GP_PIN(1, 5),	/* AVB0_RD2 */
2476 		[12] = RCAR_GP_PIN(1, 6),	/* AVB0_RD3 */
2477 		[13] = RCAR_GP_PIN(1, 7),	/* AVB0_TX_CTL */
2478 		[14] = RCAR_GP_PIN(1, 8),	/* AVB0_TXC */
2479 		[15] = RCAR_GP_PIN(1, 9),	/* AVB0_TD0 */
2480 		[16] = RCAR_GP_PIN(1, 10),	/* AVB0_TD1 */
2481 		[17] = RCAR_GP_PIN(1, 11),	/* AVB0_TD2 */
2482 		[18] = RCAR_GP_PIN(1, 12),	/* AVB0_TD3 */
2483 		[19] = RCAR_GP_PIN(1, 13),	/* AVB0_TXCREFCLK */
2484 		[20] = RCAR_GP_PIN(1, 14),	/* AVB0_MDIO */
2485 		[21] = RCAR_GP_PIN(1, 15),	/* AVB0_MDC */
2486 		[22] = RCAR_GP_PIN(1, 16),	/* AVB0_MAGIC */
2487 		[23] = RCAR_GP_PIN(1, 17),	/* AVB0_PHY_INT */
2488 		[24] = RCAR_GP_PIN(1, 18),	/* AVB0_LINK */
2489 		[25] = RCAR_GP_PIN(1, 19),	/* AVB0_AVTP_MATCH */
2490 		[26] = RCAR_GP_PIN(1, 20),	/* AVB0_AVTP_CAPTURE */
2491 		[27] = RCAR_GP_PIN(1, 21),	/* CANFD0_TX_A */
2492 		[28] = RCAR_GP_PIN(1, 22),	/* CANFD0_RX_A */
2493 		[29] = RCAR_GP_PIN(1, 23),	/* CANFD1_TX */
2494 		[30] = RCAR_GP_PIN(1, 24),	/* CANFD1_RX */
2495 		[31] = RCAR_GP_PIN(1, 25),	/* CANFD_CLK */
2496 	} },
2497 	{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
2498 		[ 0] = RCAR_GP_PIN(5, 0),	/* QSPI0_SPCLK */
2499 		[ 1] = RCAR_GP_PIN(5, 1),	/* QSPI0_MOSI_IO0 */
2500 		[ 2] = RCAR_GP_PIN(5, 2),	/* QSPI0_MISO_IO1 */
2501 		[ 3] = RCAR_GP_PIN(5, 3),	/* QSPI0_IO2 */
2502 		[ 4] = RCAR_GP_PIN(5, 4),	/* QSPI0_IO3 */
2503 		[ 5] = RCAR_GP_PIN(5, 5),	/* QSPI0_SSL */
2504 		[ 6] = RCAR_GP_PIN(5, 6),	/* QSPI1_SPCLK */
2505 		[ 7] = RCAR_GP_PIN(5, 7),	/* QSPI1_MOSI_IO0 */
2506 		[ 8] = RCAR_GP_PIN(5, 8),	/* QSPI1_MISO_IO1 */
2507 		[ 9] = RCAR_GP_PIN(5, 9),	/* QSPI1_IO2 */
2508 		[10] = RCAR_GP_PIN(5, 10),	/* QSPI1_IO3 */
2509 		[11] = RCAR_GP_PIN(5, 11),	/* QSPI1_SSL */
2510 		[12] = RCAR_GP_PIN(5, 12),	/* RPC_RESET# */
2511 		[13] = RCAR_GP_PIN(5, 13),	/* RPC_WP# */
2512 		[14] = RCAR_GP_PIN(5, 14),	/* RPC_INT# */
2513 		[15] = RCAR_GP_PIN(1, 26),	/* DIGRF_CLKIN */
2514 		[16] = RCAR_GP_PIN(1, 27),	/* DIGRF_CLKOUT */
2515 		[17] = SH_PFC_PIN_NONE,
2516 		[18] = SH_PFC_PIN_NONE,
2517 		[19] = SH_PFC_PIN_NONE,
2518 		[20] = SH_PFC_PIN_NONE,
2519 		[21] = SH_PFC_PIN_NONE,
2520 		[22] = SH_PFC_PIN_NONE,
2521 		[23] = SH_PFC_PIN_NONE,
2522 		[24] = SH_PFC_PIN_NONE,
2523 		[25] = SH_PFC_PIN_NONE,
2524 		[26] = SH_PFC_PIN_NONE,
2525 		[27] = SH_PFC_PIN_NONE,
2526 		[28] = SH_PFC_PIN_NONE,
2527 		[29] = SH_PFC_PIN_NONE,
2528 		[30] = SH_PFC_PIN_NONE,
2529 		[31] = SH_PFC_PIN_NONE,
2530 	} },
2531 	{ /* sentinel */ }
2532 };
2533 
2534 static const struct sh_pfc_soc_operations r8a77970_pfc_ops = {
2535 	.pin_to_pocctrl = r8a77970_pin_to_pocctrl,
2536 	.get_bias = rcar_pinmux_get_bias,
2537 	.set_bias = rcar_pinmux_set_bias,
2538 };
2539 
2540 const struct sh_pfc_soc_info r8a77970_pinmux_info = {
2541 	.name = "r8a77970_pfc",
2542 	.ops = &r8a77970_pfc_ops,
2543 	.unlock_reg = 0xe6060000, /* PMMR */
2544 
2545 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2546 
2547 	.pins = pinmux_pins,
2548 	.nr_pins = ARRAY_SIZE(pinmux_pins),
2549 	.groups = pinmux_groups,
2550 	.nr_groups = ARRAY_SIZE(pinmux_groups),
2551 	.functions = pinmux_functions,
2552 	.nr_functions = ARRAY_SIZE(pinmux_functions),
2553 
2554 	.cfg_regs = pinmux_config_regs,
2555 	.bias_regs = pinmux_bias_regs,
2556 	.ioctrl_regs = pinmux_ioctrl_regs,
2557 
2558 	.pinmux_data = pinmux_data,
2559 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
2560 };
2561