1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R8A779F0 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 * 7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c 8 */ 9 10 #include <linux/errno.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 14 #include "sh_pfc.h" 15 16 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) 17 18 #define CPU_ALL_GP(fn, sfx) \ 19 PORT_GP_CFG_21(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 20 PORT_GP_CFG_25(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ 21 PORT_GP_CFG_17(2, fn, sfx, CFG_FLAGS), \ 22 PORT_GP_CFG_19(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33) 23 24 #define CPU_ALL_NOGP(fn) \ 25 PIN_NOGP_CFG(PRESETOUT0_N, "PRESETOUT0#", fn, SH_PFC_PIN_CFG_PULL_DOWN), \ 26 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) 27 28 /* 29 * F_() : just information 30 * FM() : macro for FN_xxx / xxx_MARK 31 */ 32 33 /* GPSR0 */ 34 #define GPSR0_20 F_(IRQ3, IP2SR0_19_16) 35 #define GPSR0_19 F_(IRQ2, IP2SR0_15_12) 36 #define GPSR0_18 F_(IRQ1, IP2SR0_11_8) 37 #define GPSR0_17 F_(IRQ0, IP2SR0_7_4) 38 #define GPSR0_16 F_(MSIOF0_SS2, IP2SR0_3_0) 39 #define GPSR0_15 F_(MSIOF0_SS1, IP1SR0_31_28) 40 #define GPSR0_14 F_(MSIOF0_SCK, IP1SR0_27_24) 41 #define GPSR0_13 F_(MSIOF0_TXD, IP1SR0_23_20) 42 #define GPSR0_12 F_(MSIOF0_RXD, IP1SR0_19_16) 43 #define GPSR0_11 F_(MSIOF0_SYNC, IP1SR0_15_12) 44 #define GPSR0_10 F_(CTS0_N, IP1SR0_11_8) 45 #define GPSR0_9 F_(RTS0_N, IP1SR0_7_4) 46 #define GPSR0_8 F_(SCK0, IP1SR0_3_0) 47 #define GPSR0_7 F_(TX0, IP0SR0_31_28) 48 #define GPSR0_6 F_(RX0, IP0SR0_27_24) 49 #define GPSR0_5 F_(HRTS0_N, IP0SR0_23_20) 50 #define GPSR0_4 F_(HCTS0_N, IP0SR0_19_16) 51 #define GPSR0_3 F_(HTX0, IP0SR0_15_12) 52 #define GPSR0_2 F_(HRX0, IP0SR0_11_8) 53 #define GPSR0_1 F_(HSCK0, IP0SR0_7_4) 54 #define GPSR0_0 F_(SCIF_CLK, IP0SR0_3_0) 55 56 /* GPSR1 */ 57 #define GPSR1_24 FM(SD_WP) 58 #define GPSR1_23 FM(SD_CD) 59 #define GPSR1_22 FM(MMC_SD_CMD) 60 #define GPSR1_21 FM(MMC_D7) 61 #define GPSR1_20 FM(MMC_DS) 62 #define GPSR1_19 FM(MMC_D6) 63 #define GPSR1_18 FM(MMC_D4) 64 #define GPSR1_17 FM(MMC_D5) 65 #define GPSR1_16 FM(MMC_SD_D3) 66 #define GPSR1_15 FM(MMC_SD_D2) 67 #define GPSR1_14 FM(MMC_SD_D1) 68 #define GPSR1_13 FM(MMC_SD_D0) 69 #define GPSR1_12 FM(MMC_SD_CLK) 70 #define GPSR1_11 FM(GP1_11) 71 #define GPSR1_10 FM(GP1_10) 72 #define GPSR1_9 FM(GP1_09) 73 #define GPSR1_8 FM(GP1_08) 74 #define GPSR1_7 F_(GP1_07, IP0SR1_31_28) 75 #define GPSR1_6 F_(GP1_06, IP0SR1_27_24) 76 #define GPSR1_5 F_(GP1_05, IP0SR1_23_20) 77 #define GPSR1_4 F_(GP1_04, IP0SR1_19_16) 78 #define GPSR1_3 F_(GP1_03, IP0SR1_15_12) 79 #define GPSR1_2 F_(GP1_02, IP0SR1_11_8) 80 #define GPSR1_1 F_(GP1_01, IP0SR1_7_4) 81 #define GPSR1_0 F_(GP1_00, IP0SR1_3_0) 82 83 /* GPSR2 */ 84 #define GPSR2_16 FM(PCIE1_CLKREQ_N) 85 #define GPSR2_15 FM(PCIE0_CLKREQ_N) 86 #define GPSR2_14 FM(QSPI0_IO3) 87 #define GPSR2_13 FM(QSPI0_SSL) 88 #define GPSR2_12 FM(QSPI0_MISO_IO1) 89 #define GPSR2_11 FM(QSPI0_IO2) 90 #define GPSR2_10 FM(QSPI0_SPCLK) 91 #define GPSR2_9 FM(QSPI0_MOSI_IO0) 92 #define GPSR2_8 FM(QSPI1_SPCLK) 93 #define GPSR2_7 FM(QSPI1_MOSI_IO0) 94 #define GPSR2_6 FM(QSPI1_IO2) 95 #define GPSR2_5 FM(QSPI1_MISO_IO1) 96 #define GPSR2_4 FM(QSPI1_IO3) 97 #define GPSR2_3 FM(QSPI1_SSL) 98 #define GPSR2_2 FM(RPC_RESET_N) 99 #define GPSR2_1 FM(RPC_WP_N) 100 #define GPSR2_0 FM(RPC_INT_N) 101 102 /* GPSR3 */ 103 #define GPSR3_18 FM(TSN0_AVTP_CAPTURE_B) 104 #define GPSR3_17 FM(TSN0_AVTP_MATCH_B) 105 #define GPSR3_16 FM(TSN0_AVTP_PPS) 106 #define GPSR3_15 FM(TSN1_AVTP_CAPTURE_B) 107 #define GPSR3_14 FM(TSN1_AVTP_MATCH_B) 108 #define GPSR3_13 FM(TSN1_AVTP_PPS) 109 #define GPSR3_12 FM(TSN0_MAGIC_B) 110 #define GPSR3_11 FM(TSN1_PHY_INT_B) 111 #define GPSR3_10 FM(TSN0_PHY_INT_B) 112 #define GPSR3_9 FM(TSN2_PHY_INT_B) 113 #define GPSR3_8 FM(TSN0_LINK_B) 114 #define GPSR3_7 FM(TSN2_LINK_B) 115 #define GPSR3_6 FM(TSN1_LINK_B) 116 #define GPSR3_5 FM(TSN1_MDC_B) 117 #define GPSR3_4 FM(TSN0_MDC_B) 118 #define GPSR3_3 FM(TSN2_MDC_B) 119 #define GPSR3_2 FM(TSN0_MDIO_B) 120 #define GPSR3_1 FM(TSN2_MDIO_B) 121 #define GPSR3_0 FM(TSN1_MDIO_B) 122 123 /* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 - F */ 124 #define IP0SR0_3_0 FM(SCIF_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 125 #define IP0SR0_7_4 FM(HSCK0) FM(SCK3) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) FM(TSN0_AVTP_CAPTURE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 126 #define IP0SR0_11_8 FM(HRX0) FM(RX3) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) FM(TSN0_AVTP_MATCH_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 127 #define IP0SR0_15_12 FM(HTX0) FM(TX3) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 128 #define IP0SR0_19_16 FM(HCTS0_N) FM(CTS3_N) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) FM(TSN0_MDC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 129 #define IP0SR0_23_20 FM(HRTS0_N) FM(RTS3_N) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) FM(TSN0_MDIO_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 130 #define IP0SR0_27_24 FM(RX0) FM(HRX1) F_(0, 0) FM(MSIOF1_RXD) F_(0, 0) FM(TSN1_AVTP_MATCH_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 131 #define IP0SR0_31_28 FM(TX0) FM(HTX1) F_(0, 0) FM(MSIOF1_TXD) F_(0, 0) FM(TSN1_AVTP_CAPTURE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 132 /* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 - F */ 133 #define IP1SR0_3_0 FM(SCK0) FM(HSCK1) F_(0, 0) FM(MSIOF1_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 134 #define IP1SR0_7_4 FM(RTS0_N) FM(HRTS1_N) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) FM(TSN1_MDIO_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 135 #define IP1SR0_11_8 FM(CTS0_N) FM(HCTS1_N) F_(0, 0) FM(MSIOF1_SYNC) F_(0, 0) FM(TSN1_MDC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 136 #define IP1SR0_15_12 FM(MSIOF0_SYNC) FM(HCTS3_N) FM(CTS1_N) FM(IRQ4) F_(0, 0) FM(TSN0_LINK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 137 #define IP1SR0_19_16 FM(MSIOF0_RXD) FM(HRX3) FM(RX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 138 #define IP1SR0_23_20 FM(MSIOF0_TXD) FM(HTX3) FM(TX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 139 #define IP1SR0_27_24 FM(MSIOF0_SCK) FM(HSCK3) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 140 #define IP1SR0_31_28 FM(MSIOF0_SS1) FM(HRTS3_N) FM(RTS1_N) FM(IRQ5) F_(0, 0) FM(TSN1_LINK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 141 /* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 - F */ 142 #define IP2SR0_3_0 FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TSN2_LINK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 143 #define IP2SR0_7_4 FM(IRQ0) F_(0, 0) F_(0, 0) FM(MSIOF1_SS1) F_(0, 0) FM(TSN0_MAGIC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 144 #define IP2SR0_11_8 FM(IRQ1) F_(0, 0) F_(0, 0) FM(MSIOF1_SS2) F_(0, 0) FM(TSN0_PHY_INT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 145 #define IP2SR0_15_12 FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TSN1_PHY_INT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 146 #define IP2SR0_19_16 FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TSN2_PHY_INT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 147 #define IP2SR0_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 148 #define IP2SR0_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 149 #define IP2SR0_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 150 151 /* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 - F */ 152 #define IP0SR1_3_0 FM(GP1_00) FM(TCLK1) FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 153 #define IP0SR1_7_4 FM(GP1_01) FM(TCLK4) FM(HRX2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 154 #define IP0SR1_11_8 FM(GP1_02) F_(0, 0) FM(HTX2) FM(MSIOF2_SS1) F_(0, 0) FM(TSN2_MDC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 155 #define IP0SR1_15_12 FM(GP1_03) FM(TCLK2) FM(HCTS2_N) FM(MSIOF2_SS2) FM(CTS4_N) FM(TSN2_MDIO_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 156 #define IP0SR1_19_16 FM(GP1_04) FM(TCLK3) FM(HRTS2_N) FM(MSIOF2_SYNC) FM(RTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 157 #define IP0SR1_23_20 FM(GP1_05) FM(MSIOF2_SCK) FM(SCK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 158 #define IP0SR1_27_24 FM(GP1_06) FM(MSIOF2_RXD) FM(RX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 159 #define IP0SR1_31_28 FM(GP1_07) FM(MSIOF2_TXD) FM(TX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 160 161 #define PINMUX_GPSR \ 162 GPSR1_24 \ 163 GPSR1_23 \ 164 GPSR1_22 \ 165 GPSR1_21 \ 166 GPSR0_20 GPSR1_20 \ 167 GPSR0_19 GPSR1_19 \ 168 GPSR0_18 GPSR1_18 GPSR3_18 \ 169 GPSR0_17 GPSR1_17 GPSR3_17 \ 170 GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 \ 171 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 \ 172 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 \ 173 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 \ 174 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 \ 175 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 \ 176 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 \ 177 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 \ 178 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 \ 179 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 \ 180 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 \ 181 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 \ 182 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 \ 183 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 \ 184 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 \ 185 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 \ 186 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 187 188 #define PINMUX_IPSR \ 189 \ 190 FM(IP0SR0_3_0) IP0SR0_3_0 FM(IP1SR0_3_0) IP1SR0_3_0 FM(IP2SR0_3_0) IP2SR0_3_0 \ 191 FM(IP0SR0_7_4) IP0SR0_7_4 FM(IP1SR0_7_4) IP1SR0_7_4 FM(IP2SR0_7_4) IP2SR0_7_4 \ 192 FM(IP0SR0_11_8) IP0SR0_11_8 FM(IP1SR0_11_8) IP1SR0_11_8 FM(IP2SR0_11_8) IP2SR0_11_8 \ 193 FM(IP0SR0_15_12) IP0SR0_15_12 FM(IP1SR0_15_12) IP1SR0_15_12 FM(IP2SR0_15_12) IP2SR0_15_12 \ 194 FM(IP0SR0_19_16) IP0SR0_19_16 FM(IP1SR0_19_16) IP1SR0_19_16 FM(IP2SR0_19_16) IP2SR0_19_16 \ 195 FM(IP0SR0_23_20) IP0SR0_23_20 FM(IP1SR0_23_20) IP1SR0_23_20 FM(IP2SR0_23_20) IP2SR0_23_20 \ 196 FM(IP0SR0_27_24) IP0SR0_27_24 FM(IP1SR0_27_24) IP1SR0_27_24 FM(IP2SR0_27_24) IP2SR0_27_24 \ 197 FM(IP0SR0_31_28) IP0SR0_31_28 FM(IP1SR0_31_28) IP1SR0_31_28 FM(IP2SR0_31_28) IP2SR0_31_28 \ 198 \ 199 FM(IP0SR1_3_0) IP0SR1_3_0 \ 200 FM(IP0SR1_7_4) IP0SR1_7_4 \ 201 FM(IP0SR1_11_8) IP0SR1_11_8 \ 202 FM(IP0SR1_15_12) IP0SR1_15_12 \ 203 FM(IP0SR1_19_16) IP0SR1_19_16 \ 204 FM(IP0SR1_23_20) IP0SR1_23_20 \ 205 FM(IP0SR1_27_24) IP0SR1_27_24 \ 206 FM(IP0SR1_31_28) IP0SR1_31_28 207 208 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ 209 #define MOD_SEL1_11_10 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3) 210 #define MOD_SEL1_9_8 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3) 211 #define MOD_SEL1_7_6 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3) 212 #define MOD_SEL1_5_4 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3) 213 #define MOD_SEL1_3_2 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3) 214 #define MOD_SEL1_1_0 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3) 215 216 #define PINMUX_MOD_SELS \ 217 \ 218 MOD_SEL1_11_10 \ 219 MOD_SEL1_9_8 \ 220 MOD_SEL1_7_6 \ 221 MOD_SEL1_5_4 \ 222 MOD_SEL1_3_2 \ 223 MOD_SEL1_1_0 224 225 #define PINMUX_PHYS \ 226 FM(SCL0) FM(SDA0) FM(SCL1) FM(SDA1) FM(SCL2) FM(SDA2) FM(SCL3) FM(SDA3) \ 227 FM(SCL4) FM(SDA4) FM(SCL5) FM(SDA5) 228 229 enum { 230 PINMUX_RESERVED = 0, 231 232 PINMUX_DATA_BEGIN, 233 GP_ALL(DATA), 234 PINMUX_DATA_END, 235 236 #define F_(x, y) 237 #define FM(x) FN_##x, 238 PINMUX_FUNCTION_BEGIN, 239 GP_ALL(FN), 240 PINMUX_GPSR 241 PINMUX_IPSR 242 PINMUX_MOD_SELS 243 PINMUX_FUNCTION_END, 244 #undef F_ 245 #undef FM 246 247 #define F_(x, y) 248 #define FM(x) x##_MARK, 249 PINMUX_MARK_BEGIN, 250 PINMUX_GPSR 251 PINMUX_IPSR 252 PINMUX_MOD_SELS 253 PINMUX_PHYS 254 PINMUX_MARK_END, 255 #undef F_ 256 #undef FM 257 }; 258 259 static const u16 pinmux_data[] = { 260 PINMUX_DATA_GP_ALL(), 261 262 PINMUX_SINGLE(SD_WP), 263 PINMUX_SINGLE(SD_CD), 264 PINMUX_SINGLE(MMC_SD_CMD), 265 PINMUX_SINGLE(MMC_D7), 266 PINMUX_SINGLE(MMC_DS), 267 PINMUX_SINGLE(MMC_D6), 268 PINMUX_SINGLE(MMC_D4), 269 PINMUX_SINGLE(MMC_D5), 270 PINMUX_SINGLE(MMC_SD_D3), 271 PINMUX_SINGLE(MMC_SD_D2), 272 PINMUX_SINGLE(MMC_SD_D1), 273 PINMUX_SINGLE(MMC_SD_D0), 274 PINMUX_SINGLE(MMC_SD_CLK), 275 PINMUX_SINGLE(PCIE1_CLKREQ_N), 276 PINMUX_SINGLE(PCIE0_CLKREQ_N), 277 PINMUX_SINGLE(QSPI0_IO3), 278 PINMUX_SINGLE(QSPI0_SSL), 279 PINMUX_SINGLE(QSPI0_MISO_IO1), 280 PINMUX_SINGLE(QSPI0_IO2), 281 PINMUX_SINGLE(QSPI0_SPCLK), 282 PINMUX_SINGLE(QSPI0_MOSI_IO0), 283 PINMUX_SINGLE(QSPI1_SPCLK), 284 PINMUX_SINGLE(QSPI1_MOSI_IO0), 285 PINMUX_SINGLE(QSPI1_IO2), 286 PINMUX_SINGLE(QSPI1_MISO_IO1), 287 PINMUX_SINGLE(QSPI1_IO3), 288 PINMUX_SINGLE(QSPI1_SSL), 289 PINMUX_SINGLE(RPC_RESET_N), 290 PINMUX_SINGLE(RPC_WP_N), 291 PINMUX_SINGLE(RPC_INT_N), 292 293 PINMUX_SINGLE(TSN0_AVTP_CAPTURE_B), 294 PINMUX_SINGLE(TSN0_AVTP_MATCH_B), 295 PINMUX_SINGLE(TSN0_AVTP_PPS), 296 PINMUX_SINGLE(TSN1_AVTP_CAPTURE_B), 297 PINMUX_SINGLE(TSN1_AVTP_MATCH_B), 298 PINMUX_SINGLE(TSN1_AVTP_PPS), 299 PINMUX_SINGLE(TSN0_MAGIC_B), 300 PINMUX_SINGLE(TSN1_PHY_INT_B), 301 PINMUX_SINGLE(TSN0_PHY_INT_B), 302 PINMUX_SINGLE(TSN2_PHY_INT_B), 303 PINMUX_SINGLE(TSN0_LINK_B), 304 PINMUX_SINGLE(TSN2_LINK_B), 305 PINMUX_SINGLE(TSN1_LINK_B), 306 PINMUX_SINGLE(TSN1_MDC_B), 307 PINMUX_SINGLE(TSN0_MDC_B), 308 PINMUX_SINGLE(TSN2_MDC_B), 309 PINMUX_SINGLE(TSN0_MDIO_B), 310 PINMUX_SINGLE(TSN2_MDIO_B), 311 PINMUX_SINGLE(TSN1_MDIO_B), 312 313 /* IP0SR0 */ 314 PINMUX_IPSR_GPSR(IP0SR0_3_0, SCIF_CLK), 315 316 PINMUX_IPSR_GPSR(IP0SR0_7_4, HSCK0), 317 PINMUX_IPSR_GPSR(IP0SR0_7_4, SCK3), 318 PINMUX_IPSR_GPSR(IP0SR0_7_4, MSIOF3_SCK), 319 PINMUX_IPSR_GPSR(IP0SR0_7_4, TSN0_AVTP_CAPTURE_A), 320 321 PINMUX_IPSR_GPSR(IP0SR0_11_8, HRX0), 322 PINMUX_IPSR_GPSR(IP0SR0_11_8, RX3), 323 PINMUX_IPSR_GPSR(IP0SR0_11_8, MSIOF3_RXD), 324 PINMUX_IPSR_GPSR(IP0SR0_11_8, TSN0_AVTP_MATCH_A), 325 326 PINMUX_IPSR_GPSR(IP0SR0_15_12, HTX0), 327 PINMUX_IPSR_GPSR(IP0SR0_15_12, TX3), 328 PINMUX_IPSR_GPSR(IP0SR0_15_12, MSIOF3_TXD), 329 330 PINMUX_IPSR_GPSR(IP0SR0_19_16, HCTS0_N), 331 PINMUX_IPSR_GPSR(IP0SR0_19_16, CTS3_N), 332 PINMUX_IPSR_GPSR(IP0SR0_19_16, MSIOF3_SS1), 333 PINMUX_IPSR_GPSR(IP0SR0_19_16, TSN0_MDC_A), 334 335 PINMUX_IPSR_GPSR(IP0SR0_23_20, HRTS0_N), 336 PINMUX_IPSR_GPSR(IP0SR0_23_20, RTS3_N), 337 PINMUX_IPSR_GPSR(IP0SR0_23_20, MSIOF3_SS2), 338 PINMUX_IPSR_GPSR(IP0SR0_23_20, TSN0_MDIO_A), 339 340 PINMUX_IPSR_GPSR(IP0SR0_27_24, RX0), 341 PINMUX_IPSR_GPSR(IP0SR0_27_24, HRX1), 342 PINMUX_IPSR_GPSR(IP0SR0_27_24, MSIOF1_RXD), 343 PINMUX_IPSR_GPSR(IP0SR0_27_24, TSN1_AVTP_MATCH_A), 344 345 PINMUX_IPSR_GPSR(IP0SR0_31_28, TX0), 346 PINMUX_IPSR_GPSR(IP0SR0_31_28, HTX1), 347 PINMUX_IPSR_GPSR(IP0SR0_31_28, MSIOF1_TXD), 348 PINMUX_IPSR_GPSR(IP0SR0_31_28, TSN1_AVTP_CAPTURE_A), 349 350 /* IP1SR0 */ 351 PINMUX_IPSR_GPSR(IP1SR0_3_0, SCK0), 352 PINMUX_IPSR_GPSR(IP1SR0_3_0, HSCK1), 353 PINMUX_IPSR_GPSR(IP1SR0_3_0, MSIOF1_SCK), 354 355 PINMUX_IPSR_GPSR(IP1SR0_7_4, RTS0_N), 356 PINMUX_IPSR_GPSR(IP1SR0_7_4, HRTS1_N), 357 PINMUX_IPSR_GPSR(IP1SR0_7_4, MSIOF3_SYNC), 358 PINMUX_IPSR_GPSR(IP1SR0_7_4, TSN1_MDIO_A), 359 360 PINMUX_IPSR_GPSR(IP1SR0_11_8, CTS0_N), 361 PINMUX_IPSR_GPSR(IP1SR0_11_8, HCTS1_N), 362 PINMUX_IPSR_GPSR(IP1SR0_11_8, MSIOF1_SYNC), 363 PINMUX_IPSR_GPSR(IP1SR0_11_8, TSN1_MDC_A), 364 365 PINMUX_IPSR_GPSR(IP1SR0_15_12, MSIOF0_SYNC), 366 PINMUX_IPSR_GPSR(IP1SR0_15_12, HCTS3_N), 367 PINMUX_IPSR_GPSR(IP1SR0_15_12, CTS1_N), 368 PINMUX_IPSR_GPSR(IP1SR0_15_12, IRQ4), 369 PINMUX_IPSR_GPSR(IP1SR0_15_12, TSN0_LINK_A), 370 371 PINMUX_IPSR_GPSR(IP1SR0_19_16, MSIOF0_RXD), 372 PINMUX_IPSR_GPSR(IP1SR0_19_16, HRX3), 373 PINMUX_IPSR_GPSR(IP1SR0_19_16, RX1), 374 375 PINMUX_IPSR_GPSR(IP1SR0_23_20, MSIOF0_TXD), 376 PINMUX_IPSR_GPSR(IP1SR0_23_20, HTX3), 377 PINMUX_IPSR_GPSR(IP1SR0_23_20, TX1), 378 379 PINMUX_IPSR_GPSR(IP1SR0_27_24, MSIOF0_SCK), 380 PINMUX_IPSR_GPSR(IP1SR0_27_24, HSCK3), 381 PINMUX_IPSR_GPSR(IP1SR0_27_24, SCK1), 382 383 PINMUX_IPSR_GPSR(IP1SR0_31_28, MSIOF0_SS1), 384 PINMUX_IPSR_GPSR(IP1SR0_31_28, HRTS3_N), 385 PINMUX_IPSR_GPSR(IP1SR0_31_28, RTS1_N), 386 PINMUX_IPSR_GPSR(IP1SR0_31_28, IRQ5), 387 PINMUX_IPSR_GPSR(IP1SR0_31_28, TSN1_LINK_A), 388 389 /* IP2SR0 */ 390 PINMUX_IPSR_GPSR(IP2SR0_3_0, MSIOF0_SS2), 391 PINMUX_IPSR_GPSR(IP2SR0_3_0, TSN2_LINK_A), 392 393 PINMUX_IPSR_GPSR(IP2SR0_7_4, IRQ0), 394 PINMUX_IPSR_GPSR(IP2SR0_7_4, MSIOF1_SS1), 395 PINMUX_IPSR_GPSR(IP2SR0_7_4, TSN0_MAGIC_A), 396 397 PINMUX_IPSR_GPSR(IP2SR0_11_8, IRQ1), 398 PINMUX_IPSR_GPSR(IP2SR0_11_8, MSIOF1_SS2), 399 PINMUX_IPSR_GPSR(IP2SR0_11_8, TSN0_PHY_INT_A), 400 401 PINMUX_IPSR_GPSR(IP2SR0_15_12, IRQ2), 402 PINMUX_IPSR_GPSR(IP2SR0_15_12, TSN1_PHY_INT_A), 403 404 PINMUX_IPSR_GPSR(IP2SR0_19_16, IRQ3), 405 PINMUX_IPSR_GPSR(IP2SR0_19_16, TSN2_PHY_INT_A), 406 407 /* IP0SR1 */ 408 /* GP1_00 = SCL0 */ 409 PINMUX_IPSR_MSEL(IP0SR1_3_0, GP1_00, SEL_I2C0_0), 410 PINMUX_IPSR_MSEL(IP0SR1_3_0, TCLK1, SEL_I2C0_0), 411 PINMUX_IPSR_MSEL(IP0SR1_3_0, HSCK2, SEL_I2C0_0), 412 PINMUX_IPSR_PHYS(IP0SR1_3_0, SCL0, SEL_I2C0_3), 413 414 /* GP1_01 = SDA0 */ 415 PINMUX_IPSR_MSEL(IP0SR1_7_4, GP1_01, SEL_I2C0_0), 416 PINMUX_IPSR_MSEL(IP0SR1_7_4, TCLK4, SEL_I2C0_0), 417 PINMUX_IPSR_MSEL(IP0SR1_7_4, HRX2, SEL_I2C0_0), 418 PINMUX_IPSR_PHYS(IP0SR1_7_4, SDA0, SEL_I2C0_3), 419 420 /* GP1_02 = SCL1 */ 421 PINMUX_IPSR_MSEL(IP0SR1_11_8, GP1_02, SEL_I2C1_0), 422 PINMUX_IPSR_MSEL(IP0SR1_11_8, HTX2, SEL_I2C1_0), 423 PINMUX_IPSR_MSEL(IP0SR1_11_8, MSIOF2_SS1, SEL_I2C1_0), 424 PINMUX_IPSR_MSEL(IP0SR1_11_8, TSN2_MDC_A, SEL_I2C1_0), 425 PINMUX_IPSR_PHYS(IP0SR1_11_8, SCL1, SEL_I2C1_3), 426 427 /* GP1_03 = SDA1 */ 428 PINMUX_IPSR_MSEL(IP0SR1_15_12, GP1_03, SEL_I2C1_0), 429 PINMUX_IPSR_MSEL(IP0SR1_15_12, TCLK2, SEL_I2C1_0), 430 PINMUX_IPSR_MSEL(IP0SR1_15_12, HCTS2_N, SEL_I2C1_0), 431 PINMUX_IPSR_MSEL(IP0SR1_15_12, MSIOF2_SS2, SEL_I2C1_0), 432 PINMUX_IPSR_MSEL(IP0SR1_15_12, CTS4_N, SEL_I2C1_0), 433 PINMUX_IPSR_MSEL(IP0SR1_15_12, TSN2_MDIO_A, SEL_I2C1_0), 434 PINMUX_IPSR_PHYS(IP0SR1_15_12, SDA1, SEL_I2C1_3), 435 436 /* GP1_04 = SCL2 */ 437 PINMUX_IPSR_MSEL(IP0SR1_19_16, GP1_04, SEL_I2C2_0), 438 PINMUX_IPSR_MSEL(IP0SR1_19_16, TCLK3, SEL_I2C2_0), 439 PINMUX_IPSR_MSEL(IP0SR1_19_16, HRTS2_N, SEL_I2C2_0), 440 PINMUX_IPSR_MSEL(IP0SR1_19_16, MSIOF2_SYNC, SEL_I2C2_0), 441 PINMUX_IPSR_MSEL(IP0SR1_19_16, RTS4_N, SEL_I2C2_0), 442 PINMUX_IPSR_PHYS(IP0SR1_19_16, SCL2, SEL_I2C2_3), 443 444 /* GP1_05 = SDA2 */ 445 PINMUX_IPSR_MSEL(IP0SR1_23_20, GP1_05, SEL_I2C2_0), 446 PINMUX_IPSR_MSEL(IP0SR1_23_20, MSIOF2_SCK, SEL_I2C2_0), 447 PINMUX_IPSR_MSEL(IP0SR1_23_20, SCK4, SEL_I2C2_0), 448 PINMUX_IPSR_PHYS(IP0SR1_23_20, SDA2, SEL_I2C2_3), 449 450 /* GP1_06 = SCL3 */ 451 PINMUX_IPSR_MSEL(IP0SR1_27_24, GP1_06, SEL_I2C3_0), 452 PINMUX_IPSR_MSEL(IP0SR1_27_24, MSIOF2_RXD, SEL_I2C3_0), 453 PINMUX_IPSR_MSEL(IP0SR1_27_24, RX4, SEL_I2C3_0), 454 PINMUX_IPSR_PHYS(IP0SR1_27_24, SCL3, SEL_I2C3_3), 455 456 /* GP1_07 = SDA3 */ 457 PINMUX_IPSR_MSEL(IP0SR1_31_28, GP1_07, SEL_I2C3_0), 458 PINMUX_IPSR_MSEL(IP0SR1_31_28, MSIOF2_TXD, SEL_I2C3_0), 459 PINMUX_IPSR_MSEL(IP0SR1_31_28, TX4, SEL_I2C3_0), 460 PINMUX_IPSR_PHYS(IP0SR1_31_28, SDA3, SEL_I2C3_3), 461 462 /* GP1_08 = SCL4 */ 463 PINMUX_IPSR_NOGM(0, GP1_08, SEL_I2C4_0), 464 PINMUX_IPSR_NOFN(GP1_08, SCL4, SEL_I2C4_3), 465 466 /* GP1_09 = SDA4 */ 467 PINMUX_IPSR_NOGM(0, GP1_09, SEL_I2C4_0), 468 PINMUX_IPSR_NOFN(GP1_09, SDA4, SEL_I2C4_3), 469 470 /* GP1_10 = SCL5 */ 471 PINMUX_IPSR_NOGM(0, GP1_10, SEL_I2C5_0), 472 PINMUX_IPSR_NOFN(GP1_10, SCL5, SEL_I2C5_3), 473 474 /* GP1_11 = SDA5 */ 475 PINMUX_IPSR_NOGM(0, GP1_11, SEL_I2C5_0), 476 PINMUX_IPSR_NOFN(GP1_11, SDA5, SEL_I2C5_3), 477 }; 478 479 /* 480 * Pins not associated with a GPIO port. 481 */ 482 enum { 483 GP_ASSIGN_LAST(), 484 NOGP_ALL(), 485 }; 486 487 static const struct sh_pfc_pin pinmux_pins[] = { 488 PINMUX_GPIO_GP_ALL(), 489 }; 490 491 /* - HSCIF0 ----------------------------------------------------------------- */ 492 static const unsigned int hscif0_data_pins[] = { 493 /* HRX0, HTX0 */ 494 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 495 }; 496 static const unsigned int hscif0_data_mux[] = { 497 HRX0_MARK, HTX0_MARK, 498 }; 499 static const unsigned int hscif0_clk_pins[] = { 500 /* HSCK0 */ 501 RCAR_GP_PIN(0, 1), 502 }; 503 static const unsigned int hscif0_clk_mux[] = { 504 HSCK0_MARK, 505 }; 506 static const unsigned int hscif0_ctrl_pins[] = { 507 /* HRTS0#, HCTS0# */ 508 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), 509 }; 510 static const unsigned int hscif0_ctrl_mux[] = { 511 HRTS0_N_MARK, HCTS0_N_MARK, 512 }; 513 514 /* - HSCIF1 ----------------------------------------------------------------- */ 515 static const unsigned int hscif1_data_pins[] = { 516 /* HRX1, HTX1 */ 517 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 518 }; 519 static const unsigned int hscif1_data_mux[] = { 520 HRX1_MARK, HTX1_MARK, 521 }; 522 static const unsigned int hscif1_clk_pins[] = { 523 /* HSCK1 */ 524 RCAR_GP_PIN(0, 8), 525 }; 526 static const unsigned int hscif1_clk_mux[] = { 527 HSCK1_MARK, 528 }; 529 static const unsigned int hscif1_ctrl_pins[] = { 530 /* HRTS1#, HCTS1# */ 531 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 532 }; 533 static const unsigned int hscif1_ctrl_mux[] = { 534 HRTS1_N_MARK, HCTS1_N_MARK, 535 }; 536 537 /* - HSCIF2 ----------------------------------------------------------------- */ 538 static const unsigned int hscif2_data_pins[] = { 539 /* HRX2, HTX2 */ 540 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), 541 }; 542 static const unsigned int hscif2_data_mux[] = { 543 HRX2_MARK, HTX2_MARK, 544 }; 545 static const unsigned int hscif2_clk_pins[] = { 546 /* HSCK2 */ 547 RCAR_GP_PIN(1, 0), 548 }; 549 static const unsigned int hscif2_clk_mux[] = { 550 HSCK2_MARK, 551 }; 552 static const unsigned int hscif2_ctrl_pins[] = { 553 /* HRTS2#, HCTS2# */ 554 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), 555 }; 556 static const unsigned int hscif2_ctrl_mux[] = { 557 HRTS2_N_MARK, HCTS2_N_MARK, 558 }; 559 560 /* - HSCIF3 ----------------------------------------------------------------- */ 561 static const unsigned int hscif3_data_pins[] = { 562 /* HRX3, HTX3 */ 563 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 564 }; 565 static const unsigned int hscif3_data_mux[] = { 566 HRX3_MARK, HTX3_MARK, 567 }; 568 static const unsigned int hscif3_clk_pins[] = { 569 /* HSCK3 */ 570 RCAR_GP_PIN(0, 14), 571 }; 572 static const unsigned int hscif3_clk_mux[] = { 573 HSCK3_MARK, 574 }; 575 static const unsigned int hscif3_ctrl_pins[] = { 576 /* HRTS3#, HCTS3# */ 577 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11), 578 }; 579 static const unsigned int hscif3_ctrl_mux[] = { 580 HRTS3_N_MARK, HCTS3_N_MARK, 581 }; 582 583 /* - I2C0 ------------------------------------------------------------------- */ 584 static const unsigned int i2c0_pins[] = { 585 /* SDA0, SCL0 */ 586 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), 587 }; 588 static const unsigned int i2c0_mux[] = { 589 SDA0_MARK, SCL0_MARK, 590 }; 591 592 /* - I2C1 ------------------------------------------------------------------- */ 593 static const unsigned int i2c1_pins[] = { 594 /* SDA1, SCL1 */ 595 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), 596 }; 597 static const unsigned int i2c1_mux[] = { 598 SDA1_MARK, SCL1_MARK, 599 }; 600 601 /* - I2C2 ------------------------------------------------------------------- */ 602 static const unsigned int i2c2_pins[] = { 603 /* SDA2, SCL2 */ 604 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), 605 }; 606 static const unsigned int i2c2_mux[] = { 607 SDA2_MARK, SCL2_MARK, 608 }; 609 610 /* - I2C3 ------------------------------------------------------------------- */ 611 static const unsigned int i2c3_pins[] = { 612 /* SDA3, SCL3 */ 613 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), 614 }; 615 static const unsigned int i2c3_mux[] = { 616 SDA3_MARK, SCL3_MARK, 617 }; 618 619 /* - I2C4 ------------------------------------------------------------------- */ 620 static const unsigned int i2c4_pins[] = { 621 /* SDA4, SCL4 */ 622 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), 623 }; 624 static const unsigned int i2c4_mux[] = { 625 SDA4_MARK, SCL4_MARK, 626 }; 627 628 /* - I2C5 ------------------------------------------------------------------- */ 629 static const unsigned int i2c5_pins[] = { 630 /* SDA5, SCL5 */ 631 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), 632 }; 633 static const unsigned int i2c5_mux[] = { 634 SDA5_MARK, SCL5_MARK, 635 }; 636 637 638 /* - INTC-EX ---------------------------------------------------------------- */ 639 static const unsigned int intc_ex_irq0_pins[] = { 640 /* IRQ0 */ 641 RCAR_GP_PIN(0, 17), 642 }; 643 static const unsigned int intc_ex_irq0_mux[] = { 644 IRQ0_MARK, 645 }; 646 static const unsigned int intc_ex_irq1_pins[] = { 647 /* IRQ1 */ 648 RCAR_GP_PIN(0, 18), 649 }; 650 static const unsigned int intc_ex_irq1_mux[] = { 651 IRQ1_MARK, 652 }; 653 static const unsigned int intc_ex_irq2_pins[] = { 654 /* IRQ2 */ 655 RCAR_GP_PIN(0, 19), 656 }; 657 static const unsigned int intc_ex_irq2_mux[] = { 658 IRQ2_MARK, 659 }; 660 static const unsigned int intc_ex_irq3_pins[] = { 661 /* IRQ3 */ 662 RCAR_GP_PIN(0, 20), 663 }; 664 static const unsigned int intc_ex_irq3_mux[] = { 665 IRQ3_MARK, 666 }; 667 static const unsigned int intc_ex_irq4_pins[] = { 668 /* IRQ4 */ 669 RCAR_GP_PIN(0, 11), 670 }; 671 static const unsigned int intc_ex_irq4_mux[] = { 672 IRQ4_MARK, 673 }; 674 static const unsigned int intc_ex_irq5_pins[] = { 675 /* IRQ5 */ 676 RCAR_GP_PIN(0, 15), 677 }; 678 static const unsigned int intc_ex_irq5_mux[] = { 679 IRQ5_MARK, 680 }; 681 682 /* - MMC -------------------------------------------------------------------- */ 683 static const unsigned int mmc_data_pins[] = { 684 /* MMC_SD_D[0:3], MMC_D[4:7] */ 685 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), 686 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), 687 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17), 688 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 21), 689 }; 690 static const unsigned int mmc_data_mux[] = { 691 MMC_SD_D0_MARK, MMC_SD_D1_MARK, 692 MMC_SD_D2_MARK, MMC_SD_D3_MARK, 693 MMC_D4_MARK, MMC_D5_MARK, 694 MMC_D6_MARK, MMC_D7_MARK, 695 }; 696 static const unsigned int mmc_ctrl_pins[] = { 697 /* MMC_SD_CLK, MMC_SD_CMD */ 698 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 22), 699 }; 700 static const unsigned int mmc_ctrl_mux[] = { 701 MMC_SD_CLK_MARK, MMC_SD_CMD_MARK, 702 }; 703 static const unsigned int mmc_cd_pins[] = { 704 /* SD_CD */ 705 RCAR_GP_PIN(1, 23), 706 }; 707 static const unsigned int mmc_cd_mux[] = { 708 SD_CD_MARK, 709 }; 710 static const unsigned int mmc_wp_pins[] = { 711 /* SD_WP */ 712 RCAR_GP_PIN(1, 24), 713 }; 714 static const unsigned int mmc_wp_mux[] = { 715 SD_WP_MARK, 716 }; 717 static const unsigned int mmc_ds_pins[] = { 718 /* MMC_DS */ 719 RCAR_GP_PIN(1, 20), 720 }; 721 static const unsigned int mmc_ds_mux[] = { 722 MMC_DS_MARK, 723 }; 724 725 /* - MSIOF0 ----------------------------------------------------------------- */ 726 static const unsigned int msiof0_clk_pins[] = { 727 /* MSIOF0_SCK */ 728 RCAR_GP_PIN(0, 14), 729 }; 730 static const unsigned int msiof0_clk_mux[] = { 731 MSIOF0_SCK_MARK, 732 }; 733 static const unsigned int msiof0_sync_pins[] = { 734 /* MSIOF0_SYNC */ 735 RCAR_GP_PIN(0, 11), 736 }; 737 static const unsigned int msiof0_sync_mux[] = { 738 MSIOF0_SYNC_MARK, 739 }; 740 static const unsigned int msiof0_ss1_pins[] = { 741 /* MSIOF0_SS1 */ 742 RCAR_GP_PIN(0, 15), 743 }; 744 static const unsigned int msiof0_ss1_mux[] = { 745 MSIOF0_SS1_MARK, 746 }; 747 static const unsigned int msiof0_ss2_pins[] = { 748 /* MSIOF0_SS2 */ 749 RCAR_GP_PIN(0, 16), 750 }; 751 static const unsigned int msiof0_ss2_mux[] = { 752 MSIOF0_SS2_MARK, 753 }; 754 static const unsigned int msiof0_txd_pins[] = { 755 /* MSIOF0_TXD */ 756 RCAR_GP_PIN(0, 13), 757 }; 758 static const unsigned int msiof0_txd_mux[] = { 759 MSIOF0_TXD_MARK, 760 }; 761 static const unsigned int msiof0_rxd_pins[] = { 762 /* MSIOF0_RXD */ 763 RCAR_GP_PIN(0, 12), 764 }; 765 static const unsigned int msiof0_rxd_mux[] = { 766 MSIOF0_RXD_MARK, 767 }; 768 769 /* - MSIOF1 ----------------------------------------------------------------- */ 770 static const unsigned int msiof1_clk_pins[] = { 771 /* MSIOF1_SCK */ 772 RCAR_GP_PIN(0, 8), 773 }; 774 static const unsigned int msiof1_clk_mux[] = { 775 MSIOF1_SCK_MARK, 776 }; 777 static const unsigned int msiof1_sync_pins[] = { 778 /* MSIOF1_SYNC */ 779 RCAR_GP_PIN(0, 10), 780 }; 781 static const unsigned int msiof1_sync_mux[] = { 782 MSIOF1_SYNC_MARK, 783 }; 784 static const unsigned int msiof1_ss1_pins[] = { 785 /* MSIOF1_SS1 */ 786 RCAR_GP_PIN(0, 17), 787 }; 788 static const unsigned int msiof1_ss1_mux[] = { 789 MSIOF1_SS1_MARK, 790 }; 791 static const unsigned int msiof1_ss2_pins[] = { 792 /* MSIOF1_SS2 */ 793 RCAR_GP_PIN(0, 18), 794 }; 795 static const unsigned int msiof1_ss2_mux[] = { 796 MSIOF1_SS2_MARK, 797 }; 798 static const unsigned int msiof1_txd_pins[] = { 799 /* MSIOF1_TXD */ 800 RCAR_GP_PIN(0, 7), 801 }; 802 static const unsigned int msiof1_txd_mux[] = { 803 MSIOF1_TXD_MARK, 804 }; 805 static const unsigned int msiof1_rxd_pins[] = { 806 /* MSIOF1_RXD */ 807 RCAR_GP_PIN(0, 6), 808 }; 809 static const unsigned int msiof1_rxd_mux[] = { 810 MSIOF1_RXD_MARK, 811 }; 812 813 /* - MSIOF2 ----------------------------------------------------------------- */ 814 static const unsigned int msiof2_clk_pins[] = { 815 /* MSIOF2_SCK */ 816 RCAR_GP_PIN(1, 5), 817 }; 818 static const unsigned int msiof2_clk_mux[] = { 819 MSIOF2_SCK_MARK, 820 }; 821 static const unsigned int msiof2_sync_pins[] = { 822 /* MSIOF2_SYNC */ 823 RCAR_GP_PIN(1, 4), 824 }; 825 static const unsigned int msiof2_sync_mux[] = { 826 MSIOF2_SYNC_MARK, 827 }; 828 static const unsigned int msiof2_ss1_pins[] = { 829 /* MSIOF2_SS1 */ 830 RCAR_GP_PIN(1, 2), 831 }; 832 static const unsigned int msiof2_ss1_mux[] = { 833 MSIOF2_SS1_MARK, 834 }; 835 static const unsigned int msiof2_ss2_pins[] = { 836 /* MSIOF2_SS2 */ 837 RCAR_GP_PIN(1, 3), 838 }; 839 static const unsigned int msiof2_ss2_mux[] = { 840 MSIOF2_SS2_MARK, 841 }; 842 static const unsigned int msiof2_txd_pins[] = { 843 /* MSIOF2_TXD */ 844 RCAR_GP_PIN(1, 7), 845 }; 846 static const unsigned int msiof2_txd_mux[] = { 847 MSIOF2_TXD_MARK, 848 }; 849 static const unsigned int msiof2_rxd_pins[] = { 850 /* MSIOF2_RXD */ 851 RCAR_GP_PIN(1, 6), 852 }; 853 static const unsigned int msiof2_rxd_mux[] = { 854 MSIOF2_RXD_MARK, 855 }; 856 857 /* - MSIOF3 ----------------------------------------------------------------- */ 858 static const unsigned int msiof3_clk_pins[] = { 859 /* MSIOF3_SCK */ 860 RCAR_GP_PIN(0, 1), 861 }; 862 static const unsigned int msiof3_clk_mux[] = { 863 MSIOF3_SCK_MARK, 864 }; 865 static const unsigned int msiof3_sync_pins[] = { 866 /* MSIOF3_SYNC */ 867 RCAR_GP_PIN(0, 9), 868 }; 869 static const unsigned int msiof3_sync_mux[] = { 870 MSIOF3_SYNC_MARK, 871 }; 872 static const unsigned int msiof3_ss1_pins[] = { 873 /* MSIOF3_SS1 */ 874 RCAR_GP_PIN(0, 4), 875 }; 876 static const unsigned int msiof3_ss1_mux[] = { 877 MSIOF3_SS1_MARK, 878 }; 879 static const unsigned int msiof3_ss2_pins[] = { 880 /* MSIOF3_SS2 */ 881 RCAR_GP_PIN(0, 5), 882 }; 883 static const unsigned int msiof3_ss2_mux[] = { 884 MSIOF3_SS2_MARK, 885 }; 886 static const unsigned int msiof3_txd_pins[] = { 887 /* MSIOF3_TXD */ 888 RCAR_GP_PIN(0, 3), 889 }; 890 static const unsigned int msiof3_txd_mux[] = { 891 MSIOF3_TXD_MARK, 892 }; 893 static const unsigned int msiof3_rxd_pins[] = { 894 /* MSIOF3_RXD */ 895 RCAR_GP_PIN(0, 2), 896 }; 897 static const unsigned int msiof3_rxd_mux[] = { 898 MSIOF3_RXD_MARK, 899 }; 900 901 /* - PCIE ------------------------------------------------------------------- */ 902 static const unsigned int pcie0_clkreq_n_pins[] = { 903 /* PCIE0_CLKREQ# */ 904 RCAR_GP_PIN(2, 15), 905 }; 906 907 static const unsigned int pcie0_clkreq_n_mux[] = { 908 PCIE0_CLKREQ_N_MARK, 909 }; 910 911 static const unsigned int pcie1_clkreq_n_pins[] = { 912 /* PCIE1_CLKREQ# */ 913 RCAR_GP_PIN(2, 16), 914 }; 915 916 static const unsigned int pcie1_clkreq_n_mux[] = { 917 PCIE1_CLKREQ_N_MARK, 918 }; 919 920 /* - QSPI0 ------------------------------------------------------------------ */ 921 static const unsigned int qspi0_ctrl_pins[] = { 922 /* SPCLK, SSL */ 923 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), 924 }; 925 static const unsigned int qspi0_ctrl_mux[] = { 926 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, 927 }; 928 static const unsigned int qspi0_data_pins[] = { 929 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 930 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 12), 931 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 14), 932 }; 933 static const unsigned int qspi0_data_mux[] = { 934 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, 935 QSPI0_IO2_MARK, QSPI0_IO3_MARK 936 }; 937 938 /* - QSPI1 ------------------------------------------------------------------ */ 939 static const unsigned int qspi1_ctrl_pins[] = { 940 /* SPCLK, SSL */ 941 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 3), 942 }; 943 static const unsigned int qspi1_ctrl_mux[] = { 944 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, 945 }; 946 static const unsigned int qspi1_data_pins[] = { 947 /* MOSI_IO0, MISO_IO1, IO2, IO3 */ 948 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 5), 949 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 4), 950 }; 951 static const unsigned int qspi1_data_mux[] = { 952 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, 953 QSPI1_IO2_MARK, QSPI1_IO3_MARK 954 }; 955 956 /* - SCIF0 ------------------------------------------------------------------ */ 957 static const unsigned int scif0_data_pins[] = { 958 /* RX0, TX0 */ 959 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 960 }; 961 static const unsigned int scif0_data_mux[] = { 962 RX0_MARK, TX0_MARK, 963 }; 964 static const unsigned int scif0_clk_pins[] = { 965 /* SCK0 */ 966 RCAR_GP_PIN(0, 8), 967 }; 968 static const unsigned int scif0_clk_mux[] = { 969 SCK0_MARK, 970 }; 971 static const unsigned int scif0_ctrl_pins[] = { 972 /* RTS0#, CTS0# */ 973 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 974 }; 975 static const unsigned int scif0_ctrl_mux[] = { 976 RTS0_N_MARK, CTS0_N_MARK, 977 }; 978 979 /* - SCIF1 ------------------------------------------------------------------ */ 980 static const unsigned int scif1_data_pins[] = { 981 /* RX1, TX1 */ 982 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), 983 }; 984 static const unsigned int scif1_data_mux[] = { 985 RX1_MARK, TX1_MARK, 986 }; 987 static const unsigned int scif1_clk_pins[] = { 988 /* SCK1 */ 989 RCAR_GP_PIN(0, 14), 990 }; 991 static const unsigned int scif1_clk_mux[] = { 992 SCK1_MARK, 993 }; 994 static const unsigned int scif1_ctrl_pins[] = { 995 /* RTS1#, CTS1# */ 996 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11), 997 }; 998 static const unsigned int scif1_ctrl_mux[] = { 999 RTS1_N_MARK, CTS1_N_MARK, 1000 }; 1001 1002 /* - SCIF3 ------------------------------------------------------------------ */ 1003 static const unsigned int scif3_data_pins[] = { 1004 /* RX3, TX3 */ 1005 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 1006 }; 1007 static const unsigned int scif3_data_mux[] = { 1008 RX3_MARK, TX3_MARK, 1009 }; 1010 static const unsigned int scif3_clk_pins[] = { 1011 /* SCK3 */ 1012 RCAR_GP_PIN(0, 1), 1013 }; 1014 static const unsigned int scif3_clk_mux[] = { 1015 SCK3_MARK, 1016 }; 1017 static const unsigned int scif3_ctrl_pins[] = { 1018 /* RTS3#, CTS3# */ 1019 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), 1020 }; 1021 static const unsigned int scif3_ctrl_mux[] = { 1022 RTS3_N_MARK, CTS3_N_MARK, 1023 }; 1024 1025 /* - SCIF4 ------------------------------------------------------------------ */ 1026 static const unsigned int scif4_data_pins[] = { 1027 /* RX4, TX4 */ 1028 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), 1029 }; 1030 static const unsigned int scif4_data_mux[] = { 1031 RX4_MARK, TX4_MARK, 1032 }; 1033 static const unsigned int scif4_clk_pins[] = { 1034 /* SCK4 */ 1035 RCAR_GP_PIN(1, 5), 1036 }; 1037 static const unsigned int scif4_clk_mux[] = { 1038 SCK4_MARK, 1039 }; 1040 static const unsigned int scif4_ctrl_pins[] = { 1041 /* RTS4#, CTS4# */ 1042 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), 1043 }; 1044 static const unsigned int scif4_ctrl_mux[] = { 1045 RTS4_N_MARK, CTS4_N_MARK, 1046 }; 1047 1048 /* - SCIF Clock ------------------------------------------------------------- */ 1049 static const unsigned int scif_clk_pins[] = { 1050 /* SCIF_CLK */ 1051 RCAR_GP_PIN(0, 0), 1052 }; 1053 static const unsigned int scif_clk_mux[] = { 1054 SCIF_CLK_MARK, 1055 }; 1056 1057 /* - TSN0 ------------------------------------------------ */ 1058 static const unsigned int tsn0_link_a_pins[] = { 1059 /* TSN0_LINK_A */ 1060 RCAR_GP_PIN(0, 11), 1061 }; 1062 static const unsigned int tsn0_link_a_mux[] = { 1063 TSN0_LINK_A_MARK, 1064 }; 1065 static const unsigned int tsn0_magic_a_pins[] = { 1066 /* TSN0_MAGIC_A */ 1067 RCAR_GP_PIN(0, 17), 1068 }; 1069 static const unsigned int tsn0_magic_a_mux[] = { 1070 TSN0_MAGIC_A_MARK, 1071 }; 1072 static const unsigned int tsn0_phy_int_a_pins[] = { 1073 /* TSN0_PHY_INT_A */ 1074 RCAR_GP_PIN(0, 18), 1075 }; 1076 static const unsigned int tsn0_phy_int_a_mux[] = { 1077 TSN0_PHY_INT_A_MARK, 1078 }; 1079 static const unsigned int tsn0_mdio_a_pins[] = { 1080 /* TSN0_MDC_A, TSN0_MDIO_A */ 1081 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 1082 }; 1083 static const unsigned int tsn0_mdio_a_mux[] = { 1084 TSN0_MDC_A_MARK, TSN0_MDIO_A_MARK, 1085 }; 1086 static const unsigned int tsn0_link_b_pins[] = { 1087 /* TSN0_LINK_B */ 1088 RCAR_GP_PIN(3, 8), 1089 }; 1090 static const unsigned int tsn0_link_b_mux[] = { 1091 TSN0_LINK_B_MARK, 1092 }; 1093 static const unsigned int tsn0_magic_b_pins[] = { 1094 /* TSN0_MAGIC_B */ 1095 RCAR_GP_PIN(3, 12), 1096 }; 1097 static const unsigned int tsn0_magic_b_mux[] = { 1098 TSN0_MAGIC_B_MARK, 1099 }; 1100 static const unsigned int tsn0_phy_int_b_pins[] = { 1101 /* TSN0_PHY_INT_B */ 1102 RCAR_GP_PIN(3, 10), 1103 }; 1104 static const unsigned int tsn0_phy_int_b_mux[] = { 1105 TSN0_PHY_INT_B_MARK, 1106 }; 1107 static const unsigned int tsn0_mdio_b_pins[] = { 1108 /* TSN0_MDC_B, TSN0_MDIO_B */ 1109 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 2), 1110 }; 1111 static const unsigned int tsn0_mdio_b_mux[] = { 1112 TSN0_MDC_B_MARK, TSN0_MDIO_B_MARK, 1113 }; 1114 static const unsigned int tsn0_avtp_pps_pins[] = { 1115 /* TSN0_AVTP_PPS */ 1116 RCAR_GP_PIN(3, 16), 1117 }; 1118 static const unsigned int tsn0_avtp_pps_mux[] = { 1119 TSN0_AVTP_PPS_MARK, 1120 }; 1121 static const unsigned int tsn0_avtp_capture_a_pins[] = { 1122 /* TSN0_AVTP_CAPTURE_A */ 1123 RCAR_GP_PIN(0, 1), 1124 }; 1125 static const unsigned int tsn0_avtp_capture_a_mux[] = { 1126 TSN0_AVTP_CAPTURE_A_MARK, 1127 }; 1128 static const unsigned int tsn0_avtp_match_a_pins[] = { 1129 /* TSN0_AVTP_MATCH_A */ 1130 RCAR_GP_PIN(0, 2), 1131 }; 1132 static const unsigned int tsn0_avtp_match_a_mux[] = { 1133 TSN0_AVTP_MATCH_A_MARK, 1134 }; 1135 static const unsigned int tsn0_avtp_capture_b_pins[] = { 1136 /* TSN0_AVTP_CAPTURE_B */ 1137 RCAR_GP_PIN(3, 18), 1138 }; 1139 static const unsigned int tsn0_avtp_capture_b_mux[] = { 1140 TSN0_AVTP_CAPTURE_B_MARK, 1141 }; 1142 static const unsigned int tsn0_avtp_match_b_pins[] = { 1143 /* TSN0_AVTP_MATCH_B */ 1144 RCAR_GP_PIN(3, 17), 1145 }; 1146 static const unsigned int tsn0_avtp_match_b_mux[] = { 1147 TSN0_AVTP_MATCH_B_MARK, 1148 }; 1149 1150 /* - TSN1 ------------------------------------------------ */ 1151 static const unsigned int tsn1_link_a_pins[] = { 1152 /* TSN1_LINK_A */ 1153 RCAR_GP_PIN(0, 15), 1154 }; 1155 static const unsigned int tsn1_link_a_mux[] = { 1156 TSN1_LINK_A_MARK, 1157 }; 1158 static const unsigned int tsn1_phy_int_a_pins[] = { 1159 /* TSN1_PHY_INT_A */ 1160 RCAR_GP_PIN(0, 19), 1161 }; 1162 static const unsigned int tsn1_phy_int_a_mux[] = { 1163 TSN1_PHY_INT_A_MARK, 1164 }; 1165 static const unsigned int tsn1_mdio_a_pins[] = { 1166 /* TSN1_MDC_A, TSN1_MDIO_A */ 1167 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9), 1168 }; 1169 static const unsigned int tsn1_mdio_a_mux[] = { 1170 TSN1_MDC_A_MARK, TSN1_MDIO_A_MARK, 1171 }; 1172 static const unsigned int tsn1_link_b_pins[] = { 1173 /* TSN1_LINK_B */ 1174 RCAR_GP_PIN(3, 6), 1175 }; 1176 static const unsigned int tsn1_link_b_mux[] = { 1177 TSN1_LINK_B_MARK, 1178 }; 1179 static const unsigned int tsn1_phy_int_b_pins[] = { 1180 /* TSN1_PHY_INT_B */ 1181 RCAR_GP_PIN(3, 11), 1182 }; 1183 static const unsigned int tsn1_phy_int_b_mux[] = { 1184 TSN1_PHY_INT_B_MARK, 1185 }; 1186 static const unsigned int tsn1_mdio_b_pins[] = { 1187 /* TSN1_MDC_B, TSN1_MDIO_B */ 1188 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0), 1189 }; 1190 static const unsigned int tsn1_mdio_b_mux[] = { 1191 TSN1_MDC_B_MARK, TSN1_MDIO_B_MARK, 1192 }; 1193 static const unsigned int tsn1_avtp_pps_pins[] = { 1194 /* TSN1_AVTP_PPS */ 1195 RCAR_GP_PIN(3, 13), 1196 }; 1197 static const unsigned int tsn1_avtp_pps_mux[] = { 1198 TSN0_AVTP_PPS_MARK, 1199 }; 1200 static const unsigned int tsn1_avtp_capture_a_pins[] = { 1201 /* TSN1_AVTP_CAPTURE_A */ 1202 RCAR_GP_PIN(0, 7), 1203 }; 1204 static const unsigned int tsn1_avtp_capture_a_mux[] = { 1205 TSN1_AVTP_CAPTURE_A_MARK, 1206 }; 1207 static const unsigned int tsn1_avtp_match_a_pins[] = { 1208 /* TSN1_AVTP_MATCH_A */ 1209 RCAR_GP_PIN(0, 6), 1210 }; 1211 static const unsigned int tsn1_avtp_match_a_mux[] = { 1212 TSN1_AVTP_MATCH_A_MARK, 1213 }; 1214 static const unsigned int tsn1_avtp_capture_b_pins[] = { 1215 /* TSN1_AVTP_CAPTURE_B */ 1216 RCAR_GP_PIN(3, 15), 1217 }; 1218 static const unsigned int tsn1_avtp_capture_b_mux[] = { 1219 TSN1_AVTP_CAPTURE_B_MARK, 1220 }; 1221 static const unsigned int tsn1_avtp_match_b_pins[] = { 1222 /* TSN1_AVTP_MATCH_B */ 1223 RCAR_GP_PIN(3, 14), 1224 }; 1225 static const unsigned int tsn1_avtp_match_b_mux[] = { 1226 TSN1_AVTP_MATCH_B_MARK, 1227 }; 1228 1229 /* - TSN2 ------------------------------------------------ */ 1230 static const unsigned int tsn2_link_a_pins[] = { 1231 /* TSN2_LINK_A */ 1232 RCAR_GP_PIN(0, 16), 1233 }; 1234 static const unsigned int tsn2_link_a_mux[] = { 1235 TSN2_LINK_A_MARK, 1236 }; 1237 static const unsigned int tsn2_phy_int_a_pins[] = { 1238 /* TSN2_PHY_INT_A */ 1239 RCAR_GP_PIN(0, 20), 1240 }; 1241 static const unsigned int tsn2_phy_int_a_mux[] = { 1242 TSN2_PHY_INT_A_MARK, 1243 }; 1244 static const unsigned int tsn2_mdio_a_pins[] = { 1245 /* TSN2_MDC_A, TSN2_MDIO_A */ 1246 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 1247 }; 1248 static const unsigned int tsn2_mdio_a_mux[] = { 1249 TSN2_MDC_A_MARK, TSN2_MDIO_A_MARK, 1250 }; 1251 static const unsigned int tsn2_link_b_pins[] = { 1252 /* TSN2_LINK_B */ 1253 RCAR_GP_PIN(3, 7), 1254 }; 1255 static const unsigned int tsn2_link_b_mux[] = { 1256 TSN2_LINK_B_MARK, 1257 }; 1258 static const unsigned int tsn2_phy_int_b_pins[] = { 1259 /* TSN2_PHY_INT_B */ 1260 RCAR_GP_PIN(3, 9), 1261 }; 1262 static const unsigned int tsn2_phy_int_b_mux[] = { 1263 TSN2_PHY_INT_B_MARK, 1264 }; 1265 static const unsigned int tsn2_mdio_b_pins[] = { 1266 /* TSN2_MDC_B, TSN2_MDIO_B */ 1267 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 1), 1268 }; 1269 static const unsigned int tsn2_mdio_b_mux[] = { 1270 TSN2_MDC_B_MARK, TSN2_MDIO_B_MARK, 1271 }; 1272 1273 static const struct sh_pfc_pin_group pinmux_groups[] = { 1274 SH_PFC_PIN_GROUP(hscif0_data), 1275 SH_PFC_PIN_GROUP(hscif0_clk), 1276 SH_PFC_PIN_GROUP(hscif0_ctrl), 1277 SH_PFC_PIN_GROUP(hscif1_data), 1278 SH_PFC_PIN_GROUP(hscif1_clk), 1279 SH_PFC_PIN_GROUP(hscif1_ctrl), 1280 SH_PFC_PIN_GROUP(hscif2_data), 1281 SH_PFC_PIN_GROUP(hscif2_clk), 1282 SH_PFC_PIN_GROUP(hscif2_ctrl), 1283 SH_PFC_PIN_GROUP(hscif3_data), 1284 SH_PFC_PIN_GROUP(hscif3_clk), 1285 SH_PFC_PIN_GROUP(hscif3_ctrl), 1286 SH_PFC_PIN_GROUP(i2c0), 1287 SH_PFC_PIN_GROUP(i2c1), 1288 SH_PFC_PIN_GROUP(i2c2), 1289 SH_PFC_PIN_GROUP(i2c3), 1290 SH_PFC_PIN_GROUP(i2c4), 1291 SH_PFC_PIN_GROUP(i2c5), 1292 SH_PFC_PIN_GROUP(intc_ex_irq0), 1293 SH_PFC_PIN_GROUP(intc_ex_irq1), 1294 SH_PFC_PIN_GROUP(intc_ex_irq2), 1295 SH_PFC_PIN_GROUP(intc_ex_irq3), 1296 SH_PFC_PIN_GROUP(intc_ex_irq4), 1297 SH_PFC_PIN_GROUP(intc_ex_irq5), 1298 BUS_DATA_PIN_GROUP(mmc_data, 1), 1299 BUS_DATA_PIN_GROUP(mmc_data, 4), 1300 BUS_DATA_PIN_GROUP(mmc_data, 8), 1301 SH_PFC_PIN_GROUP(mmc_ctrl), 1302 SH_PFC_PIN_GROUP(mmc_cd), 1303 SH_PFC_PIN_GROUP(mmc_wp), 1304 SH_PFC_PIN_GROUP(mmc_ds), 1305 SH_PFC_PIN_GROUP(msiof0_clk), 1306 SH_PFC_PIN_GROUP(msiof0_sync), 1307 SH_PFC_PIN_GROUP(msiof0_ss1), 1308 SH_PFC_PIN_GROUP(msiof0_ss2), 1309 SH_PFC_PIN_GROUP(msiof0_txd), 1310 SH_PFC_PIN_GROUP(msiof0_rxd), 1311 SH_PFC_PIN_GROUP(msiof1_clk), 1312 SH_PFC_PIN_GROUP(msiof1_sync), 1313 SH_PFC_PIN_GROUP(msiof1_ss1), 1314 SH_PFC_PIN_GROUP(msiof1_ss2), 1315 SH_PFC_PIN_GROUP(msiof1_txd), 1316 SH_PFC_PIN_GROUP(msiof1_rxd), 1317 SH_PFC_PIN_GROUP(msiof2_clk), 1318 SH_PFC_PIN_GROUP(msiof2_sync), 1319 SH_PFC_PIN_GROUP(msiof2_ss1), 1320 SH_PFC_PIN_GROUP(msiof2_ss2), 1321 SH_PFC_PIN_GROUP(msiof2_txd), 1322 SH_PFC_PIN_GROUP(msiof2_rxd), 1323 SH_PFC_PIN_GROUP(msiof3_clk), 1324 SH_PFC_PIN_GROUP(msiof3_sync), 1325 SH_PFC_PIN_GROUP(msiof3_ss1), 1326 SH_PFC_PIN_GROUP(msiof3_ss2), 1327 SH_PFC_PIN_GROUP(msiof3_txd), 1328 SH_PFC_PIN_GROUP(msiof3_rxd), 1329 SH_PFC_PIN_GROUP(pcie0_clkreq_n), 1330 SH_PFC_PIN_GROUP(pcie1_clkreq_n), 1331 SH_PFC_PIN_GROUP(qspi0_ctrl), 1332 BUS_DATA_PIN_GROUP(qspi0_data, 2), 1333 BUS_DATA_PIN_GROUP(qspi0_data, 4), 1334 SH_PFC_PIN_GROUP(qspi1_ctrl), 1335 BUS_DATA_PIN_GROUP(qspi1_data, 2), 1336 BUS_DATA_PIN_GROUP(qspi1_data, 4), 1337 SH_PFC_PIN_GROUP(scif0_data), 1338 SH_PFC_PIN_GROUP(scif0_clk), 1339 SH_PFC_PIN_GROUP(scif0_ctrl), 1340 SH_PFC_PIN_GROUP(scif1_data), 1341 SH_PFC_PIN_GROUP(scif1_clk), 1342 SH_PFC_PIN_GROUP(scif1_ctrl), 1343 SH_PFC_PIN_GROUP(scif3_data), 1344 SH_PFC_PIN_GROUP(scif3_clk), 1345 SH_PFC_PIN_GROUP(scif3_ctrl), 1346 SH_PFC_PIN_GROUP(scif4_data), 1347 SH_PFC_PIN_GROUP(scif4_clk), 1348 SH_PFC_PIN_GROUP(scif4_ctrl), 1349 SH_PFC_PIN_GROUP(scif_clk), 1350 SH_PFC_PIN_GROUP(tsn0_link_a), 1351 SH_PFC_PIN_GROUP(tsn0_magic_a), 1352 SH_PFC_PIN_GROUP(tsn0_phy_int_a), 1353 SH_PFC_PIN_GROUP(tsn0_mdio_a), 1354 SH_PFC_PIN_GROUP(tsn0_link_b), 1355 SH_PFC_PIN_GROUP(tsn0_magic_b), 1356 SH_PFC_PIN_GROUP(tsn0_phy_int_b), 1357 SH_PFC_PIN_GROUP(tsn0_mdio_b), 1358 SH_PFC_PIN_GROUP(tsn0_avtp_pps), 1359 SH_PFC_PIN_GROUP(tsn0_avtp_capture_a), 1360 SH_PFC_PIN_GROUP(tsn0_avtp_match_a), 1361 SH_PFC_PIN_GROUP(tsn0_avtp_capture_b), 1362 SH_PFC_PIN_GROUP(tsn0_avtp_match_b), 1363 SH_PFC_PIN_GROUP(tsn1_link_a), 1364 SH_PFC_PIN_GROUP(tsn1_phy_int_a), 1365 SH_PFC_PIN_GROUP(tsn1_mdio_a), 1366 SH_PFC_PIN_GROUP(tsn1_link_b), 1367 SH_PFC_PIN_GROUP(tsn1_phy_int_b), 1368 SH_PFC_PIN_GROUP(tsn1_mdio_b), 1369 SH_PFC_PIN_GROUP(tsn1_avtp_pps), 1370 SH_PFC_PIN_GROUP(tsn1_avtp_capture_a), 1371 SH_PFC_PIN_GROUP(tsn1_avtp_match_a), 1372 SH_PFC_PIN_GROUP(tsn1_avtp_capture_b), 1373 SH_PFC_PIN_GROUP(tsn1_avtp_match_b), 1374 SH_PFC_PIN_GROUP(tsn2_link_a), 1375 SH_PFC_PIN_GROUP(tsn2_phy_int_a), 1376 SH_PFC_PIN_GROUP(tsn2_mdio_a), 1377 SH_PFC_PIN_GROUP(tsn2_link_b), 1378 SH_PFC_PIN_GROUP(tsn2_phy_int_b), 1379 SH_PFC_PIN_GROUP(tsn2_mdio_b), 1380 }; 1381 1382 static const char * const hscif0_groups[] = { 1383 "hscif0_data", 1384 "hscif0_clk", 1385 "hscif0_ctrl", 1386 }; 1387 1388 static const char * const hscif1_groups[] = { 1389 "hscif1_data", 1390 "hscif1_clk", 1391 "hscif1_ctrl", 1392 }; 1393 1394 static const char * const hscif2_groups[] = { 1395 "hscif2_data", 1396 "hscif2_clk", 1397 "hscif2_ctrl", 1398 }; 1399 1400 static const char * const hscif3_groups[] = { 1401 "hscif3_data", 1402 "hscif3_clk", 1403 "hscif3_ctrl", 1404 }; 1405 1406 static const char * const i2c0_groups[] = { 1407 "i2c0", 1408 }; 1409 1410 static const char * const i2c1_groups[] = { 1411 "i2c1", 1412 }; 1413 1414 static const char * const i2c2_groups[] = { 1415 "i2c2", 1416 }; 1417 1418 static const char * const i2c3_groups[] = { 1419 "i2c3", 1420 }; 1421 1422 static const char * const i2c4_groups[] = { 1423 "i2c4", 1424 }; 1425 1426 static const char * const i2c5_groups[] = { 1427 "i2c5", 1428 }; 1429 1430 static const char * const intc_ex_groups[] = { 1431 "intc_ex_irq0", 1432 "intc_ex_irq1", 1433 "intc_ex_irq2", 1434 "intc_ex_irq3", 1435 "intc_ex_irq4", 1436 "intc_ex_irq5", 1437 }; 1438 1439 static const char * const mmc_groups[] = { 1440 "mmc_data1", 1441 "mmc_data4", 1442 "mmc_data8", 1443 "mmc_ctrl", 1444 "mmc_cd", 1445 "mmc_wp", 1446 "mmc_ds", 1447 }; 1448 1449 static const char * const msiof0_groups[] = { 1450 "msiof0_clk", 1451 "msiof0_sync", 1452 "msiof0_ss1", 1453 "msiof0_ss2", 1454 "msiof0_txd", 1455 "msiof0_rxd", 1456 }; 1457 1458 static const char * const msiof1_groups[] = { 1459 "msiof1_clk", 1460 "msiof1_sync", 1461 "msiof1_ss1", 1462 "msiof1_ss2", 1463 "msiof1_txd", 1464 "msiof1_rxd", 1465 }; 1466 1467 static const char * const msiof2_groups[] = { 1468 "msiof2_clk", 1469 "msiof2_sync", 1470 "msiof2_ss1", 1471 "msiof2_ss2", 1472 "msiof2_txd", 1473 "msiof2_rxd", 1474 }; 1475 1476 static const char * const msiof3_groups[] = { 1477 "msiof3_clk", 1478 "msiof3_sync", 1479 "msiof3_ss1", 1480 "msiof3_ss2", 1481 "msiof3_txd", 1482 "msiof3_rxd", 1483 }; 1484 1485 static const char * const pcie_groups[] = { 1486 "pcie0_clkreq_n", 1487 "pcie1_clkreq_n", 1488 }; 1489 1490 static const char * const qspi0_groups[] = { 1491 "qspi0_ctrl", 1492 "qspi0_data2", 1493 "qspi0_data4", 1494 }; 1495 1496 static const char * const qspi1_groups[] = { 1497 "qspi1_ctrl", 1498 "qspi1_data2", 1499 "qspi1_data4", 1500 }; 1501 1502 static const char * const scif0_groups[] = { 1503 "scif0_data", 1504 "scif0_clk", 1505 "scif0_ctrl", 1506 }; 1507 1508 static const char * const scif1_groups[] = { 1509 "scif1_data", 1510 "scif1_clk", 1511 "scif1_ctrl", 1512 }; 1513 1514 static const char * const scif3_groups[] = { 1515 "scif3_data", 1516 "scif3_clk", 1517 "scif3_ctrl", 1518 }; 1519 1520 static const char * const scif4_groups[] = { 1521 "scif4_data", 1522 "scif4_clk", 1523 "scif4_ctrl", 1524 }; 1525 1526 static const char * const scif_clk_groups[] = { 1527 "scif_clk", 1528 }; 1529 1530 static const char * const tsn0_groups[] = { 1531 "tsn0_link_a", 1532 "tsn0_magic_a", 1533 "tsn0_phy_int_a", 1534 "tsn0_mdio_a", 1535 "tsn0_link_b", 1536 "tsn0_magic_b", 1537 "tsn0_phy_int_b", 1538 "tsn0_mdio_b", 1539 "tsn0_avtp_pps", 1540 "tsn0_avtp_capture_a", 1541 "tsn0_avtp_match_a", 1542 "tsn0_avtp_capture_b", 1543 "tsn0_avtp_match_b", 1544 }; 1545 1546 static const char * const tsn1_groups[] = { 1547 "tsn1_link_a", 1548 "tsn1_phy_int_a", 1549 "tsn1_mdio_a", 1550 "tsn1_link_b", 1551 "tsn1_phy_int_b", 1552 "tsn1_mdio_b", 1553 "tsn1_avtp_pps", 1554 "tsn1_avtp_capture_a", 1555 "tsn1_avtp_match_a", 1556 "tsn1_avtp_capture_b", 1557 "tsn1_avtp_match_b", 1558 }; 1559 1560 static const char * const tsn2_groups[] = { 1561 "tsn2_link_a", 1562 "tsn2_phy_int_a", 1563 "tsn2_mdio_a", 1564 "tsn2_link_b", 1565 "tsn2_phy_int_b", 1566 "tsn2_mdio_b", 1567 }; 1568 1569 static const struct sh_pfc_function pinmux_functions[] = { 1570 SH_PFC_FUNCTION(hscif0), 1571 SH_PFC_FUNCTION(hscif1), 1572 SH_PFC_FUNCTION(hscif2), 1573 SH_PFC_FUNCTION(hscif3), 1574 SH_PFC_FUNCTION(i2c0), 1575 SH_PFC_FUNCTION(i2c1), 1576 SH_PFC_FUNCTION(i2c2), 1577 SH_PFC_FUNCTION(i2c3), 1578 SH_PFC_FUNCTION(i2c4), 1579 SH_PFC_FUNCTION(i2c5), 1580 SH_PFC_FUNCTION(intc_ex), 1581 SH_PFC_FUNCTION(mmc), 1582 SH_PFC_FUNCTION(msiof0), 1583 SH_PFC_FUNCTION(msiof1), 1584 SH_PFC_FUNCTION(msiof2), 1585 SH_PFC_FUNCTION(msiof3), 1586 SH_PFC_FUNCTION(pcie), 1587 SH_PFC_FUNCTION(qspi0), 1588 SH_PFC_FUNCTION(qspi1), 1589 SH_PFC_FUNCTION(scif0), 1590 SH_PFC_FUNCTION(scif1), 1591 SH_PFC_FUNCTION(scif3), 1592 SH_PFC_FUNCTION(scif4), 1593 SH_PFC_FUNCTION(scif_clk), 1594 SH_PFC_FUNCTION(tsn0), 1595 SH_PFC_FUNCTION(tsn1), 1596 SH_PFC_FUNCTION(tsn2), 1597 }; 1598 1599 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 1600 #define F_(x, y) FN_##y 1601 #define FM(x) FN_##x 1602 { PINMUX_CFG_REG("GPSR0", 0xe6050040, 32, 1, GROUP( 1603 0, 0, 1604 0, 0, 1605 0, 0, 1606 0, 0, 1607 0, 0, 1608 0, 0, 1609 0, 0, 1610 0, 0, 1611 0, 0, 1612 0, 0, 1613 0, 0, 1614 GP_0_20_FN, GPSR0_20, 1615 GP_0_19_FN, GPSR0_19, 1616 GP_0_18_FN, GPSR0_18, 1617 GP_0_17_FN, GPSR0_17, 1618 GP_0_16_FN, GPSR0_16, 1619 GP_0_15_FN, GPSR0_15, 1620 GP_0_14_FN, GPSR0_14, 1621 GP_0_13_FN, GPSR0_13, 1622 GP_0_12_FN, GPSR0_12, 1623 GP_0_11_FN, GPSR0_11, 1624 GP_0_10_FN, GPSR0_10, 1625 GP_0_9_FN, GPSR0_9, 1626 GP_0_8_FN, GPSR0_8, 1627 GP_0_7_FN, GPSR0_7, 1628 GP_0_6_FN, GPSR0_6, 1629 GP_0_5_FN, GPSR0_5, 1630 GP_0_4_FN, GPSR0_4, 1631 GP_0_3_FN, GPSR0_3, 1632 GP_0_2_FN, GPSR0_2, 1633 GP_0_1_FN, GPSR0_1, 1634 GP_0_0_FN, GPSR0_0, )) 1635 }, 1636 { PINMUX_CFG_REG("GPSR1", 0xe6050840, 32, 1, GROUP( 1637 0, 0, 1638 0, 0, 1639 0, 0, 1640 0, 0, 1641 0, 0, 1642 0, 0, 1643 0, 0, 1644 GP_1_24_FN, GPSR1_24, 1645 GP_1_23_FN, GPSR1_23, 1646 GP_1_22_FN, GPSR1_22, 1647 GP_1_21_FN, GPSR1_21, 1648 GP_1_20_FN, GPSR1_20, 1649 GP_1_19_FN, GPSR1_19, 1650 GP_1_18_FN, GPSR1_18, 1651 GP_1_17_FN, GPSR1_17, 1652 GP_1_16_FN, GPSR1_16, 1653 GP_1_15_FN, GPSR1_15, 1654 GP_1_14_FN, GPSR1_14, 1655 GP_1_13_FN, GPSR1_13, 1656 GP_1_12_FN, GPSR1_12, 1657 GP_1_11_FN, GPSR1_11, 1658 GP_1_10_FN, GPSR1_10, 1659 GP_1_9_FN, GPSR1_9, 1660 GP_1_8_FN, GPSR1_8, 1661 GP_1_7_FN, GPSR1_7, 1662 GP_1_6_FN, GPSR1_6, 1663 GP_1_5_FN, GPSR1_5, 1664 GP_1_4_FN, GPSR1_4, 1665 GP_1_3_FN, GPSR1_3, 1666 GP_1_2_FN, GPSR1_2, 1667 GP_1_1_FN, GPSR1_1, 1668 GP_1_0_FN, GPSR1_0, )) 1669 }, 1670 { PINMUX_CFG_REG("GPSR2", 0xe6051040, 32, 1, GROUP( 1671 0, 0, 1672 0, 0, 1673 0, 0, 1674 0, 0, 1675 0, 0, 1676 0, 0, 1677 0, 0, 1678 0, 0, 1679 0, 0, 1680 0, 0, 1681 0, 0, 1682 0, 0, 1683 0, 0, 1684 0, 0, 1685 0, 0, 1686 GP_2_16_FN, GPSR2_16, 1687 GP_2_15_FN, GPSR2_15, 1688 GP_2_14_FN, GPSR2_14, 1689 GP_2_13_FN, GPSR2_13, 1690 GP_2_12_FN, GPSR2_12, 1691 GP_2_11_FN, GPSR2_11, 1692 GP_2_10_FN, GPSR2_10, 1693 GP_2_9_FN, GPSR2_9, 1694 GP_2_8_FN, GPSR2_8, 1695 GP_2_7_FN, GPSR2_7, 1696 GP_2_6_FN, GPSR2_6, 1697 GP_2_5_FN, GPSR2_5, 1698 GP_2_4_FN, GPSR2_4, 1699 GP_2_3_FN, GPSR2_3, 1700 GP_2_2_FN, GPSR2_2, 1701 GP_2_1_FN, GPSR2_1, 1702 GP_2_0_FN, GPSR2_0, )) 1703 }, 1704 { PINMUX_CFG_REG("GPSR3", 0xe6051840, 32, 1, GROUP( 1705 0, 0, 1706 0, 0, 1707 0, 0, 1708 0, 0, 1709 0, 0, 1710 0, 0, 1711 0, 0, 1712 0, 0, 1713 0, 0, 1714 0, 0, 1715 0, 0, 1716 0, 0, 1717 0, 0, 1718 GP_3_18_FN, GPSR3_18, 1719 GP_3_17_FN, GPSR3_17, 1720 GP_3_16_FN, GPSR3_16, 1721 GP_3_15_FN, GPSR3_15, 1722 GP_3_14_FN, GPSR3_14, 1723 GP_3_13_FN, GPSR3_13, 1724 GP_3_12_FN, GPSR3_12, 1725 GP_3_11_FN, GPSR3_11, 1726 GP_3_10_FN, GPSR3_10, 1727 GP_3_9_FN, GPSR3_9, 1728 GP_3_8_FN, GPSR3_8, 1729 GP_3_7_FN, GPSR3_7, 1730 GP_3_6_FN, GPSR3_6, 1731 GP_3_5_FN, GPSR3_5, 1732 GP_3_4_FN, GPSR3_4, 1733 GP_3_3_FN, GPSR3_3, 1734 GP_3_2_FN, GPSR3_2, 1735 GP_3_1_FN, GPSR3_1, 1736 GP_3_0_FN, GPSR3_0, )) 1737 }, 1738 #undef F_ 1739 #undef FM 1740 1741 #define F_(x, y) x, 1742 #define FM(x) FN_##x, 1743 { PINMUX_CFG_REG("IP0SR0", 0xe6050060, 32, 4, GROUP( 1744 IP0SR0_31_28 1745 IP0SR0_27_24 1746 IP0SR0_23_20 1747 IP0SR0_19_16 1748 IP0SR0_15_12 1749 IP0SR0_11_8 1750 IP0SR0_7_4 1751 IP0SR0_3_0)) 1752 }, 1753 { PINMUX_CFG_REG("IP1SR0", 0xe6050064, 32, 4, GROUP( 1754 IP1SR0_31_28 1755 IP1SR0_27_24 1756 IP1SR0_23_20 1757 IP1SR0_19_16 1758 IP1SR0_15_12 1759 IP1SR0_11_8 1760 IP1SR0_7_4 1761 IP1SR0_3_0)) 1762 }, 1763 { PINMUX_CFG_REG("IP2SR0", 0xe6050068, 32, 4, GROUP( 1764 IP2SR0_31_28 1765 IP2SR0_27_24 1766 IP2SR0_23_20 1767 IP2SR0_19_16 1768 IP2SR0_15_12 1769 IP2SR0_11_8 1770 IP2SR0_7_4 1771 IP2SR0_3_0)) 1772 }, 1773 { PINMUX_CFG_REG("IP0SR1", 0xe6050860, 32, 4, GROUP( 1774 IP0SR1_31_28 1775 IP0SR1_27_24 1776 IP0SR1_23_20 1777 IP0SR1_19_16 1778 IP0SR1_15_12 1779 IP0SR1_11_8 1780 IP0SR1_7_4 1781 IP0SR1_3_0)) 1782 }, 1783 #undef F_ 1784 #undef FM 1785 1786 #define F_(x, y) x, 1787 #define FM(x) FN_##x, 1788 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6050900, 32, 1789 GROUP(4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2), 1790 GROUP( 1791 /* RESERVED 31, 30, 29, 28 */ 1792 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1793 /* RESERVED 27, 26, 25, 24 */ 1794 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1795 /* RESERVED 23, 22, 21, 20 */ 1796 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1797 /* RESERVED 19, 18, 17, 16 */ 1798 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1799 /* RESERVED 15, 14, 13, 12 */ 1800 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1801 MOD_SEL1_11_10 1802 MOD_SEL1_9_8 1803 MOD_SEL1_7_6 1804 MOD_SEL1_5_4 1805 MOD_SEL1_3_2 1806 MOD_SEL1_1_0)) 1807 }, 1808 { /* sentinel */ }, 1809 }; 1810 1811 static const struct pinmux_drive_reg pinmux_drive_regs[] = { 1812 { PINMUX_DRIVE_REG("DRV0CTRL0", 0xe6050080) { 1813 { RCAR_GP_PIN(0, 7), 28, 3 }, /* TX0 */ 1814 { RCAR_GP_PIN(0, 6), 24, 3 }, /* RX0 */ 1815 { RCAR_GP_PIN(0, 5), 20, 3 }, /* HRTS0_N */ 1816 { RCAR_GP_PIN(0, 4), 16, 3 }, /* HCTS0_N */ 1817 { RCAR_GP_PIN(0, 3), 12, 3 }, /* HTX0 */ 1818 { RCAR_GP_PIN(0, 2), 8, 3 }, /* HRX0 */ 1819 { RCAR_GP_PIN(0, 1), 4, 3 }, /* HSCK0 */ 1820 { RCAR_GP_PIN(0, 0), 0, 3 }, /* SCIF_CLK */ 1821 } }, 1822 { PINMUX_DRIVE_REG("DRV1CTRL0", 0xe6050084) { 1823 { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF0_SS1 */ 1824 { RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF0_SCK */ 1825 { RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF0_TXD */ 1826 { RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF0_RXD */ 1827 { RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF0_SYNC */ 1828 { RCAR_GP_PIN(0, 10), 8, 3 }, /* CTS0_N */ 1829 { RCAR_GP_PIN(0, 9), 4, 3 }, /* RTS0_N */ 1830 { RCAR_GP_PIN(0, 8), 0, 3 }, /* SCK0 */ 1831 } }, 1832 { PINMUX_DRIVE_REG("DRV2CTRL0", 0xe6050088) { 1833 { RCAR_GP_PIN(0, 20), 16, 3 }, /* IRQ3 */ 1834 { RCAR_GP_PIN(0, 19), 12, 3 }, /* IRQ2 */ 1835 { RCAR_GP_PIN(0, 18), 8, 3 }, /* IRQ1 */ 1836 { RCAR_GP_PIN(0, 17), 4, 3 }, /* IRQ0 */ 1837 { RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF0_SS2 */ 1838 } }, 1839 { PINMUX_DRIVE_REG("DRV0CTRL1", 0xe6050880) { 1840 { RCAR_GP_PIN(1, 7), 28, 3 }, /* GP1_07 */ 1841 { RCAR_GP_PIN(1, 6), 24, 3 }, /* GP1_06 */ 1842 { RCAR_GP_PIN(1, 5), 20, 3 }, /* GP1_05 */ 1843 { RCAR_GP_PIN(1, 4), 16, 3 }, /* GP1_04 */ 1844 { RCAR_GP_PIN(1, 3), 12, 3 }, /* GP1_03 */ 1845 { RCAR_GP_PIN(1, 2), 8, 3 }, /* GP1_02 */ 1846 { RCAR_GP_PIN(1, 1), 4, 3 }, /* GP1_01 */ 1847 { RCAR_GP_PIN(1, 0), 0, 3 }, /* GP1_00 */ 1848 } }, 1849 { PINMUX_DRIVE_REG("DRV1CTRL1", 0xe6050884) { 1850 { RCAR_GP_PIN(1, 15), 28, 3 }, /* MMC_SD_D2 */ 1851 { RCAR_GP_PIN(1, 14), 24, 3 }, /* MMC_SD_D1 */ 1852 { RCAR_GP_PIN(1, 13), 20, 3 }, /* MMC_SD_D0 */ 1853 { RCAR_GP_PIN(1, 12), 16, 3 }, /* MMC_SD_CLK */ 1854 { RCAR_GP_PIN(1, 11), 12, 3 }, /* GP1_11 */ 1855 { RCAR_GP_PIN(1, 10), 8, 3 }, /* GP1_10 */ 1856 { RCAR_GP_PIN(1, 9), 4, 3 }, /* GP1_09 */ 1857 { RCAR_GP_PIN(1, 8), 0, 3 }, /* GP1_08 */ 1858 } }, 1859 { PINMUX_DRIVE_REG("DRV2CTRL1", 0xe6050888) { 1860 { RCAR_GP_PIN(1, 23), 28, 3 }, /* SD_CD */ 1861 { RCAR_GP_PIN(1, 22), 24, 3 }, /* MMC_SD_CMD */ 1862 { RCAR_GP_PIN(1, 21), 20, 3 }, /* MMC_D7 */ 1863 { RCAR_GP_PIN(1, 20), 16, 3 }, /* MMC_DS */ 1864 { RCAR_GP_PIN(1, 19), 12, 3 }, /* MMC_D6 */ 1865 { RCAR_GP_PIN(1, 18), 8, 3 }, /* MMC_D4 */ 1866 { RCAR_GP_PIN(1, 17), 4, 3 }, /* MMC_D5 */ 1867 { RCAR_GP_PIN(1, 16), 0, 3 }, /* MMC_SD_D3 */ 1868 } }, 1869 { PINMUX_DRIVE_REG("DRV3CTRL1", 0xe605088c) { 1870 { RCAR_GP_PIN(1, 24), 0, 3 }, /* SD_WP */ 1871 } }, 1872 { PINMUX_DRIVE_REG("DRV0CTRL2", 0xe6051080) { 1873 { RCAR_GP_PIN(2, 7), 28, 2 }, /* QSPI1_MOSI_IO0 */ 1874 { RCAR_GP_PIN(2, 6), 24, 2 }, /* QSPI1_IO2 */ 1875 { RCAR_GP_PIN(2, 5), 20, 2 }, /* QSPI1_MISO_IO1 */ 1876 { RCAR_GP_PIN(2, 4), 16, 2 }, /* QSPI1_IO3 */ 1877 { RCAR_GP_PIN(2, 3), 12, 2 }, /* QSPI1_SSL */ 1878 { RCAR_GP_PIN(2, 2), 8, 2 }, /* RPC_RESET_N */ 1879 { RCAR_GP_PIN(2, 1), 4, 2 }, /* RPC_WP_N */ 1880 { RCAR_GP_PIN(2, 0), 0, 2 }, /* RPC_INT_N */ 1881 } }, 1882 { PINMUX_DRIVE_REG("DRV1CTRL2", 0xe6051084) { 1883 { RCAR_GP_PIN(2, 15), 28, 3 }, /* PCIE0_CLKREQ_N */ 1884 { RCAR_GP_PIN(2, 14), 24, 2 }, /* QSPI0_IO3 */ 1885 { RCAR_GP_PIN(2, 13), 20, 2 }, /* QSPI0_SSL */ 1886 { RCAR_GP_PIN(2, 12), 16, 2 }, /* QSPI0_MISO_IO1 */ 1887 { RCAR_GP_PIN(2, 11), 12, 2 }, /* QSPI0_IO2 */ 1888 { RCAR_GP_PIN(2, 10), 8, 2 }, /* QSPI0_SPCLK */ 1889 { RCAR_GP_PIN(2, 9), 4, 2 }, /* QSPI0_MOSI_IO0 */ 1890 { RCAR_GP_PIN(2, 8), 0, 2 }, /* QSPI1_SPCLK */ 1891 } }, 1892 { PINMUX_DRIVE_REG("DRV2CTRL2", 0xe6051088) { 1893 { RCAR_GP_PIN(2, 16), 0, 3 }, /* PCIE1_CLKREQ_N */ 1894 } }, 1895 { PINMUX_DRIVE_REG("DRV0CTRL3", 0xe6051880) { 1896 { RCAR_GP_PIN(3, 7), 28, 3 }, /* TSN2_LINK_B */ 1897 { RCAR_GP_PIN(3, 6), 24, 3 }, /* TSN1_LINK_B */ 1898 { RCAR_GP_PIN(3, 5), 20, 3 }, /* TSN1_MDC_B */ 1899 { RCAR_GP_PIN(3, 4), 16, 3 }, /* TSN0_MDC_B */ 1900 { RCAR_GP_PIN(3, 3), 12, 3 }, /* TSN2_MDC_B */ 1901 { RCAR_GP_PIN(3, 2), 8, 3 }, /* TSN0_MDIO_B */ 1902 { RCAR_GP_PIN(3, 1), 4, 3 }, /* TSN2_MDIO_B */ 1903 { RCAR_GP_PIN(3, 0), 0, 3 }, /* TSN1_MDIO_B */ 1904 } }, 1905 { PINMUX_DRIVE_REG("DRV1CTRL3", 0xe6051884) { 1906 { RCAR_GP_PIN(3, 15), 28, 3 }, /* TSN1_AVTP_CAPTURE_B */ 1907 { RCAR_GP_PIN(3, 14), 24, 3 }, /* TSN1_AVTP_MATCH_B */ 1908 { RCAR_GP_PIN(3, 13), 20, 3 }, /* TSN1_AVTP_PPS */ 1909 { RCAR_GP_PIN(3, 12), 16, 3 }, /* TSN0_MAGIC_B */ 1910 { RCAR_GP_PIN(3, 11), 12, 3 }, /* TSN1_PHY_INT_B */ 1911 { RCAR_GP_PIN(3, 10), 8, 3 }, /* TSN0_PHY_INT_B */ 1912 { RCAR_GP_PIN(3, 9), 4, 3 }, /* TSN2_PHY_INT_B */ 1913 { RCAR_GP_PIN(3, 8), 0, 3 }, /* TSN0_LINK_B */ 1914 } }, 1915 { PINMUX_DRIVE_REG("DRV2CTRL3", 0xe6051888) { 1916 { RCAR_GP_PIN(3, 18), 8, 3 }, /* TSN0_AVTP_CAPTURE_B */ 1917 { RCAR_GP_PIN(3, 17), 4, 3 }, /* TSN0_AVTP_MATCH_B */ 1918 { RCAR_GP_PIN(3, 16), 0, 3 }, /* TSN0_AVTP_PPS */ 1919 } }, 1920 { /* sentinel */ }, 1921 }; 1922 1923 enum ioctrl_regs { 1924 POC0, 1925 POC1, 1926 POC2, 1927 POC3, 1928 TD0SEL1, 1929 }; 1930 1931 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { 1932 [POC0] = { 0xe60500a0, }, 1933 [POC1] = { 0xe60508a0, }, 1934 [POC2] = { 0xe60510a0, }, 1935 [POC3] = { 0xe60518a0, }, 1936 [TD0SEL1] = { 0xe6050920, }, 1937 { /* sentinel */ }, 1938 }; 1939 1940 static int r8a779f0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) 1941 { 1942 int bit = pin & 0x1f; 1943 1944 *pocctrl = pinmux_ioctrl_regs[POC0].reg; 1945 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 20)) 1946 return bit; 1947 1948 *pocctrl = pinmux_ioctrl_regs[POC1].reg; 1949 if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 24)) 1950 return bit; 1951 1952 *pocctrl = pinmux_ioctrl_regs[POC3].reg; 1953 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 18)) 1954 return bit; 1955 1956 return -EINVAL; 1957 } 1958 1959 static const struct pinmux_bias_reg pinmux_bias_regs[] = { 1960 { PINMUX_BIAS_REG("PUEN0", 0xe60500c0, "PUD0", 0xe60500e0) { 1961 [ 0] = RCAR_GP_PIN(0, 0), /* SCIF_CLK */ 1962 [ 1] = RCAR_GP_PIN(0, 1), /* HSCK0 */ 1963 [ 2] = RCAR_GP_PIN(0, 2), /* HRX0 */ 1964 [ 3] = RCAR_GP_PIN(0, 3), /* HTX0 */ 1965 [ 4] = RCAR_GP_PIN(0, 4), /* HCTS0_N */ 1966 [ 5] = RCAR_GP_PIN(0, 5), /* HRTS0_N */ 1967 [ 6] = RCAR_GP_PIN(0, 6), /* RX0 */ 1968 [ 7] = RCAR_GP_PIN(0, 7), /* TX0 */ 1969 [ 8] = RCAR_GP_PIN(0, 8), /* SCK0 */ 1970 [ 9] = RCAR_GP_PIN(0, 9), /* RTS0_N */ 1971 [10] = RCAR_GP_PIN(0, 10), /* CTS0_N */ 1972 [11] = RCAR_GP_PIN(0, 11), /* MSIOF0_SYNC */ 1973 [12] = RCAR_GP_PIN(0, 12), /* MSIOF0_RXD */ 1974 [13] = RCAR_GP_PIN(0, 13), /* MSIOF0_TXD */ 1975 [14] = RCAR_GP_PIN(0, 14), /* MSIOF0_SCK */ 1976 [15] = RCAR_GP_PIN(0, 15), /* MSIOF0_SS1 */ 1977 [16] = RCAR_GP_PIN(0, 16), /* MSIOF0_SS2 */ 1978 [17] = RCAR_GP_PIN(0, 17), /* IRQ0 */ 1979 [18] = RCAR_GP_PIN(0, 18), /* IRQ1 */ 1980 [19] = RCAR_GP_PIN(0, 19), /* IRQ2 */ 1981 [20] = RCAR_GP_PIN(0, 20), /* IRQ3 */ 1982 [21] = SH_PFC_PIN_NONE, 1983 [22] = SH_PFC_PIN_NONE, 1984 [23] = SH_PFC_PIN_NONE, 1985 [24] = SH_PFC_PIN_NONE, 1986 [25] = SH_PFC_PIN_NONE, 1987 [26] = SH_PFC_PIN_NONE, 1988 [27] = SH_PFC_PIN_NONE, 1989 [28] = SH_PFC_PIN_NONE, 1990 [29] = SH_PFC_PIN_NONE, 1991 [30] = SH_PFC_PIN_NONE, 1992 [31] = SH_PFC_PIN_NONE, 1993 } }, 1994 { PINMUX_BIAS_REG("PUEN1", 0xe60508c0, "PUD1", 0xe60508e0) { 1995 [ 0] = RCAR_GP_PIN(1, 0), /* GP1_00 */ 1996 [ 1] = RCAR_GP_PIN(1, 1), /* GP1_01 */ 1997 [ 2] = RCAR_GP_PIN(1, 2), /* GP1_02 */ 1998 [ 3] = RCAR_GP_PIN(1, 3), /* GP1_03 */ 1999 [ 4] = RCAR_GP_PIN(1, 4), /* GP1_04 */ 2000 [ 5] = RCAR_GP_PIN(1, 5), /* GP1_05 */ 2001 [ 6] = RCAR_GP_PIN(1, 6), /* GP1_06 */ 2002 [ 7] = RCAR_GP_PIN(1, 7), /* GP1_07 */ 2003 [ 8] = RCAR_GP_PIN(1, 8), /* GP1_08 */ 2004 [ 9] = RCAR_GP_PIN(1, 9), /* GP1_09 */ 2005 [10] = RCAR_GP_PIN(1, 10), /* GP1_10 */ 2006 [11] = RCAR_GP_PIN(1, 11), /* GP1_11 */ 2007 [12] = RCAR_GP_PIN(1, 12), /* MMC_SD_CLK */ 2008 [13] = RCAR_GP_PIN(1, 13), /* MMC_SD_D0 */ 2009 [14] = RCAR_GP_PIN(1, 14), /* MMC_SD_D1 */ 2010 [15] = RCAR_GP_PIN(1, 15), /* MMC_SD_D2 */ 2011 [16] = RCAR_GP_PIN(1, 16), /* MMC_SD_D3 */ 2012 [17] = RCAR_GP_PIN(1, 17), /* MMC_D5 */ 2013 [18] = RCAR_GP_PIN(1, 18), /* MMC_D4 */ 2014 [19] = RCAR_GP_PIN(1, 19), /* MMC_D6 */ 2015 [20] = RCAR_GP_PIN(1, 20), /* MMC_DS */ 2016 [21] = RCAR_GP_PIN(1, 21), /* MMC_D7 */ 2017 [22] = RCAR_GP_PIN(1, 22), /* MMC_SD_CMD */ 2018 [23] = RCAR_GP_PIN(1, 23), /* SD_CD */ 2019 [24] = RCAR_GP_PIN(1, 24), /* SD_WP */ 2020 [25] = SH_PFC_PIN_NONE, 2021 [26] = SH_PFC_PIN_NONE, 2022 [27] = SH_PFC_PIN_NONE, 2023 [28] = SH_PFC_PIN_NONE, 2024 [29] = SH_PFC_PIN_NONE, 2025 [30] = SH_PFC_PIN_NONE, 2026 [31] = SH_PFC_PIN_NONE, 2027 } }, 2028 { PINMUX_BIAS_REG("PUEN2", 0xe60510c0, "PUD2", 0xe60510e0) { 2029 [ 0] = RCAR_GP_PIN(2, 0), /* RPC_INT_N */ 2030 [ 1] = RCAR_GP_PIN(2, 1), /* RPC_WP_N */ 2031 [ 2] = RCAR_GP_PIN(2, 2), /* RPC_RESET_N */ 2032 [ 3] = RCAR_GP_PIN(2, 3), /* QSPI1_SSL */ 2033 [ 4] = RCAR_GP_PIN(2, 4), /* QSPI1_IO3 */ 2034 [ 5] = RCAR_GP_PIN(2, 5), /* QSPI1_MISO_IO1 */ 2035 [ 6] = RCAR_GP_PIN(2, 6), /* QSPI1_IO2 */ 2036 [ 7] = RCAR_GP_PIN(2, 7), /* QSPI1_MOSI_IO0 */ 2037 [ 8] = RCAR_GP_PIN(2, 8), /* QSPI1_SPCLK */ 2038 [ 9] = RCAR_GP_PIN(2, 9), /* QSPI0_MOSI_IO0 */ 2039 [10] = RCAR_GP_PIN(2, 10), /* QSPI0_SPCLK */ 2040 [11] = RCAR_GP_PIN(2, 11), /* QSPI0_IO2 */ 2041 [12] = RCAR_GP_PIN(2, 12), /* QSPI0_MISO_IO1 */ 2042 [13] = RCAR_GP_PIN(2, 13), /* QSPI0_SSL */ 2043 [14] = RCAR_GP_PIN(2, 14), /* QSPI0_IO3 */ 2044 [15] = RCAR_GP_PIN(2, 15), /* PCIE0_CLKREQ_N */ 2045 [16] = RCAR_GP_PIN(2, 16), /* PCIE1_CLKREQ_N */ 2046 [17] = SH_PFC_PIN_NONE, 2047 [18] = SH_PFC_PIN_NONE, 2048 [19] = SH_PFC_PIN_NONE, 2049 [20] = SH_PFC_PIN_NONE, 2050 [21] = SH_PFC_PIN_NONE, 2051 [22] = SH_PFC_PIN_NONE, 2052 [23] = SH_PFC_PIN_NONE, 2053 [24] = SH_PFC_PIN_NONE, 2054 [25] = SH_PFC_PIN_NONE, 2055 [26] = SH_PFC_PIN_NONE, 2056 [27] = SH_PFC_PIN_NONE, 2057 [28] = SH_PFC_PIN_NONE, 2058 [29] = SH_PFC_PIN_NONE, 2059 [30] = SH_PFC_PIN_NONE, 2060 [31] = SH_PFC_PIN_NONE, 2061 } }, 2062 { PINMUX_BIAS_REG("PUEN3", 0xe60518c0, "PUD3", 0xe60518e0) { 2063 [ 0] = RCAR_GP_PIN(3, 0), /* TSN1_MDIO_B */ 2064 [ 1] = RCAR_GP_PIN(3, 1), /* TSN2_MDIO_B */ 2065 [ 2] = RCAR_GP_PIN(3, 2), /* TSN0_MDIO_B */ 2066 [ 3] = RCAR_GP_PIN(3, 3), /* TSN2_MDC_B */ 2067 [ 4] = RCAR_GP_PIN(3, 4), /* TSN0_MDC_B */ 2068 [ 5] = RCAR_GP_PIN(3, 5), /* TSN1_MDC_B */ 2069 [ 6] = RCAR_GP_PIN(3, 6), /* TSN1_LINK_B */ 2070 [ 7] = RCAR_GP_PIN(3, 7), /* TSN2_LINK_B */ 2071 [ 8] = RCAR_GP_PIN(3, 8), /* TSN0_LINK_B */ 2072 [ 9] = RCAR_GP_PIN(3, 9), /* TSN2_PHY_INT_B */ 2073 [10] = RCAR_GP_PIN(3, 10), /* TSN0_PHY_INT_B */ 2074 [11] = RCAR_GP_PIN(3, 11), /* TSN1_PHY_INT_B */ 2075 [12] = RCAR_GP_PIN(3, 12), /* TSN0_MAGIC_B */ 2076 [13] = RCAR_GP_PIN(3, 13), /* TSN1_AVTP_PPS */ 2077 [14] = RCAR_GP_PIN(3, 14), /* TSN1_AVTP_MATCH_B */ 2078 [15] = RCAR_GP_PIN(3, 15), /* TSN1_AVTP_CAPTURE_B */ 2079 [16] = RCAR_GP_PIN(3, 16), /* TSN0_AVTP_PPS */ 2080 [17] = RCAR_GP_PIN(3, 17), /* TSN0_AVTP_MATCH_B */ 2081 [18] = RCAR_GP_PIN(3, 18), /* TSN0_AVTP_CAPTURE_B */ 2082 [19] = SH_PFC_PIN_NONE, 2083 [20] = SH_PFC_PIN_NONE, 2084 [21] = SH_PFC_PIN_NONE, 2085 [22] = SH_PFC_PIN_NONE, 2086 [23] = SH_PFC_PIN_NONE, 2087 [24] = SH_PFC_PIN_NONE, 2088 [25] = SH_PFC_PIN_NONE, 2089 [26] = SH_PFC_PIN_NONE, 2090 [27] = SH_PFC_PIN_NONE, 2091 [28] = SH_PFC_PIN_NONE, 2092 [29] = SH_PFC_PIN_NONE, 2093 [30] = SH_PFC_PIN_NONE, 2094 [31] = SH_PFC_PIN_NONE, 2095 } }, 2096 { /* sentinel */ }, 2097 }; 2098 2099 static const struct sh_pfc_soc_operations r8a779f0_pfc_ops = { 2100 .pin_to_pocctrl = r8a779f0_pin_to_pocctrl, 2101 .get_bias = rcar_pinmux_get_bias, 2102 .set_bias = rcar_pinmux_set_bias, 2103 }; 2104 2105 const struct sh_pfc_soc_info r8a779f0_pinmux_info = { 2106 .name = "r8a779f0_pfc", 2107 .ops = &r8a779f0_pfc_ops, 2108 .unlock_reg = 0x1ff, /* PMMRn mask */ 2109 2110 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 2111 2112 .pins = pinmux_pins, 2113 .nr_pins = ARRAY_SIZE(pinmux_pins), 2114 .groups = pinmux_groups, 2115 .nr_groups = ARRAY_SIZE(pinmux_groups), 2116 .functions = pinmux_functions, 2117 .nr_functions = ARRAY_SIZE(pinmux_functions), 2118 2119 .cfg_regs = pinmux_config_regs, 2120 .drive_regs = pinmux_drive_regs, 2121 .bias_regs = pinmux_bias_regs, 2122 .ioctrl_regs = pinmux_ioctrl_regs, 2123 2124 .pinmux_data = pinmux_data, 2125 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 2126 }; 2127