1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/G2L Pin Control and GPIO driver core 4 * 5 * Copyright (C) 2021 Renesas Electronics Corporation. 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/mutex.h> 15 #include <linux/of.h> 16 #include <linux/of_irq.h> 17 #include <linux/platform_device.h> 18 #include <linux/seq_file.h> 19 #include <linux/spinlock.h> 20 21 #include <linux/pinctrl/consumer.h> 22 #include <linux/pinctrl/pinconf-generic.h> 23 #include <linux/pinctrl/pinconf.h> 24 #include <linux/pinctrl/pinctrl.h> 25 #include <linux/pinctrl/pinmux.h> 26 27 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 28 29 #include "../core.h" 30 #include "../pinconf.h" 31 #include "../pinmux.h" 32 33 #define DRV_NAME "pinctrl-rzg2l" 34 35 /* 36 * Use 16 lower bits [15:0] for pin identifier 37 * Use 16 higher bits [31:16] for pin mux function 38 */ 39 #define MUX_PIN_ID_MASK GENMASK(15, 0) 40 #define MUX_FUNC_MASK GENMASK(31, 16) 41 #define MUX_FUNC_OFFS 16 42 #define MUX_FUNC(pinconf) (((pinconf) & MUX_FUNC_MASK) >> MUX_FUNC_OFFS) 43 44 /* PIN capabilities */ 45 #define PIN_CFG_IOLH_A BIT(0) 46 #define PIN_CFG_IOLH_B BIT(1) 47 #define PIN_CFG_SR BIT(2) 48 #define PIN_CFG_IEN BIT(3) 49 #define PIN_CFG_PUPD BIT(4) 50 #define PIN_CFG_IO_VMC_SD0 BIT(5) 51 #define PIN_CFG_IO_VMC_SD1 BIT(6) 52 #define PIN_CFG_IO_VMC_QSPI BIT(7) 53 #define PIN_CFG_IO_VMC_ETH0 BIT(8) 54 #define PIN_CFG_IO_VMC_ETH1 BIT(9) 55 #define PIN_CFG_FILONOFF BIT(10) 56 #define PIN_CFG_FILNUM BIT(11) 57 #define PIN_CFG_FILCLKSEL BIT(12) 58 #define PIN_CFG_IOLH_C BIT(13) 59 #define PIN_CFG_SOFT_PS BIT(14) 60 61 #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ 62 (PIN_CFG_IOLH_##group | \ 63 PIN_CFG_PUPD | \ 64 PIN_CFG_FILONOFF | \ 65 PIN_CFG_FILNUM | \ 66 PIN_CFG_FILCLKSEL) 67 68 #define RZG2L_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \ 69 PIN_CFG_SR) 70 71 #define RZG3S_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \ 72 PIN_CFG_SOFT_PS) 73 74 #define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \ 75 PIN_CFG_FILONOFF | \ 76 PIN_CFG_FILNUM | \ 77 PIN_CFG_FILCLKSEL) 78 79 /* 80 * n indicates number of pins in the port, a is the register index 81 * and f is pin configuration capabilities supported. 82 */ 83 #define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f)) 84 #define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28) 85 86 /* 87 * BIT(31) indicates dedicated pin, p is the register index while 88 * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits 89 * (b * 8) and f is the pin configuration capabilities supported. 90 */ 91 #define RZG2L_SINGLE_PIN BIT(31) 92 #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ 93 ((p) << 24) | ((b) << 20) | (f)) 94 #define RZG2L_SINGLE_PIN_GET_BIT(x) (((x) & GENMASK(22, 20)) >> 20) 95 96 #define RZG2L_PIN_CFG_TO_CAPS(cfg) ((cfg) & GENMASK(19, 0)) 97 #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ 98 (((cfg) & GENMASK(30, 24)) >> 24) : \ 99 (((cfg) & GENMASK(26, 20)) >> 20)) 100 101 #define P(off) (0x0000 + (off)) 102 #define PM(off) (0x0100 + (off) * 2) 103 #define PMC(off) (0x0200 + (off)) 104 #define PFC(off) (0x0400 + (off) * 4) 105 #define PIN(off) (0x0800 + (off)) 106 #define IOLH(off) (0x1000 + (off) * 8) 107 #define IEN(off) (0x1800 + (off) * 8) 108 #define ISEL(off) (0x2C00 + (off) * 8) 109 #define SD_CH(off, ch) ((off) + (ch) * 4) 110 #define QSPI (0x3008) 111 112 #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ 113 #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ 114 115 #define PWPR_B0WI BIT(7) /* Bit Write Disable */ 116 #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ 117 118 #define PM_MASK 0x03 119 #define PVDD_MASK 0x01 120 #define PFC_MASK 0x07 121 #define IEN_MASK 0x01 122 #define IOLH_MASK 0x03 123 124 #define PM_INPUT 0x1 125 #define PM_OUTPUT 0x2 126 127 #define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT) 128 #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT) 129 130 #define RZG2L_TINT_MAX_INTERRUPT 32 131 #define RZG2L_TINT_IRQ_START_INDEX 9 132 #define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i)) 133 134 /** 135 * struct rzg2l_register_offsets - specific register offsets 136 * @pwpr: PWPR register offset 137 * @sd_ch: SD_CH register offset 138 */ 139 struct rzg2l_register_offsets { 140 u16 pwpr; 141 u16 sd_ch; 142 }; 143 144 /** 145 * enum rzg2l_iolh_index - starting indices in IOLH specific arrays 146 * @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source 147 * @RZG2L_IOLH_IDX_2V5: starting index for 2V5 power source 148 * @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source 149 * @RZG2L_IOLH_IDX_MAX: maximum index 150 */ 151 enum rzg2l_iolh_index { 152 RZG2L_IOLH_IDX_1V8 = 0, 153 RZG2L_IOLH_IDX_2V5 = 4, 154 RZG2L_IOLH_IDX_3V3 = 8, 155 RZG2L_IOLH_IDX_MAX = 12, 156 }; 157 158 /* Maximum number of driver strength entries per power source. */ 159 #define RZG2L_IOLH_MAX_DS_ENTRIES (4) 160 161 /** 162 * struct rzg2l_hwcfg - hardware configuration data structure 163 * @regs: hardware specific register offsets 164 * @iolh_groupa_ua: IOLH group A uA specific values 165 * @iolh_groupb_ua: IOLH group B uA specific values 166 * @iolh_groupc_ua: IOLH group C uA specific values 167 * @iolh_groupb_oi: IOLH group B output impedance specific values 168 * @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported) 169 * @func_base: base number for port function (see register PFC) 170 */ 171 struct rzg2l_hwcfg { 172 const struct rzg2l_register_offsets regs; 173 u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX]; 174 u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX]; 175 u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX]; 176 u16 iolh_groupb_oi[4]; 177 bool drive_strength_ua; 178 u8 func_base; 179 }; 180 181 struct rzg2l_dedicated_configs { 182 const char *name; 183 u32 config; 184 }; 185 186 struct rzg2l_pinctrl_data { 187 const char * const *port_pins; 188 const u32 *port_pin_configs; 189 unsigned int n_ports; 190 const struct rzg2l_dedicated_configs *dedicated_pins; 191 unsigned int n_port_pins; 192 unsigned int n_dedicated_pins; 193 const struct rzg2l_hwcfg *hwcfg; 194 }; 195 196 /** 197 * struct rzg2l_pinctrl_pin_settings - pin data 198 * @power_source: power source 199 * @drive_strength_ua: drive strength (in micro amps) 200 */ 201 struct rzg2l_pinctrl_pin_settings { 202 u16 power_source; 203 u16 drive_strength_ua; 204 }; 205 206 struct rzg2l_pinctrl { 207 struct pinctrl_dev *pctl; 208 struct pinctrl_desc desc; 209 struct pinctrl_pin_desc *pins; 210 211 const struct rzg2l_pinctrl_data *data; 212 void __iomem *base; 213 struct device *dev; 214 215 struct gpio_chip gpio_chip; 216 struct pinctrl_gpio_range gpio_range; 217 DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT); 218 spinlock_t bitmap_lock; /* protect tint_slot bitmap */ 219 unsigned int hwirq[RZG2L_TINT_MAX_INTERRUPT]; 220 221 spinlock_t lock; /* lock read/write registers */ 222 struct mutex mutex; /* serialize adding groups and functions */ 223 224 struct rzg2l_pinctrl_pin_settings *settings; 225 }; 226 227 static const u16 available_ps[] = { 1800, 2500, 3300 }; 228 229 static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, 230 u8 pin, u8 off, u8 func) 231 { 232 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; 233 unsigned long flags; 234 u32 reg; 235 236 spin_lock_irqsave(&pctrl->lock, flags); 237 238 /* Set pin to 'Non-use (Hi-Z input protection)' */ 239 reg = readw(pctrl->base + PM(off)); 240 reg &= ~(PM_MASK << (pin * 2)); 241 writew(reg, pctrl->base + PM(off)); 242 243 /* Temporarily switch to GPIO mode with PMC register */ 244 reg = readb(pctrl->base + PMC(off)); 245 writeb(reg & ~BIT(pin), pctrl->base + PMC(off)); 246 247 /* Set the PWPR register to allow PFC register to write */ 248 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ 249 writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */ 250 251 /* Select Pin function mode with PFC register */ 252 reg = readl(pctrl->base + PFC(off)); 253 reg &= ~(PFC_MASK << (pin * 4)); 254 writel(reg | (func << (pin * 4)), pctrl->base + PFC(off)); 255 256 /* Set the PWPR register to be write-protected */ 257 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ 258 writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */ 259 260 /* Switch to Peripheral pin function with PMC register */ 261 reg = readb(pctrl->base + PMC(off)); 262 writeb(reg | BIT(pin), pctrl->base + PMC(off)); 263 264 spin_unlock_irqrestore(&pctrl->lock, flags); 265 }; 266 267 static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, 268 unsigned int func_selector, 269 unsigned int group_selector) 270 { 271 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 272 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 273 struct function_desc *func; 274 unsigned int i, *psel_val; 275 struct group_desc *group; 276 int *pins; 277 278 func = pinmux_generic_get_function(pctldev, func_selector); 279 if (!func) 280 return -EINVAL; 281 group = pinctrl_generic_get_group(pctldev, group_selector); 282 if (!group) 283 return -EINVAL; 284 285 psel_val = func->data; 286 pins = group->pins; 287 288 for (i = 0; i < group->num_pins; i++) { 289 unsigned int *pin_data = pctrl->desc.pins[pins[i]].drv_data; 290 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 291 u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]); 292 293 dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", 294 RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base); 295 296 rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); 297 } 298 299 return 0; 300 }; 301 302 static int rzg2l_map_add_config(struct pinctrl_map *map, 303 const char *group_or_pin, 304 enum pinctrl_map_type type, 305 unsigned long *configs, 306 unsigned int num_configs) 307 { 308 unsigned long *cfgs; 309 310 cfgs = kmemdup(configs, num_configs * sizeof(*cfgs), 311 GFP_KERNEL); 312 if (!cfgs) 313 return -ENOMEM; 314 315 map->type = type; 316 map->data.configs.group_or_pin = group_or_pin; 317 map->data.configs.configs = cfgs; 318 map->data.configs.num_configs = num_configs; 319 320 return 0; 321 } 322 323 static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, 324 struct device_node *np, 325 struct device_node *parent, 326 struct pinctrl_map **map, 327 unsigned int *num_maps, 328 unsigned int *index) 329 { 330 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 331 struct pinctrl_map *maps = *map; 332 unsigned int nmaps = *num_maps; 333 unsigned long *configs = NULL; 334 unsigned int *pins, *psel_val; 335 unsigned int num_pinmux = 0; 336 unsigned int idx = *index; 337 unsigned int num_pins, i; 338 unsigned int num_configs; 339 struct property *pinmux; 340 struct property *prop; 341 int ret, gsel, fsel; 342 const char **pin_fn; 343 const char *name; 344 const char *pin; 345 346 pinmux = of_find_property(np, "pinmux", NULL); 347 if (pinmux) 348 num_pinmux = pinmux->length / sizeof(u32); 349 350 ret = of_property_count_strings(np, "pins"); 351 if (ret == -EINVAL) { 352 num_pins = 0; 353 } else if (ret < 0) { 354 dev_err(pctrl->dev, "Invalid pins list in DT\n"); 355 return ret; 356 } else { 357 num_pins = ret; 358 } 359 360 if (!num_pinmux && !num_pins) 361 return 0; 362 363 if (num_pinmux && num_pins) { 364 dev_err(pctrl->dev, 365 "DT node must contain either a pinmux or pins and not both\n"); 366 return -EINVAL; 367 } 368 369 ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs); 370 if (ret < 0) 371 return ret; 372 373 if (num_pins && !num_configs) { 374 dev_err(pctrl->dev, "DT node must contain a config\n"); 375 ret = -ENODEV; 376 goto done; 377 } 378 379 if (num_pinmux) 380 nmaps += 1; 381 382 if (num_pins) 383 nmaps += num_pins; 384 385 maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL); 386 if (!maps) { 387 ret = -ENOMEM; 388 goto done; 389 } 390 391 *map = maps; 392 *num_maps = nmaps; 393 if (num_pins) { 394 of_property_for_each_string(np, "pins", prop, pin) { 395 ret = rzg2l_map_add_config(&maps[idx], pin, 396 PIN_MAP_TYPE_CONFIGS_PIN, 397 configs, num_configs); 398 if (ret < 0) 399 goto done; 400 401 idx++; 402 } 403 ret = 0; 404 goto done; 405 } 406 407 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); 408 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), 409 GFP_KERNEL); 410 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); 411 if (!pins || !psel_val || !pin_fn) { 412 ret = -ENOMEM; 413 goto done; 414 } 415 416 /* Collect pin locations and mux settings from DT properties */ 417 for (i = 0; i < num_pinmux; ++i) { 418 u32 value; 419 420 ret = of_property_read_u32_index(np, "pinmux", i, &value); 421 if (ret) 422 goto done; 423 pins[i] = value & MUX_PIN_ID_MASK; 424 psel_val[i] = MUX_FUNC(value); 425 } 426 427 if (parent) { 428 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn", 429 parent, np); 430 if (!name) { 431 ret = -ENOMEM; 432 goto done; 433 } 434 } else { 435 name = np->name; 436 } 437 438 mutex_lock(&pctrl->mutex); 439 440 /* Register a single pin group listing all the pins we read from DT */ 441 gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL); 442 if (gsel < 0) { 443 ret = gsel; 444 goto unlock; 445 } 446 447 /* 448 * Register a single group function where the 'data' is an array PSEL 449 * register values read from DT. 450 */ 451 pin_fn[0] = name; 452 fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val); 453 if (fsel < 0) { 454 ret = fsel; 455 goto remove_group; 456 } 457 458 mutex_unlock(&pctrl->mutex); 459 460 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; 461 maps[idx].data.mux.group = name; 462 maps[idx].data.mux.function = name; 463 idx++; 464 465 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); 466 ret = 0; 467 goto done; 468 469 remove_group: 470 pinctrl_generic_remove_group(pctldev, gsel); 471 unlock: 472 mutex_unlock(&pctrl->mutex); 473 done: 474 *index = idx; 475 kfree(configs); 476 return ret; 477 } 478 479 static void rzg2l_dt_free_map(struct pinctrl_dev *pctldev, 480 struct pinctrl_map *map, 481 unsigned int num_maps) 482 { 483 unsigned int i; 484 485 if (!map) 486 return; 487 488 for (i = 0; i < num_maps; ++i) { 489 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || 490 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 491 kfree(map[i].data.configs.configs); 492 } 493 kfree(map); 494 } 495 496 static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, 497 struct device_node *np, 498 struct pinctrl_map **map, 499 unsigned int *num_maps) 500 { 501 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 502 struct device_node *child; 503 unsigned int index; 504 int ret; 505 506 *map = NULL; 507 *num_maps = 0; 508 index = 0; 509 510 for_each_child_of_node(np, child) { 511 ret = rzg2l_dt_subnode_to_map(pctldev, child, np, map, 512 num_maps, &index); 513 if (ret < 0) { 514 of_node_put(child); 515 goto done; 516 } 517 } 518 519 if (*num_maps == 0) { 520 ret = rzg2l_dt_subnode_to_map(pctldev, np, NULL, map, 521 num_maps, &index); 522 if (ret < 0) 523 goto done; 524 } 525 526 if (*num_maps) 527 return 0; 528 529 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); 530 ret = -EINVAL; 531 532 done: 533 rzg2l_dt_free_map(pctldev, *map, *num_maps); 534 535 return ret; 536 } 537 538 static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, 539 u32 cfg, u32 port, u8 bit) 540 { 541 u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg); 542 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); 543 u32 data; 544 545 if (bit >= pincount || port >= pctrl->data->n_port_pins) 546 return -EINVAL; 547 548 data = pctrl->data->port_pin_configs[port]; 549 if (off != RZG2L_PIN_CFG_TO_PORT_OFFSET(data)) 550 return -EINVAL; 551 552 return 0; 553 } 554 555 static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, 556 u8 bit, u32 mask) 557 { 558 void __iomem *addr = pctrl->base + offset; 559 560 /* handle _L/_H for 32-bit register read/write */ 561 if (bit >= 4) { 562 bit -= 4; 563 addr += 4; 564 } 565 566 return (readl(addr) >> (bit * 8)) & mask; 567 } 568 569 static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, 570 u8 bit, u32 mask, u32 val) 571 { 572 void __iomem *addr = pctrl->base + offset; 573 unsigned long flags; 574 u32 reg; 575 576 /* handle _L/_H for 32-bit register read/write */ 577 if (bit >= 4) { 578 bit -= 4; 579 addr += 4; 580 } 581 582 spin_lock_irqsave(&pctrl->lock, flags); 583 reg = readl(addr) & ~(mask << (bit * 8)); 584 writel(reg | (val << (bit * 8)), addr); 585 spin_unlock_irqrestore(&pctrl->lock, flags); 586 } 587 588 static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 caps) 589 { 590 if (caps & PIN_CFG_IO_VMC_SD0) 591 return SD_CH(regs->sd_ch, 0); 592 if (caps & PIN_CFG_IO_VMC_SD1) 593 return SD_CH(regs->sd_ch, 1); 594 if (caps & PIN_CFG_IO_VMC_QSPI) 595 return QSPI; 596 597 return -EINVAL; 598 } 599 600 static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps) 601 { 602 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 603 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 604 int pwr_reg; 605 606 if (caps & PIN_CFG_SOFT_PS) 607 return pctrl->settings[pin].power_source; 608 609 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); 610 if (pwr_reg < 0) 611 return pwr_reg; 612 613 return (readl(pctrl->base + pwr_reg) & PVDD_MASK) ? 1800 : 3300; 614 } 615 616 static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps) 617 { 618 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 619 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 620 int pwr_reg; 621 622 if (caps & PIN_CFG_SOFT_PS) { 623 pctrl->settings[pin].power_source = ps; 624 return 0; 625 } 626 627 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); 628 if (pwr_reg < 0) 629 return pwr_reg; 630 631 writel((ps == 1800) ? PVDD_1800 : PVDD_3300, pctrl->base + pwr_reg); 632 pctrl->settings[pin].power_source = ps; 633 634 return 0; 635 } 636 637 static bool rzg2l_ps_is_supported(u16 ps) 638 { 639 unsigned int i; 640 641 for (i = 0; i < ARRAY_SIZE(available_ps); i++) { 642 if (available_ps[i] == ps) 643 return true; 644 } 645 646 return false; 647 } 648 649 static enum rzg2l_iolh_index rzg2l_ps_to_iolh_idx(u16 ps) 650 { 651 unsigned int i; 652 653 for (i = 0; i < ARRAY_SIZE(available_ps); i++) { 654 if (available_ps[i] == ps) 655 break; 656 } 657 658 /* 659 * We multiply with RZG2L_IOLH_MAX_DS_ENTRIES as we have 660 * RZG2L_IOLH_MAX_DS_ENTRIES DS values per power source 661 */ 662 return i * RZG2L_IOLH_MAX_DS_ENTRIES; 663 } 664 665 static u16 rzg2l_iolh_val_to_ua(const struct rzg2l_hwcfg *hwcfg, u32 caps, u8 val) 666 { 667 if (caps & PIN_CFG_IOLH_A) 668 return hwcfg->iolh_groupa_ua[val]; 669 670 if (caps & PIN_CFG_IOLH_B) 671 return hwcfg->iolh_groupb_ua[val]; 672 673 if (caps & PIN_CFG_IOLH_C) 674 return hwcfg->iolh_groupc_ua[val]; 675 676 /* Should not happen. */ 677 return 0; 678 } 679 680 static int rzg2l_iolh_ua_to_val(const struct rzg2l_hwcfg *hwcfg, u32 caps, 681 enum rzg2l_iolh_index ps_index, u16 ua) 682 { 683 const u16 *array = NULL; 684 unsigned int i; 685 686 if (caps & PIN_CFG_IOLH_A) 687 array = &hwcfg->iolh_groupa_ua[ps_index]; 688 689 if (caps & PIN_CFG_IOLH_B) 690 array = &hwcfg->iolh_groupb_ua[ps_index]; 691 692 if (caps & PIN_CFG_IOLH_C) 693 array = &hwcfg->iolh_groupc_ua[ps_index]; 694 695 if (!array) 696 return -EINVAL; 697 698 for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) { 699 if (array[i] == ua) 700 return i; 701 } 702 703 return -EINVAL; 704 } 705 706 static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps, 707 enum rzg2l_iolh_index iolh_idx, 708 u16 ds) 709 { 710 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 711 const u16 *array = NULL; 712 unsigned int i; 713 714 if (caps & PIN_CFG_IOLH_A) 715 array = hwcfg->iolh_groupa_ua; 716 717 if (caps & PIN_CFG_IOLH_B) 718 array = hwcfg->iolh_groupb_ua; 719 720 if (caps & PIN_CFG_IOLH_C) 721 array = hwcfg->iolh_groupc_ua; 722 723 /* Should not happen. */ 724 if (!array) 725 return false; 726 727 if (!array[iolh_idx]) 728 return false; 729 730 for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) { 731 if (array[iolh_idx + i] == ds) 732 return true; 733 } 734 735 return false; 736 } 737 738 static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, 739 unsigned int _pin, 740 unsigned long *config) 741 { 742 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 743 enum pin_config_param param = pinconf_to_config_param(*config); 744 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 745 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 746 unsigned int *pin_data = pin->drv_data; 747 unsigned int arg = 0; 748 u32 off, cfg; 749 int ret; 750 u8 bit; 751 752 if (!pin_data) 753 return -EINVAL; 754 755 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 756 cfg = RZG2L_PIN_CFG_TO_CAPS(*pin_data); 757 if (*pin_data & RZG2L_SINGLE_PIN) { 758 bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); 759 } else { 760 bit = RZG2L_PIN_ID_TO_PIN(_pin); 761 762 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) 763 return -EINVAL; 764 } 765 766 switch (param) { 767 case PIN_CONFIG_INPUT_ENABLE: 768 if (!(cfg & PIN_CFG_IEN)) 769 return -EINVAL; 770 arg = rzg2l_read_pin_config(pctrl, IEN(off), bit, IEN_MASK); 771 if (!arg) 772 return -EINVAL; 773 break; 774 775 case PIN_CONFIG_POWER_SOURCE: 776 ret = rzg2l_get_power_source(pctrl, _pin, cfg); 777 if (ret < 0) 778 return ret; 779 arg = ret; 780 break; 781 782 case PIN_CONFIG_DRIVE_STRENGTH: { 783 unsigned int index; 784 785 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) 786 return -EINVAL; 787 788 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); 789 /* 790 * Drive strenght mA is supported only by group A and only 791 * for 3V3 port source. 792 */ 793 arg = hwcfg->iolh_groupa_ua[index + RZG2L_IOLH_IDX_3V3] / 1000; 794 break; 795 } 796 797 case PIN_CONFIG_DRIVE_STRENGTH_UA: { 798 enum rzg2l_iolh_index iolh_idx; 799 u8 val; 800 801 if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) || 802 !hwcfg->drive_strength_ua) 803 return -EINVAL; 804 805 ret = rzg2l_get_power_source(pctrl, _pin, cfg); 806 if (ret < 0) 807 return ret; 808 iolh_idx = rzg2l_ps_to_iolh_idx(ret); 809 val = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); 810 arg = rzg2l_iolh_val_to_ua(hwcfg, cfg, iolh_idx + val); 811 break; 812 } 813 814 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { 815 unsigned int index; 816 817 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) 818 return -EINVAL; 819 820 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); 821 arg = hwcfg->iolh_groupb_oi[index]; 822 break; 823 } 824 825 default: 826 return -ENOTSUPP; 827 } 828 829 *config = pinconf_to_config_packed(param, arg); 830 831 return 0; 832 }; 833 834 static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, 835 unsigned int _pin, 836 unsigned long *_configs, 837 unsigned int num_configs) 838 { 839 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 840 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 841 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 842 struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin]; 843 unsigned int *pin_data = pin->drv_data; 844 enum pin_config_param param; 845 unsigned int i; 846 u32 cfg, off; 847 int ret; 848 u8 bit; 849 850 if (!pin_data) 851 return -EINVAL; 852 853 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 854 cfg = RZG2L_PIN_CFG_TO_CAPS(*pin_data); 855 if (*pin_data & RZG2L_SINGLE_PIN) { 856 bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); 857 } else { 858 bit = RZG2L_PIN_ID_TO_PIN(_pin); 859 860 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) 861 return -EINVAL; 862 } 863 864 for (i = 0; i < num_configs; i++) { 865 param = pinconf_to_config_param(_configs[i]); 866 switch (param) { 867 case PIN_CONFIG_INPUT_ENABLE: { 868 unsigned int arg = 869 pinconf_to_config_argument(_configs[i]); 870 871 if (!(cfg & PIN_CFG_IEN)) 872 return -EINVAL; 873 874 rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, !!arg); 875 break; 876 } 877 878 case PIN_CONFIG_POWER_SOURCE: 879 settings.power_source = pinconf_to_config_argument(_configs[i]); 880 break; 881 882 case PIN_CONFIG_DRIVE_STRENGTH: { 883 unsigned int arg = pinconf_to_config_argument(_configs[i]); 884 unsigned int index; 885 886 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) 887 return -EINVAL; 888 889 for (index = RZG2L_IOLH_IDX_3V3; 890 index < RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES; index++) { 891 if (arg == (hwcfg->iolh_groupa_ua[index] / 1000)) 892 break; 893 } 894 if (index == (RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES)) 895 return -EINVAL; 896 897 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); 898 break; 899 } 900 901 case PIN_CONFIG_DRIVE_STRENGTH_UA: 902 if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) || 903 !hwcfg->drive_strength_ua) 904 return -EINVAL; 905 906 settings.drive_strength_ua = pinconf_to_config_argument(_configs[i]); 907 break; 908 909 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { 910 unsigned int arg = pinconf_to_config_argument(_configs[i]); 911 unsigned int index; 912 913 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) 914 return -EINVAL; 915 916 for (index = 0; index < ARRAY_SIZE(hwcfg->iolh_groupb_oi); index++) { 917 if (arg == hwcfg->iolh_groupb_oi[index]) 918 break; 919 } 920 if (index == ARRAY_SIZE(hwcfg->iolh_groupb_oi)) 921 return -EINVAL; 922 923 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); 924 break; 925 } 926 927 default: 928 return -EOPNOTSUPP; 929 } 930 } 931 932 /* Apply power source. */ 933 if (settings.power_source != pctrl->settings[_pin].power_source) { 934 ret = rzg2l_ps_is_supported(settings.power_source); 935 if (!ret) 936 return -EINVAL; 937 938 /* Apply power source. */ 939 ret = rzg2l_set_power_source(pctrl, _pin, cfg, settings.power_source); 940 if (ret) 941 return ret; 942 } 943 944 /* Apply drive strength. */ 945 if (settings.drive_strength_ua != pctrl->settings[_pin].drive_strength_ua) { 946 enum rzg2l_iolh_index iolh_idx; 947 int val; 948 949 iolh_idx = rzg2l_ps_to_iolh_idx(settings.power_source); 950 ret = rzg2l_ds_is_supported(pctrl, cfg, iolh_idx, 951 settings.drive_strength_ua); 952 if (!ret) 953 return -EINVAL; 954 955 /* Get register value for this PS/DS tuple. */ 956 val = rzg2l_iolh_ua_to_val(hwcfg, cfg, iolh_idx, settings.drive_strength_ua); 957 if (val < 0) 958 return val; 959 960 /* Apply drive strength. */ 961 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, val); 962 pctrl->settings[_pin].drive_strength_ua = settings.drive_strength_ua; 963 } 964 965 return 0; 966 } 967 968 static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev, 969 unsigned int group, 970 unsigned long *configs, 971 unsigned int num_configs) 972 { 973 const unsigned int *pins; 974 unsigned int i, npins; 975 int ret; 976 977 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 978 if (ret) 979 return ret; 980 981 for (i = 0; i < npins; i++) { 982 ret = rzg2l_pinctrl_pinconf_set(pctldev, pins[i], configs, 983 num_configs); 984 if (ret) 985 return ret; 986 } 987 988 return 0; 989 }; 990 991 static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, 992 unsigned int group, 993 unsigned long *config) 994 { 995 const unsigned int *pins; 996 unsigned int i, npins, prev_config = 0; 997 int ret; 998 999 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 1000 if (ret) 1001 return ret; 1002 1003 for (i = 0; i < npins; i++) { 1004 ret = rzg2l_pinctrl_pinconf_get(pctldev, pins[i], config); 1005 if (ret) 1006 return ret; 1007 1008 /* Check config matching between to pin */ 1009 if (i && prev_config != *config) 1010 return -EOPNOTSUPP; 1011 1012 prev_config = *config; 1013 } 1014 1015 return 0; 1016 }; 1017 1018 static const struct pinctrl_ops rzg2l_pinctrl_pctlops = { 1019 .get_groups_count = pinctrl_generic_get_group_count, 1020 .get_group_name = pinctrl_generic_get_group_name, 1021 .get_group_pins = pinctrl_generic_get_group_pins, 1022 .dt_node_to_map = rzg2l_dt_node_to_map, 1023 .dt_free_map = rzg2l_dt_free_map, 1024 }; 1025 1026 static const struct pinmux_ops rzg2l_pinctrl_pmxops = { 1027 .get_functions_count = pinmux_generic_get_function_count, 1028 .get_function_name = pinmux_generic_get_function_name, 1029 .get_function_groups = pinmux_generic_get_function_groups, 1030 .set_mux = rzg2l_pinctrl_set_mux, 1031 .strict = true, 1032 }; 1033 1034 static const struct pinconf_ops rzg2l_pinctrl_confops = { 1035 .is_generic = true, 1036 .pin_config_get = rzg2l_pinctrl_pinconf_get, 1037 .pin_config_set = rzg2l_pinctrl_pinconf_set, 1038 .pin_config_group_set = rzg2l_pinctrl_pinconf_group_set, 1039 .pin_config_group_get = rzg2l_pinctrl_pinconf_group_get, 1040 .pin_config_config_dbg_show = pinconf_generic_dump_config, 1041 }; 1042 1043 static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) 1044 { 1045 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1046 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1047 u32 *pin_data = pin_desc->drv_data; 1048 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1049 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 1050 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1051 unsigned long flags; 1052 u8 reg8; 1053 int ret; 1054 1055 ret = rzg2l_validate_gpio_pin(pctrl, *pin_data, port, bit); 1056 if (ret) 1057 return ret; 1058 1059 ret = pinctrl_gpio_request(chip, offset); 1060 if (ret) 1061 return ret; 1062 1063 spin_lock_irqsave(&pctrl->lock, flags); 1064 1065 /* Select GPIO mode in PMC Register */ 1066 reg8 = readb(pctrl->base + PMC(off)); 1067 reg8 &= ~BIT(bit); 1068 writeb(reg8, pctrl->base + PMC(off)); 1069 1070 spin_unlock_irqrestore(&pctrl->lock, flags); 1071 1072 return 0; 1073 } 1074 1075 static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset, 1076 bool output) 1077 { 1078 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1079 unsigned int *pin_data = pin_desc->drv_data; 1080 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1081 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1082 unsigned long flags; 1083 u16 reg16; 1084 1085 spin_lock_irqsave(&pctrl->lock, flags); 1086 1087 reg16 = readw(pctrl->base + PM(off)); 1088 reg16 &= ~(PM_MASK << (bit * 2)); 1089 1090 reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2); 1091 writew(reg16, pctrl->base + PM(off)); 1092 1093 spin_unlock_irqrestore(&pctrl->lock, flags); 1094 } 1095 1096 static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1097 { 1098 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1099 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1100 unsigned int *pin_data = pin_desc->drv_data; 1101 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1102 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1103 1104 if (!(readb(pctrl->base + PMC(off)) & BIT(bit))) { 1105 u16 reg16; 1106 1107 reg16 = readw(pctrl->base + PM(off)); 1108 reg16 = (reg16 >> (bit * 2)) & PM_MASK; 1109 if (reg16 == PM_OUTPUT) 1110 return GPIO_LINE_DIRECTION_OUT; 1111 } 1112 1113 return GPIO_LINE_DIRECTION_IN; 1114 } 1115 1116 static int rzg2l_gpio_direction_input(struct gpio_chip *chip, 1117 unsigned int offset) 1118 { 1119 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1120 1121 rzg2l_gpio_set_direction(pctrl, offset, false); 1122 1123 return 0; 1124 } 1125 1126 static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset, 1127 int value) 1128 { 1129 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1130 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1131 unsigned int *pin_data = pin_desc->drv_data; 1132 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1133 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1134 unsigned long flags; 1135 u8 reg8; 1136 1137 spin_lock_irqsave(&pctrl->lock, flags); 1138 1139 reg8 = readb(pctrl->base + P(off)); 1140 1141 if (value) 1142 writeb(reg8 | BIT(bit), pctrl->base + P(off)); 1143 else 1144 writeb(reg8 & ~BIT(bit), pctrl->base + P(off)); 1145 1146 spin_unlock_irqrestore(&pctrl->lock, flags); 1147 } 1148 1149 static int rzg2l_gpio_direction_output(struct gpio_chip *chip, 1150 unsigned int offset, int value) 1151 { 1152 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1153 1154 rzg2l_gpio_set(chip, offset, value); 1155 rzg2l_gpio_set_direction(pctrl, offset, true); 1156 1157 return 0; 1158 } 1159 1160 static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset) 1161 { 1162 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1163 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1164 unsigned int *pin_data = pin_desc->drv_data; 1165 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1166 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1167 u16 reg16; 1168 1169 reg16 = readw(pctrl->base + PM(off)); 1170 reg16 = (reg16 >> (bit * 2)) & PM_MASK; 1171 1172 if (reg16 == PM_INPUT) 1173 return !!(readb(pctrl->base + PIN(off)) & BIT(bit)); 1174 else if (reg16 == PM_OUTPUT) 1175 return !!(readb(pctrl->base + P(off)) & BIT(bit)); 1176 else 1177 return -EINVAL; 1178 } 1179 1180 static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset) 1181 { 1182 unsigned int virq; 1183 1184 pinctrl_gpio_free(chip, offset); 1185 1186 virq = irq_find_mapping(chip->irq.domain, offset); 1187 if (virq) 1188 irq_dispose_mapping(virq); 1189 1190 /* 1191 * Set the GPIO as an input to ensure that the next GPIO request won't 1192 * drive the GPIO pin as an output. 1193 */ 1194 rzg2l_gpio_direction_input(chip, offset); 1195 } 1196 1197 static const char * const rzg2l_gpio_names[] = { 1198 "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7", 1199 "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7", 1200 "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7", 1201 "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7", 1202 "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7", 1203 "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7", 1204 "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7", 1205 "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7", 1206 "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7", 1207 "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7", 1208 "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7", 1209 "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7", 1210 "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7", 1211 "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7", 1212 "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7", 1213 "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7", 1214 "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7", 1215 "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7", 1216 "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7", 1217 "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7", 1218 "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7", 1219 "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7", 1220 "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7", 1221 "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7", 1222 "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7", 1223 "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7", 1224 "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7", 1225 "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7", 1226 "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7", 1227 "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7", 1228 "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7", 1229 "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7", 1230 "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7", 1231 "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7", 1232 "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7", 1233 "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7", 1234 "P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7", 1235 "P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7", 1236 "P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7", 1237 "P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7", 1238 "P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7", 1239 "P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7", 1240 "P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7", 1241 "P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7", 1242 "P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7", 1243 "P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7", 1244 "P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7", 1245 "P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7", 1246 "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7", 1247 }; 1248 1249 static const u32 r9a07g044_gpio_configs[] = { 1250 RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS), 1251 RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS), 1252 RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS), 1253 RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS), 1254 RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS), 1255 RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS), 1256 RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS), 1257 RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS), 1258 RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS), 1259 RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS), 1260 RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS), 1261 RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS), 1262 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), 1263 RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS), 1264 RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS), 1265 RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS), 1266 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), 1267 RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS), 1268 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS), 1269 RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS), 1270 RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1271 RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1272 RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1273 RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1274 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1275 RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1276 RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1277 RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1278 RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1279 RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1280 RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1281 RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1282 RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1283 RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1284 RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1285 RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1286 RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1287 RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1288 RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS), 1289 RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS), 1290 RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS), 1291 RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS), 1292 RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS), 1293 RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS), 1294 RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS), 1295 RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS), 1296 RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS), 1297 RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS), 1298 RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), 1299 }; 1300 1301 static const u32 r9a07g043_gpio_configs[] = { 1302 RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS), 1303 RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1304 RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1305 RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1306 RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1307 RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS), 1308 RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS), 1309 RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1310 RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1311 RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1312 RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1313 RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS), 1314 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), 1315 RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS), 1316 RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS), 1317 RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS), 1318 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), 1319 RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS), 1320 RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), 1321 }; 1322 1323 static const u32 r9a08g045_gpio_configs[] = { 1324 RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */ 1325 RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1326 PIN_CFG_IO_VMC_ETH0)), /* P1 */ 1327 RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1328 PIN_CFG_IO_VMC_ETH0)), /* P2 */ 1329 RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1330 PIN_CFG_IO_VMC_ETH0)), /* P3 */ 1331 RZG2L_GPIO_PORT_PACK(6, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1332 PIN_CFG_IO_VMC_ETH0)), /* P4 */ 1333 RZG2L_GPIO_PORT_PACK(5, 0x21, RZG3S_MPXED_PIN_FUNCS(A)), /* P5 */ 1334 RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */ 1335 RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1336 PIN_CFG_IO_VMC_ETH1)), /* P7 */ 1337 RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1338 PIN_CFG_IO_VMC_ETH1)), /* P8 */ 1339 RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1340 PIN_CFG_IO_VMC_ETH1)), /* P9 */ 1341 RZG2L_GPIO_PORT_PACK(5, 0x37, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1342 PIN_CFG_IO_VMC_ETH1)), /* P10 */ 1343 RZG2L_GPIO_PORT_PACK(4, 0x23, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P11 */ 1344 RZG2L_GPIO_PORT_PACK(2, 0x24, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P12 */ 1345 RZG2L_GPIO_PORT_PACK(5, 0x25, RZG3S_MPXED_PIN_FUNCS(A)), /* P13 */ 1346 RZG2L_GPIO_PORT_PACK(3, 0x26, RZG3S_MPXED_PIN_FUNCS(A)), /* P14 */ 1347 RZG2L_GPIO_PORT_PACK(4, 0x27, RZG3S_MPXED_PIN_FUNCS(A)), /* P15 */ 1348 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG3S_MPXED_PIN_FUNCS(A)), /* P16 */ 1349 RZG2L_GPIO_PORT_PACK(4, 0x29, RZG3S_MPXED_PIN_FUNCS(A)), /* P17 */ 1350 RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */ 1351 }; 1352 1353 static const struct { 1354 struct rzg2l_dedicated_configs common[35]; 1355 struct rzg2l_dedicated_configs rzg2l_pins[7]; 1356 } rzg2l_dedicated_pins = { 1357 .common = { 1358 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, 1359 (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) }, 1360 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, 1361 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, 1362 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0, 1363 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, 1364 { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) }, 1365 { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) }, 1366 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0, 1367 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, 1368 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1, 1369 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1370 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2, 1371 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, 1372 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0, 1373 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1374 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1, 1375 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1376 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2, 1377 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1378 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3, 1379 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1380 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4, 1381 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1382 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5, 1383 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1384 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6, 1385 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1386 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7, 1387 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1388 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0, 1389 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) }, 1390 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1, 1391 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1392 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0, 1393 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1394 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1, 1395 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1396 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2, 1397 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1398 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3, 1399 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1400 { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0, 1401 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1402 { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1, 1403 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1404 { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2, 1405 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1406 { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3, 1407 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1408 { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4, 1409 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1410 { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5, 1411 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1412 { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0, 1413 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1414 { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1, 1415 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1416 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) }, 1417 { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) }, 1418 { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) }, 1419 { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) }, 1420 { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) }, 1421 }, 1422 .rzg2l_pins = { 1423 { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1424 { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, 1425 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1426 { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1, 1427 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1428 { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2, 1429 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1430 { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3, 1431 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1432 { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4, 1433 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1434 { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5, 1435 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1436 } 1437 }; 1438 1439 static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = { 1440 { "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | 1441 PIN_CFG_FILCLKSEL)) }, 1442 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN | 1443 PIN_CFG_SOFT_PS)) }, 1444 { "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) }, 1445 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) }, 1446 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) }, 1447 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1448 PIN_CFG_IO_VMC_SD0)) }, 1449 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) }, 1450 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1451 PIN_CFG_IO_VMC_SD0)) }, 1452 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1453 PIN_CFG_IO_VMC_SD0)) }, 1454 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1455 PIN_CFG_IO_VMC_SD0)) }, 1456 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1457 PIN_CFG_IO_VMC_SD0)) }, 1458 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1459 PIN_CFG_IO_VMC_SD0)) }, 1460 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1461 PIN_CFG_IO_VMC_SD0)) }, 1462 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1463 PIN_CFG_IO_VMC_SD0)) }, 1464 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1465 PIN_CFG_IO_VMC_SD0)) }, 1466 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD1)) }, 1467 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1468 PIN_CFG_IO_VMC_SD1)) }, 1469 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1470 PIN_CFG_IO_VMC_SD1)) }, 1471 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1472 PIN_CFG_IO_VMC_SD1)) }, 1473 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1474 PIN_CFG_IO_VMC_SD1)) }, 1475 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 1476 PIN_CFG_IO_VMC_SD1)) }, 1477 }; 1478 1479 static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data) 1480 { 1481 unsigned int gpioint; 1482 unsigned int i; 1483 u32 port, bit; 1484 1485 port = virq / 8; 1486 bit = virq % 8; 1487 1488 if (port >= data->n_ports || 1489 bit >= RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[port])) 1490 return -EINVAL; 1491 1492 gpioint = bit; 1493 for (i = 0; i < port; i++) 1494 gpioint += RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[i]); 1495 1496 return gpioint; 1497 } 1498 1499 static void rzg2l_gpio_irq_disable(struct irq_data *d) 1500 { 1501 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1502 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 1503 unsigned int hwirq = irqd_to_hwirq(d); 1504 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; 1505 unsigned int *pin_data = pin_desc->drv_data; 1506 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1507 u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq); 1508 unsigned long flags; 1509 void __iomem *addr; 1510 1511 irq_chip_disable_parent(d); 1512 1513 addr = pctrl->base + ISEL(off); 1514 if (bit >= 4) { 1515 bit -= 4; 1516 addr += 4; 1517 } 1518 1519 spin_lock_irqsave(&pctrl->lock, flags); 1520 writel(readl(addr) & ~BIT(bit * 8), addr); 1521 spin_unlock_irqrestore(&pctrl->lock, flags); 1522 1523 gpiochip_disable_irq(gc, hwirq); 1524 } 1525 1526 static void rzg2l_gpio_irq_enable(struct irq_data *d) 1527 { 1528 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1529 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 1530 unsigned int hwirq = irqd_to_hwirq(d); 1531 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; 1532 unsigned int *pin_data = pin_desc->drv_data; 1533 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1534 u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq); 1535 unsigned long flags; 1536 void __iomem *addr; 1537 1538 gpiochip_enable_irq(gc, hwirq); 1539 1540 addr = pctrl->base + ISEL(off); 1541 if (bit >= 4) { 1542 bit -= 4; 1543 addr += 4; 1544 } 1545 1546 spin_lock_irqsave(&pctrl->lock, flags); 1547 writel(readl(addr) | BIT(bit * 8), addr); 1548 spin_unlock_irqrestore(&pctrl->lock, flags); 1549 1550 irq_chip_enable_parent(d); 1551 } 1552 1553 static int rzg2l_gpio_irq_set_type(struct irq_data *d, unsigned int type) 1554 { 1555 return irq_chip_set_type_parent(d, type); 1556 } 1557 1558 static void rzg2l_gpio_irqc_eoi(struct irq_data *d) 1559 { 1560 irq_chip_eoi_parent(d); 1561 } 1562 1563 static void rzg2l_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p) 1564 { 1565 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 1566 1567 seq_printf(p, dev_name(gc->parent)); 1568 } 1569 1570 static const struct irq_chip rzg2l_gpio_irqchip = { 1571 .name = "rzg2l-gpio", 1572 .irq_disable = rzg2l_gpio_irq_disable, 1573 .irq_enable = rzg2l_gpio_irq_enable, 1574 .irq_mask = irq_chip_mask_parent, 1575 .irq_unmask = irq_chip_unmask_parent, 1576 .irq_set_type = rzg2l_gpio_irq_set_type, 1577 .irq_eoi = rzg2l_gpio_irqc_eoi, 1578 .irq_print_chip = rzg2l_gpio_irq_print_chip, 1579 .flags = IRQCHIP_IMMUTABLE, 1580 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1581 }; 1582 1583 static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, 1584 unsigned int child, 1585 unsigned int child_type, 1586 unsigned int *parent, 1587 unsigned int *parent_type) 1588 { 1589 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); 1590 unsigned long flags; 1591 int gpioint, irq; 1592 1593 gpioint = rzg2l_gpio_get_gpioint(child, pctrl->data); 1594 if (gpioint < 0) 1595 return gpioint; 1596 1597 spin_lock_irqsave(&pctrl->bitmap_lock, flags); 1598 irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1)); 1599 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); 1600 if (irq < 0) 1601 return -ENOSPC; 1602 pctrl->hwirq[irq] = child; 1603 irq += RZG2L_TINT_IRQ_START_INDEX; 1604 1605 /* All these interrupts are level high in the CPU */ 1606 *parent_type = IRQ_TYPE_LEVEL_HIGH; 1607 *parent = RZG2L_PACK_HWIRQ(gpioint, irq); 1608 return 0; 1609 } 1610 1611 static int rzg2l_gpio_populate_parent_fwspec(struct gpio_chip *chip, 1612 union gpio_irq_fwspec *gfwspec, 1613 unsigned int parent_hwirq, 1614 unsigned int parent_type) 1615 { 1616 struct irq_fwspec *fwspec = &gfwspec->fwspec; 1617 1618 fwspec->fwnode = chip->irq.parent_domain->fwnode; 1619 fwspec->param_count = 2; 1620 fwspec->param[0] = parent_hwirq; 1621 fwspec->param[1] = parent_type; 1622 1623 return 0; 1624 } 1625 1626 static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq, 1627 unsigned int nr_irqs) 1628 { 1629 struct irq_data *d; 1630 1631 d = irq_domain_get_irq_data(domain, virq); 1632 if (d) { 1633 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1634 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 1635 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1636 unsigned long flags; 1637 unsigned int i; 1638 1639 for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { 1640 if (pctrl->hwirq[i] == hwirq) { 1641 spin_lock_irqsave(&pctrl->bitmap_lock, flags); 1642 bitmap_release_region(pctrl->tint_slot, i, get_order(1)); 1643 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); 1644 pctrl->hwirq[i] = 0; 1645 break; 1646 } 1647 } 1648 } 1649 irq_domain_free_irqs_common(domain, virq, nr_irqs); 1650 } 1651 1652 static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc, 1653 unsigned long *valid_mask, 1654 unsigned int ngpios) 1655 { 1656 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); 1657 struct gpio_chip *chip = &pctrl->gpio_chip; 1658 unsigned int offset; 1659 1660 /* Forbid unused lines to be mapped as IRQs */ 1661 for (offset = 0; offset < chip->ngpio; offset++) { 1662 u32 port, bit; 1663 1664 port = offset / 8; 1665 bit = offset % 8; 1666 1667 if (port >= pctrl->data->n_ports || 1668 bit >= RZG2L_GPIO_PORT_GET_PINCNT(pctrl->data->port_pin_configs[port])) 1669 clear_bit(offset, valid_mask); 1670 } 1671 } 1672 1673 static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) 1674 { 1675 struct device_node *np = pctrl->dev->of_node; 1676 struct gpio_chip *chip = &pctrl->gpio_chip; 1677 const char *name = dev_name(pctrl->dev); 1678 struct irq_domain *parent_domain; 1679 struct of_phandle_args of_args; 1680 struct device_node *parent_np; 1681 struct gpio_irq_chip *girq; 1682 int ret; 1683 1684 parent_np = of_irq_find_parent(np); 1685 if (!parent_np) 1686 return -ENXIO; 1687 1688 parent_domain = irq_find_host(parent_np); 1689 of_node_put(parent_np); 1690 if (!parent_domain) 1691 return -EPROBE_DEFER; 1692 1693 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args); 1694 if (ret) { 1695 dev_err(pctrl->dev, "Unable to parse gpio-ranges\n"); 1696 return ret; 1697 } 1698 1699 if (of_args.args[0] != 0 || of_args.args[1] != 0 || 1700 of_args.args[2] != pctrl->data->n_port_pins) { 1701 dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n"); 1702 return -EINVAL; 1703 } 1704 1705 chip->names = pctrl->data->port_pins; 1706 chip->request = rzg2l_gpio_request; 1707 chip->free = rzg2l_gpio_free; 1708 chip->get_direction = rzg2l_gpio_get_direction; 1709 chip->direction_input = rzg2l_gpio_direction_input; 1710 chip->direction_output = rzg2l_gpio_direction_output; 1711 chip->get = rzg2l_gpio_get; 1712 chip->set = rzg2l_gpio_set; 1713 chip->label = name; 1714 chip->parent = pctrl->dev; 1715 chip->owner = THIS_MODULE; 1716 chip->base = -1; 1717 chip->ngpio = of_args.args[2]; 1718 1719 girq = &chip->irq; 1720 gpio_irq_chip_set_chip(girq, &rzg2l_gpio_irqchip); 1721 girq->fwnode = of_node_to_fwnode(np); 1722 girq->parent_domain = parent_domain; 1723 girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq; 1724 girq->populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec; 1725 girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free; 1726 girq->init_valid_mask = rzg2l_init_irq_valid_mask; 1727 1728 pctrl->gpio_range.id = 0; 1729 pctrl->gpio_range.pin_base = 0; 1730 pctrl->gpio_range.base = 0; 1731 pctrl->gpio_range.npins = chip->ngpio; 1732 pctrl->gpio_range.name = chip->label; 1733 pctrl->gpio_range.gc = chip; 1734 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); 1735 if (ret) { 1736 dev_err(pctrl->dev, "failed to add GPIO controller\n"); 1737 return ret; 1738 } 1739 1740 dev_dbg(pctrl->dev, "Registered gpio controller\n"); 1741 1742 return 0; 1743 } 1744 1745 static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) 1746 { 1747 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 1748 struct pinctrl_pin_desc *pins; 1749 unsigned int i, j; 1750 u32 *pin_data; 1751 int ret; 1752 1753 pctrl->desc.name = DRV_NAME; 1754 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; 1755 pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops; 1756 pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops; 1757 pctrl->desc.confops = &rzg2l_pinctrl_confops; 1758 pctrl->desc.owner = THIS_MODULE; 1759 1760 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); 1761 if (!pins) 1762 return -ENOMEM; 1763 1764 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, 1765 sizeof(*pin_data), GFP_KERNEL); 1766 if (!pin_data) 1767 return -ENOMEM; 1768 1769 pctrl->pins = pins; 1770 pctrl->desc.pins = pins; 1771 1772 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { 1773 pins[i].number = i; 1774 pins[i].name = pctrl->data->port_pins[i]; 1775 if (i && !(i % RZG2L_PINS_PER_PORT)) 1776 j++; 1777 pin_data[i] = pctrl->data->port_pin_configs[j]; 1778 pins[i].drv_data = &pin_data[i]; 1779 } 1780 1781 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { 1782 unsigned int index = pctrl->data->n_port_pins + i; 1783 1784 pins[index].number = index; 1785 pins[index].name = pctrl->data->dedicated_pins[i].name; 1786 pin_data[index] = pctrl->data->dedicated_pins[i].config; 1787 pins[index].drv_data = &pin_data[index]; 1788 } 1789 1790 pctrl->settings = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pctrl->settings), 1791 GFP_KERNEL); 1792 if (!pctrl->settings) 1793 return -ENOMEM; 1794 1795 for (i = 0; hwcfg->drive_strength_ua && i < pctrl->desc.npins; i++) { 1796 if (pin_data[i] & PIN_CFG_SOFT_PS) { 1797 pctrl->settings[i].power_source = 3300; 1798 } else { 1799 ret = rzg2l_get_power_source(pctrl, i, pin_data[i]); 1800 if (ret < 0) 1801 continue; 1802 pctrl->settings[i].power_source = ret; 1803 } 1804 } 1805 1806 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, 1807 &pctrl->pctl); 1808 if (ret) { 1809 dev_err(pctrl->dev, "pinctrl registration failed\n"); 1810 return ret; 1811 } 1812 1813 ret = pinctrl_enable(pctrl->pctl); 1814 if (ret) { 1815 dev_err(pctrl->dev, "pinctrl enable failed\n"); 1816 return ret; 1817 } 1818 1819 ret = rzg2l_gpio_register(pctrl); 1820 if (ret) { 1821 dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret); 1822 return ret; 1823 } 1824 1825 return 0; 1826 } 1827 1828 static int rzg2l_pinctrl_probe(struct platform_device *pdev) 1829 { 1830 struct rzg2l_pinctrl *pctrl; 1831 struct clk *clk; 1832 int ret; 1833 1834 BUILD_BUG_ON(ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT > 1835 ARRAY_SIZE(rzg2l_gpio_names)); 1836 1837 BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT > 1838 ARRAY_SIZE(rzg2l_gpio_names)); 1839 1840 BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT > 1841 ARRAY_SIZE(rzg2l_gpio_names)); 1842 1843 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1844 if (!pctrl) 1845 return -ENOMEM; 1846 1847 pctrl->dev = &pdev->dev; 1848 1849 pctrl->data = of_device_get_match_data(&pdev->dev); 1850 if (!pctrl->data) 1851 return -EINVAL; 1852 1853 pctrl->base = devm_platform_ioremap_resource(pdev, 0); 1854 if (IS_ERR(pctrl->base)) 1855 return PTR_ERR(pctrl->base); 1856 1857 clk = devm_clk_get_enabled(pctrl->dev, NULL); 1858 if (IS_ERR(clk)) 1859 return dev_err_probe(pctrl->dev, PTR_ERR(clk), 1860 "failed to enable GPIO clk\n"); 1861 1862 spin_lock_init(&pctrl->lock); 1863 spin_lock_init(&pctrl->bitmap_lock); 1864 mutex_init(&pctrl->mutex); 1865 1866 platform_set_drvdata(pdev, pctrl); 1867 1868 ret = rzg2l_pinctrl_register(pctrl); 1869 if (ret) 1870 return ret; 1871 1872 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); 1873 return 0; 1874 } 1875 1876 static const struct rzg2l_hwcfg rzg2l_hwcfg = { 1877 .regs = { 1878 .pwpr = 0x3014, 1879 .sd_ch = 0x3000, 1880 }, 1881 .iolh_groupa_ua = { 1882 /* 3v3 power source */ 1883 [RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000, 1884 }, 1885 .iolh_groupb_oi = { 100, 66, 50, 33, }, 1886 }; 1887 1888 static const struct rzg2l_hwcfg rzg3s_hwcfg = { 1889 .regs = { 1890 .pwpr = 0x3000, 1891 .sd_ch = 0x3004, 1892 }, 1893 .iolh_groupa_ua = { 1894 /* 1v8 power source */ 1895 [RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000, 1896 /* 3v3 power source */ 1897 [RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000, 1898 }, 1899 .iolh_groupb_ua = { 1900 /* 1v8 power source */ 1901 [RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000, 1902 /* 3v3 power source */ 1903 [RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000, 1904 }, 1905 .iolh_groupc_ua = { 1906 /* 1v8 power source */ 1907 [RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800, 1908 /* 2v5 source */ 1909 [RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100, 1910 /* 3v3 power source */ 1911 [RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050, 1912 }, 1913 .drive_strength_ua = true, 1914 .func_base = 1, 1915 }; 1916 1917 static struct rzg2l_pinctrl_data r9a07g043_data = { 1918 .port_pins = rzg2l_gpio_names, 1919 .port_pin_configs = r9a07g043_gpio_configs, 1920 .n_ports = ARRAY_SIZE(r9a07g043_gpio_configs), 1921 .dedicated_pins = rzg2l_dedicated_pins.common, 1922 .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, 1923 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), 1924 .hwcfg = &rzg2l_hwcfg, 1925 }; 1926 1927 static struct rzg2l_pinctrl_data r9a07g044_data = { 1928 .port_pins = rzg2l_gpio_names, 1929 .port_pin_configs = r9a07g044_gpio_configs, 1930 .n_ports = ARRAY_SIZE(r9a07g044_gpio_configs), 1931 .dedicated_pins = rzg2l_dedicated_pins.common, 1932 .n_port_pins = ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT, 1933 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + 1934 ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), 1935 .hwcfg = &rzg2l_hwcfg, 1936 }; 1937 1938 static struct rzg2l_pinctrl_data r9a08g045_data = { 1939 .port_pins = rzg2l_gpio_names, 1940 .port_pin_configs = r9a08g045_gpio_configs, 1941 .n_ports = ARRAY_SIZE(r9a08g045_gpio_configs), 1942 .dedicated_pins = rzg3s_dedicated_pins, 1943 .n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT, 1944 .n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins), 1945 .hwcfg = &rzg3s_hwcfg, 1946 }; 1947 1948 static const struct of_device_id rzg2l_pinctrl_of_table[] = { 1949 { 1950 .compatible = "renesas,r9a07g043-pinctrl", 1951 .data = &r9a07g043_data, 1952 }, 1953 { 1954 .compatible = "renesas,r9a07g044-pinctrl", 1955 .data = &r9a07g044_data, 1956 }, 1957 { 1958 .compatible = "renesas,r9a08g045-pinctrl", 1959 .data = &r9a08g045_data, 1960 }, 1961 { /* sentinel */ } 1962 }; 1963 1964 static struct platform_driver rzg2l_pinctrl_driver = { 1965 .driver = { 1966 .name = DRV_NAME, 1967 .of_match_table = of_match_ptr(rzg2l_pinctrl_of_table), 1968 }, 1969 .probe = rzg2l_pinctrl_probe, 1970 }; 1971 1972 static int __init rzg2l_pinctrl_init(void) 1973 { 1974 return platform_driver_register(&rzg2l_pinctrl_driver); 1975 } 1976 core_initcall(rzg2l_pinctrl_init); 1977 1978 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); 1979 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family"); 1980