1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Intel Core SoC Power Management Controller Header File 4 * 5 * Copyright (c) 2016, Intel Corporation. 6 * All Rights Reserved. 7 * 8 * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> 9 * Vishwanath Somayaji <vishwanath.somayaji@intel.com> 10 */ 11 12 #ifndef PMC_CORE_H 13 #define PMC_CORE_H 14 15 #include <linux/acpi.h> 16 #include <linux/bits.h> 17 #include <linux/platform_device.h> 18 19 struct telem_endpoint; 20 21 #define SLP_S0_RES_COUNTER_MASK GENMASK(31, 0) 22 23 #define PMC_BASE_ADDR_DEFAULT 0xFE000000 24 #define MAX_NUM_PMC 3 25 26 /* Sunrise Point Power Management Controller PCI Device ID */ 27 #define SPT_PMC_PCI_DEVICE_ID 0x9d21 28 #define SPT_PMC_BASE_ADDR_OFFSET 0x48 29 #define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET 0x13c 30 #define SPT_PMC_PM_CFG_OFFSET 0x18 31 #define SPT_PMC_PM_STS_OFFSET 0x1c 32 #define SPT_PMC_MTPMC_OFFSET 0x20 33 #define SPT_PMC_MFPMC_OFFSET 0x38 34 #define SPT_PMC_LTR_IGNORE_OFFSET 0x30C 35 #define SPT_PMC_VRIC1_OFFSET 0x31c 36 #define SPT_PMC_MPHY_CORE_STS_0 0x1143 37 #define SPT_PMC_MPHY_CORE_STS_1 0x1142 38 #define SPT_PMC_MPHY_COM_STS_0 0x1155 39 #define SPT_PMC_MMIO_REG_LEN 0x1000 40 #define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x68 41 #define PMC_BASE_ADDR_MASK ~(SPT_PMC_MMIO_REG_LEN - 1) 42 #define MTPMC_MASK 0xffff0000 43 #define PPFEAR_MAX_NUM_ENTRIES 12 44 #define SPT_PPFEAR_NUM_ENTRIES 5 45 #define SPT_PMC_READ_DISABLE_BIT 0x16 46 #define SPT_PMC_MSG_FULL_STS_BIT 0x18 47 #define NUM_RETRIES 100 48 #define SPT_NUM_IP_IGN_ALLOWED 17 49 50 #define SPT_PMC_LTR_CUR_PLT 0x350 51 #define SPT_PMC_LTR_CUR_ASLT 0x354 52 #define SPT_PMC_LTR_SPA 0x360 53 #define SPT_PMC_LTR_SPB 0x364 54 #define SPT_PMC_LTR_SATA 0x368 55 #define SPT_PMC_LTR_GBE 0x36C 56 #define SPT_PMC_LTR_XHCI 0x370 57 #define SPT_PMC_LTR_RESERVED 0x374 58 #define SPT_PMC_LTR_ME 0x378 59 #define SPT_PMC_LTR_EVA 0x37C 60 #define SPT_PMC_LTR_SPC 0x380 61 #define SPT_PMC_LTR_AZ 0x384 62 #define SPT_PMC_LTR_LPSS 0x38C 63 #define SPT_PMC_LTR_CAM 0x390 64 #define SPT_PMC_LTR_SPD 0x394 65 #define SPT_PMC_LTR_SPE 0x398 66 #define SPT_PMC_LTR_ESPI 0x39C 67 #define SPT_PMC_LTR_SCC 0x3A0 68 #define SPT_PMC_LTR_ISH 0x3A4 69 70 /* Sunrise Point: PGD PFET Enable Ack Status Registers */ 71 enum ppfear_regs { 72 SPT_PMC_XRAM_PPFEAR0A = 0x590, 73 SPT_PMC_XRAM_PPFEAR0B, 74 SPT_PMC_XRAM_PPFEAR0C, 75 SPT_PMC_XRAM_PPFEAR0D, 76 SPT_PMC_XRAM_PPFEAR1A, 77 }; 78 79 #define SPT_PMC_BIT_PMC BIT(0) 80 #define SPT_PMC_BIT_OPI BIT(1) 81 #define SPT_PMC_BIT_SPI BIT(2) 82 #define SPT_PMC_BIT_XHCI BIT(3) 83 #define SPT_PMC_BIT_SPA BIT(4) 84 #define SPT_PMC_BIT_SPB BIT(5) 85 #define SPT_PMC_BIT_SPC BIT(6) 86 #define SPT_PMC_BIT_GBE BIT(7) 87 88 #define SPT_PMC_BIT_SATA BIT(0) 89 #define SPT_PMC_BIT_HDA_PGD0 BIT(1) 90 #define SPT_PMC_BIT_HDA_PGD1 BIT(2) 91 #define SPT_PMC_BIT_HDA_PGD2 BIT(3) 92 #define SPT_PMC_BIT_HDA_PGD3 BIT(4) 93 #define SPT_PMC_BIT_RSVD_0B BIT(5) 94 #define SPT_PMC_BIT_LPSS BIT(6) 95 #define SPT_PMC_BIT_LPC BIT(7) 96 97 #define SPT_PMC_BIT_SMB BIT(0) 98 #define SPT_PMC_BIT_ISH BIT(1) 99 #define SPT_PMC_BIT_P2SB BIT(2) 100 #define SPT_PMC_BIT_DFX BIT(3) 101 #define SPT_PMC_BIT_SCC BIT(4) 102 #define SPT_PMC_BIT_RSVD_0C BIT(5) 103 #define SPT_PMC_BIT_FUSE BIT(6) 104 #define SPT_PMC_BIT_CAMREA BIT(7) 105 106 #define SPT_PMC_BIT_RSVD_0D BIT(0) 107 #define SPT_PMC_BIT_USB3_OTG BIT(1) 108 #define SPT_PMC_BIT_EXI BIT(2) 109 #define SPT_PMC_BIT_CSE BIT(3) 110 #define SPT_PMC_BIT_CSME_KVM BIT(4) 111 #define SPT_PMC_BIT_CSME_PMT BIT(5) 112 #define SPT_PMC_BIT_CSME_CLINK BIT(6) 113 #define SPT_PMC_BIT_CSME_PTIO BIT(7) 114 115 #define SPT_PMC_BIT_CSME_USBR BIT(0) 116 #define SPT_PMC_BIT_CSME_SUSRAM BIT(1) 117 #define SPT_PMC_BIT_CSME_SMT BIT(2) 118 #define SPT_PMC_BIT_RSVD_1A BIT(3) 119 #define SPT_PMC_BIT_CSME_SMS2 BIT(4) 120 #define SPT_PMC_BIT_CSME_SMS1 BIT(5) 121 #define SPT_PMC_BIT_CSME_RTC BIT(6) 122 #define SPT_PMC_BIT_CSME_PSF BIT(7) 123 124 #define SPT_PMC_BIT_MPHY_LANE0 BIT(0) 125 #define SPT_PMC_BIT_MPHY_LANE1 BIT(1) 126 #define SPT_PMC_BIT_MPHY_LANE2 BIT(2) 127 #define SPT_PMC_BIT_MPHY_LANE3 BIT(3) 128 #define SPT_PMC_BIT_MPHY_LANE4 BIT(4) 129 #define SPT_PMC_BIT_MPHY_LANE5 BIT(5) 130 #define SPT_PMC_BIT_MPHY_LANE6 BIT(6) 131 #define SPT_PMC_BIT_MPHY_LANE7 BIT(7) 132 133 #define SPT_PMC_BIT_MPHY_LANE8 BIT(0) 134 #define SPT_PMC_BIT_MPHY_LANE9 BIT(1) 135 #define SPT_PMC_BIT_MPHY_LANE10 BIT(2) 136 #define SPT_PMC_BIT_MPHY_LANE11 BIT(3) 137 #define SPT_PMC_BIT_MPHY_LANE12 BIT(4) 138 #define SPT_PMC_BIT_MPHY_LANE13 BIT(5) 139 #define SPT_PMC_BIT_MPHY_LANE14 BIT(6) 140 #define SPT_PMC_BIT_MPHY_LANE15 BIT(7) 141 142 #define SPT_PMC_BIT_MPHY_CMN_LANE0 BIT(0) 143 #define SPT_PMC_BIT_MPHY_CMN_LANE1 BIT(1) 144 #define SPT_PMC_BIT_MPHY_CMN_LANE2 BIT(2) 145 #define SPT_PMC_BIT_MPHY_CMN_LANE3 BIT(3) 146 147 #define SPT_PMC_VRIC1_SLPS0LVEN BIT(13) 148 #define SPT_PMC_VRIC1_XTALSDQDIS BIT(22) 149 150 /* Cannonlake Power Management Controller register offsets */ 151 #define CNP_PMC_SLPS0_DBG_OFFSET 0x10B4 152 #define CNP_PMC_PM_CFG_OFFSET 0x1818 153 #define CNP_PMC_SLP_S0_RES_COUNTER_OFFSET 0x193C 154 #define CNP_PMC_LTR_IGNORE_OFFSET 0x1B0C 155 /* Cannonlake: PGD PFET Enable Ack Status Register(s) start */ 156 #define CNP_PMC_HOST_PPFEAR0A 0x1D90 157 158 #define CNP_PMC_LATCH_SLPS0_EVENTS BIT(31) 159 160 #define CNP_PMC_MMIO_REG_LEN 0x2000 161 #define CNP_PPFEAR_NUM_ENTRIES 8 162 #define CNP_PMC_READ_DISABLE_BIT 22 163 #define CNP_NUM_IP_IGN_ALLOWED 19 164 #define CNP_PMC_LTR_CUR_PLT 0x1B50 165 #define CNP_PMC_LTR_CUR_ASLT 0x1B54 166 #define CNP_PMC_LTR_SPA 0x1B60 167 #define CNP_PMC_LTR_SPB 0x1B64 168 #define CNP_PMC_LTR_SATA 0x1B68 169 #define CNP_PMC_LTR_GBE 0x1B6C 170 #define CNP_PMC_LTR_XHCI 0x1B70 171 #define CNP_PMC_LTR_RESERVED 0x1B74 172 #define CNP_PMC_LTR_ME 0x1B78 173 #define CNP_PMC_LTR_EVA 0x1B7C 174 #define CNP_PMC_LTR_SPC 0x1B80 175 #define CNP_PMC_LTR_AZ 0x1B84 176 #define CNP_PMC_LTR_LPSS 0x1B8C 177 #define CNP_PMC_LTR_CAM 0x1B90 178 #define CNP_PMC_LTR_SPD 0x1B94 179 #define CNP_PMC_LTR_SPE 0x1B98 180 #define CNP_PMC_LTR_ESPI 0x1B9C 181 #define CNP_PMC_LTR_SCC 0x1BA0 182 #define CNP_PMC_LTR_ISH 0x1BA4 183 #define CNP_PMC_LTR_CNV 0x1BF0 184 #define CNP_PMC_LTR_EMMC 0x1BF4 185 #define CNP_PMC_LTR_UFSX2 0x1BF8 186 187 #define LTR_DECODED_VAL GENMASK(9, 0) 188 #define LTR_DECODED_SCALE GENMASK(12, 10) 189 #define LTR_REQ_SNOOP BIT(15) 190 #define LTR_REQ_NONSNOOP BIT(31) 191 192 #define ICL_PPFEAR_NUM_ENTRIES 9 193 #define ICL_NUM_IP_IGN_ALLOWED 20 194 #define ICL_PMC_LTR_WIGIG 0x1BFC 195 #define ICL_PMC_SLP_S0_RES_COUNTER_STEP 0x64 196 197 #define LPM_MAX_NUM_MODES 8 198 #define LPM_DEFAULT_PRI { 7, 6, 2, 5, 4, 1, 3, 0 } 199 200 #define GET_X2_COUNTER(v) ((v) >> 1) 201 #define LPM_STS_LATCH_MODE BIT(31) 202 203 #define TGL_PMC_SLP_S0_RES_COUNTER_STEP 0x7A 204 #define TGL_PMC_LTR_THC0 0x1C04 205 #define TGL_PMC_LTR_THC1 0x1C08 206 #define TGL_NUM_IP_IGN_ALLOWED 23 207 #define TGL_PMC_LPM_RES_COUNTER_STEP_X2 61 /* 30.5us * 2 */ 208 209 #define ADL_PMC_LTR_SPF 0x1C00 210 #define ADL_NUM_IP_IGN_ALLOWED 23 211 #define ADL_PMC_SLP_S0_RES_COUNTER_OFFSET 0x1098 212 213 /* 214 * Tigerlake Power Management Controller register offsets 215 */ 216 #define TGL_LPM_STS_LATCH_EN_OFFSET 0x1C34 217 #define TGL_LPM_EN_OFFSET 0x1C78 218 #define TGL_LPM_RESIDENCY_OFFSET 0x1C80 219 220 /* Tigerlake Low Power Mode debug registers */ 221 #define TGL_LPM_STATUS_OFFSET 0x1C3C 222 #define TGL_LPM_LIVE_STATUS_OFFSET 0x1C5C 223 #define TGL_LPM_PRI_OFFSET 0x1C7C 224 #define TGL_LPM_NUM_MAPS 6 225 226 /* Tigerlake PSON residency register */ 227 #define TGL_PSON_RESIDENCY_OFFSET 0x18f8 228 #define TGL_PSON_RES_COUNTER_STEP 0x7A 229 230 /* Extended Test Mode Register 3 (CNL and later) */ 231 #define ETR3_OFFSET 0x1048 232 #define ETR3_CF9GR BIT(20) 233 #define ETR3_CF9LOCK BIT(31) 234 235 /* Extended Test Mode Register LPM bits (TGL and later */ 236 #define ETR3_CLEAR_LPM_EVENTS BIT(28) 237 238 /* Alder Lake Power Management Controller register offsets */ 239 #define ADL_LPM_EN_OFFSET 0x179C 240 #define ADL_LPM_RESIDENCY_OFFSET 0x17A4 241 #define ADL_LPM_NUM_MODES 2 242 #define ADL_LPM_NUM_MAPS 14 243 244 /* Alder Lake Low Power Mode debug registers */ 245 #define ADL_LPM_STATUS_OFFSET 0x170C 246 #define ADL_LPM_PRI_OFFSET 0x17A0 247 #define ADL_LPM_STATUS_LATCH_EN_OFFSET 0x1704 248 #define ADL_LPM_LIVE_STATUS_OFFSET 0x1764 249 250 /* Meteor Lake Power Management Controller register offsets */ 251 #define MTL_LPM_EN_OFFSET 0x1798 252 #define MTL_LPM_RESIDENCY_OFFSET 0x17A0 253 254 /* Meteor Lake Low Power Mode debug registers */ 255 #define MTL_LPM_PRI_OFFSET 0x179C 256 #define MTL_LPM_STATUS_LATCH_EN_OFFSET 0x16F8 257 #define MTL_LPM_STATUS_OFFSET 0x1700 258 #define MTL_LPM_LIVE_STATUS_OFFSET 0x175C 259 #define MTL_PMC_LTR_IOE_PMC 0x1C0C 260 #define MTL_PMC_LTR_ESE 0x1BAC 261 #define MTL_PMC_LTR_RESERVED 0x1BA4 262 #define MTL_IOE_PMC_MMIO_REG_LEN 0x23A4 263 #define MTL_SOCM_NUM_IP_IGN_ALLOWED 25 264 #define MTL_SOC_PMC_MMIO_REG_LEN 0x2708 265 #define MTL_PMC_LTR_SPG 0x1B74 266 #define ARL_SOCS_PMC_LTR_RESERVED 0x1B88 267 #define ARL_SOCS_NUM_IP_IGN_ALLOWED 26 268 #define ARL_PMC_LTR_DMI3 0x1BE4 269 #define ARL_PCH_PMC_MMIO_REG_LEN 0x2720 270 271 /* Meteor Lake PGD PFET Enable Ack Status */ 272 #define MTL_SOCM_PPFEAR_NUM_ENTRIES 8 273 #define MTL_IOE_PPFEAR_NUM_ENTRIES 10 274 #define ARL_SOCS_PPFEAR_NUM_ENTRIES 9 275 276 /* Die C6 from PUNIT telemetry */ 277 #define MTL_PMT_DMU_DIE_C6_OFFSET 15 278 #define MTL_PMT_DMU_GUID 0x1A067102 279 #define ARL_PMT_DMU_GUID 0x1A06A000 280 281 #define LNL_PMC_MMIO_REG_LEN 0x2708 282 #define LNL_PMC_LTR_OSSE 0x1B88 283 #define LNL_NUM_IP_IGN_ALLOWED 27 284 #define LNL_PPFEAR_NUM_ENTRIES 12 285 286 extern const char *pmc_lpm_modes[]; 287 288 struct pmc_bit_map { 289 const char *name; 290 u32 bit_mask; 291 }; 292 293 /** 294 * struct pmc_reg_map - Structure used to define parameter unique to a 295 PCH family 296 * @pfear_sts: Maps name of IP block to PPFEAR* bit 297 * @mphy_sts: Maps name of MPHY lane to MPHY status lane status bit 298 * @pll_sts: Maps name of PLL to corresponding bit status 299 * @slps0_dbg_maps: Array of SLP_S0_DBG* registers containing debug info 300 * @ltr_show_sts: Maps PCH IP Names to their MMIO register offsets 301 * @slp_s0_offset: PWRMBASE offset to read SLP_S0 residency 302 * @ltr_ignore_offset: PWRMBASE offset to read/write LTR ignore bit 303 * @regmap_length: Length of memory to map from PWRMBASE address to access 304 * @ppfear0_offset: PWRMBASE offset to read PPFEAR* 305 * @ppfear_buckets: Number of 8 bits blocks to read all IP blocks from 306 * PPFEAR 307 * @pm_cfg_offset: PWRMBASE offset to PM_CFG register 308 * @pm_read_disable_bit: Bit index to read PMC_READ_DISABLE 309 * @slps0_dbg_offset: PWRMBASE offset to SLP_S0_DEBUG_REG* 310 * 311 * Each PCH has unique set of register offsets and bit indexes. This structure 312 * captures them to have a common implementation. 313 */ 314 struct pmc_reg_map { 315 const struct pmc_bit_map **pfear_sts; 316 const struct pmc_bit_map *mphy_sts; 317 const struct pmc_bit_map *pll_sts; 318 const struct pmc_bit_map **slps0_dbg_maps; 319 const struct pmc_bit_map *ltr_show_sts; 320 const struct pmc_bit_map *msr_sts; 321 const struct pmc_bit_map **lpm_sts; 322 const u32 slp_s0_offset; 323 const int slp_s0_res_counter_step; 324 const u32 ltr_ignore_offset; 325 const int regmap_length; 326 const u32 ppfear0_offset; 327 const int ppfear_buckets; 328 const u32 pm_cfg_offset; 329 const int pm_read_disable_bit; 330 const u32 slps0_dbg_offset; 331 const u32 ltr_ignore_max; 332 const u32 pm_vric1_offset; 333 /* Low Power Mode registers */ 334 const int lpm_num_maps; 335 const int lpm_num_modes; 336 const int lpm_res_counter_step_x2; 337 const u32 lpm_sts_latch_en_offset; 338 const u32 lpm_en_offset; 339 const u32 lpm_priority_offset; 340 const u32 lpm_residency_offset; 341 const u32 lpm_status_offset; 342 const u32 lpm_live_status_offset; 343 const u32 etr3_offset; 344 const u8 *lpm_reg_index; 345 const u32 pson_residency_offset; 346 const u32 pson_residency_counter_step; 347 }; 348 349 /** 350 * struct pmc_info - Structure to keep pmc info 351 * @devid: device id of the pmc device 352 * @map: pointer to a pmc_reg_map struct that contains platform 353 * specific attributes 354 */ 355 struct pmc_info { 356 u32 guid; 357 u16 devid; 358 const struct pmc_reg_map *map; 359 }; 360 361 /** 362 * struct pmc - pmc private info structure 363 * @base_addr: contains pmc base address 364 * @regbase: pointer to io-remapped memory location 365 * @map: pointer to pmc_reg_map struct that contains platform 366 * specific attributes 367 * @lpm_req_regs: List of substate requirements 368 * 369 * pmc contains info about one power management controller device. 370 */ 371 struct pmc { 372 u64 base_addr; 373 void __iomem *regbase; 374 const struct pmc_reg_map *map; 375 u32 *lpm_req_regs; 376 }; 377 378 /** 379 * struct pmc_dev - pmc device structure 380 * @devs: pointer to an array of pmc pointers 381 * @pdev: pointer to platform_device struct 382 * @ssram_pcidev: pointer to pci device struct for the PMC SSRAM 383 * @crystal_freq: crystal frequency from cpuid 384 * @dbgfs_dir: path to debugfs interface 385 * @pmc_xram_read_bit: flag to indicate whether PMC XRAM shadow registers 386 * used to read MPHY PG and PLL status are available 387 * @mutex_lock: mutex to complete one transcation 388 * @pc10_counter: PC10 residency counter 389 * @s0ix_counter: S0ix residency (step adjusted) 390 * @num_lpm_modes: Count of enabled modes 391 * @lpm_en_modes: Array of enabled modes from lowest to highest priority 392 * @suspend: Function to perform platform specific suspend 393 * @resume: Function to perform platform specific resume 394 * 395 * pmc_dev contains info about power management controller device. 396 */ 397 struct pmc_dev { 398 struct pmc *pmcs[MAX_NUM_PMC]; 399 struct dentry *dbgfs_dir; 400 struct platform_device *pdev; 401 struct pci_dev *ssram_pcidev; 402 unsigned int crystal_freq; 403 int pmc_xram_read_bit; 404 struct mutex lock; /* generic mutex lock for PMC Core */ 405 406 u64 pc10_counter; 407 u64 s0ix_counter; 408 int num_lpm_modes; 409 int lpm_en_modes[LPM_MAX_NUM_MODES]; 410 void (*suspend)(struct pmc_dev *pmcdev); 411 int (*resume)(struct pmc_dev *pmcdev); 412 413 bool has_die_c6; 414 u32 die_c6_offset; 415 struct telem_endpoint *punit_ep; 416 struct pmc_info *regmap_list; 417 }; 418 419 enum pmc_index { 420 PMC_IDX_MAIN, 421 PMC_IDX_SOC = PMC_IDX_MAIN, 422 PMC_IDX_IOE, 423 PMC_IDX_PCH, 424 PMC_IDX_MAX 425 }; 426 427 extern const struct pmc_bit_map msr_map[]; 428 extern const struct pmc_bit_map spt_pll_map[]; 429 extern const struct pmc_bit_map spt_mphy_map[]; 430 extern const struct pmc_bit_map spt_pfear_map[]; 431 extern const struct pmc_bit_map *ext_spt_pfear_map[]; 432 extern const struct pmc_bit_map spt_ltr_show_map[]; 433 extern const struct pmc_reg_map spt_reg_map; 434 extern const struct pmc_bit_map cnp_pfear_map[]; 435 extern const struct pmc_bit_map *ext_cnp_pfear_map[]; 436 extern const struct pmc_bit_map cnp_slps0_dbg0_map[]; 437 extern const struct pmc_bit_map cnp_slps0_dbg1_map[]; 438 extern const struct pmc_bit_map cnp_slps0_dbg2_map[]; 439 extern const struct pmc_bit_map *cnp_slps0_dbg_maps[]; 440 extern const struct pmc_bit_map cnp_ltr_show_map[]; 441 extern const struct pmc_reg_map cnp_reg_map; 442 extern const struct pmc_bit_map icl_pfear_map[]; 443 extern const struct pmc_bit_map *ext_icl_pfear_map[]; 444 extern const struct pmc_reg_map icl_reg_map; 445 extern const struct pmc_bit_map tgl_pfear_map[]; 446 extern const struct pmc_bit_map *ext_tgl_pfear_map[]; 447 extern const struct pmc_bit_map tgl_clocksource_status_map[]; 448 extern const struct pmc_bit_map tgl_power_gating_status_map[]; 449 extern const struct pmc_bit_map tgl_d3_status_map[]; 450 extern const struct pmc_bit_map tgl_vnn_req_status_map[]; 451 extern const struct pmc_bit_map tgl_vnn_misc_status_map[]; 452 extern const struct pmc_bit_map tgl_signal_status_map[]; 453 extern const struct pmc_bit_map *tgl_lpm_maps[]; 454 extern const struct pmc_reg_map tgl_reg_map; 455 extern const struct pmc_reg_map tgl_h_reg_map; 456 extern const struct pmc_bit_map adl_pfear_map[]; 457 extern const struct pmc_bit_map *ext_adl_pfear_map[]; 458 extern const struct pmc_bit_map adl_ltr_show_map[]; 459 extern const struct pmc_bit_map adl_clocksource_status_map[]; 460 extern const struct pmc_bit_map adl_power_gating_status_0_map[]; 461 extern const struct pmc_bit_map adl_power_gating_status_1_map[]; 462 extern const struct pmc_bit_map adl_power_gating_status_2_map[]; 463 extern const struct pmc_bit_map adl_d3_status_0_map[]; 464 extern const struct pmc_bit_map adl_d3_status_1_map[]; 465 extern const struct pmc_bit_map adl_d3_status_2_map[]; 466 extern const struct pmc_bit_map adl_d3_status_3_map[]; 467 extern const struct pmc_bit_map adl_vnn_req_status_0_map[]; 468 extern const struct pmc_bit_map adl_vnn_req_status_1_map[]; 469 extern const struct pmc_bit_map adl_vnn_req_status_2_map[]; 470 extern const struct pmc_bit_map adl_vnn_req_status_3_map[]; 471 extern const struct pmc_bit_map adl_vnn_misc_status_map[]; 472 extern const struct pmc_bit_map *adl_lpm_maps[]; 473 extern const struct pmc_reg_map adl_reg_map; 474 extern const struct pmc_bit_map mtl_socm_pfear_map[]; 475 extern const struct pmc_bit_map *ext_mtl_socm_pfear_map[]; 476 extern const struct pmc_bit_map mtl_socm_ltr_show_map[]; 477 extern const struct pmc_bit_map mtl_socm_clocksource_status_map[]; 478 extern const struct pmc_bit_map mtl_socm_power_gating_status_0_map[]; 479 extern const struct pmc_bit_map mtl_socm_power_gating_status_1_map[]; 480 extern const struct pmc_bit_map mtl_socm_power_gating_status_2_map[]; 481 extern const struct pmc_bit_map mtl_socm_d3_status_0_map[]; 482 extern const struct pmc_bit_map mtl_socm_d3_status_1_map[]; 483 extern const struct pmc_bit_map mtl_socm_d3_status_2_map[]; 484 extern const struct pmc_bit_map mtl_socm_d3_status_3_map[]; 485 extern const struct pmc_bit_map mtl_socm_vnn_req_status_0_map[]; 486 extern const struct pmc_bit_map mtl_socm_vnn_req_status_1_map[]; 487 extern const struct pmc_bit_map mtl_socm_vnn_req_status_2_map[]; 488 extern const struct pmc_bit_map mtl_socm_vnn_req_status_3_map[]; 489 extern const struct pmc_bit_map mtl_socm_vnn_misc_status_map[]; 490 extern const struct pmc_bit_map mtl_socm_signal_status_map[]; 491 extern const struct pmc_bit_map *mtl_socm_lpm_maps[]; 492 extern const struct pmc_reg_map mtl_socm_reg_map; 493 extern const struct pmc_bit_map mtl_ioep_pfear_map[]; 494 extern const struct pmc_bit_map *ext_mtl_ioep_pfear_map[]; 495 extern const struct pmc_bit_map mtl_ioep_ltr_show_map[]; 496 extern const struct pmc_bit_map mtl_ioep_clocksource_status_map[]; 497 extern const struct pmc_bit_map mtl_ioep_power_gating_status_0_map[]; 498 extern const struct pmc_bit_map mtl_ioep_power_gating_status_1_map[]; 499 extern const struct pmc_bit_map mtl_ioep_power_gating_status_2_map[]; 500 extern const struct pmc_bit_map mtl_ioep_d3_status_0_map[]; 501 extern const struct pmc_bit_map mtl_ioep_d3_status_1_map[]; 502 extern const struct pmc_bit_map mtl_ioep_d3_status_2_map[]; 503 extern const struct pmc_bit_map mtl_ioep_d3_status_3_map[]; 504 extern const struct pmc_bit_map mtl_ioep_vnn_req_status_0_map[]; 505 extern const struct pmc_bit_map mtl_ioep_vnn_req_status_1_map[]; 506 extern const struct pmc_bit_map mtl_ioep_vnn_req_status_2_map[]; 507 extern const struct pmc_bit_map mtl_ioep_vnn_req_status_3_map[]; 508 extern const struct pmc_bit_map mtl_ioep_vnn_misc_status_map[]; 509 extern const struct pmc_bit_map *mtl_ioep_lpm_maps[]; 510 extern const struct pmc_reg_map mtl_ioep_reg_map; 511 extern const struct pmc_bit_map mtl_ioem_pfear_map[]; 512 extern const struct pmc_bit_map *ext_mtl_ioem_pfear_map[]; 513 extern const struct pmc_bit_map mtl_ioem_power_gating_status_1_map[]; 514 extern const struct pmc_bit_map mtl_ioem_vnn_req_status_1_map[]; 515 extern const struct pmc_bit_map *mtl_ioem_lpm_maps[]; 516 extern const struct pmc_reg_map mtl_ioem_reg_map; 517 extern const struct pmc_reg_map lnl_socm_reg_map; 518 519 /* LNL */ 520 extern const struct pmc_bit_map lnl_ltr_show_map[]; 521 extern const struct pmc_bit_map lnl_clocksource_status_map[]; 522 extern const struct pmc_bit_map lnl_power_gating_status_0_map[]; 523 extern const struct pmc_bit_map lnl_power_gating_status_1_map[]; 524 extern const struct pmc_bit_map lnl_power_gating_status_2_map[]; 525 extern const struct pmc_bit_map lnl_d3_status_0_map[]; 526 extern const struct pmc_bit_map lnl_d3_status_1_map[]; 527 extern const struct pmc_bit_map lnl_d3_status_2_map[]; 528 extern const struct pmc_bit_map lnl_d3_status_3_map[]; 529 extern const struct pmc_bit_map lnl_vnn_req_status_0_map[]; 530 extern const struct pmc_bit_map lnl_vnn_req_status_1_map[]; 531 extern const struct pmc_bit_map lnl_vnn_req_status_2_map[]; 532 extern const struct pmc_bit_map lnl_vnn_req_status_3_map[]; 533 extern const struct pmc_bit_map lnl_vnn_misc_status_map[]; 534 extern const struct pmc_bit_map *lnl_lpm_maps[]; 535 extern const struct pmc_bit_map lnl_pfear_map[]; 536 extern const struct pmc_bit_map *ext_lnl_pfear_map[]; 537 538 /* ARL */ 539 extern const struct pmc_bit_map arl_socs_ltr_show_map[]; 540 extern const struct pmc_bit_map arl_socs_clocksource_status_map[]; 541 extern const struct pmc_bit_map arl_socs_power_gating_status_0_map[]; 542 extern const struct pmc_bit_map arl_socs_power_gating_status_1_map[]; 543 extern const struct pmc_bit_map arl_socs_power_gating_status_2_map[]; 544 extern const struct pmc_bit_map arl_socs_d3_status_2_map[]; 545 extern const struct pmc_bit_map arl_socs_d3_status_3_map[]; 546 extern const struct pmc_bit_map arl_socs_vnn_req_status_3_map[]; 547 extern const struct pmc_bit_map *arl_socs_lpm_maps[]; 548 extern const struct pmc_bit_map arl_socs_pfear_map[]; 549 extern const struct pmc_bit_map *ext_arl_socs_pfear_map[]; 550 extern const struct pmc_reg_map arl_socs_reg_map; 551 extern const struct pmc_bit_map arl_pchs_ltr_show_map[]; 552 extern const struct pmc_bit_map arl_pchs_clocksource_status_map[]; 553 extern const struct pmc_bit_map arl_pchs_power_gating_status_0_map[]; 554 extern const struct pmc_bit_map arl_pchs_power_gating_status_1_map[]; 555 extern const struct pmc_bit_map arl_pchs_power_gating_status_2_map[]; 556 extern const struct pmc_bit_map arl_pchs_d3_status_0_map[]; 557 extern const struct pmc_bit_map arl_pchs_d3_status_1_map[]; 558 extern const struct pmc_bit_map arl_pchs_d3_status_2_map[]; 559 extern const struct pmc_bit_map arl_pchs_d3_status_3_map[]; 560 extern const struct pmc_bit_map arl_pchs_vnn_req_status_0_map[]; 561 extern const struct pmc_bit_map arl_pchs_vnn_req_status_1_map[]; 562 extern const struct pmc_bit_map arl_pchs_vnn_req_status_2_map[]; 563 extern const struct pmc_bit_map arl_pchs_vnn_req_status_3_map[]; 564 extern const struct pmc_bit_map arl_pchs_vnn_misc_status_map[]; 565 extern const struct pmc_bit_map arl_pchs_signal_status_map[]; 566 extern const struct pmc_bit_map *arl_pchs_lpm_maps[]; 567 extern const struct pmc_reg_map arl_pchs_reg_map; 568 569 extern void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev); 570 extern int pmc_core_ssram_get_lpm_reqs(struct pmc_dev *pmcdev); 571 int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value, int ignore); 572 573 int pmc_core_resume_common(struct pmc_dev *pmcdev); 574 int get_primary_reg_base(struct pmc *pmc); 575 extern void pmc_core_get_low_power_modes(struct pmc_dev *pmcdev); 576 extern void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, u32 guid); 577 extern void pmc_core_set_device_d3(unsigned int device); 578 579 extern int pmc_core_ssram_init(struct pmc_dev *pmcdev, int func); 580 581 int spt_core_init(struct pmc_dev *pmcdev); 582 int cnp_core_init(struct pmc_dev *pmcdev); 583 int icl_core_init(struct pmc_dev *pmcdev); 584 int tgl_core_init(struct pmc_dev *pmcdev); 585 int tgl_l_core_init(struct pmc_dev *pmcdev); 586 int tgl_core_generic_init(struct pmc_dev *pmcdev, int pch_tp); 587 int adl_core_init(struct pmc_dev *pmcdev); 588 int mtl_core_init(struct pmc_dev *pmcdev); 589 int arl_core_init(struct pmc_dev *pmcdev); 590 int lnl_core_init(struct pmc_dev *pmcdev); 591 592 void cnl_suspend(struct pmc_dev *pmcdev); 593 int cnl_resume(struct pmc_dev *pmcdev); 594 595 #define pmc_for_each_mode(i, mode, pmcdev) \ 596 for (i = 0, mode = pmcdev->lpm_en_modes[i]; \ 597 i < pmcdev->num_lpm_modes; \ 598 i++, mode = pmcdev->lpm_en_modes[i]) 599 600 #define DEFINE_PMC_CORE_ATTR_WRITE(__name) \ 601 static int __name ## _open(struct inode *inode, struct file *file) \ 602 { \ 603 return single_open(file, __name ## _show, inode->i_private); \ 604 } \ 605 \ 606 static const struct file_operations __name ## _fops = { \ 607 .owner = THIS_MODULE, \ 608 .open = __name ## _open, \ 609 .read = seq_read, \ 610 .write = __name ## _write, \ 611 .release = single_release, \ 612 } 613 614 #endif /* PMC_CORE_H */ 615