1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* 3 * Mellanox platform driver 4 * 5 * Copyright (C) 2016-2018 Mellanox Technologies 6 * Copyright (C) 2016-2018 Vadim Pasternak <vadimp@mellanox.com> 7 */ 8 9 #include <linux/device.h> 10 #include <linux/dmi.h> 11 #include <linux/i2c.h> 12 #include <linux/i2c-mux.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/platform_data/i2c-mux-reg.h> 17 #include <linux/platform_data/mlxreg.h> 18 #include <linux/regmap.h> 19 20 #define MLX_PLAT_DEVICE_NAME "mlxplat" 21 22 /* LPC bus IO offsets */ 23 #define MLXPLAT_CPLD_LPC_I2C_BASE_ADRR 0x2000 24 #define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500 25 #define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET 0x00 26 #define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET 0x01 27 #define MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET 0x02 28 #define MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET 0x03 29 #define MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET 0x04 30 #define MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET 0x05 31 #define MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET 0x06 32 #define MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET 0x07 33 #define MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET 0x08 34 #define MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET 0x09 35 #define MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET 0x0a 36 #define MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET 0x0b 37 #define MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET 0x19 38 #define MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET 0x1c 39 #define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d 40 #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e 41 #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0x1f 42 #define MLXPLAT_CPLD_LPC_REG_LED1_OFFSET 0x20 43 #define MLXPLAT_CPLD_LPC_REG_LED2_OFFSET 0x21 44 #define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22 45 #define MLXPLAT_CPLD_LPC_REG_LED4_OFFSET 0x23 46 #define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24 47 #define MLXPLAT_CPLD_LPC_REG_LED6_OFFSET 0x25 48 #define MLXPLAT_CPLD_LPC_REG_LED7_OFFSET 0x26 49 #define MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION 0x2a 50 #define MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET 0x2b 51 #define MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET 0x2d 52 #define MLXPLAT_CPLD_LPC_REG_GP0_OFFSET 0x2e 53 #define MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET 0x2f 54 #define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET 0x30 55 #define MLXPLAT_CPLD_LPC_REG_WP1_OFFSET 0x31 56 #define MLXPLAT_CPLD_LPC_REG_GP2_OFFSET 0x32 57 #define MLXPLAT_CPLD_LPC_REG_WP2_OFFSET 0x33 58 #define MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE 0x34 59 #define MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET 0x35 60 #define MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET 0x36 61 #define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET 0x37 62 #define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a 63 #define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b 64 #define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40 65 #define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41 66 #define MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET 0x42 67 #define MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET 0x43 68 #define MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET 0x44 69 #define MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET 0x45 70 #define MLXPLAT_CPLD_LPC_REG_GWP_OFFSET 0x4a 71 #define MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET 0x4b 72 #define MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET 0x4c 73 #define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50 74 #define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET 0x51 75 #define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET 0x52 76 #define MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET 0x53 77 #define MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET 0x54 78 #define MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET 0x55 79 #define MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET 0x56 80 #define MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET 0x57 81 #define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET 0x58 82 #define MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET 0x59 83 #define MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET 0x5a 84 #define MLXPLAT_CPLD_LPC_REG_PWR_OFFSET 0x64 85 #define MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET 0x65 86 #define MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET 0x66 87 #define MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET 0x70 88 #define MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET 0x71 89 #define MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET 0x72 90 #define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88 91 #define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89 92 #define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a 93 #define MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET 0x9a 94 #define MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET 0x9b 95 #define MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET 0x9c 96 #define MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET 0x9d 97 #define MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET 0x9e 98 #define MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET 0x9f 99 #define MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET 0xa0 100 #define MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET 0xa1 101 #define MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET 0xa2 102 #define MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET 0xa3 103 #define MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET 0xa4 104 #define MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET 0xa5 105 #define MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET 0xa6 106 #define MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET 0xa7 107 #define MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET 0xa8 108 #define MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET 0xa9 109 #define MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET 0xaa 110 #define MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET 0xab 111 #define MLXPLAT_CPLD_LPC_REG_LC_PWR_ON 0xb2 112 #define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET 0xc7 113 #define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET 0xc8 114 #define MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET 0xc9 115 #define MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET 0xcb 116 #define MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET 0xcd 117 #define MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET 0xce 118 #define MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET 0xcf 119 #define MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET 0xd1 120 #define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET 0xd2 121 #define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET 0xd3 122 #define MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET 0xde 123 #define MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET 0xdf 124 #define MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET 0xe0 125 #define MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET 0xe1 126 #define MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET 0xe2 127 #define MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET 0xe3 128 #define MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET 0xe4 129 #define MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET 0xe5 130 #define MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET 0xe6 131 #define MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET 0xe7 132 #define MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET 0xe8 133 #define MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET 0xe9 134 #define MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET 0xea 135 #define MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET 0xeb 136 #define MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET 0xec 137 #define MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET 0xed 138 #define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0xee 139 #define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0xef 140 #define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0xf0 141 #define MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET 0xf1 142 #define MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET 0xf2 143 #define MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET 0xf3 144 #define MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET 0xf4 145 #define MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET 0xf5 146 #define MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET 0xf6 147 #define MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET 0xf7 148 #define MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET 0xf8 149 #define MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET 0xf9 150 #define MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET 0xfa 151 #define MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET 0xfb 152 #define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0xfc 153 #define MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET 0xfd 154 #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100 155 #define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb 156 #define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda 157 #define MLXPLAT_CPLD_LPC_I2C_CH3_OFF 0xdc 158 #define MLXPLAT_CPLD_LPC_I2C_CH4_OFF 0xdd 159 160 #define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL 161 #define MLXPLAT_CPLD_LPC_REG1 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 162 MLXPLAT_CPLD_LPC_I2C_CH1_OFF) | \ 163 MLXPLAT_CPLD_LPC_PIO_OFFSET) 164 #define MLXPLAT_CPLD_LPC_REG2 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 165 MLXPLAT_CPLD_LPC_I2C_CH2_OFF) | \ 166 MLXPLAT_CPLD_LPC_PIO_OFFSET) 167 #define MLXPLAT_CPLD_LPC_REG3 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 168 MLXPLAT_CPLD_LPC_I2C_CH3_OFF) | \ 169 MLXPLAT_CPLD_LPC_PIO_OFFSET) 170 #define MLXPLAT_CPLD_LPC_REG4 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 171 MLXPLAT_CPLD_LPC_I2C_CH4_OFF) | \ 172 MLXPLAT_CPLD_LPC_PIO_OFFSET) 173 174 /* Masks for aggregation, psu, pwr and fan event in CPLD related registers. */ 175 #define MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF 0x04 176 #define MLXPLAT_CPLD_AGGR_PSU_MASK_DEF 0x08 177 #define MLXPLAT_CPLD_AGGR_PWR_MASK_DEF 0x08 178 #define MLXPLAT_CPLD_AGGR_FAN_MASK_DEF 0x40 179 #define MLXPLAT_CPLD_AGGR_MASK_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \ 180 MLXPLAT_CPLD_AGGR_PSU_MASK_DEF | \ 181 MLXPLAT_CPLD_AGGR_FAN_MASK_DEF) 182 #define MLXPLAT_CPLD_AGGR_ASIC_MASK_NG 0x01 183 #define MLXPLAT_CPLD_AGGR_MASK_NG_DEF 0x04 184 #define MLXPLAT_CPLD_AGGR_MASK_COMEX BIT(0) 185 #define MLXPLAT_CPLD_AGGR_MASK_LC BIT(3) 186 #define MLXPLAT_CPLD_AGGR_MASK_MODULAR (MLXPLAT_CPLD_AGGR_MASK_NG_DEF | \ 187 MLXPLAT_CPLD_AGGR_MASK_COMEX | \ 188 MLXPLAT_CPLD_AGGR_MASK_LC) 189 #define MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT BIT(0) 190 #define MLXPLAT_CPLD_AGGR_MASK_LC_RDY BIT(1) 191 #define MLXPLAT_CPLD_AGGR_MASK_LC_PG BIT(2) 192 #define MLXPLAT_CPLD_AGGR_MASK_LC_SCRD BIT(3) 193 #define MLXPLAT_CPLD_AGGR_MASK_LC_SYNC BIT(4) 194 #define MLXPLAT_CPLD_AGGR_MASK_LC_ACT BIT(5) 195 #define MLXPLAT_CPLD_AGGR_MASK_LC_SDWN BIT(6) 196 #define MLXPLAT_CPLD_AGGR_MASK_LC_LOW (MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT | \ 197 MLXPLAT_CPLD_AGGR_MASK_LC_RDY | \ 198 MLXPLAT_CPLD_AGGR_MASK_LC_PG | \ 199 MLXPLAT_CPLD_AGGR_MASK_LC_SCRD | \ 200 MLXPLAT_CPLD_AGGR_MASK_LC_SYNC | \ 201 MLXPLAT_CPLD_AGGR_MASK_LC_ACT | \ 202 MLXPLAT_CPLD_AGGR_MASK_LC_SDWN) 203 #define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc1 204 #define MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2 BIT(2) 205 #define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6) 206 #define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0) 207 #define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0) 208 #define MLXPLAT_CPLD_PSU_EXT_MASK GENMASK(3, 0) 209 #define MLXPLAT_CPLD_PWR_EXT_MASK GENMASK(3, 0) 210 #define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0) 211 #define MLXPLAT_CPLD_ASIC_MASK GENMASK(1, 0) 212 #define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(6, 0) 213 #define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4) 214 #define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0) 215 #define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4) 216 #define MLXPLAT_CPLD_GWP_MASK GENMASK(0, 0) 217 #define MLXPLAT_CPLD_I2C_CAP_BIT 0x04 218 #define MLXPLAT_CPLD_I2C_CAP_MASK GENMASK(5, MLXPLAT_CPLD_I2C_CAP_BIT) 219 220 /* Masks for aggregation for comex carriers */ 221 #define MLXPLAT_CPLD_AGGR_MASK_CARRIER BIT(1) 222 #define MLXPLAT_CPLD_AGGR_MASK_CARR_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \ 223 MLXPLAT_CPLD_AGGR_MASK_CARRIER) 224 #define MLXPLAT_CPLD_LOW_AGGRCX_MASK 0xc1 225 226 /* Masks for aggregation for modular systems */ 227 #define MLXPLAT_CPLD_LPC_LC_MASK GENMASK(7, 0) 228 229 /* Default I2C parent bus number */ 230 #define MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR 1 231 232 /* Maximum number of possible physical buses equipped on system */ 233 #define MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM 16 234 #define MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM 24 235 236 /* Number of channels in group */ 237 #define MLXPLAT_CPLD_GRP_CHNL_NUM 8 238 239 /* Start channel numbers */ 240 #define MLXPLAT_CPLD_CH1 2 241 #define MLXPLAT_CPLD_CH2 10 242 #define MLXPLAT_CPLD_CH3 18 243 #define MLXPLAT_CPLD_CH2_ETH_MODULAR 3 244 #define MLXPLAT_CPLD_CH3_ETH_MODULAR 43 245 #define MLXPLAT_CPLD_CH4_ETH_MODULAR 51 246 247 /* Number of LPC attached MUX platform devices */ 248 #define MLXPLAT_CPLD_LPC_MUX_DEVS 4 249 250 /* Hotplug devices adapter numbers */ 251 #define MLXPLAT_CPLD_NR_NONE -1 252 #define MLXPLAT_CPLD_PSU_DEFAULT_NR 10 253 #define MLXPLAT_CPLD_PSU_MSNXXXX_NR 4 254 #define MLXPLAT_CPLD_FAN1_DEFAULT_NR 11 255 #define MLXPLAT_CPLD_FAN2_DEFAULT_NR 12 256 #define MLXPLAT_CPLD_FAN3_DEFAULT_NR 13 257 #define MLXPLAT_CPLD_FAN4_DEFAULT_NR 14 258 #define MLXPLAT_CPLD_NR_ASIC 3 259 #define MLXPLAT_CPLD_NR_LC_BASE 34 260 261 #define MLXPLAT_CPLD_NR_LC_SET(nr) (MLXPLAT_CPLD_NR_LC_BASE + (nr)) 262 #define MLXPLAT_CPLD_LC_ADDR 0x32 263 264 /* Masks and default values for watchdogs */ 265 #define MLXPLAT_CPLD_WD1_CLEAR_MASK GENMASK(7, 1) 266 #define MLXPLAT_CPLD_WD2_CLEAR_MASK (GENMASK(7, 0) & ~BIT(1)) 267 268 #define MLXPLAT_CPLD_WD_TYPE1_TO_MASK GENMASK(7, 4) 269 #define MLXPLAT_CPLD_WD_TYPE2_TO_MASK 0 270 #define MLXPLAT_CPLD_WD_RESET_ACT_MASK GENMASK(7, 1) 271 #define MLXPLAT_CPLD_WD_FAN_ACT_MASK (GENMASK(7, 0) & ~BIT(4)) 272 #define MLXPLAT_CPLD_WD_COUNT_ACT_MASK (GENMASK(7, 0) & ~BIT(7)) 273 #define MLXPLAT_CPLD_WD_CPBLTY_MASK (GENMASK(7, 0) & ~BIT(6)) 274 #define MLXPLAT_CPLD_WD_DFLT_TIMEOUT 30 275 #define MLXPLAT_CPLD_WD3_DFLT_TIMEOUT 600 276 #define MLXPLAT_CPLD_WD_MAX_DEVS 2 277 278 #define MLXPLAT_CPLD_LPC_SYSIRQ 17 279 280 /* Minimum power required for turning on Ethernet modular system (WATT) */ 281 #define MLXPLAT_CPLD_ETH_MODULAR_PWR_MIN 50 282 283 /* mlxplat_priv - platform private data 284 * @pdev_i2c - i2c controller platform device 285 * @pdev_mux - array of mux platform devices 286 * @pdev_hotplug - hotplug platform devices 287 * @pdev_led - led platform devices 288 * @pdev_io_regs - register access platform devices 289 * @pdev_fan - FAN platform devices 290 * @pdev_wd - array of watchdog platform devices 291 * @regmap: device register map 292 */ 293 struct mlxplat_priv { 294 struct platform_device *pdev_i2c; 295 struct platform_device *pdev_mux[MLXPLAT_CPLD_LPC_MUX_DEVS]; 296 struct platform_device *pdev_hotplug; 297 struct platform_device *pdev_led; 298 struct platform_device *pdev_io_regs; 299 struct platform_device *pdev_fan; 300 struct platform_device *pdev_wd[MLXPLAT_CPLD_WD_MAX_DEVS]; 301 void *regmap; 302 }; 303 304 /* Regions for LPC I2C controller and LPC base register space */ 305 static const struct resource mlxplat_lpc_resources[] = { 306 [0] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_I2C_BASE_ADRR, 307 MLXPLAT_CPLD_LPC_IO_RANGE, 308 "mlxplat_cpld_lpc_i2c_ctrl", IORESOURCE_IO), 309 [1] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_REG_BASE_ADRR, 310 MLXPLAT_CPLD_LPC_IO_RANGE, 311 "mlxplat_cpld_lpc_regs", 312 IORESOURCE_IO), 313 }; 314 315 /* Platform i2c next generation systems data */ 316 static struct mlxreg_core_data mlxplat_mlxcpld_i2c_ng_items_data[] = { 317 { 318 .reg = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 319 .mask = MLXPLAT_CPLD_I2C_CAP_MASK, 320 .bit = MLXPLAT_CPLD_I2C_CAP_BIT, 321 }, 322 }; 323 324 static struct mlxreg_core_item mlxplat_mlxcpld_i2c_ng_items[] = { 325 { 326 .data = mlxplat_mlxcpld_i2c_ng_items_data, 327 }, 328 }; 329 330 /* Platform next generation systems i2c data */ 331 static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_i2c_ng_data = { 332 .items = mlxplat_mlxcpld_i2c_ng_items, 333 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 334 .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX, 335 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET, 336 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_I2C, 337 }; 338 339 /* Platform default channels */ 340 static const int mlxplat_default_channels[][MLXPLAT_CPLD_GRP_CHNL_NUM] = { 341 { 342 MLXPLAT_CPLD_CH1, MLXPLAT_CPLD_CH1 + 1, MLXPLAT_CPLD_CH1 + 2, 343 MLXPLAT_CPLD_CH1 + 3, MLXPLAT_CPLD_CH1 + 4, MLXPLAT_CPLD_CH1 + 344 5, MLXPLAT_CPLD_CH1 + 6, MLXPLAT_CPLD_CH1 + 7 345 }, 346 { 347 MLXPLAT_CPLD_CH2, MLXPLAT_CPLD_CH2 + 1, MLXPLAT_CPLD_CH2 + 2, 348 MLXPLAT_CPLD_CH2 + 3, MLXPLAT_CPLD_CH2 + 4, MLXPLAT_CPLD_CH2 + 349 5, MLXPLAT_CPLD_CH2 + 6, MLXPLAT_CPLD_CH2 + 7 350 }, 351 }; 352 353 /* Platform channels for MSN21xx system family */ 354 static const int mlxplat_msn21xx_channels[] = { 1, 2, 3, 4, 5, 6, 7, 8 }; 355 356 /* Platform mux data */ 357 static struct i2c_mux_reg_platform_data mlxplat_default_mux_data[] = { 358 { 359 .parent = 1, 360 .base_nr = MLXPLAT_CPLD_CH1, 361 .write_only = 1, 362 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 363 .reg_size = 1, 364 .idle_in_use = 1, 365 }, 366 { 367 .parent = 1, 368 .base_nr = MLXPLAT_CPLD_CH2, 369 .write_only = 1, 370 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 371 .reg_size = 1, 372 .idle_in_use = 1, 373 }, 374 375 }; 376 377 /* Platform mux configuration variables */ 378 static int mlxplat_max_adap_num; 379 static int mlxplat_mux_num; 380 static struct i2c_mux_reg_platform_data *mlxplat_mux_data; 381 382 /* Platform extended mux data */ 383 static struct i2c_mux_reg_platform_data mlxplat_extended_mux_data[] = { 384 { 385 .parent = 1, 386 .base_nr = MLXPLAT_CPLD_CH1, 387 .write_only = 1, 388 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 389 .reg_size = 1, 390 .idle_in_use = 1, 391 }, 392 { 393 .parent = 1, 394 .base_nr = MLXPLAT_CPLD_CH2, 395 .write_only = 1, 396 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG3, 397 .reg_size = 1, 398 .idle_in_use = 1, 399 }, 400 { 401 .parent = 1, 402 .base_nr = MLXPLAT_CPLD_CH3, 403 .write_only = 1, 404 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 405 .reg_size = 1, 406 .idle_in_use = 1, 407 }, 408 409 }; 410 411 /* Platform channels for modular system family */ 412 static const int mlxplat_modular_upper_channel[] = { 1 }; 413 static const int mlxplat_modular_channels[] = { 414 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 415 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 416 38, 39, 40 417 }; 418 419 /* Platform modular mux data */ 420 static struct i2c_mux_reg_platform_data mlxplat_modular_mux_data[] = { 421 { 422 .parent = 1, 423 .base_nr = MLXPLAT_CPLD_CH1, 424 .write_only = 1, 425 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG4, 426 .reg_size = 1, 427 .idle_in_use = 1, 428 .values = mlxplat_modular_upper_channel, 429 .n_values = ARRAY_SIZE(mlxplat_modular_upper_channel), 430 }, 431 { 432 .parent = 1, 433 .base_nr = MLXPLAT_CPLD_CH2_ETH_MODULAR, 434 .write_only = 1, 435 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 436 .reg_size = 1, 437 .idle_in_use = 1, 438 .values = mlxplat_modular_channels, 439 .n_values = ARRAY_SIZE(mlxplat_modular_channels), 440 }, 441 { 442 .parent = MLXPLAT_CPLD_CH1, 443 .base_nr = MLXPLAT_CPLD_CH3_ETH_MODULAR, 444 .write_only = 1, 445 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG3, 446 .reg_size = 1, 447 .idle_in_use = 1, 448 .values = mlxplat_msn21xx_channels, 449 .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), 450 }, 451 { 452 .parent = 1, 453 .base_nr = MLXPLAT_CPLD_CH4_ETH_MODULAR, 454 .write_only = 1, 455 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 456 .reg_size = 1, 457 .idle_in_use = 1, 458 .values = mlxplat_msn21xx_channels, 459 .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), 460 }, 461 }; 462 463 /* Platform hotplug devices */ 464 static struct i2c_board_info mlxplat_mlxcpld_pwr[] = { 465 { 466 I2C_BOARD_INFO("dps460", 0x59), 467 }, 468 { 469 I2C_BOARD_INFO("dps460", 0x58), 470 }, 471 }; 472 473 static struct i2c_board_info mlxplat_mlxcpld_ext_pwr[] = { 474 { 475 I2C_BOARD_INFO("dps460", 0x5b), 476 }, 477 { 478 I2C_BOARD_INFO("dps460", 0x5a), 479 }, 480 }; 481 482 static struct i2c_board_info mlxplat_mlxcpld_fan[] = { 483 { 484 I2C_BOARD_INFO("24c32", 0x50), 485 }, 486 { 487 I2C_BOARD_INFO("24c32", 0x50), 488 }, 489 { 490 I2C_BOARD_INFO("24c32", 0x50), 491 }, 492 { 493 I2C_BOARD_INFO("24c32", 0x50), 494 }, 495 }; 496 497 /* Platform hotplug comex carrier system family data */ 498 static struct mlxreg_core_data mlxplat_mlxcpld_comex_psu_items_data[] = { 499 { 500 .label = "psu1", 501 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 502 .mask = BIT(0), 503 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 504 }, 505 { 506 .label = "psu2", 507 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 508 .mask = BIT(1), 509 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 510 }, 511 }; 512 513 /* Platform hotplug default data */ 514 static struct mlxreg_core_data mlxplat_mlxcpld_default_psu_items_data[] = { 515 { 516 .label = "psu1", 517 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 518 .mask = BIT(0), 519 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 520 }, 521 { 522 .label = "psu2", 523 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 524 .mask = BIT(1), 525 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 526 }, 527 }; 528 529 static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_items_data[] = { 530 { 531 .label = "pwr1", 532 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 533 .mask = BIT(0), 534 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 535 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR, 536 }, 537 { 538 .label = "pwr2", 539 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 540 .mask = BIT(1), 541 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 542 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR, 543 }, 544 }; 545 546 static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_wc_items_data[] = { 547 { 548 .label = "pwr1", 549 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 550 .mask = BIT(0), 551 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 552 }, 553 { 554 .label = "pwr2", 555 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 556 .mask = BIT(1), 557 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 558 }, 559 }; 560 561 static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_items_data[] = { 562 { 563 .label = "fan1", 564 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 565 .mask = BIT(0), 566 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[0], 567 .hpdev.nr = MLXPLAT_CPLD_FAN1_DEFAULT_NR, 568 }, 569 { 570 .label = "fan2", 571 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 572 .mask = BIT(1), 573 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[1], 574 .hpdev.nr = MLXPLAT_CPLD_FAN2_DEFAULT_NR, 575 }, 576 { 577 .label = "fan3", 578 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 579 .mask = BIT(2), 580 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[2], 581 .hpdev.nr = MLXPLAT_CPLD_FAN3_DEFAULT_NR, 582 }, 583 { 584 .label = "fan4", 585 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 586 .mask = BIT(3), 587 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[3], 588 .hpdev.nr = MLXPLAT_CPLD_FAN4_DEFAULT_NR, 589 }, 590 }; 591 592 static struct mlxreg_core_data mlxplat_mlxcpld_default_asic_items_data[] = { 593 { 594 .label = "asic1", 595 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 596 .mask = MLXPLAT_CPLD_ASIC_MASK, 597 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 598 }, 599 }; 600 601 static struct mlxreg_core_data mlxplat_mlxcpld_default_asic2_items_data[] = { 602 { 603 .label = "asic2", 604 .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, 605 .mask = MLXPLAT_CPLD_ASIC_MASK, 606 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 607 }, 608 }; 609 610 static struct mlxreg_core_item mlxplat_mlxcpld_default_items[] = { 611 { 612 .data = mlxplat_mlxcpld_default_psu_items_data, 613 .aggr_mask = MLXPLAT_CPLD_AGGR_PSU_MASK_DEF, 614 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 615 .mask = MLXPLAT_CPLD_PSU_MASK, 616 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data), 617 .inversed = 1, 618 .health = false, 619 }, 620 { 621 .data = mlxplat_mlxcpld_default_pwr_items_data, 622 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 623 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 624 .mask = MLXPLAT_CPLD_PWR_MASK, 625 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data), 626 .inversed = 0, 627 .health = false, 628 }, 629 { 630 .data = mlxplat_mlxcpld_default_fan_items_data, 631 .aggr_mask = MLXPLAT_CPLD_AGGR_FAN_MASK_DEF, 632 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 633 .mask = MLXPLAT_CPLD_FAN_MASK, 634 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_items_data), 635 .inversed = 1, 636 .health = false, 637 }, 638 { 639 .data = mlxplat_mlxcpld_default_asic_items_data, 640 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 641 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 642 .mask = MLXPLAT_CPLD_ASIC_MASK, 643 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 644 .inversed = 0, 645 .health = true, 646 }, 647 }; 648 649 static struct mlxreg_core_item mlxplat_mlxcpld_comex_items[] = { 650 { 651 .data = mlxplat_mlxcpld_comex_psu_items_data, 652 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 653 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 654 .mask = MLXPLAT_CPLD_PSU_MASK, 655 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data), 656 .inversed = 1, 657 .health = false, 658 }, 659 { 660 .data = mlxplat_mlxcpld_default_pwr_items_data, 661 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 662 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 663 .mask = MLXPLAT_CPLD_PWR_MASK, 664 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data), 665 .inversed = 0, 666 .health = false, 667 }, 668 { 669 .data = mlxplat_mlxcpld_default_fan_items_data, 670 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 671 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 672 .mask = MLXPLAT_CPLD_FAN_MASK, 673 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_items_data), 674 .inversed = 1, 675 .health = false, 676 }, 677 { 678 .data = mlxplat_mlxcpld_default_asic_items_data, 679 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 680 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 681 .mask = MLXPLAT_CPLD_ASIC_MASK, 682 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 683 .inversed = 0, 684 .health = true, 685 }, 686 }; 687 688 static 689 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_data = { 690 .items = mlxplat_mlxcpld_default_items, 691 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_items), 692 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 693 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 694 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 695 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 696 }; 697 698 static struct mlxreg_core_item mlxplat_mlxcpld_default_wc_items[] = { 699 { 700 .data = mlxplat_mlxcpld_comex_psu_items_data, 701 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 702 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 703 .mask = MLXPLAT_CPLD_PSU_MASK, 704 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data), 705 .inversed = 1, 706 .health = false, 707 }, 708 { 709 .data = mlxplat_mlxcpld_default_pwr_wc_items_data, 710 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 711 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 712 .mask = MLXPLAT_CPLD_PWR_MASK, 713 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data), 714 .inversed = 0, 715 .health = false, 716 }, 717 { 718 .data = mlxplat_mlxcpld_default_asic_items_data, 719 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 720 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 721 .mask = MLXPLAT_CPLD_ASIC_MASK, 722 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 723 .inversed = 0, 724 .health = true, 725 }, 726 }; 727 728 static 729 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_wc_data = { 730 .items = mlxplat_mlxcpld_default_wc_items, 731 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_wc_items), 732 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 733 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 734 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 735 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 736 }; 737 738 static 739 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_comex_data = { 740 .items = mlxplat_mlxcpld_comex_items, 741 .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_items), 742 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 743 .mask = MLXPLAT_CPLD_AGGR_MASK_CARR_DEF, 744 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET, 745 .mask_low = MLXPLAT_CPLD_LOW_AGGRCX_MASK, 746 }; 747 748 static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_pwr_items_data[] = { 749 { 750 .label = "pwr1", 751 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 752 .mask = BIT(0), 753 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 754 }, 755 { 756 .label = "pwr2", 757 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 758 .mask = BIT(1), 759 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 760 }, 761 }; 762 763 /* Platform hotplug MSN21xx system family data */ 764 static struct mlxreg_core_item mlxplat_mlxcpld_msn21xx_items[] = { 765 { 766 .data = mlxplat_mlxcpld_msn21xx_pwr_items_data, 767 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 768 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 769 .mask = MLXPLAT_CPLD_PWR_MASK, 770 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_pwr_items_data), 771 .inversed = 0, 772 .health = false, 773 }, 774 { 775 .data = mlxplat_mlxcpld_default_asic_items_data, 776 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 777 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 778 .mask = MLXPLAT_CPLD_ASIC_MASK, 779 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 780 .inversed = 0, 781 .health = true, 782 }, 783 }; 784 785 static 786 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn21xx_data = { 787 .items = mlxplat_mlxcpld_msn21xx_items, 788 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_items), 789 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 790 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 791 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 792 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 793 }; 794 795 /* Platform hotplug msn274x system family data */ 796 static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_psu_items_data[] = { 797 { 798 .label = "psu1", 799 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 800 .mask = BIT(0), 801 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 802 }, 803 { 804 .label = "psu2", 805 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 806 .mask = BIT(1), 807 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 808 }, 809 }; 810 811 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_pwr_items_data[] = { 812 { 813 .label = "pwr1", 814 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 815 .mask = BIT(0), 816 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 817 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 818 }, 819 { 820 .label = "pwr2", 821 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 822 .mask = BIT(1), 823 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 824 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 825 }, 826 }; 827 828 static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_fan_items_data[] = { 829 { 830 .label = "fan1", 831 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 832 .mask = BIT(0), 833 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 834 }, 835 { 836 .label = "fan2", 837 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 838 .mask = BIT(1), 839 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 840 }, 841 { 842 .label = "fan3", 843 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 844 .mask = BIT(2), 845 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 846 }, 847 { 848 .label = "fan4", 849 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 850 .mask = BIT(3), 851 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 852 }, 853 }; 854 855 static struct mlxreg_core_item mlxplat_mlxcpld_msn274x_items[] = { 856 { 857 .data = mlxplat_mlxcpld_msn274x_psu_items_data, 858 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 859 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 860 .mask = MLXPLAT_CPLD_PSU_MASK, 861 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_psu_items_data), 862 .inversed = 1, 863 .health = false, 864 }, 865 { 866 .data = mlxplat_mlxcpld_default_ng_pwr_items_data, 867 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 868 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 869 .mask = MLXPLAT_CPLD_PWR_MASK, 870 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_pwr_items_data), 871 .inversed = 0, 872 .health = false, 873 }, 874 { 875 .data = mlxplat_mlxcpld_msn274x_fan_items_data, 876 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 877 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 878 .mask = MLXPLAT_CPLD_FAN_MASK, 879 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_fan_items_data), 880 .inversed = 1, 881 .health = false, 882 }, 883 { 884 .data = mlxplat_mlxcpld_default_asic_items_data, 885 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 886 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 887 .mask = MLXPLAT_CPLD_ASIC_MASK, 888 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 889 .inversed = 0, 890 .health = true, 891 }, 892 }; 893 894 static 895 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn274x_data = { 896 .items = mlxplat_mlxcpld_msn274x_items, 897 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_items), 898 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 899 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 900 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 901 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 902 }; 903 904 /* Platform hotplug MSN201x system family data */ 905 static struct mlxreg_core_data mlxplat_mlxcpld_msn201x_pwr_items_data[] = { 906 { 907 .label = "pwr1", 908 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 909 .mask = BIT(0), 910 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 911 }, 912 { 913 .label = "pwr2", 914 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 915 .mask = BIT(1), 916 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 917 }, 918 }; 919 920 static struct mlxreg_core_item mlxplat_mlxcpld_msn201x_items[] = { 921 { 922 .data = mlxplat_mlxcpld_msn201x_pwr_items_data, 923 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 924 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 925 .mask = MLXPLAT_CPLD_PWR_MASK, 926 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_pwr_items_data), 927 .inversed = 0, 928 .health = false, 929 }, 930 { 931 .data = mlxplat_mlxcpld_default_asic_items_data, 932 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 933 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 934 .mask = MLXPLAT_CPLD_ASIC_MASK, 935 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 936 .inversed = 0, 937 .health = true, 938 }, 939 }; 940 941 static 942 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn201x_data = { 943 .items = mlxplat_mlxcpld_msn201x_items, 944 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_items), 945 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 946 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 947 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 948 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 949 }; 950 951 /* Platform hotplug next generation system family data */ 952 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_psu_items_data[] = { 953 { 954 .label = "psu1", 955 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 956 .mask = BIT(0), 957 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 958 }, 959 { 960 .label = "psu2", 961 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 962 .mask = BIT(1), 963 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 964 }, 965 }; 966 967 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_fan_items_data[] = { 968 { 969 .label = "fan1", 970 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 971 .mask = BIT(0), 972 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 973 .bit = BIT(0), 974 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 975 }, 976 { 977 .label = "fan2", 978 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 979 .mask = BIT(1), 980 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 981 .bit = BIT(1), 982 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 983 }, 984 { 985 .label = "fan3", 986 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 987 .mask = BIT(2), 988 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 989 .bit = BIT(2), 990 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 991 }, 992 { 993 .label = "fan4", 994 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 995 .mask = BIT(3), 996 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 997 .bit = BIT(3), 998 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 999 }, 1000 { 1001 .label = "fan5", 1002 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1003 .mask = BIT(4), 1004 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1005 .bit = BIT(4), 1006 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1007 }, 1008 { 1009 .label = "fan6", 1010 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1011 .mask = BIT(5), 1012 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1013 .bit = BIT(5), 1014 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1015 }, 1016 { 1017 .label = "fan7", 1018 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1019 .mask = BIT(6), 1020 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1021 .bit = BIT(6), 1022 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1023 }, 1024 }; 1025 1026 static struct mlxreg_core_item mlxplat_mlxcpld_default_ng_items[] = { 1027 { 1028 .data = mlxplat_mlxcpld_default_ng_psu_items_data, 1029 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1030 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1031 .mask = MLXPLAT_CPLD_PSU_MASK, 1032 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_psu_items_data), 1033 .inversed = 1, 1034 .health = false, 1035 }, 1036 { 1037 .data = mlxplat_mlxcpld_default_ng_pwr_items_data, 1038 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1039 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1040 .mask = MLXPLAT_CPLD_PWR_MASK, 1041 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_pwr_items_data), 1042 .inversed = 0, 1043 .health = false, 1044 }, 1045 { 1046 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 1047 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1048 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1049 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 1050 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 1051 .inversed = 1, 1052 .health = false, 1053 }, 1054 { 1055 .data = mlxplat_mlxcpld_default_asic_items_data, 1056 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1057 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1058 .mask = MLXPLAT_CPLD_ASIC_MASK, 1059 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 1060 .inversed = 0, 1061 .health = true, 1062 }, 1063 }; 1064 1065 static 1066 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_ng_data = { 1067 .items = mlxplat_mlxcpld_default_ng_items, 1068 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_items), 1069 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1070 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 1071 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1072 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 1073 }; 1074 1075 /* Platform hotplug extended system family data */ 1076 static struct mlxreg_core_data mlxplat_mlxcpld_ext_psu_items_data[] = { 1077 { 1078 .label = "psu1", 1079 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1080 .mask = BIT(0), 1081 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1082 }, 1083 { 1084 .label = "psu2", 1085 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1086 .mask = BIT(1), 1087 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1088 }, 1089 { 1090 .label = "psu3", 1091 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1092 .mask = BIT(2), 1093 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1094 }, 1095 { 1096 .label = "psu4", 1097 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1098 .mask = BIT(3), 1099 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1100 }, 1101 }; 1102 1103 static struct mlxreg_core_data mlxplat_mlxcpld_ext_pwr_items_data[] = { 1104 { 1105 .label = "pwr1", 1106 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1107 .mask = BIT(0), 1108 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 1109 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1110 }, 1111 { 1112 .label = "pwr2", 1113 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1114 .mask = BIT(1), 1115 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 1116 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1117 }, 1118 { 1119 .label = "pwr3", 1120 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1121 .mask = BIT(2), 1122 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0], 1123 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1124 }, 1125 { 1126 .label = "pwr4", 1127 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1128 .mask = BIT(3), 1129 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1], 1130 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1131 }, 1132 }; 1133 1134 static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = { 1135 { 1136 .data = mlxplat_mlxcpld_ext_psu_items_data, 1137 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1138 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1139 .mask = MLXPLAT_CPLD_PSU_EXT_MASK, 1140 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 1141 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data), 1142 .inversed = 1, 1143 .health = false, 1144 }, 1145 { 1146 .data = mlxplat_mlxcpld_ext_pwr_items_data, 1147 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1148 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1149 .mask = MLXPLAT_CPLD_PWR_EXT_MASK, 1150 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 1151 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data), 1152 .inversed = 0, 1153 .health = false, 1154 }, 1155 { 1156 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 1157 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1158 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1159 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 1160 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 1161 .inversed = 1, 1162 .health = false, 1163 }, 1164 { 1165 .data = mlxplat_mlxcpld_default_asic_items_data, 1166 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1167 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1168 .mask = MLXPLAT_CPLD_ASIC_MASK, 1169 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 1170 .inversed = 0, 1171 .health = true, 1172 }, 1173 { 1174 .data = mlxplat_mlxcpld_default_asic2_items_data, 1175 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1176 .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, 1177 .mask = MLXPLAT_CPLD_ASIC_MASK, 1178 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic2_items_data), 1179 .inversed = 0, 1180 .health = true, 1181 } 1182 }; 1183 1184 static 1185 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = { 1186 .items = mlxplat_mlxcpld_ext_items, 1187 .counter = ARRAY_SIZE(mlxplat_mlxcpld_ext_items), 1188 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1189 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 1190 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1191 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2, 1192 }; 1193 1194 static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = { 1195 { 1196 .label = "pwr1", 1197 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1198 .mask = BIT(0), 1199 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 1200 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1201 }, 1202 { 1203 .label = "pwr2", 1204 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1205 .mask = BIT(1), 1206 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 1207 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1208 }, 1209 { 1210 .label = "pwr3", 1211 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1212 .mask = BIT(2), 1213 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0], 1214 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1215 }, 1216 { 1217 .label = "pwr4", 1218 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1219 .mask = BIT(3), 1220 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1], 1221 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1222 }, 1223 }; 1224 1225 static 1226 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_lc_act = { 1227 .irq = MLXPLAT_CPLD_LPC_SYSIRQ, 1228 }; 1229 1230 static struct mlxreg_core_data mlxplat_mlxcpld_modular_asic_items_data[] = { 1231 { 1232 .label = "asic1", 1233 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1234 .mask = MLXPLAT_CPLD_ASIC_MASK, 1235 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1236 }, 1237 }; 1238 1239 static struct i2c_board_info mlxplat_mlxcpld_lc_i2c_dev[] = { 1240 { 1241 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1242 .platform_data = &mlxplat_mlxcpld_lc_act, 1243 }, 1244 { 1245 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1246 .platform_data = &mlxplat_mlxcpld_lc_act, 1247 }, 1248 { 1249 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1250 .platform_data = &mlxplat_mlxcpld_lc_act, 1251 }, 1252 { 1253 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1254 .platform_data = &mlxplat_mlxcpld_lc_act, 1255 }, 1256 { 1257 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1258 .platform_data = &mlxplat_mlxcpld_lc_act, 1259 }, 1260 { 1261 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1262 .platform_data = &mlxplat_mlxcpld_lc_act, 1263 }, 1264 { 1265 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1266 .platform_data = &mlxplat_mlxcpld_lc_act, 1267 }, 1268 { 1269 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1270 .platform_data = &mlxplat_mlxcpld_lc_act, 1271 }, 1272 }; 1273 1274 static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_modular_lc_notifier[] = { 1275 { 1276 .identity = "lc1", 1277 }, 1278 { 1279 .identity = "lc2", 1280 }, 1281 { 1282 .identity = "lc3", 1283 }, 1284 { 1285 .identity = "lc4", 1286 }, 1287 { 1288 .identity = "lc5", 1289 }, 1290 { 1291 .identity = "lc6", 1292 }, 1293 { 1294 .identity = "lc7", 1295 }, 1296 { 1297 .identity = "lc8", 1298 }, 1299 }; 1300 1301 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pr_items_data[] = { 1302 { 1303 .label = "lc1_present", 1304 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1305 .mask = BIT(0), 1306 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1307 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1308 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1309 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1310 .slot = 1, 1311 }, 1312 { 1313 .label = "lc2_present", 1314 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1315 .mask = BIT(1), 1316 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1317 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1318 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1319 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1320 .slot = 2, 1321 }, 1322 { 1323 .label = "lc3_present", 1324 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1325 .mask = BIT(2), 1326 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1327 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1328 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1329 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1330 .slot = 3, 1331 }, 1332 { 1333 .label = "lc4_present", 1334 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1335 .mask = BIT(3), 1336 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1337 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1338 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1339 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1340 .slot = 4, 1341 }, 1342 { 1343 .label = "lc5_present", 1344 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1345 .mask = BIT(4), 1346 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1347 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1348 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1349 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1350 .slot = 5, 1351 }, 1352 { 1353 .label = "lc6_present", 1354 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1355 .mask = BIT(5), 1356 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1357 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1358 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1359 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1360 .slot = 6, 1361 }, 1362 { 1363 .label = "lc7_present", 1364 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1365 .mask = BIT(6), 1366 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1367 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1368 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1369 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1370 .slot = 7, 1371 }, 1372 { 1373 .label = "lc8_present", 1374 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1375 .mask = BIT(7), 1376 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1377 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1378 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1379 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1380 .slot = 8, 1381 }, 1382 }; 1383 1384 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ver_items_data[] = { 1385 { 1386 .label = "lc1_verified", 1387 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1388 .mask = BIT(0), 1389 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1390 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1391 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1392 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1393 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1394 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1395 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1396 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1397 .slot = 1, 1398 }, 1399 { 1400 .label = "lc2_verified", 1401 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1402 .mask = BIT(1), 1403 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1404 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1405 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1406 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1407 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1408 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1409 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1410 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1411 .slot = 2, 1412 }, 1413 { 1414 .label = "lc3_verified", 1415 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1416 .mask = BIT(2), 1417 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1418 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1419 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1420 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1421 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1422 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1423 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1424 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1425 .slot = 3, 1426 }, 1427 { 1428 .label = "lc4_verified", 1429 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1430 .mask = BIT(3), 1431 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1432 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1433 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1434 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1435 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1436 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1437 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1438 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1439 .slot = 4, 1440 }, 1441 { 1442 .label = "lc5_verified", 1443 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1444 .mask = BIT(4), 1445 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1446 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1447 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1448 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1449 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1450 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1451 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1452 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1453 .slot = 5, 1454 }, 1455 { 1456 .label = "lc6_verified", 1457 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1458 .mask = BIT(5), 1459 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1460 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1461 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1462 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1463 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1464 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1465 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1466 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1467 .slot = 6, 1468 }, 1469 { 1470 .label = "lc7_verified", 1471 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1472 .mask = BIT(6), 1473 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1474 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1475 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1476 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1477 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1478 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1479 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1480 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1481 .slot = 7, 1482 }, 1483 { 1484 .label = "lc8_verified", 1485 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1486 .mask = BIT(7), 1487 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1488 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1489 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1490 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1491 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1492 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1493 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1494 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1495 .slot = 8, 1496 }, 1497 }; 1498 1499 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pg_data[] = { 1500 { 1501 .label = "lc1_powered", 1502 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1503 .mask = BIT(0), 1504 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1505 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1506 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1507 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1508 .slot = 1, 1509 }, 1510 { 1511 .label = "lc2_powered", 1512 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1513 .mask = BIT(1), 1514 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1515 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1516 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1517 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1518 .slot = 2, 1519 }, 1520 { 1521 .label = "lc3_powered", 1522 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1523 .mask = BIT(2), 1524 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1525 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1526 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1527 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1528 .slot = 3, 1529 }, 1530 { 1531 .label = "lc4_powered", 1532 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1533 .mask = BIT(3), 1534 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1535 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1536 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1537 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1538 .slot = 4, 1539 }, 1540 { 1541 .label = "lc5_powered", 1542 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1543 .mask = BIT(4), 1544 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1545 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1546 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1547 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1548 .slot = 5, 1549 }, 1550 { 1551 .label = "lc6_powered", 1552 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1553 .mask = BIT(5), 1554 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1555 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1556 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1557 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1558 .slot = 6, 1559 }, 1560 { 1561 .label = "lc7_powered", 1562 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1563 .mask = BIT(6), 1564 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1565 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1566 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1567 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1568 .slot = 7, 1569 }, 1570 { 1571 .label = "lc8_powered", 1572 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1573 .mask = BIT(7), 1574 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1575 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1576 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1577 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1578 .slot = 8, 1579 }, 1580 }; 1581 1582 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ready_data[] = { 1583 { 1584 .label = "lc1_ready", 1585 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1586 .mask = BIT(0), 1587 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1588 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1589 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1590 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1591 .slot = 1, 1592 }, 1593 { 1594 .label = "lc2_ready", 1595 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1596 .mask = BIT(1), 1597 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1598 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1599 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1600 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1601 .slot = 2, 1602 }, 1603 { 1604 .label = "lc3_ready", 1605 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1606 .mask = BIT(2), 1607 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1608 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1609 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1610 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1611 .slot = 3, 1612 }, 1613 { 1614 .label = "lc4_ready", 1615 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1616 .mask = BIT(3), 1617 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1618 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1619 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1620 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1621 .slot = 4, 1622 }, 1623 { 1624 .label = "lc5_ready", 1625 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1626 .mask = BIT(4), 1627 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1628 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1629 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1630 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1631 .slot = 5, 1632 }, 1633 { 1634 .label = "lc6_ready", 1635 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1636 .mask = BIT(5), 1637 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1638 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1639 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1640 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1641 .slot = 6, 1642 }, 1643 { 1644 .label = "lc7_ready", 1645 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1646 .mask = BIT(6), 1647 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1648 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1649 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1650 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1651 .slot = 7, 1652 }, 1653 { 1654 .label = "lc8_ready", 1655 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1656 .mask = BIT(7), 1657 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1658 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1659 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1660 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1661 .slot = 8, 1662 }, 1663 }; 1664 1665 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_synced_data[] = { 1666 { 1667 .label = "lc1_synced", 1668 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1669 .mask = BIT(0), 1670 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1671 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1672 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1673 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1674 .slot = 1, 1675 }, 1676 { 1677 .label = "lc2_synced", 1678 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1679 .mask = BIT(1), 1680 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1681 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1682 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1683 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1684 .slot = 2, 1685 }, 1686 { 1687 .label = "lc3_synced", 1688 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1689 .mask = BIT(2), 1690 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1691 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1692 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1693 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1694 .slot = 3, 1695 }, 1696 { 1697 .label = "lc4_synced", 1698 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1699 .mask = BIT(3), 1700 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1701 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1702 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1703 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1704 .slot = 4, 1705 }, 1706 { 1707 .label = "lc5_synced", 1708 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1709 .mask = BIT(4), 1710 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1711 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1712 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1713 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1714 .slot = 5, 1715 }, 1716 { 1717 .label = "lc6_synced", 1718 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1719 .mask = BIT(5), 1720 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1721 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1722 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1723 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1724 .slot = 6, 1725 }, 1726 { 1727 .label = "lc7_synced", 1728 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1729 .mask = BIT(6), 1730 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1731 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1732 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1733 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1734 .slot = 7, 1735 }, 1736 { 1737 .label = "lc8_synced", 1738 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1739 .mask = BIT(7), 1740 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1741 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1742 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1743 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1744 .slot = 8, 1745 }, 1746 }; 1747 1748 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_act_data[] = { 1749 { 1750 .label = "lc1_active", 1751 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1752 .mask = BIT(0), 1753 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1754 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1755 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1756 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1757 .slot = 1, 1758 }, 1759 { 1760 .label = "lc2_active", 1761 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1762 .mask = BIT(1), 1763 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1764 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1765 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1766 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1767 .slot = 2, 1768 }, 1769 { 1770 .label = "lc3_active", 1771 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1772 .mask = BIT(2), 1773 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1774 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1775 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1776 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1777 .slot = 3, 1778 }, 1779 { 1780 .label = "lc4_active", 1781 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1782 .mask = BIT(3), 1783 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1784 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1785 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1786 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1787 .slot = 4, 1788 }, 1789 { 1790 .label = "lc5_active", 1791 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1792 .mask = BIT(4), 1793 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1794 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1795 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1796 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1797 .slot = 5, 1798 }, 1799 { 1800 .label = "lc6_active", 1801 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1802 .mask = BIT(5), 1803 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1804 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1805 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1806 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1807 .slot = 6, 1808 }, 1809 { 1810 .label = "lc7_active", 1811 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1812 .mask = BIT(6), 1813 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1814 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1815 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1816 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1817 .slot = 7, 1818 }, 1819 { 1820 .label = "lc8_active", 1821 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1822 .mask = BIT(7), 1823 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1824 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1825 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1826 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1827 .slot = 8, 1828 }, 1829 }; 1830 1831 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_sd_data[] = { 1832 { 1833 .label = "lc1_shutdown", 1834 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 1835 .mask = BIT(0), 1836 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1837 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1838 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1839 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1840 .slot = 1, 1841 }, 1842 { 1843 .label = "lc2_shutdown", 1844 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 1845 .mask = BIT(1), 1846 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1847 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1848 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1849 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1850 .slot = 2, 1851 }, 1852 { 1853 .label = "lc3_shutdown", 1854 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 1855 .mask = BIT(2), 1856 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1857 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1858 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1859 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1860 .slot = 3, 1861 }, 1862 { 1863 .label = "lc4_shutdown", 1864 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 1865 .mask = BIT(3), 1866 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1867 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1868 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1869 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1870 .slot = 4, 1871 }, 1872 { 1873 .label = "lc5_shutdown", 1874 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 1875 .mask = BIT(4), 1876 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1877 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1878 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1879 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1880 .slot = 5, 1881 }, 1882 { 1883 .label = "lc6_shutdown", 1884 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 1885 .mask = BIT(5), 1886 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1887 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1888 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1889 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1890 .slot = 6, 1891 }, 1892 { 1893 .label = "lc7_shutdown", 1894 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 1895 .mask = BIT(6), 1896 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1897 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1898 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1899 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1900 .slot = 7, 1901 }, 1902 { 1903 .label = "lc8_shutdown", 1904 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 1905 .mask = BIT(7), 1906 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1907 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1908 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1909 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1910 .slot = 8, 1911 }, 1912 }; 1913 1914 static struct mlxreg_core_item mlxplat_mlxcpld_modular_items[] = { 1915 { 1916 .data = mlxplat_mlxcpld_ext_psu_items_data, 1917 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1918 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1919 .mask = MLXPLAT_CPLD_PSU_EXT_MASK, 1920 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 1921 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data), 1922 .inversed = 1, 1923 .health = false, 1924 }, 1925 { 1926 .data = mlxplat_mlxcpld_modular_pwr_items_data, 1927 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1928 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1929 .mask = MLXPLAT_CPLD_PWR_EXT_MASK, 1930 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 1931 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data), 1932 .inversed = 0, 1933 .health = false, 1934 }, 1935 { 1936 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 1937 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1938 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1939 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 1940 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 1941 .inversed = 1, 1942 .health = false, 1943 }, 1944 { 1945 .data = mlxplat_mlxcpld_modular_asic_items_data, 1946 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1947 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1948 .mask = MLXPLAT_CPLD_ASIC_MASK, 1949 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_asic_items_data), 1950 .inversed = 0, 1951 .health = true, 1952 }, 1953 { 1954 .data = mlxplat_mlxcpld_modular_lc_pr_items_data, 1955 .kind = MLXREG_HOTPLUG_LC_PRESENT, 1956 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 1957 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1958 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 1959 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_pr_items_data), 1960 .inversed = 1, 1961 .health = false, 1962 }, 1963 { 1964 .data = mlxplat_mlxcpld_modular_lc_ver_items_data, 1965 .kind = MLXREG_HOTPLUG_LC_VERIFIED, 1966 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 1967 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1968 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 1969 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_ver_items_data), 1970 .inversed = 0, 1971 .health = false, 1972 }, 1973 { 1974 .data = mlxplat_mlxcpld_modular_lc_pg_data, 1975 .kind = MLXREG_HOTPLUG_LC_POWERED, 1976 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 1977 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1978 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 1979 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_pg_data), 1980 .inversed = 0, 1981 .health = false, 1982 }, 1983 { 1984 .data = mlxplat_mlxcpld_modular_lc_ready_data, 1985 .kind = MLXREG_HOTPLUG_LC_READY, 1986 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 1987 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1988 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 1989 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_ready_data), 1990 .inversed = 0, 1991 .health = false, 1992 }, 1993 { 1994 .data = mlxplat_mlxcpld_modular_lc_synced_data, 1995 .kind = MLXREG_HOTPLUG_LC_SYNCED, 1996 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 1997 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1998 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 1999 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_synced_data), 2000 .inversed = 0, 2001 .health = false, 2002 }, 2003 { 2004 .data = mlxplat_mlxcpld_modular_lc_act_data, 2005 .kind = MLXREG_HOTPLUG_LC_ACTIVE, 2006 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2007 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2008 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2009 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_act_data), 2010 .inversed = 0, 2011 .health = false, 2012 }, 2013 { 2014 .data = mlxplat_mlxcpld_modular_lc_sd_data, 2015 .kind = MLXREG_HOTPLUG_LC_THERMAL, 2016 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2017 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2018 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2019 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_sd_data), 2020 .inversed = 0, 2021 .health = false, 2022 }, 2023 }; 2024 2025 static 2026 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_modular_data = { 2027 .items = mlxplat_mlxcpld_modular_items, 2028 .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_items), 2029 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 2030 .mask = MLXPLAT_CPLD_AGGR_MASK_MODULAR, 2031 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 2032 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 2033 }; 2034 2035 /* Platform hotplug for NVLink blade systems family data */ 2036 static struct mlxreg_core_data mlxplat_mlxcpld_global_wp_items_data[] = { 2037 { 2038 .label = "global_wp_grant", 2039 .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET, 2040 .mask = MLXPLAT_CPLD_GWP_MASK, 2041 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2042 }, 2043 }; 2044 2045 static struct mlxreg_core_item mlxplat_mlxcpld_nvlink_blade_items[] = { 2046 { 2047 .data = mlxplat_mlxcpld_global_wp_items_data, 2048 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2049 .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET, 2050 .mask = MLXPLAT_CPLD_GWP_MASK, 2051 .count = ARRAY_SIZE(mlxplat_mlxcpld_global_wp_items_data), 2052 .inversed = 0, 2053 .health = false, 2054 }, 2055 }; 2056 2057 static 2058 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_nvlink_blade_data = { 2059 .items = mlxplat_mlxcpld_nvlink_blade_items, 2060 .counter = ARRAY_SIZE(mlxplat_mlxcpld_nvlink_blade_items), 2061 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 2062 .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX, 2063 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 2064 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 2065 }; 2066 2067 /* Platform led default data */ 2068 static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = { 2069 { 2070 .label = "status:green", 2071 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2072 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2073 }, 2074 { 2075 .label = "status:red", 2076 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2077 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2078 }, 2079 { 2080 .label = "psu:green", 2081 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2082 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2083 }, 2084 { 2085 .label = "psu:red", 2086 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2087 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2088 }, 2089 { 2090 .label = "fan1:green", 2091 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2092 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2093 }, 2094 { 2095 .label = "fan1:red", 2096 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2097 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2098 }, 2099 { 2100 .label = "fan2:green", 2101 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2102 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2103 }, 2104 { 2105 .label = "fan2:red", 2106 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2107 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2108 }, 2109 { 2110 .label = "fan3:green", 2111 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2112 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2113 }, 2114 { 2115 .label = "fan3:red", 2116 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2117 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2118 }, 2119 { 2120 .label = "fan4:green", 2121 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2122 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2123 }, 2124 { 2125 .label = "fan4:red", 2126 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2127 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2128 }, 2129 }; 2130 2131 static struct mlxreg_core_platform_data mlxplat_default_led_data = { 2132 .data = mlxplat_mlxcpld_default_led_data, 2133 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_data), 2134 }; 2135 2136 /* Platform led default data for water cooling */ 2137 static struct mlxreg_core_data mlxplat_mlxcpld_default_led_wc_data[] = { 2138 { 2139 .label = "status:green", 2140 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2141 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2142 }, 2143 { 2144 .label = "status:red", 2145 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2146 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2147 }, 2148 { 2149 .label = "psu:green", 2150 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2151 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2152 }, 2153 { 2154 .label = "psu:red", 2155 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2156 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2157 }, 2158 }; 2159 2160 static struct mlxreg_core_platform_data mlxplat_default_led_wc_data = { 2161 .data = mlxplat_mlxcpld_default_led_wc_data, 2162 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_wc_data), 2163 }; 2164 2165 /* Platform led default data for water cooling Ethernet switch blade */ 2166 static struct mlxreg_core_data mlxplat_mlxcpld_default_led_eth_wc_blade_data[] = { 2167 { 2168 .label = "status:green", 2169 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2170 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2171 }, 2172 { 2173 .label = "status:red", 2174 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2175 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2176 }, 2177 }; 2178 2179 static struct mlxreg_core_platform_data mlxplat_default_led_eth_wc_blade_data = { 2180 .data = mlxplat_mlxcpld_default_led_eth_wc_blade_data, 2181 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_eth_wc_blade_data), 2182 }; 2183 2184 /* Platform led MSN21xx system family data */ 2185 static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_led_data[] = { 2186 { 2187 .label = "status:green", 2188 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2189 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2190 }, 2191 { 2192 .label = "status:red", 2193 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2194 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2195 }, 2196 { 2197 .label = "fan:green", 2198 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2199 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2200 }, 2201 { 2202 .label = "fan:red", 2203 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2204 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2205 }, 2206 { 2207 .label = "psu1:green", 2208 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2209 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2210 }, 2211 { 2212 .label = "psu1:red", 2213 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2214 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2215 }, 2216 { 2217 .label = "psu2:green", 2218 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2219 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2220 }, 2221 { 2222 .label = "psu2:red", 2223 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2224 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2225 }, 2226 { 2227 .label = "uid:blue", 2228 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 2229 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2230 }, 2231 }; 2232 2233 static struct mlxreg_core_platform_data mlxplat_msn21xx_led_data = { 2234 .data = mlxplat_mlxcpld_msn21xx_led_data, 2235 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_led_data), 2236 }; 2237 2238 /* Platform led for default data for 200GbE systems */ 2239 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_led_data[] = { 2240 { 2241 .label = "status:green", 2242 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2243 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2244 }, 2245 { 2246 .label = "status:orange", 2247 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2248 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2249 }, 2250 { 2251 .label = "psu:green", 2252 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2253 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2254 }, 2255 { 2256 .label = "psu:orange", 2257 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2258 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2259 }, 2260 { 2261 .label = "fan1:green", 2262 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2263 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2264 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2265 .bit = BIT(0), 2266 }, 2267 { 2268 .label = "fan1:orange", 2269 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2270 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2271 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2272 .bit = BIT(0), 2273 }, 2274 { 2275 .label = "fan2:green", 2276 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2277 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2278 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2279 .bit = BIT(1), 2280 }, 2281 { 2282 .label = "fan2:orange", 2283 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2284 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2285 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2286 .bit = BIT(1), 2287 }, 2288 { 2289 .label = "fan3:green", 2290 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2291 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2292 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2293 .bit = BIT(2), 2294 }, 2295 { 2296 .label = "fan3:orange", 2297 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2298 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2299 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2300 .bit = BIT(2), 2301 }, 2302 { 2303 .label = "fan4:green", 2304 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2305 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2306 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2307 .bit = BIT(3), 2308 }, 2309 { 2310 .label = "fan4:orange", 2311 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2312 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2313 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2314 .bit = BIT(3), 2315 }, 2316 { 2317 .label = "fan5:green", 2318 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2319 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2320 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2321 .bit = BIT(4), 2322 }, 2323 { 2324 .label = "fan5:orange", 2325 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2326 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2327 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2328 .bit = BIT(4), 2329 }, 2330 { 2331 .label = "fan6:green", 2332 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2333 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2334 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2335 .bit = BIT(5), 2336 }, 2337 { 2338 .label = "fan6:orange", 2339 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2340 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2341 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2342 .bit = BIT(5), 2343 }, 2344 { 2345 .label = "fan7:green", 2346 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 2347 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2348 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2349 .bit = BIT(6), 2350 }, 2351 { 2352 .label = "fan7:orange", 2353 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 2354 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2355 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2356 .bit = BIT(6), 2357 }, 2358 { 2359 .label = "uid:blue", 2360 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 2361 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2362 }, 2363 }; 2364 2365 static struct mlxreg_core_platform_data mlxplat_default_ng_led_data = { 2366 .data = mlxplat_mlxcpld_default_ng_led_data, 2367 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_led_data), 2368 }; 2369 2370 /* Platform led for Comex based 100GbE systems */ 2371 static struct mlxreg_core_data mlxplat_mlxcpld_comex_100G_led_data[] = { 2372 { 2373 .label = "status:green", 2374 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2375 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2376 }, 2377 { 2378 .label = "status:red", 2379 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2380 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2381 }, 2382 { 2383 .label = "psu:green", 2384 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2385 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2386 }, 2387 { 2388 .label = "psu:red", 2389 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2390 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2391 }, 2392 { 2393 .label = "fan1:green", 2394 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2395 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2396 }, 2397 { 2398 .label = "fan1:red", 2399 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2400 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2401 }, 2402 { 2403 .label = "fan2:green", 2404 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2405 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2406 }, 2407 { 2408 .label = "fan2:red", 2409 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2410 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2411 }, 2412 { 2413 .label = "fan3:green", 2414 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2415 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2416 }, 2417 { 2418 .label = "fan3:red", 2419 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2420 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2421 }, 2422 { 2423 .label = "fan4:green", 2424 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2425 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2426 }, 2427 { 2428 .label = "fan4:red", 2429 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2430 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2431 }, 2432 { 2433 .label = "uid:blue", 2434 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 2435 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2436 }, 2437 }; 2438 2439 static struct mlxreg_core_platform_data mlxplat_comex_100G_led_data = { 2440 .data = mlxplat_mlxcpld_comex_100G_led_data, 2441 .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_100G_led_data), 2442 }; 2443 2444 /* Platform led for data for modular systems */ 2445 static struct mlxreg_core_data mlxplat_mlxcpld_modular_led_data[] = { 2446 { 2447 .label = "status:green", 2448 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2449 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2450 }, 2451 { 2452 .label = "status:orange", 2453 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2454 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2455 }, 2456 { 2457 .label = "psu:green", 2458 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2459 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2460 }, 2461 { 2462 .label = "psu:orange", 2463 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2464 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2465 }, 2466 { 2467 .label = "fan1:green", 2468 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2469 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2470 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2471 .bit = BIT(0), 2472 }, 2473 { 2474 .label = "fan1:orange", 2475 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2476 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2477 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2478 .bit = BIT(0), 2479 }, 2480 { 2481 .label = "fan2:green", 2482 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2483 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2484 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2485 .bit = BIT(1), 2486 }, 2487 { 2488 .label = "fan2:orange", 2489 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2490 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2491 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2492 .bit = BIT(1), 2493 }, 2494 { 2495 .label = "fan3:green", 2496 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2497 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2498 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2499 .bit = BIT(2), 2500 }, 2501 { 2502 .label = "fan3:orange", 2503 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2504 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2505 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2506 .bit = BIT(2), 2507 }, 2508 { 2509 .label = "fan4:green", 2510 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2511 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2512 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2513 .bit = BIT(3), 2514 }, 2515 { 2516 .label = "fan4:orange", 2517 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2518 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2519 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2520 .bit = BIT(3), 2521 }, 2522 { 2523 .label = "fan5:green", 2524 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2525 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2526 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2527 .bit = BIT(4), 2528 }, 2529 { 2530 .label = "fan5:orange", 2531 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2532 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2533 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2534 .bit = BIT(4), 2535 }, 2536 { 2537 .label = "fan6:green", 2538 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2539 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2540 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2541 .bit = BIT(5), 2542 }, 2543 { 2544 .label = "fan6:orange", 2545 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2546 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2547 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2548 .bit = BIT(5), 2549 }, 2550 { 2551 .label = "fan7:green", 2552 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 2553 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2554 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2555 .bit = BIT(6), 2556 }, 2557 { 2558 .label = "fan7:orange", 2559 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 2560 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2561 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2562 .bit = BIT(6), 2563 }, 2564 { 2565 .label = "uid:blue", 2566 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 2567 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2568 }, 2569 { 2570 .label = "fan_front:green", 2571 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 2572 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2573 }, 2574 { 2575 .label = "fan_front:orange", 2576 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 2577 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2578 }, 2579 { 2580 .label = "mgmt:green", 2581 .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, 2582 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2583 }, 2584 { 2585 .label = "mgmt:orange", 2586 .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, 2587 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2588 }, 2589 }; 2590 2591 static struct mlxreg_core_platform_data mlxplat_modular_led_data = { 2592 .data = mlxplat_mlxcpld_modular_led_data, 2593 .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_led_data), 2594 }; 2595 2596 /* Platform register access default */ 2597 static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = { 2598 { 2599 .label = "cpld1_version", 2600 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 2601 .bit = GENMASK(7, 0), 2602 .mode = 0444, 2603 }, 2604 { 2605 .label = "cpld2_version", 2606 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 2607 .bit = GENMASK(7, 0), 2608 .mode = 0444, 2609 }, 2610 { 2611 .label = "cpld1_pn", 2612 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 2613 .bit = GENMASK(15, 0), 2614 .mode = 0444, 2615 .regnum = 2, 2616 }, 2617 { 2618 .label = "cpld2_pn", 2619 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 2620 .bit = GENMASK(15, 0), 2621 .mode = 0444, 2622 .regnum = 2, 2623 }, 2624 { 2625 .label = "cpld1_version_min", 2626 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 2627 .bit = GENMASK(7, 0), 2628 .mode = 0444, 2629 }, 2630 { 2631 .label = "cpld2_version_min", 2632 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 2633 .bit = GENMASK(7, 0), 2634 .mode = 0444, 2635 }, 2636 { 2637 .label = "reset_long_pb", 2638 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2639 .mask = GENMASK(7, 0) & ~BIT(0), 2640 .mode = 0444, 2641 }, 2642 { 2643 .label = "reset_short_pb", 2644 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2645 .mask = GENMASK(7, 0) & ~BIT(1), 2646 .mode = 0444, 2647 }, 2648 { 2649 .label = "reset_aux_pwr_or_ref", 2650 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2651 .mask = GENMASK(7, 0) & ~BIT(2), 2652 .mode = 0444, 2653 }, 2654 { 2655 .label = "reset_main_pwr_fail", 2656 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2657 .mask = GENMASK(7, 0) & ~BIT(3), 2658 .mode = 0444, 2659 }, 2660 { 2661 .label = "reset_sw_reset", 2662 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2663 .mask = GENMASK(7, 0) & ~BIT(4), 2664 .mode = 0444, 2665 }, 2666 { 2667 .label = "reset_fw_reset", 2668 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2669 .mask = GENMASK(7, 0) & ~BIT(5), 2670 .mode = 0444, 2671 }, 2672 { 2673 .label = "reset_hotswap_or_wd", 2674 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2675 .mask = GENMASK(7, 0) & ~BIT(6), 2676 .mode = 0444, 2677 }, 2678 { 2679 .label = "reset_asic_thermal", 2680 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2681 .mask = GENMASK(7, 0) & ~BIT(7), 2682 .mode = 0444, 2683 }, 2684 { 2685 .label = "psu1_on", 2686 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2687 .mask = GENMASK(7, 0) & ~BIT(0), 2688 .mode = 0200, 2689 }, 2690 { 2691 .label = "psu2_on", 2692 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2693 .mask = GENMASK(7, 0) & ~BIT(1), 2694 .mode = 0200, 2695 }, 2696 { 2697 .label = "pwr_cycle", 2698 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2699 .mask = GENMASK(7, 0) & ~BIT(2), 2700 .mode = 0200, 2701 }, 2702 { 2703 .label = "pwr_down", 2704 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2705 .mask = GENMASK(7, 0) & ~BIT(3), 2706 .mode = 0200, 2707 }, 2708 { 2709 .label = "select_iio", 2710 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 2711 .mask = GENMASK(7, 0) & ~BIT(6), 2712 .mode = 0644, 2713 }, 2714 { 2715 .label = "asic_health", 2716 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 2717 .mask = MLXPLAT_CPLD_ASIC_MASK, 2718 .bit = 1, 2719 .mode = 0444, 2720 }, 2721 }; 2722 2723 static struct mlxreg_core_platform_data mlxplat_default_regs_io_data = { 2724 .data = mlxplat_mlxcpld_default_regs_io_data, 2725 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_regs_io_data), 2726 }; 2727 2728 /* Platform register access MSN21xx, MSN201x, MSN274x systems families data */ 2729 static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = { 2730 { 2731 .label = "cpld1_version", 2732 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 2733 .bit = GENMASK(7, 0), 2734 .mode = 0444, 2735 }, 2736 { 2737 .label = "cpld2_version", 2738 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 2739 .bit = GENMASK(7, 0), 2740 .mode = 0444, 2741 }, 2742 { 2743 .label = "cpld1_pn", 2744 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 2745 .bit = GENMASK(15, 0), 2746 .mode = 0444, 2747 .regnum = 2, 2748 }, 2749 { 2750 .label = "cpld2_pn", 2751 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 2752 .bit = GENMASK(15, 0), 2753 .mode = 0444, 2754 .regnum = 2, 2755 }, 2756 { 2757 .label = "cpld1_version_min", 2758 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 2759 .bit = GENMASK(7, 0), 2760 .mode = 0444, 2761 }, 2762 { 2763 .label = "cpld2_version_min", 2764 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 2765 .bit = GENMASK(7, 0), 2766 .mode = 0444, 2767 }, 2768 { 2769 .label = "reset_long_pb", 2770 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2771 .mask = GENMASK(7, 0) & ~BIT(0), 2772 .mode = 0444, 2773 }, 2774 { 2775 .label = "reset_short_pb", 2776 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2777 .mask = GENMASK(7, 0) & ~BIT(1), 2778 .mode = 0444, 2779 }, 2780 { 2781 .label = "reset_aux_pwr_or_ref", 2782 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2783 .mask = GENMASK(7, 0) & ~BIT(2), 2784 .mode = 0444, 2785 }, 2786 { 2787 .label = "reset_sw_reset", 2788 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2789 .mask = GENMASK(7, 0) & ~BIT(3), 2790 .mode = 0444, 2791 }, 2792 { 2793 .label = "reset_main_pwr_fail", 2794 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2795 .mask = GENMASK(7, 0) & ~BIT(4), 2796 .mode = 0444, 2797 }, 2798 { 2799 .label = "reset_asic_thermal", 2800 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2801 .mask = GENMASK(7, 0) & ~BIT(5), 2802 .mode = 0444, 2803 }, 2804 { 2805 .label = "reset_hotswap_or_halt", 2806 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2807 .mask = GENMASK(7, 0) & ~BIT(6), 2808 .mode = 0444, 2809 }, 2810 { 2811 .label = "reset_sff_wd", 2812 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 2813 .mask = GENMASK(7, 0) & ~BIT(6), 2814 .mode = 0444, 2815 }, 2816 { 2817 .label = "psu1_on", 2818 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2819 .mask = GENMASK(7, 0) & ~BIT(0), 2820 .mode = 0200, 2821 }, 2822 { 2823 .label = "psu2_on", 2824 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2825 .mask = GENMASK(7, 0) & ~BIT(1), 2826 .mode = 0200, 2827 }, 2828 { 2829 .label = "pwr_cycle", 2830 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2831 .mask = GENMASK(7, 0) & ~BIT(2), 2832 .mode = 0200, 2833 }, 2834 { 2835 .label = "pwr_down", 2836 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2837 .mask = GENMASK(7, 0) & ~BIT(3), 2838 .mode = 0200, 2839 }, 2840 { 2841 .label = "select_iio", 2842 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 2843 .mask = GENMASK(7, 0) & ~BIT(6), 2844 .mode = 0644, 2845 }, 2846 { 2847 .label = "asic_health", 2848 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 2849 .mask = MLXPLAT_CPLD_ASIC_MASK, 2850 .bit = 1, 2851 .mode = 0444, 2852 }, 2853 }; 2854 2855 static struct mlxreg_core_platform_data mlxplat_msn21xx_regs_io_data = { 2856 .data = mlxplat_mlxcpld_msn21xx_regs_io_data, 2857 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_regs_io_data), 2858 }; 2859 2860 /* Platform register access for next generation systems families data */ 2861 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { 2862 { 2863 .label = "cpld1_version", 2864 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 2865 .bit = GENMASK(7, 0), 2866 .mode = 0444, 2867 }, 2868 { 2869 .label = "cpld2_version", 2870 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 2871 .bit = GENMASK(7, 0), 2872 .mode = 0444, 2873 }, 2874 { 2875 .label = "cpld3_version", 2876 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, 2877 .bit = GENMASK(7, 0), 2878 .mode = 0444, 2879 }, 2880 { 2881 .label = "cpld4_version", 2882 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET, 2883 .bit = GENMASK(7, 0), 2884 .mode = 0444, 2885 }, 2886 { 2887 .label = "cpld1_pn", 2888 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 2889 .bit = GENMASK(15, 0), 2890 .mode = 0444, 2891 .regnum = 2, 2892 }, 2893 { 2894 .label = "cpld2_pn", 2895 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 2896 .bit = GENMASK(15, 0), 2897 .mode = 0444, 2898 .regnum = 2, 2899 }, 2900 { 2901 .label = "cpld3_pn", 2902 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET, 2903 .bit = GENMASK(15, 0), 2904 .mode = 0444, 2905 .regnum = 2, 2906 }, 2907 { 2908 .label = "cpld4_pn", 2909 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET, 2910 .bit = GENMASK(15, 0), 2911 .mode = 0444, 2912 .regnum = 2, 2913 }, 2914 { 2915 .label = "cpld1_version_min", 2916 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 2917 .bit = GENMASK(7, 0), 2918 .mode = 0444, 2919 }, 2920 { 2921 .label = "cpld2_version_min", 2922 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 2923 .bit = GENMASK(7, 0), 2924 .mode = 0444, 2925 }, 2926 { 2927 .label = "cpld3_version_min", 2928 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET, 2929 .bit = GENMASK(7, 0), 2930 .mode = 0444, 2931 }, 2932 { 2933 .label = "cpld4_version_min", 2934 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET, 2935 .bit = GENMASK(7, 0), 2936 .mode = 0444, 2937 }, 2938 { 2939 .label = "asic_reset", 2940 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, 2941 .mask = GENMASK(7, 0) & ~BIT(3), 2942 .mode = 0200, 2943 }, 2944 { 2945 .label = "asic2_reset", 2946 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, 2947 .mask = GENMASK(7, 0) & ~BIT(2), 2948 .mode = 0200, 2949 }, 2950 { 2951 .label = "reset_long_pb", 2952 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2953 .mask = GENMASK(7, 0) & ~BIT(0), 2954 .mode = 0444, 2955 }, 2956 { 2957 .label = "reset_short_pb", 2958 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2959 .mask = GENMASK(7, 0) & ~BIT(1), 2960 .mode = 0444, 2961 }, 2962 { 2963 .label = "reset_aux_pwr_or_ref", 2964 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2965 .mask = GENMASK(7, 0) & ~BIT(2), 2966 .mode = 0444, 2967 }, 2968 { 2969 .label = "reset_from_comex", 2970 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2971 .mask = GENMASK(7, 0) & ~BIT(4), 2972 .mode = 0444, 2973 }, 2974 { 2975 .label = "reset_from_asic", 2976 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2977 .mask = GENMASK(7, 0) & ~BIT(5), 2978 .mode = 0444, 2979 }, 2980 { 2981 .label = "reset_swb_wd", 2982 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2983 .mask = GENMASK(7, 0) & ~BIT(6), 2984 .mode = 0444, 2985 }, 2986 { 2987 .label = "reset_asic_thermal", 2988 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2989 .mask = GENMASK(7, 0) & ~BIT(7), 2990 .mode = 0444, 2991 }, 2992 { 2993 .label = "reset_comex_pwr_fail", 2994 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 2995 .mask = GENMASK(7, 0) & ~BIT(3), 2996 .mode = 0444, 2997 }, 2998 { 2999 .label = "reset_platform", 3000 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3001 .mask = GENMASK(7, 0) & ~BIT(4), 3002 .mode = 0444, 3003 }, 3004 { 3005 .label = "reset_soc", 3006 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3007 .mask = GENMASK(7, 0) & ~BIT(5), 3008 .mode = 0444, 3009 }, 3010 { 3011 .label = "reset_comex_wd", 3012 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3013 .mask = GENMASK(7, 0) & ~BIT(6), 3014 .mode = 0444, 3015 }, 3016 { 3017 .label = "reset_voltmon_upgrade_fail", 3018 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3019 .mask = GENMASK(7, 0) & ~BIT(0), 3020 .mode = 0444, 3021 }, 3022 { 3023 .label = "reset_system", 3024 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3025 .mask = GENMASK(7, 0) & ~BIT(1), 3026 .mode = 0444, 3027 }, 3028 { 3029 .label = "reset_sw_pwr_off", 3030 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3031 .mask = GENMASK(7, 0) & ~BIT(2), 3032 .mode = 0444, 3033 }, 3034 { 3035 .label = "reset_comex_thermal", 3036 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3037 .mask = GENMASK(7, 0) & ~BIT(3), 3038 .mode = 0444, 3039 }, 3040 { 3041 .label = "reset_reload_bios", 3042 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3043 .mask = GENMASK(7, 0) & ~BIT(5), 3044 .mode = 0444, 3045 }, 3046 { 3047 .label = "reset_ac_pwr_fail", 3048 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3049 .mask = GENMASK(7, 0) & ~BIT(6), 3050 .mode = 0444, 3051 }, 3052 { 3053 .label = "psu1_on", 3054 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3055 .mask = GENMASK(7, 0) & ~BIT(0), 3056 .mode = 0200, 3057 }, 3058 { 3059 .label = "psu2_on", 3060 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3061 .mask = GENMASK(7, 0) & ~BIT(1), 3062 .mode = 0200, 3063 }, 3064 { 3065 .label = "pwr_cycle", 3066 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3067 .mask = GENMASK(7, 0) & ~BIT(2), 3068 .mode = 0200, 3069 }, 3070 { 3071 .label = "pwr_down", 3072 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3073 .mask = GENMASK(7, 0) & ~BIT(3), 3074 .mode = 0200, 3075 }, 3076 { 3077 .label = "jtag_enable", 3078 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 3079 .mask = GENMASK(7, 0) & ~BIT(4), 3080 .mode = 0644, 3081 }, 3082 { 3083 .label = "asic_health", 3084 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 3085 .mask = MLXPLAT_CPLD_ASIC_MASK, 3086 .bit = 1, 3087 .mode = 0444, 3088 }, 3089 { 3090 .label = "asic2_health", 3091 .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, 3092 .mask = MLXPLAT_CPLD_ASIC_MASK, 3093 .bit = 1, 3094 .mode = 0444, 3095 }, 3096 { 3097 .label = "fan_dir", 3098 .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, 3099 .bit = GENMASK(7, 0), 3100 .mode = 0444, 3101 }, 3102 { 3103 .label = "bios_safe_mode", 3104 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3105 .mask = GENMASK(7, 0) & ~BIT(4), 3106 .mode = 0444, 3107 }, 3108 { 3109 .label = "bios_active_image", 3110 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3111 .mask = GENMASK(7, 0) & ~BIT(5), 3112 .mode = 0444, 3113 }, 3114 { 3115 .label = "bios_auth_fail", 3116 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3117 .mask = GENMASK(7, 0) & ~BIT(6), 3118 .mode = 0444, 3119 }, 3120 { 3121 .label = "bios_upgrade_fail", 3122 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3123 .mask = GENMASK(7, 0) & ~BIT(7), 3124 .mode = 0444, 3125 }, 3126 { 3127 .label = "voltreg_update_status", 3128 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, 3129 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, 3130 .bit = 5, 3131 .mode = 0444, 3132 }, 3133 { 3134 .label = "vpd_wp", 3135 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 3136 .mask = GENMASK(7, 0) & ~BIT(3), 3137 .mode = 0644, 3138 }, 3139 { 3140 .label = "pcie_asic_reset_dis", 3141 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 3142 .mask = GENMASK(7, 0) & ~BIT(4), 3143 .mode = 0644, 3144 }, 3145 { 3146 .label = "config1", 3147 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, 3148 .bit = GENMASK(7, 0), 3149 .mode = 0444, 3150 }, 3151 { 3152 .label = "config2", 3153 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, 3154 .bit = GENMASK(7, 0), 3155 .mode = 0444, 3156 }, 3157 { 3158 .label = "config3", 3159 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, 3160 .bit = GENMASK(7, 0), 3161 .mode = 0444, 3162 }, 3163 { 3164 .label = "ufm_version", 3165 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, 3166 .bit = GENMASK(7, 0), 3167 .mode = 0444, 3168 }, 3169 }; 3170 3171 static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = { 3172 .data = mlxplat_mlxcpld_default_ng_regs_io_data, 3173 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_regs_io_data), 3174 }; 3175 3176 /* Platform register access for modular systems families data */ 3177 static struct mlxreg_core_data mlxplat_mlxcpld_modular_regs_io_data[] = { 3178 { 3179 .label = "cpld1_version", 3180 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 3181 .bit = GENMASK(7, 0), 3182 .mode = 0444, 3183 }, 3184 { 3185 .label = "cpld2_version", 3186 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 3187 .bit = GENMASK(7, 0), 3188 .mode = 0444, 3189 }, 3190 { 3191 .label = "cpld3_version", 3192 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, 3193 .bit = GENMASK(7, 0), 3194 .mode = 0444, 3195 }, 3196 { 3197 .label = "cpld4_version", 3198 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET, 3199 .bit = GENMASK(7, 0), 3200 .mode = 0444, 3201 }, 3202 { 3203 .label = "cpld1_pn", 3204 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 3205 .bit = GENMASK(15, 0), 3206 .mode = 0444, 3207 .regnum = 2, 3208 }, 3209 { 3210 .label = "cpld2_pn", 3211 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 3212 .bit = GENMASK(15, 0), 3213 .mode = 0444, 3214 .regnum = 2, 3215 }, 3216 { 3217 .label = "cpld3_pn", 3218 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET, 3219 .bit = GENMASK(15, 0), 3220 .mode = 0444, 3221 .regnum = 2, 3222 }, 3223 { 3224 .label = "cpld4_pn", 3225 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET, 3226 .bit = GENMASK(15, 0), 3227 .mode = 0444, 3228 .regnum = 2, 3229 }, 3230 { 3231 .label = "cpld1_version_min", 3232 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 3233 .bit = GENMASK(7, 0), 3234 .mode = 0444, 3235 }, 3236 { 3237 .label = "cpld2_version_min", 3238 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 3239 .bit = GENMASK(7, 0), 3240 .mode = 0444, 3241 }, 3242 { 3243 .label = "cpld3_version_min", 3244 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET, 3245 .bit = GENMASK(7, 0), 3246 .mode = 0444, 3247 }, 3248 { 3249 .label = "cpld4_version_min", 3250 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET, 3251 .bit = GENMASK(7, 0), 3252 .mode = 0444, 3253 }, 3254 { 3255 .label = "lc1_enable", 3256 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 3257 .mask = GENMASK(7, 0) & ~BIT(0), 3258 .mode = 0644, 3259 }, 3260 { 3261 .label = "lc2_enable", 3262 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 3263 .mask = GENMASK(7, 0) & ~BIT(1), 3264 .mode = 0644, 3265 }, 3266 { 3267 .label = "lc3_enable", 3268 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 3269 .mask = GENMASK(7, 0) & ~BIT(2), 3270 .mode = 0644, 3271 }, 3272 { 3273 .label = "lc4_enable", 3274 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 3275 .mask = GENMASK(7, 0) & ~BIT(3), 3276 .mode = 0644, 3277 }, 3278 { 3279 .label = "lc5_enable", 3280 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 3281 .mask = GENMASK(7, 0) & ~BIT(4), 3282 .mode = 0644, 3283 }, 3284 { 3285 .label = "lc6_enable", 3286 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 3287 .mask = GENMASK(7, 0) & ~BIT(5), 3288 .mode = 0644, 3289 }, 3290 { 3291 .label = "lc7_enable", 3292 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 3293 .mask = GENMASK(7, 0) & ~BIT(6), 3294 .mode = 0644, 3295 }, 3296 { 3297 .label = "lc8_enable", 3298 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 3299 .mask = GENMASK(7, 0) & ~BIT(7), 3300 .mode = 0644, 3301 }, 3302 { 3303 .label = "reset_long_pb", 3304 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3305 .mask = GENMASK(7, 0) & ~BIT(0), 3306 .mode = 0444, 3307 }, 3308 { 3309 .label = "reset_short_pb", 3310 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3311 .mask = GENMASK(7, 0) & ~BIT(1), 3312 .mode = 0444, 3313 }, 3314 { 3315 .label = "reset_aux_pwr_or_fu", 3316 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3317 .mask = GENMASK(7, 0) & ~BIT(2), 3318 .mode = 0444, 3319 }, 3320 { 3321 .label = "reset_mgmt_dc_dc_pwr_fail", 3322 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3323 .mask = GENMASK(7, 0) & ~BIT(3), 3324 .mode = 0444, 3325 }, 3326 { 3327 .label = "reset_sys_comex_bios", 3328 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3329 .mask = GENMASK(7, 0) & ~BIT(5), 3330 .mode = 0444, 3331 }, 3332 { 3333 .label = "reset_sw_reset", 3334 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3335 .mask = GENMASK(7, 0) & ~BIT(0), 3336 .mode = 0444, 3337 }, 3338 { 3339 .label = "reset_aux_pwr_or_reload", 3340 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3341 .mask = GENMASK(7, 0) & ~BIT(2), 3342 .mode = 0444, 3343 }, 3344 { 3345 .label = "reset_comex_pwr_fail", 3346 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3347 .mask = GENMASK(7, 0) & ~BIT(3), 3348 .mode = 0444, 3349 }, 3350 { 3351 .label = "reset_platform", 3352 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3353 .mask = GENMASK(7, 0) & ~BIT(4), 3354 .mode = 0444, 3355 }, 3356 { 3357 .label = "reset_soc", 3358 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3359 .mask = GENMASK(7, 0) & ~BIT(5), 3360 .mode = 0444, 3361 }, 3362 { 3363 .label = "reset_pwr_off_from_carrier", 3364 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3365 .mask = GENMASK(7, 0) & ~BIT(7), 3366 .mode = 0444, 3367 }, 3368 { 3369 .label = "reset_swb_wd", 3370 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3371 .mask = GENMASK(7, 0) & ~BIT(0), 3372 .mode = 0444, 3373 }, 3374 { 3375 .label = "reset_swb_aux_pwr_or_fu", 3376 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3377 .mask = GENMASK(7, 0) & ~BIT(2), 3378 .mode = 0444, 3379 }, 3380 { 3381 .label = "reset_swb_dc_dc_pwr_fail", 3382 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3383 .mask = GENMASK(7, 0) & ~BIT(3), 3384 .mode = 0444, 3385 }, 3386 { 3387 .label = "reset_swb_12v_fail", 3388 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3389 .mask = GENMASK(7, 0) & ~BIT(4), 3390 .mode = 0444, 3391 }, 3392 { 3393 .label = "reset_system", 3394 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3395 .mask = GENMASK(7, 0) & ~BIT(5), 3396 .mode = 0444, 3397 }, 3398 { 3399 .label = "reset_thermal_spc_or_pciesw", 3400 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3401 .mask = GENMASK(7, 0) & ~BIT(7), 3402 .mode = 0444, 3403 }, 3404 { 3405 .label = "bios_safe_mode", 3406 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3407 .mask = GENMASK(7, 0) & ~BIT(4), 3408 .mode = 0444, 3409 }, 3410 { 3411 .label = "bios_active_image", 3412 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3413 .mask = GENMASK(7, 0) & ~BIT(5), 3414 .mode = 0444, 3415 }, 3416 { 3417 .label = "bios_auth_fail", 3418 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3419 .mask = GENMASK(7, 0) & ~BIT(6), 3420 .mode = 0444, 3421 }, 3422 { 3423 .label = "bios_upgrade_fail", 3424 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3425 .mask = GENMASK(7, 0) & ~BIT(7), 3426 .mode = 0444, 3427 }, 3428 { 3429 .label = "voltreg_update_status", 3430 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, 3431 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, 3432 .bit = 5, 3433 .mode = 0444, 3434 }, 3435 { 3436 .label = "vpd_wp", 3437 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 3438 .mask = GENMASK(7, 0) & ~BIT(3), 3439 .mode = 0644, 3440 }, 3441 { 3442 .label = "pcie_asic_reset_dis", 3443 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 3444 .mask = GENMASK(7, 0) & ~BIT(4), 3445 .mode = 0644, 3446 }, 3447 { 3448 .label = "shutdown_unlock", 3449 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 3450 .mask = GENMASK(7, 0) & ~BIT(5), 3451 .mode = 0644, 3452 }, 3453 { 3454 .label = "lc1_rst_mask", 3455 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 3456 .mask = GENMASK(7, 0) & ~BIT(0), 3457 .mode = 0200, 3458 }, 3459 { 3460 .label = "lc2_rst_mask", 3461 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 3462 .mask = GENMASK(7, 0) & ~BIT(1), 3463 .mode = 0200, 3464 }, 3465 { 3466 .label = "lc3_rst_mask", 3467 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 3468 .mask = GENMASK(7, 0) & ~BIT(2), 3469 .mode = 0200, 3470 }, 3471 { 3472 .label = "lc4_rst_mask", 3473 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 3474 .mask = GENMASK(7, 0) & ~BIT(3), 3475 .mode = 0200, 3476 }, 3477 { 3478 .label = "lc5_rst_mask", 3479 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 3480 .mask = GENMASK(7, 0) & ~BIT(4), 3481 .mode = 0200, 3482 }, 3483 { 3484 .label = "lc6_rst_mask", 3485 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 3486 .mask = GENMASK(7, 0) & ~BIT(5), 3487 .mode = 0200, 3488 }, 3489 { 3490 .label = "lc7_rst_mask", 3491 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 3492 .mask = GENMASK(7, 0) & ~BIT(6), 3493 .mode = 0200, 3494 }, 3495 { 3496 .label = "lc8_rst_mask", 3497 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 3498 .mask = GENMASK(7, 0) & ~BIT(7), 3499 .mode = 0200, 3500 }, 3501 { 3502 .label = "psu1_on", 3503 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3504 .mask = GENMASK(7, 0) & ~BIT(0), 3505 .mode = 0200, 3506 }, 3507 { 3508 .label = "psu2_on", 3509 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3510 .mask = GENMASK(7, 0) & ~BIT(1), 3511 .mode = 0200, 3512 }, 3513 { 3514 .label = "pwr_cycle", 3515 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3516 .mask = GENMASK(7, 0) & ~BIT(2), 3517 .mode = 0200, 3518 }, 3519 { 3520 .label = "pwr_down", 3521 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3522 .mask = GENMASK(7, 0) & ~BIT(3), 3523 .mode = 0200, 3524 }, 3525 { 3526 .label = "psu3_on", 3527 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3528 .mask = GENMASK(7, 0) & ~BIT(4), 3529 .mode = 0200, 3530 }, 3531 { 3532 .label = "psu4_on", 3533 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3534 .mask = GENMASK(7, 0) & ~BIT(5), 3535 .mode = 0200, 3536 }, 3537 { 3538 .label = "auto_power_mode", 3539 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3540 .mask = GENMASK(7, 0) & ~BIT(6), 3541 .mode = 0644, 3542 }, 3543 { 3544 .label = "pm_mgmt_en", 3545 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3546 .mask = GENMASK(7, 0) & ~BIT(7), 3547 .mode = 0644, 3548 }, 3549 { 3550 .label = "jtag_enable", 3551 .reg = MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE, 3552 .mask = GENMASK(3, 0), 3553 .bit = 1, 3554 .mode = 0644, 3555 }, 3556 { 3557 .label = "safe_bios_dis", 3558 .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, 3559 .mask = GENMASK(7, 0) & ~BIT(5), 3560 .mode = 0644, 3561 }, 3562 { 3563 .label = "safe_bios_dis_wp", 3564 .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET, 3565 .mask = GENMASK(7, 0) & ~BIT(5), 3566 .mode = 0644, 3567 }, 3568 { 3569 .label = "asic_health", 3570 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 3571 .mask = MLXPLAT_CPLD_ASIC_MASK, 3572 .bit = 1, 3573 .mode = 0444, 3574 }, 3575 { 3576 .label = "fan_dir", 3577 .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, 3578 .bit = GENMASK(7, 0), 3579 .mode = 0444, 3580 }, 3581 { 3582 .label = "lc1_pwr", 3583 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 3584 .mask = GENMASK(7, 0) & ~BIT(0), 3585 .mode = 0644, 3586 }, 3587 { 3588 .label = "lc2_pwr", 3589 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 3590 .mask = GENMASK(7, 0) & ~BIT(1), 3591 .mode = 0644, 3592 }, 3593 { 3594 .label = "lc3_pwr", 3595 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 3596 .mask = GENMASK(7, 0) & ~BIT(2), 3597 .mode = 0644, 3598 }, 3599 { 3600 .label = "lc4_pwr", 3601 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 3602 .mask = GENMASK(7, 0) & ~BIT(3), 3603 .mode = 0644, 3604 }, 3605 { 3606 .label = "lc5_pwr", 3607 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 3608 .mask = GENMASK(7, 0) & ~BIT(4), 3609 .mode = 0644, 3610 }, 3611 { 3612 .label = "lc6_pwr", 3613 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 3614 .mask = GENMASK(7, 0) & ~BIT(5), 3615 .mode = 0644, 3616 }, 3617 { 3618 .label = "lc7_pwr", 3619 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 3620 .mask = GENMASK(7, 0) & ~BIT(6), 3621 .mode = 0644, 3622 }, 3623 { 3624 .label = "lc8_pwr", 3625 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 3626 .mask = GENMASK(7, 0) & ~BIT(7), 3627 .mode = 0644, 3628 }, 3629 { 3630 .label = "config1", 3631 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, 3632 .bit = GENMASK(7, 0), 3633 .mode = 0444, 3634 }, 3635 { 3636 .label = "config2", 3637 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, 3638 .bit = GENMASK(7, 0), 3639 .mode = 0444, 3640 }, 3641 { 3642 .label = "config3", 3643 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, 3644 .bit = GENMASK(7, 0), 3645 .mode = 0444, 3646 }, 3647 { 3648 .label = "ufm_version", 3649 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, 3650 .bit = GENMASK(7, 0), 3651 .mode = 0444, 3652 }, 3653 }; 3654 3655 static struct mlxreg_core_platform_data mlxplat_modular_regs_io_data = { 3656 .data = mlxplat_mlxcpld_modular_regs_io_data, 3657 .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_regs_io_data), 3658 }; 3659 3660 /* Platform register access for NVLink blade systems family data */ 3661 static struct mlxreg_core_data mlxplat_mlxcpld_nvlink_blade_regs_io_data[] = { 3662 { 3663 .label = "cpld1_version", 3664 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 3665 .bit = GENMASK(7, 0), 3666 .mode = 0444, 3667 }, 3668 { 3669 .label = "cpld1_pn", 3670 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 3671 .bit = GENMASK(15, 0), 3672 .mode = 0444, 3673 .regnum = 2, 3674 }, 3675 { 3676 .label = "cpld1_version_min", 3677 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 3678 .bit = GENMASK(7, 0), 3679 .mode = 0444, 3680 }, 3681 { 3682 .label = "reset_aux_pwr_or_ref", 3683 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3684 .mask = GENMASK(7, 0) & ~BIT(2), 3685 .mode = 0444, 3686 }, 3687 { 3688 .label = "reset_from_comex", 3689 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3690 .mask = GENMASK(7, 0) & ~BIT(4), 3691 .mode = 0444, 3692 }, 3693 { 3694 .label = "reset_comex_pwr_fail", 3695 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3696 .mask = GENMASK(7, 0) & ~BIT(3), 3697 .mode = 0444, 3698 }, 3699 { 3700 .label = "reset_platform", 3701 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3702 .mask = GENMASK(7, 0) & ~BIT(4), 3703 .mode = 0444, 3704 }, 3705 { 3706 .label = "reset_soc", 3707 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3708 .mask = GENMASK(7, 0) & ~BIT(5), 3709 .mode = 0444, 3710 }, 3711 { 3712 .label = "reset_comex_wd", 3713 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3714 .mask = GENMASK(7, 0) & ~BIT(6), 3715 .mode = 0444, 3716 }, 3717 { 3718 .label = "reset_voltmon_upgrade_fail", 3719 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3720 .mask = GENMASK(7, 0) & ~BIT(0), 3721 .mode = 0444, 3722 }, 3723 { 3724 .label = "reset_system", 3725 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3726 .mask = GENMASK(7, 0) & ~BIT(1), 3727 .mode = 0444, 3728 }, 3729 { 3730 .label = "reset_sw_pwr_off", 3731 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3732 .mask = GENMASK(7, 0) & ~BIT(2), 3733 .mode = 0444, 3734 }, 3735 { 3736 .label = "reset_comex_thermal", 3737 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3738 .mask = GENMASK(7, 0) & ~BIT(3), 3739 .mode = 0444, 3740 }, 3741 { 3742 .label = "reset_reload_bios", 3743 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3744 .mask = GENMASK(7, 0) & ~BIT(5), 3745 .mode = 0444, 3746 }, 3747 { 3748 .label = "reset_ac_pwr_fail", 3749 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3750 .mask = GENMASK(7, 0) & ~BIT(6), 3751 .mode = 0444, 3752 }, 3753 { 3754 .label = "pwr_cycle", 3755 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3756 .mask = GENMASK(7, 0) & ~BIT(2), 3757 .mode = 0200, 3758 }, 3759 { 3760 .label = "pwr_down", 3761 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3762 .mask = GENMASK(7, 0) & ~BIT(3), 3763 .mode = 0200, 3764 }, 3765 { 3766 .label = "global_wp_request", 3767 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 3768 .mask = GENMASK(7, 0) & ~BIT(0), 3769 .mode = 0644, 3770 }, 3771 { 3772 .label = "jtag_enable", 3773 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 3774 .mask = GENMASK(7, 0) & ~BIT(4), 3775 .mode = 0644, 3776 }, 3777 { 3778 .label = "comm_chnl_ready", 3779 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 3780 .mask = GENMASK(7, 0) & ~BIT(6), 3781 .mode = 0200, 3782 }, 3783 { 3784 .label = "bios_safe_mode", 3785 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3786 .mask = GENMASK(7, 0) & ~BIT(4), 3787 .mode = 0444, 3788 }, 3789 { 3790 .label = "bios_active_image", 3791 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3792 .mask = GENMASK(7, 0) & ~BIT(5), 3793 .mode = 0444, 3794 }, 3795 { 3796 .label = "bios_auth_fail", 3797 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3798 .mask = GENMASK(7, 0) & ~BIT(6), 3799 .mode = 0444, 3800 }, 3801 { 3802 .label = "bios_upgrade_fail", 3803 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3804 .mask = GENMASK(7, 0) & ~BIT(7), 3805 .mode = 0444, 3806 }, 3807 { 3808 .label = "voltreg_update_status", 3809 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, 3810 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, 3811 .bit = 5, 3812 .mode = 0444, 3813 }, 3814 { 3815 .label = "vpd_wp", 3816 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 3817 .mask = GENMASK(7, 0) & ~BIT(3), 3818 .mode = 0644, 3819 }, 3820 { 3821 .label = "pcie_asic_reset_dis", 3822 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 3823 .mask = GENMASK(7, 0) & ~BIT(4), 3824 .mode = 0644, 3825 }, 3826 { 3827 .label = "global_wp_response", 3828 .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET, 3829 .mask = GENMASK(7, 0) & ~BIT(0), 3830 .mode = 0444, 3831 }, 3832 { 3833 .label = "config1", 3834 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, 3835 .bit = GENMASK(7, 0), 3836 .mode = 0444, 3837 }, 3838 { 3839 .label = "config2", 3840 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, 3841 .bit = GENMASK(7, 0), 3842 .mode = 0444, 3843 }, 3844 { 3845 .label = "config3", 3846 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, 3847 .bit = GENMASK(7, 0), 3848 .mode = 0444, 3849 }, 3850 { 3851 .label = "ufm_version", 3852 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, 3853 .bit = GENMASK(7, 0), 3854 .mode = 0444, 3855 }, 3856 }; 3857 3858 static struct mlxreg_core_platform_data mlxplat_nvlink_blade_regs_io_data = { 3859 .data = mlxplat_mlxcpld_nvlink_blade_regs_io_data, 3860 .counter = ARRAY_SIZE(mlxplat_mlxcpld_nvlink_blade_regs_io_data), 3861 }; 3862 3863 /* Platform FAN default */ 3864 static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = { 3865 { 3866 .label = "pwm1", 3867 .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET, 3868 }, 3869 { 3870 .label = "pwm2", 3871 .reg = MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET, 3872 }, 3873 { 3874 .label = "pwm3", 3875 .reg = MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET, 3876 }, 3877 { 3878 .label = "pwm4", 3879 .reg = MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET, 3880 }, 3881 { 3882 .label = "tacho1", 3883 .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET, 3884 .mask = GENMASK(7, 0), 3885 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 3886 .bit = BIT(0), 3887 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3888 3889 }, 3890 { 3891 .label = "tacho2", 3892 .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET, 3893 .mask = GENMASK(7, 0), 3894 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 3895 .bit = BIT(1), 3896 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3897 }, 3898 { 3899 .label = "tacho3", 3900 .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET, 3901 .mask = GENMASK(7, 0), 3902 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 3903 .bit = BIT(2), 3904 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3905 }, 3906 { 3907 .label = "tacho4", 3908 .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET, 3909 .mask = GENMASK(7, 0), 3910 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 3911 .bit = BIT(3), 3912 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3913 }, 3914 { 3915 .label = "tacho5", 3916 .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET, 3917 .mask = GENMASK(7, 0), 3918 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 3919 .bit = BIT(4), 3920 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3921 }, 3922 { 3923 .label = "tacho6", 3924 .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET, 3925 .mask = GENMASK(7, 0), 3926 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 3927 .bit = BIT(5), 3928 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3929 }, 3930 { 3931 .label = "tacho7", 3932 .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET, 3933 .mask = GENMASK(7, 0), 3934 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 3935 .bit = BIT(6), 3936 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3937 }, 3938 { 3939 .label = "tacho8", 3940 .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET, 3941 .mask = GENMASK(7, 0), 3942 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 3943 .bit = BIT(7), 3944 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3945 }, 3946 { 3947 .label = "tacho9", 3948 .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET, 3949 .mask = GENMASK(7, 0), 3950 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 3951 .bit = BIT(0), 3952 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3953 }, 3954 { 3955 .label = "tacho10", 3956 .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET, 3957 .mask = GENMASK(7, 0), 3958 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 3959 .bit = BIT(1), 3960 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3961 }, 3962 { 3963 .label = "tacho11", 3964 .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET, 3965 .mask = GENMASK(7, 0), 3966 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 3967 .bit = BIT(2), 3968 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3969 }, 3970 { 3971 .label = "tacho12", 3972 .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET, 3973 .mask = GENMASK(7, 0), 3974 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 3975 .bit = BIT(3), 3976 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3977 }, 3978 { 3979 .label = "tacho13", 3980 .reg = MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET, 3981 .mask = GENMASK(7, 0), 3982 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 3983 .bit = BIT(4), 3984 }, 3985 { 3986 .label = "tacho14", 3987 .reg = MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET, 3988 .mask = GENMASK(7, 0), 3989 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 3990 .bit = BIT(5), 3991 }, 3992 { 3993 .label = "conf", 3994 .capability = MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET, 3995 }, 3996 }; 3997 3998 static struct mlxreg_core_platform_data mlxplat_default_fan_data = { 3999 .data = mlxplat_mlxcpld_default_fan_data, 4000 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_data), 4001 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 4002 }; 4003 4004 /* Watchdog type1: hardware implementation version1 4005 * (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140 systems). 4006 */ 4007 static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type1[] = { 4008 { 4009 .label = "action", 4010 .reg = MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 4011 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 4012 .bit = 0, 4013 }, 4014 { 4015 .label = "timeout", 4016 .reg = MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET, 4017 .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK, 4018 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 4019 }, 4020 { 4021 .label = "ping", 4022 .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET, 4023 .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK, 4024 .bit = 0, 4025 }, 4026 { 4027 .label = "reset", 4028 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4029 .mask = GENMASK(7, 0) & ~BIT(6), 4030 .bit = 6, 4031 }, 4032 }; 4033 4034 static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type1[] = { 4035 { 4036 .label = "action", 4037 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 4038 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 4039 .bit = 4, 4040 }, 4041 { 4042 .label = "timeout", 4043 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 4044 .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK, 4045 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 4046 }, 4047 { 4048 .label = "ping", 4049 .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET, 4050 .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK, 4051 .bit = 1, 4052 }, 4053 }; 4054 4055 static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type1[] = { 4056 { 4057 .data = mlxplat_mlxcpld_wd_main_regs_type1, 4058 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type1), 4059 .version = MLX_WDT_TYPE1, 4060 .identity = "mlx-wdt-main", 4061 }, 4062 { 4063 .data = mlxplat_mlxcpld_wd_aux_regs_type1, 4064 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type1), 4065 .version = MLX_WDT_TYPE1, 4066 .identity = "mlx-wdt-aux", 4067 }, 4068 }; 4069 4070 /* Watchdog type2: hardware implementation version 2 4071 * (all systems except (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140). 4072 */ 4073 static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type2[] = { 4074 { 4075 .label = "action", 4076 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 4077 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 4078 .bit = 0, 4079 }, 4080 { 4081 .label = "timeout", 4082 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 4083 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 4084 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 4085 }, 4086 { 4087 .label = "timeleft", 4088 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET, 4089 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 4090 }, 4091 { 4092 .label = "ping", 4093 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 4094 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 4095 .bit = 0, 4096 }, 4097 { 4098 .label = "reset", 4099 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4100 .mask = GENMASK(7, 0) & ~BIT(6), 4101 .bit = 6, 4102 }, 4103 }; 4104 4105 static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type2[] = { 4106 { 4107 .label = "action", 4108 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 4109 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 4110 .bit = 4, 4111 }, 4112 { 4113 .label = "timeout", 4114 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET, 4115 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 4116 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 4117 }, 4118 { 4119 .label = "timeleft", 4120 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET, 4121 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 4122 }, 4123 { 4124 .label = "ping", 4125 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 4126 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 4127 .bit = 4, 4128 }, 4129 }; 4130 4131 static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type2[] = { 4132 { 4133 .data = mlxplat_mlxcpld_wd_main_regs_type2, 4134 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type2), 4135 .version = MLX_WDT_TYPE2, 4136 .identity = "mlx-wdt-main", 4137 }, 4138 { 4139 .data = mlxplat_mlxcpld_wd_aux_regs_type2, 4140 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type2), 4141 .version = MLX_WDT_TYPE2, 4142 .identity = "mlx-wdt-aux", 4143 }, 4144 }; 4145 4146 /* Watchdog type3: hardware implementation version 3 4147 * Can be on all systems. It's differentiated by WD capability bit. 4148 * Old systems (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140) 4149 * still have only one main watchdog. 4150 */ 4151 static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type3[] = { 4152 { 4153 .label = "action", 4154 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 4155 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 4156 .bit = 0, 4157 }, 4158 { 4159 .label = "timeout", 4160 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 4161 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 4162 .health_cntr = MLXPLAT_CPLD_WD3_DFLT_TIMEOUT, 4163 }, 4164 { 4165 .label = "timeleft", 4166 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 4167 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 4168 }, 4169 { 4170 .label = "ping", 4171 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 4172 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 4173 .bit = 0, 4174 }, 4175 { 4176 .label = "reset", 4177 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4178 .mask = GENMASK(7, 0) & ~BIT(6), 4179 .bit = 6, 4180 }, 4181 }; 4182 4183 static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type3[] = { 4184 { 4185 .label = "action", 4186 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 4187 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 4188 .bit = 4, 4189 }, 4190 { 4191 .label = "timeout", 4192 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET, 4193 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 4194 .health_cntr = MLXPLAT_CPLD_WD3_DFLT_TIMEOUT, 4195 }, 4196 { 4197 .label = "timeleft", 4198 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET, 4199 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 4200 }, 4201 { 4202 .label = "ping", 4203 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 4204 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 4205 .bit = 4, 4206 }, 4207 }; 4208 4209 static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type3[] = { 4210 { 4211 .data = mlxplat_mlxcpld_wd_main_regs_type3, 4212 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type3), 4213 .version = MLX_WDT_TYPE3, 4214 .identity = "mlx-wdt-main", 4215 }, 4216 { 4217 .data = mlxplat_mlxcpld_wd_aux_regs_type3, 4218 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type3), 4219 .version = MLX_WDT_TYPE3, 4220 .identity = "mlx-wdt-aux", 4221 }, 4222 }; 4223 4224 static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) 4225 { 4226 switch (reg) { 4227 case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: 4228 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 4229 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 4230 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 4231 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 4232 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 4233 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: 4234 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: 4235 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 4236 case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: 4237 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 4238 case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: 4239 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 4240 case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET: 4241 case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: 4242 case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: 4243 case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: 4244 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 4245 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 4246 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 4247 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 4248 case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: 4249 case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: 4250 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 4251 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 4252 case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: 4253 case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: 4254 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 4255 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 4256 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 4257 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 4258 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 4259 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 4260 case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: 4261 case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET: 4262 case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET: 4263 case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET: 4264 case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET: 4265 case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET: 4266 case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET: 4267 case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET: 4268 case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET: 4269 case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET: 4270 case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET: 4271 case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET: 4272 case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET: 4273 case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET: 4274 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: 4275 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: 4276 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: 4277 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET: 4278 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET: 4279 case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET: 4280 case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET: 4281 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 4282 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: 4283 case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET: 4284 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 4285 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: 4286 case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: 4287 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 4288 case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: 4289 case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: 4290 case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET: 4291 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 4292 return true; 4293 } 4294 return false; 4295 } 4296 4297 static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) 4298 { 4299 switch (reg) { 4300 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET: 4301 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET: 4302 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: 4303 case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: 4304 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: 4305 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET: 4306 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: 4307 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET: 4308 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET: 4309 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET: 4310 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET: 4311 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET: 4312 case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: 4313 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: 4314 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: 4315 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET: 4316 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 4317 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 4318 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 4319 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 4320 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 4321 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: 4322 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: 4323 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: 4324 case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: 4325 case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET: 4326 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 4327 case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: 4328 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 4329 case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: 4330 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 4331 case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET: 4332 case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: 4333 case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: 4334 case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: 4335 case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: 4336 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 4337 case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET: 4338 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 4339 case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET: 4340 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 4341 case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET: 4342 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 4343 case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET: 4344 case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: 4345 case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: 4346 case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: 4347 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 4348 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 4349 case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET: 4350 case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: 4351 case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: 4352 case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: 4353 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 4354 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 4355 case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET: 4356 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 4357 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 4358 case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: 4359 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 4360 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 4361 case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET: 4362 case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: 4363 case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET: 4364 case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET: 4365 case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET: 4366 case MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET: 4367 case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET: 4368 case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET: 4369 case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET: 4370 case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET: 4371 case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET: 4372 case MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET: 4373 case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET: 4374 case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET: 4375 case MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET: 4376 case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET: 4377 case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET: 4378 case MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET: 4379 case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET: 4380 case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET: 4381 case MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET: 4382 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: 4383 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: 4384 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: 4385 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET: 4386 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET: 4387 case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET: 4388 case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET: 4389 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 4390 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: 4391 case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET: 4392 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 4393 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: 4394 case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: 4395 case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: 4396 case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: 4397 case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: 4398 case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET: 4399 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 4400 case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: 4401 case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: 4402 case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET: 4403 case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET: 4404 case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET: 4405 case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET: 4406 case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET: 4407 case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET: 4408 case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET: 4409 case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET: 4410 case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET: 4411 case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET: 4412 case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET: 4413 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET: 4414 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: 4415 case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET: 4416 case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET: 4417 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 4418 case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET: 4419 case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: 4420 case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET: 4421 case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET: 4422 case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET: 4423 case MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET: 4424 case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET: 4425 case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: 4426 case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET: 4427 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: 4428 return true; 4429 } 4430 return false; 4431 } 4432 4433 static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) 4434 { 4435 switch (reg) { 4436 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET: 4437 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET: 4438 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: 4439 case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: 4440 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: 4441 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET: 4442 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: 4443 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET: 4444 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET: 4445 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET: 4446 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET: 4447 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET: 4448 case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: 4449 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: 4450 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: 4451 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET: 4452 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 4453 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 4454 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 4455 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 4456 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 4457 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: 4458 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: 4459 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: 4460 case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: 4461 case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET: 4462 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 4463 case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: 4464 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 4465 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 4466 case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: 4467 case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: 4468 case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: 4469 case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: 4470 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 4471 case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET: 4472 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 4473 case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET: 4474 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 4475 case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET: 4476 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 4477 case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET: 4478 case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: 4479 case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: 4480 case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: 4481 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 4482 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 4483 case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET: 4484 case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: 4485 case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: 4486 case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: 4487 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 4488 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 4489 case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET: 4490 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 4491 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 4492 case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: 4493 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 4494 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 4495 case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET: 4496 case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: 4497 case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET: 4498 case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET: 4499 case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET: 4500 case MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET: 4501 case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET: 4502 case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET: 4503 case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET: 4504 case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET: 4505 case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET: 4506 case MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET: 4507 case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET: 4508 case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET: 4509 case MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET: 4510 case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET: 4511 case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET: 4512 case MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET: 4513 case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET: 4514 case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET: 4515 case MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET: 4516 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: 4517 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: 4518 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: 4519 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 4520 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: 4521 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 4522 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: 4523 case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: 4524 case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: 4525 case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: 4526 case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET: 4527 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 4528 case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: 4529 case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: 4530 case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET: 4531 case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET: 4532 case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET: 4533 case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET: 4534 case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET: 4535 case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET: 4536 case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET: 4537 case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET: 4538 case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET: 4539 case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET: 4540 case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET: 4541 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET: 4542 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: 4543 case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET: 4544 case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET: 4545 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 4546 case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET: 4547 case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: 4548 case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET: 4549 case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET: 4550 case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET: 4551 case MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET: 4552 case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET: 4553 case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: 4554 case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET: 4555 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: 4556 return true; 4557 } 4558 return false; 4559 } 4560 4561 static const struct reg_default mlxplat_mlxcpld_regmap_default[] = { 4562 { MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, 0x00 }, 4563 { MLXPLAT_CPLD_LPC_REG_WP2_OFFSET, 0x00 }, 4564 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 4565 { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 }, 4566 }; 4567 4568 static const struct reg_default mlxplat_mlxcpld_regmap_ng[] = { 4569 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 4570 { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 }, 4571 }; 4572 4573 static const struct reg_default mlxplat_mlxcpld_regmap_comex_default[] = { 4574 { MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET, 4575 MLXPLAT_CPLD_LOW_AGGRCX_MASK }, 4576 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 4577 }; 4578 4579 static const struct reg_default mlxplat_mlxcpld_regmap_ng400[] = { 4580 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 4581 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, 4582 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, 4583 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, 4584 }; 4585 4586 static const struct reg_default mlxplat_mlxcpld_regmap_eth_modular[] = { 4587 { MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 0x61 }, 4588 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 4589 { MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET, 0x00 }, 4590 { MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET, 0x00 }, 4591 { MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET, 0x00 }, 4592 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, 4593 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, 4594 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, 4595 { MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET, 4596 MLXPLAT_CPLD_AGGR_MASK_LC_LOW }, 4597 }; 4598 4599 struct mlxplat_mlxcpld_regmap_context { 4600 void __iomem *base; 4601 }; 4602 4603 static struct mlxplat_mlxcpld_regmap_context mlxplat_mlxcpld_regmap_ctx; 4604 4605 static int 4606 mlxplat_mlxcpld_reg_read(void *context, unsigned int reg, unsigned int *val) 4607 { 4608 struct mlxplat_mlxcpld_regmap_context *ctx = context; 4609 4610 *val = ioread8(ctx->base + reg); 4611 return 0; 4612 } 4613 4614 static int 4615 mlxplat_mlxcpld_reg_write(void *context, unsigned int reg, unsigned int val) 4616 { 4617 struct mlxplat_mlxcpld_regmap_context *ctx = context; 4618 4619 iowrite8(val, ctx->base + reg); 4620 return 0; 4621 } 4622 4623 static const struct regmap_config mlxplat_mlxcpld_regmap_config = { 4624 .reg_bits = 8, 4625 .val_bits = 8, 4626 .max_register = 255, 4627 .cache_type = REGCACHE_FLAT, 4628 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 4629 .readable_reg = mlxplat_mlxcpld_readable_reg, 4630 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 4631 .reg_defaults = mlxplat_mlxcpld_regmap_default, 4632 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_default), 4633 .reg_read = mlxplat_mlxcpld_reg_read, 4634 .reg_write = mlxplat_mlxcpld_reg_write, 4635 }; 4636 4637 static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng = { 4638 .reg_bits = 8, 4639 .val_bits = 8, 4640 .max_register = 255, 4641 .cache_type = REGCACHE_FLAT, 4642 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 4643 .readable_reg = mlxplat_mlxcpld_readable_reg, 4644 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 4645 .reg_defaults = mlxplat_mlxcpld_regmap_ng, 4646 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng), 4647 .reg_read = mlxplat_mlxcpld_reg_read, 4648 .reg_write = mlxplat_mlxcpld_reg_write, 4649 }; 4650 4651 static const struct regmap_config mlxplat_mlxcpld_regmap_config_comex = { 4652 .reg_bits = 8, 4653 .val_bits = 8, 4654 .max_register = 255, 4655 .cache_type = REGCACHE_FLAT, 4656 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 4657 .readable_reg = mlxplat_mlxcpld_readable_reg, 4658 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 4659 .reg_defaults = mlxplat_mlxcpld_regmap_comex_default, 4660 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_comex_default), 4661 .reg_read = mlxplat_mlxcpld_reg_read, 4662 .reg_write = mlxplat_mlxcpld_reg_write, 4663 }; 4664 4665 static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng400 = { 4666 .reg_bits = 8, 4667 .val_bits = 8, 4668 .max_register = 255, 4669 .cache_type = REGCACHE_FLAT, 4670 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 4671 .readable_reg = mlxplat_mlxcpld_readable_reg, 4672 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 4673 .reg_defaults = mlxplat_mlxcpld_regmap_ng400, 4674 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng400), 4675 .reg_read = mlxplat_mlxcpld_reg_read, 4676 .reg_write = mlxplat_mlxcpld_reg_write, 4677 }; 4678 4679 static const struct regmap_config mlxplat_mlxcpld_regmap_config_eth_modular = { 4680 .reg_bits = 8, 4681 .val_bits = 8, 4682 .max_register = 255, 4683 .cache_type = REGCACHE_FLAT, 4684 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 4685 .readable_reg = mlxplat_mlxcpld_readable_reg, 4686 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 4687 .reg_defaults = mlxplat_mlxcpld_regmap_eth_modular, 4688 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_eth_modular), 4689 .reg_read = mlxplat_mlxcpld_reg_read, 4690 .reg_write = mlxplat_mlxcpld_reg_write, 4691 }; 4692 4693 static struct resource mlxplat_mlxcpld_resources[] = { 4694 [0] = DEFINE_RES_IRQ_NAMED(MLXPLAT_CPLD_LPC_SYSIRQ, "mlxreg-hotplug"), 4695 }; 4696 4697 static struct platform_device *mlxplat_dev; 4698 static struct mlxreg_core_hotplug_platform_data *mlxplat_i2c; 4699 static struct mlxreg_core_hotplug_platform_data *mlxplat_hotplug; 4700 static struct mlxreg_core_platform_data *mlxplat_led; 4701 static struct mlxreg_core_platform_data *mlxplat_regs_io; 4702 static struct mlxreg_core_platform_data *mlxplat_fan; 4703 static struct mlxreg_core_platform_data 4704 *mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS]; 4705 static const struct regmap_config *mlxplat_regmap_config; 4706 4707 static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi) 4708 { 4709 int i; 4710 4711 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 4712 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 4713 mlxplat_mux_data = mlxplat_default_mux_data; 4714 for (i = 0; i < mlxplat_mux_num; i++) { 4715 mlxplat_mux_data[i].values = mlxplat_default_channels[i]; 4716 mlxplat_mux_data[i].n_values = 4717 ARRAY_SIZE(mlxplat_default_channels[i]); 4718 } 4719 mlxplat_hotplug = &mlxplat_mlxcpld_default_data; 4720 mlxplat_hotplug->deferred_nr = 4721 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 4722 mlxplat_led = &mlxplat_default_led_data; 4723 mlxplat_regs_io = &mlxplat_default_regs_io_data; 4724 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 4725 4726 return 1; 4727 } 4728 4729 static int __init mlxplat_dmi_default_wc_matched(const struct dmi_system_id *dmi) 4730 { 4731 int i; 4732 4733 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 4734 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 4735 mlxplat_mux_data = mlxplat_default_mux_data; 4736 for (i = 0; i < mlxplat_mux_num; i++) { 4737 mlxplat_mux_data[i].values = mlxplat_default_channels[i]; 4738 mlxplat_mux_data[i].n_values = 4739 ARRAY_SIZE(mlxplat_default_channels[i]); 4740 } 4741 mlxplat_hotplug = &mlxplat_mlxcpld_default_wc_data; 4742 mlxplat_hotplug->deferred_nr = 4743 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 4744 mlxplat_led = &mlxplat_default_led_wc_data; 4745 mlxplat_regs_io = &mlxplat_default_regs_io_data; 4746 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 4747 4748 return 1; 4749 } 4750 4751 static int __init mlxplat_dmi_default_eth_wc_blade_matched(const struct dmi_system_id *dmi) 4752 { 4753 int i; 4754 4755 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 4756 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 4757 mlxplat_mux_data = mlxplat_default_mux_data; 4758 for (i = 0; i < mlxplat_mux_num; i++) { 4759 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 4760 mlxplat_mux_data[i].n_values = 4761 ARRAY_SIZE(mlxplat_msn21xx_channels); 4762 } 4763 mlxplat_hotplug = &mlxplat_mlxcpld_default_wc_data; 4764 mlxplat_hotplug->deferred_nr = 4765 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 4766 mlxplat_led = &mlxplat_default_led_eth_wc_blade_data; 4767 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 4768 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 4769 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 4770 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 4771 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng; 4772 4773 return 1; 4774 } 4775 4776 static int __init mlxplat_dmi_msn21xx_matched(const struct dmi_system_id *dmi) 4777 { 4778 int i; 4779 4780 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 4781 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 4782 mlxplat_mux_data = mlxplat_default_mux_data; 4783 for (i = 0; i < mlxplat_mux_num; i++) { 4784 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 4785 mlxplat_mux_data[i].n_values = 4786 ARRAY_SIZE(mlxplat_msn21xx_channels); 4787 } 4788 mlxplat_hotplug = &mlxplat_mlxcpld_msn21xx_data; 4789 mlxplat_hotplug->deferred_nr = 4790 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 4791 mlxplat_led = &mlxplat_msn21xx_led_data; 4792 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 4793 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 4794 4795 return 1; 4796 } 4797 4798 static int __init mlxplat_dmi_msn274x_matched(const struct dmi_system_id *dmi) 4799 { 4800 int i; 4801 4802 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 4803 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 4804 mlxplat_mux_data = mlxplat_default_mux_data; 4805 for (i = 0; i < mlxplat_mux_num; i++) { 4806 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 4807 mlxplat_mux_data[i].n_values = 4808 ARRAY_SIZE(mlxplat_msn21xx_channels); 4809 } 4810 mlxplat_hotplug = &mlxplat_mlxcpld_msn274x_data; 4811 mlxplat_hotplug->deferred_nr = 4812 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 4813 mlxplat_led = &mlxplat_default_led_data; 4814 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 4815 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 4816 4817 return 1; 4818 } 4819 4820 static int __init mlxplat_dmi_msn201x_matched(const struct dmi_system_id *dmi) 4821 { 4822 int i; 4823 4824 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 4825 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 4826 mlxplat_mux_data = mlxplat_default_mux_data; 4827 for (i = 0; i < mlxplat_mux_num; i++) { 4828 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 4829 mlxplat_mux_data[i].n_values = 4830 ARRAY_SIZE(mlxplat_msn21xx_channels); 4831 } 4832 mlxplat_hotplug = &mlxplat_mlxcpld_msn201x_data; 4833 mlxplat_hotplug->deferred_nr = 4834 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 4835 mlxplat_led = &mlxplat_msn21xx_led_data; 4836 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 4837 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 4838 4839 return 1; 4840 } 4841 4842 static int __init mlxplat_dmi_qmb7xx_matched(const struct dmi_system_id *dmi) 4843 { 4844 int i; 4845 4846 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 4847 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 4848 mlxplat_mux_data = mlxplat_default_mux_data; 4849 for (i = 0; i < mlxplat_mux_num; i++) { 4850 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 4851 mlxplat_mux_data[i].n_values = 4852 ARRAY_SIZE(mlxplat_msn21xx_channels); 4853 } 4854 mlxplat_hotplug = &mlxplat_mlxcpld_default_ng_data; 4855 mlxplat_hotplug->deferred_nr = 4856 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 4857 mlxplat_led = &mlxplat_default_ng_led_data; 4858 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 4859 mlxplat_fan = &mlxplat_default_fan_data; 4860 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 4861 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 4862 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 4863 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng; 4864 4865 return 1; 4866 } 4867 4868 static int __init mlxplat_dmi_comex_matched(const struct dmi_system_id *dmi) 4869 { 4870 int i; 4871 4872 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM; 4873 mlxplat_mux_num = ARRAY_SIZE(mlxplat_extended_mux_data); 4874 mlxplat_mux_data = mlxplat_extended_mux_data; 4875 for (i = 0; i < mlxplat_mux_num; i++) { 4876 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 4877 mlxplat_mux_data[i].n_values = 4878 ARRAY_SIZE(mlxplat_msn21xx_channels); 4879 } 4880 mlxplat_hotplug = &mlxplat_mlxcpld_comex_data; 4881 mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM; 4882 mlxplat_led = &mlxplat_comex_100G_led_data; 4883 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 4884 mlxplat_fan = &mlxplat_default_fan_data; 4885 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 4886 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 4887 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_comex; 4888 4889 return 1; 4890 } 4891 4892 static int __init mlxplat_dmi_ng400_matched(const struct dmi_system_id *dmi) 4893 { 4894 int i; 4895 4896 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 4897 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 4898 mlxplat_mux_data = mlxplat_default_mux_data; 4899 for (i = 0; i < mlxplat_mux_num; i++) { 4900 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 4901 mlxplat_mux_data[i].n_values = 4902 ARRAY_SIZE(mlxplat_msn21xx_channels); 4903 } 4904 mlxplat_hotplug = &mlxplat_mlxcpld_ext_data; 4905 mlxplat_hotplug->deferred_nr = 4906 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 4907 mlxplat_led = &mlxplat_default_ng_led_data; 4908 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 4909 mlxplat_fan = &mlxplat_default_fan_data; 4910 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 4911 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 4912 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 4913 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; 4914 4915 return 1; 4916 } 4917 4918 static int __init mlxplat_dmi_modular_matched(const struct dmi_system_id *dmi) 4919 { 4920 int i; 4921 4922 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 4923 mlxplat_mux_num = ARRAY_SIZE(mlxplat_modular_mux_data); 4924 mlxplat_mux_data = mlxplat_modular_mux_data; 4925 mlxplat_hotplug = &mlxplat_mlxcpld_modular_data; 4926 mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_CH4_ETH_MODULAR; 4927 mlxplat_led = &mlxplat_modular_led_data; 4928 mlxplat_regs_io = &mlxplat_modular_regs_io_data; 4929 mlxplat_fan = &mlxplat_default_fan_data; 4930 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 4931 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 4932 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 4933 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_eth_modular; 4934 4935 return 1; 4936 } 4937 4938 static int __init mlxplat_dmi_nvlink_blade_matched(const struct dmi_system_id *dmi) 4939 { 4940 int i; 4941 4942 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 4943 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 4944 mlxplat_mux_data = mlxplat_default_mux_data; 4945 mlxplat_hotplug = &mlxplat_mlxcpld_nvlink_blade_data; 4946 mlxplat_hotplug->deferred_nr = 4947 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 4948 for (i = 0; i < mlxplat_mux_num; i++) { 4949 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 4950 mlxplat_mux_data[i].n_values = 4951 ARRAY_SIZE(mlxplat_msn21xx_channels); 4952 } 4953 mlxplat_regs_io = &mlxplat_nvlink_blade_regs_io_data; 4954 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 4955 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; 4956 4957 return 1; 4958 } 4959 4960 static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { 4961 { 4962 .callback = mlxplat_dmi_default_wc_matched, 4963 .matches = { 4964 DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"), 4965 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI138"), 4966 }, 4967 }, 4968 { 4969 .callback = mlxplat_dmi_default_matched, 4970 .matches = { 4971 DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"), 4972 }, 4973 }, 4974 { 4975 .callback = mlxplat_dmi_msn21xx_matched, 4976 .matches = { 4977 DMI_MATCH(DMI_BOARD_NAME, "VMOD0002"), 4978 }, 4979 }, 4980 { 4981 .callback = mlxplat_dmi_msn274x_matched, 4982 .matches = { 4983 DMI_MATCH(DMI_BOARD_NAME, "VMOD0003"), 4984 }, 4985 }, 4986 { 4987 .callback = mlxplat_dmi_msn201x_matched, 4988 .matches = { 4989 DMI_MATCH(DMI_BOARD_NAME, "VMOD0004"), 4990 }, 4991 }, 4992 { 4993 .callback = mlxplat_dmi_default_eth_wc_blade_matched, 4994 .matches = { 4995 DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"), 4996 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI139"), 4997 }, 4998 }, 4999 { 5000 .callback = mlxplat_dmi_qmb7xx_matched, 5001 .matches = { 5002 DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"), 5003 }, 5004 }, 5005 { 5006 .callback = mlxplat_dmi_qmb7xx_matched, 5007 .matches = { 5008 DMI_MATCH(DMI_BOARD_NAME, "VMOD0007"), 5009 }, 5010 }, 5011 { 5012 .callback = mlxplat_dmi_comex_matched, 5013 .matches = { 5014 DMI_MATCH(DMI_BOARD_NAME, "VMOD0009"), 5015 }, 5016 }, 5017 { 5018 .callback = mlxplat_dmi_ng400_matched, 5019 .matches = { 5020 DMI_MATCH(DMI_BOARD_NAME, "VMOD0010"), 5021 }, 5022 }, 5023 { 5024 .callback = mlxplat_dmi_modular_matched, 5025 .matches = { 5026 DMI_MATCH(DMI_BOARD_NAME, "VMOD0011"), 5027 }, 5028 }, 5029 { 5030 .callback = mlxplat_dmi_nvlink_blade_matched, 5031 .matches = { 5032 DMI_MATCH(DMI_BOARD_NAME, "VMOD0015"), 5033 }, 5034 }, 5035 { 5036 .callback = mlxplat_dmi_msn274x_matched, 5037 .matches = { 5038 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 5039 DMI_MATCH(DMI_PRODUCT_NAME, "MSN274"), 5040 }, 5041 }, 5042 { 5043 .callback = mlxplat_dmi_default_matched, 5044 .matches = { 5045 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 5046 DMI_MATCH(DMI_PRODUCT_NAME, "MSN24"), 5047 }, 5048 }, 5049 { 5050 .callback = mlxplat_dmi_default_matched, 5051 .matches = { 5052 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 5053 DMI_MATCH(DMI_PRODUCT_NAME, "MSN27"), 5054 }, 5055 }, 5056 { 5057 .callback = mlxplat_dmi_default_matched, 5058 .matches = { 5059 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 5060 DMI_MATCH(DMI_PRODUCT_NAME, "MSB"), 5061 }, 5062 }, 5063 { 5064 .callback = mlxplat_dmi_default_matched, 5065 .matches = { 5066 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 5067 DMI_MATCH(DMI_PRODUCT_NAME, "MSX"), 5068 }, 5069 }, 5070 { 5071 .callback = mlxplat_dmi_msn21xx_matched, 5072 .matches = { 5073 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 5074 DMI_MATCH(DMI_PRODUCT_NAME, "MSN21"), 5075 }, 5076 }, 5077 { 5078 .callback = mlxplat_dmi_msn201x_matched, 5079 .matches = { 5080 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 5081 DMI_MATCH(DMI_PRODUCT_NAME, "MSN201"), 5082 }, 5083 }, 5084 { 5085 .callback = mlxplat_dmi_qmb7xx_matched, 5086 .matches = { 5087 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 5088 DMI_MATCH(DMI_PRODUCT_NAME, "MQM87"), 5089 }, 5090 }, 5091 { 5092 .callback = mlxplat_dmi_qmb7xx_matched, 5093 .matches = { 5094 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 5095 DMI_MATCH(DMI_PRODUCT_NAME, "MSN37"), 5096 }, 5097 }, 5098 { 5099 .callback = mlxplat_dmi_qmb7xx_matched, 5100 .matches = { 5101 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 5102 DMI_MATCH(DMI_PRODUCT_NAME, "MSN34"), 5103 }, 5104 }, 5105 { 5106 .callback = mlxplat_dmi_qmb7xx_matched, 5107 .matches = { 5108 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 5109 DMI_MATCH(DMI_PRODUCT_NAME, "MSN38"), 5110 }, 5111 }, 5112 { } 5113 }; 5114 5115 MODULE_DEVICE_TABLE(dmi, mlxplat_dmi_table); 5116 5117 static int mlxplat_mlxcpld_verify_bus_topology(int *nr) 5118 { 5119 struct i2c_adapter *search_adap; 5120 int shift, i; 5121 5122 /* Scan adapters from expected id to verify it is free. */ 5123 *nr = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; 5124 for (i = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; i < 5125 mlxplat_max_adap_num; i++) { 5126 search_adap = i2c_get_adapter(i); 5127 if (search_adap) { 5128 i2c_put_adapter(search_adap); 5129 continue; 5130 } 5131 5132 /* Return if expected parent adapter is free. */ 5133 if (i == MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR) 5134 return 0; 5135 break; 5136 } 5137 5138 /* Return with error if free id for adapter is not found. */ 5139 if (i == mlxplat_max_adap_num) 5140 return -ENODEV; 5141 5142 /* Shift adapter ids, since expected parent adapter is not free. */ 5143 *nr = i; 5144 for (i = 0; i < mlxplat_mux_num; i++) { 5145 shift = *nr - mlxplat_mux_data[i].parent; 5146 mlxplat_mux_data[i].parent = *nr; 5147 mlxplat_mux_data[i].base_nr += shift; 5148 if (shift > 0) 5149 mlxplat_hotplug->shift_nr = shift; 5150 } 5151 5152 return 0; 5153 } 5154 5155 static int mlxplat_mlxcpld_check_wd_capability(void *regmap) 5156 { 5157 u32 regval; 5158 int i, rc; 5159 5160 rc = regmap_read(regmap, MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 5161 ®val); 5162 if (rc) 5163 return rc; 5164 5165 if (!(regval & ~MLXPLAT_CPLD_WD_CPBLTY_MASK)) { 5166 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type3); i++) { 5167 if (mlxplat_wd_data[i]) 5168 mlxplat_wd_data[i] = 5169 &mlxplat_mlxcpld_wd_set_type3[i]; 5170 } 5171 } 5172 5173 return 0; 5174 } 5175 5176 static int __init mlxplat_init(void) 5177 { 5178 struct mlxplat_priv *priv; 5179 int i, j, nr, err; 5180 5181 if (!dmi_check_system(mlxplat_dmi_table)) 5182 return -ENODEV; 5183 5184 mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, PLATFORM_DEVID_NONE, 5185 mlxplat_lpc_resources, 5186 ARRAY_SIZE(mlxplat_lpc_resources)); 5187 5188 if (IS_ERR(mlxplat_dev)) 5189 return PTR_ERR(mlxplat_dev); 5190 5191 priv = devm_kzalloc(&mlxplat_dev->dev, sizeof(struct mlxplat_priv), 5192 GFP_KERNEL); 5193 if (!priv) { 5194 err = -ENOMEM; 5195 goto fail_alloc; 5196 } 5197 platform_set_drvdata(mlxplat_dev, priv); 5198 5199 mlxplat_mlxcpld_regmap_ctx.base = devm_ioport_map(&mlxplat_dev->dev, 5200 mlxplat_lpc_resources[1].start, 1); 5201 if (!mlxplat_mlxcpld_regmap_ctx.base) { 5202 err = -ENOMEM; 5203 goto fail_alloc; 5204 } 5205 5206 if (!mlxplat_regmap_config) 5207 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config; 5208 5209 priv->regmap = devm_regmap_init(&mlxplat_dev->dev, NULL, 5210 &mlxplat_mlxcpld_regmap_ctx, 5211 mlxplat_regmap_config); 5212 if (IS_ERR(priv->regmap)) { 5213 err = PTR_ERR(priv->regmap); 5214 goto fail_alloc; 5215 } 5216 5217 err = mlxplat_mlxcpld_verify_bus_topology(&nr); 5218 if (nr < 0) 5219 goto fail_alloc; 5220 5221 nr = (nr == mlxplat_max_adap_num) ? -1 : nr; 5222 if (mlxplat_i2c) 5223 mlxplat_i2c->regmap = priv->regmap; 5224 priv->pdev_i2c = platform_device_register_resndata(&mlxplat_dev->dev, "i2c_mlxcpld", 5225 nr, mlxplat_mlxcpld_resources, 5226 ARRAY_SIZE(mlxplat_mlxcpld_resources), 5227 mlxplat_i2c, sizeof(*mlxplat_i2c)); 5228 if (IS_ERR(priv->pdev_i2c)) { 5229 err = PTR_ERR(priv->pdev_i2c); 5230 goto fail_alloc; 5231 } 5232 5233 for (i = 0; i < mlxplat_mux_num; i++) { 5234 priv->pdev_mux[i] = platform_device_register_resndata(&priv->pdev_i2c->dev, 5235 "i2c-mux-reg", i, NULL, 0, 5236 &mlxplat_mux_data[i], 5237 sizeof(mlxplat_mux_data[i])); 5238 if (IS_ERR(priv->pdev_mux[i])) { 5239 err = PTR_ERR(priv->pdev_mux[i]); 5240 goto fail_platform_mux_register; 5241 } 5242 } 5243 5244 /* Add hotplug driver */ 5245 if (mlxplat_hotplug) { 5246 mlxplat_hotplug->regmap = priv->regmap; 5247 priv->pdev_hotplug = 5248 platform_device_register_resndata(&mlxplat_dev->dev, 5249 "mlxreg-hotplug", PLATFORM_DEVID_NONE, 5250 mlxplat_mlxcpld_resources, 5251 ARRAY_SIZE(mlxplat_mlxcpld_resources), 5252 mlxplat_hotplug, sizeof(*mlxplat_hotplug)); 5253 if (IS_ERR(priv->pdev_hotplug)) { 5254 err = PTR_ERR(priv->pdev_hotplug); 5255 goto fail_platform_mux_register; 5256 } 5257 } 5258 5259 /* Set default registers. */ 5260 for (j = 0; j < mlxplat_regmap_config->num_reg_defaults; j++) { 5261 err = regmap_write(priv->regmap, 5262 mlxplat_regmap_config->reg_defaults[j].reg, 5263 mlxplat_regmap_config->reg_defaults[j].def); 5264 if (err) 5265 goto fail_platform_mux_register; 5266 } 5267 5268 /* Add LED driver. */ 5269 if (mlxplat_led) { 5270 mlxplat_led->regmap = priv->regmap; 5271 priv->pdev_led = 5272 platform_device_register_resndata(&mlxplat_dev->dev, "leds-mlxreg", 5273 PLATFORM_DEVID_NONE, NULL, 0, mlxplat_led, 5274 sizeof(*mlxplat_led)); 5275 if (IS_ERR(priv->pdev_led)) { 5276 err = PTR_ERR(priv->pdev_led); 5277 goto fail_platform_hotplug_register; 5278 } 5279 } 5280 5281 /* Add registers io access driver. */ 5282 if (mlxplat_regs_io) { 5283 mlxplat_regs_io->regmap = priv->regmap; 5284 priv->pdev_io_regs = platform_device_register_resndata(&mlxplat_dev->dev, 5285 "mlxreg-io", 5286 PLATFORM_DEVID_NONE, NULL, 5287 0, mlxplat_regs_io, 5288 sizeof(*mlxplat_regs_io)); 5289 if (IS_ERR(priv->pdev_io_regs)) { 5290 err = PTR_ERR(priv->pdev_io_regs); 5291 goto fail_platform_led_register; 5292 } 5293 } 5294 5295 /* Add FAN driver. */ 5296 if (mlxplat_fan) { 5297 mlxplat_fan->regmap = priv->regmap; 5298 priv->pdev_fan = platform_device_register_resndata(&mlxplat_dev->dev, "mlxreg-fan", 5299 PLATFORM_DEVID_NONE, NULL, 0, 5300 mlxplat_fan, 5301 sizeof(*mlxplat_fan)); 5302 if (IS_ERR(priv->pdev_fan)) { 5303 err = PTR_ERR(priv->pdev_fan); 5304 goto fail_platform_io_regs_register; 5305 } 5306 } 5307 5308 /* Add WD drivers. */ 5309 err = mlxplat_mlxcpld_check_wd_capability(priv->regmap); 5310 if (err) 5311 goto fail_platform_wd_register; 5312 for (j = 0; j < MLXPLAT_CPLD_WD_MAX_DEVS; j++) { 5313 if (mlxplat_wd_data[j]) { 5314 mlxplat_wd_data[j]->regmap = priv->regmap; 5315 priv->pdev_wd[j] = 5316 platform_device_register_resndata(&mlxplat_dev->dev, "mlx-wdt", j, 5317 NULL, 0, mlxplat_wd_data[j], 5318 sizeof(*mlxplat_wd_data[j])); 5319 if (IS_ERR(priv->pdev_wd[j])) { 5320 err = PTR_ERR(priv->pdev_wd[j]); 5321 goto fail_platform_wd_register; 5322 } 5323 } 5324 } 5325 5326 /* Sync registers with hardware. */ 5327 regcache_mark_dirty(priv->regmap); 5328 err = regcache_sync(priv->regmap); 5329 if (err) 5330 goto fail_platform_wd_register; 5331 5332 return 0; 5333 5334 fail_platform_wd_register: 5335 while (--j >= 0) 5336 platform_device_unregister(priv->pdev_wd[j]); 5337 if (mlxplat_fan) 5338 platform_device_unregister(priv->pdev_fan); 5339 fail_platform_io_regs_register: 5340 if (mlxplat_regs_io) 5341 platform_device_unregister(priv->pdev_io_regs); 5342 fail_platform_led_register: 5343 if (mlxplat_led) 5344 platform_device_unregister(priv->pdev_led); 5345 fail_platform_hotplug_register: 5346 if (mlxplat_hotplug) 5347 platform_device_unregister(priv->pdev_hotplug); 5348 fail_platform_mux_register: 5349 while (--i >= 0) 5350 platform_device_unregister(priv->pdev_mux[i]); 5351 platform_device_unregister(priv->pdev_i2c); 5352 fail_alloc: 5353 platform_device_unregister(mlxplat_dev); 5354 5355 return err; 5356 } 5357 module_init(mlxplat_init); 5358 5359 static void __exit mlxplat_exit(void) 5360 { 5361 struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); 5362 int i; 5363 5364 for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0 ; i--) 5365 platform_device_unregister(priv->pdev_wd[i]); 5366 if (priv->pdev_fan) 5367 platform_device_unregister(priv->pdev_fan); 5368 if (priv->pdev_io_regs) 5369 platform_device_unregister(priv->pdev_io_regs); 5370 if (priv->pdev_led) 5371 platform_device_unregister(priv->pdev_led); 5372 if (priv->pdev_hotplug) 5373 platform_device_unregister(priv->pdev_hotplug); 5374 5375 for (i = mlxplat_mux_num - 1; i >= 0 ; i--) 5376 platform_device_unregister(priv->pdev_mux[i]); 5377 5378 platform_device_unregister(priv->pdev_i2c); 5379 platform_device_unregister(mlxplat_dev); 5380 } 5381 module_exit(mlxplat_exit); 5382 5383 MODULE_AUTHOR("Vadim Pasternak (vadimp@mellanox.com)"); 5384 MODULE_DESCRIPTION("Mellanox platform driver"); 5385 MODULE_LICENSE("Dual BSD/GPL"); 5386