1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* 3 * Mellanox platform driver 4 * 5 * Copyright (C) 2016-2018 Mellanox Technologies 6 * Copyright (C) 2016-2018 Vadim Pasternak <vadimp@mellanox.com> 7 */ 8 9 #include <linux/device.h> 10 #include <linux/dmi.h> 11 #include <linux/i2c.h> 12 #include <linux/i2c-mux.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/platform_device.h> 17 #include <linux/platform_data/i2c-mux-reg.h> 18 #include <linux/platform_data/mlxreg.h> 19 #include <linux/reboot.h> 20 #include <linux/regmap.h> 21 22 #define MLX_PLAT_DEVICE_NAME "mlxplat" 23 24 /* LPC bus IO offsets */ 25 #define MLXPLAT_CPLD_LPC_I2C_BASE_ADRR 0x2000 26 #define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500 27 #define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET 0x00 28 #define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET 0x01 29 #define MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET 0x02 30 #define MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET 0x03 31 #define MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET 0x04 32 #define MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET 0x05 33 #define MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET 0x06 34 #define MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET 0x07 35 #define MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET 0x08 36 #define MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET 0x09 37 #define MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET 0x0a 38 #define MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET 0x0b 39 #define MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET 0x17 40 #define MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET 0x19 41 #define MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET 0x1c 42 #define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d 43 #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e 44 #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0x1f 45 #define MLXPLAT_CPLD_LPC_REG_LED1_OFFSET 0x20 46 #define MLXPLAT_CPLD_LPC_REG_LED2_OFFSET 0x21 47 #define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22 48 #define MLXPLAT_CPLD_LPC_REG_LED4_OFFSET 0x23 49 #define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24 50 #define MLXPLAT_CPLD_LPC_REG_LED6_OFFSET 0x25 51 #define MLXPLAT_CPLD_LPC_REG_LED7_OFFSET 0x26 52 #define MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION 0x2a 53 #define MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET 0x2b 54 #define MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET 0x2d 55 #define MLXPLAT_CPLD_LPC_REG_GP0_OFFSET 0x2e 56 #define MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET 0x2f 57 #define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET 0x30 58 #define MLXPLAT_CPLD_LPC_REG_WP1_OFFSET 0x31 59 #define MLXPLAT_CPLD_LPC_REG_GP2_OFFSET 0x32 60 #define MLXPLAT_CPLD_LPC_REG_WP2_OFFSET 0x33 61 #define MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE 0x34 62 #define MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET 0x35 63 #define MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET 0x36 64 #define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET 0x37 65 #define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a 66 #define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b 67 #define MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET 0x3c 68 #define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40 69 #define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41 70 #define MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET 0x42 71 #define MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET 0x43 72 #define MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET 0x44 73 #define MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET 0x45 74 #define MLXPLAT_CPLD_LPC_REG_BRD_OFFSET 0x47 75 #define MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET 0x48 76 #define MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET 0x49 77 #define MLXPLAT_CPLD_LPC_REG_GWP_OFFSET 0x4a 78 #define MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET 0x4b 79 #define MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET 0x4c 80 #define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50 81 #define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET 0x51 82 #define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET 0x52 83 #define MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET 0x53 84 #define MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET 0x54 85 #define MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET 0x55 86 #define MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET 0x56 87 #define MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET 0x57 88 #define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET 0x58 89 #define MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET 0x59 90 #define MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET 0x5a 91 #define MLXPLAT_CPLD_LPC_REG_PWR_OFFSET 0x64 92 #define MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET 0x65 93 #define MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET 0x66 94 #define MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET 0x70 95 #define MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET 0x71 96 #define MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET 0x72 97 #define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88 98 #define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89 99 #define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a 100 #define MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET 0x8e 101 #define MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET 0x8f 102 #define MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET 0x90 103 #define MLXPLAT_CPLD_LPC_REG_EROT_OFFSET 0x91 104 #define MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET 0x92 105 #define MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET 0x93 106 #define MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET 0x94 107 #define MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET 0x95 108 #define MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET 0x96 109 #define MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET 0x97 110 #define MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET 0x98 111 #define MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET 0x99 112 #define MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET 0x9a 113 #define MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET 0x9b 114 #define MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET 0x9c 115 #define MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET 0x9d 116 #define MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET 0x9e 117 #define MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET 0x9f 118 #define MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET 0xa0 119 #define MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET 0xa1 120 #define MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET 0xa2 121 #define MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET 0xa3 122 #define MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET 0xa4 123 #define MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET 0xa5 124 #define MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET 0xa6 125 #define MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET 0xa7 126 #define MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET 0xa8 127 #define MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET 0xa9 128 #define MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET 0xaa 129 #define MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET 0xab 130 #define MLXPLAT_CPLD_LPC_REG_LC_PWR_ON 0xb2 131 #define MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET 0xb6 132 #define MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET 0xb7 133 #define MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET 0xb8 134 #define MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET 0xb9 135 #define MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET 0xc2 136 #define MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT 0xc3 137 #define MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET 0xc4 138 #define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET 0xc7 139 #define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET 0xc8 140 #define MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET 0xc9 141 #define MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET 0xcb 142 #define MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET 0xcd 143 #define MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET 0xce 144 #define MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET 0xcf 145 #define MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET 0xd1 146 #define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET 0xd2 147 #define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET 0xd3 148 #define MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET 0xd9 149 #define MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET 0xdb 150 #define MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET 0xda 151 #define MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET 0xdc 152 #define MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET 0xdd 153 #define MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET 0xde 154 #define MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET 0xdf 155 #define MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET 0xe0 156 #define MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET 0xe1 157 #define MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET 0xe2 158 #define MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET 0xe3 159 #define MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET 0xe4 160 #define MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET 0xe5 161 #define MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET 0xe6 162 #define MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET 0xe7 163 #define MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET 0xe8 164 #define MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET 0xe9 165 #define MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET 0xea 166 #define MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET 0xeb 167 #define MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET 0xec 168 #define MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET 0xed 169 #define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0xee 170 #define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0xef 171 #define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0xf0 172 #define MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET 0xf1 173 #define MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET 0xf2 174 #define MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET 0xf3 175 #define MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET 0xf4 176 #define MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET 0xf5 177 #define MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET 0xf6 178 #define MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET 0xf7 179 #define MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET 0xf8 180 #define MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET 0xf9 181 #define MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET 0xfa 182 #define MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET 0xfb 183 #define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0xfc 184 #define MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET 0xfd 185 #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100 186 187 #define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL 188 #define MLXPLAT_CPLD_LPC_REG1 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 189 MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET) | \ 190 MLXPLAT_CPLD_LPC_PIO_OFFSET) 191 #define MLXPLAT_CPLD_LPC_REG2 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 192 MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET) | \ 193 MLXPLAT_CPLD_LPC_PIO_OFFSET) 194 #define MLXPLAT_CPLD_LPC_REG3 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 195 MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET) | \ 196 MLXPLAT_CPLD_LPC_PIO_OFFSET) 197 #define MLXPLAT_CPLD_LPC_REG4 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 198 MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET) | \ 199 MLXPLAT_CPLD_LPC_PIO_OFFSET) 200 201 /* Masks for aggregation, psu, pwr and fan event in CPLD related registers. */ 202 #define MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF 0x04 203 #define MLXPLAT_CPLD_AGGR_PSU_MASK_DEF 0x08 204 #define MLXPLAT_CPLD_AGGR_PWR_MASK_DEF 0x08 205 #define MLXPLAT_CPLD_AGGR_FAN_MASK_DEF 0x40 206 #define MLXPLAT_CPLD_AGGR_MASK_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \ 207 MLXPLAT_CPLD_AGGR_PSU_MASK_DEF | \ 208 MLXPLAT_CPLD_AGGR_FAN_MASK_DEF) 209 #define MLXPLAT_CPLD_AGGR_ASIC_MASK_NG 0x01 210 #define MLXPLAT_CPLD_AGGR_MASK_NG_DEF 0x04 211 #define MLXPLAT_CPLD_AGGR_MASK_COMEX BIT(0) 212 #define MLXPLAT_CPLD_AGGR_MASK_LC BIT(3) 213 #define MLXPLAT_CPLD_AGGR_MASK_MODULAR (MLXPLAT_CPLD_AGGR_MASK_NG_DEF | \ 214 MLXPLAT_CPLD_AGGR_MASK_COMEX | \ 215 MLXPLAT_CPLD_AGGR_MASK_LC) 216 #define MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT BIT(0) 217 #define MLXPLAT_CPLD_AGGR_MASK_LC_RDY BIT(1) 218 #define MLXPLAT_CPLD_AGGR_MASK_LC_PG BIT(2) 219 #define MLXPLAT_CPLD_AGGR_MASK_LC_SCRD BIT(3) 220 #define MLXPLAT_CPLD_AGGR_MASK_LC_SYNC BIT(4) 221 #define MLXPLAT_CPLD_AGGR_MASK_LC_ACT BIT(5) 222 #define MLXPLAT_CPLD_AGGR_MASK_LC_SDWN BIT(6) 223 #define MLXPLAT_CPLD_AGGR_MASK_LC_LOW (MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT | \ 224 MLXPLAT_CPLD_AGGR_MASK_LC_RDY | \ 225 MLXPLAT_CPLD_AGGR_MASK_LC_PG | \ 226 MLXPLAT_CPLD_AGGR_MASK_LC_SCRD | \ 227 MLXPLAT_CPLD_AGGR_MASK_LC_SYNC | \ 228 MLXPLAT_CPLD_AGGR_MASK_LC_ACT | \ 229 MLXPLAT_CPLD_AGGR_MASK_LC_SDWN) 230 #define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc1 231 #define MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2 BIT(2) 232 #define MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT GENMASK(5, 4) 233 #define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6) 234 #define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0) 235 #define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0) 236 #define MLXPLAT_CPLD_PSU_EXT_MASK GENMASK(3, 0) 237 #define MLXPLAT_CPLD_PWR_EXT_MASK GENMASK(3, 0) 238 #define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0) 239 #define MLXPLAT_CPLD_ASIC_MASK GENMASK(1, 0) 240 #define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(6, 0) 241 #define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4) 242 #define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0) 243 #define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4) 244 #define MLXPLAT_CPLD_GWP_MASK GENMASK(0, 0) 245 #define MLXPLAT_CPLD_EROT_MASK GENMASK(1, 0) 246 #define MLXPLAT_CPLD_FU_CAP_MASK GENMASK(1, 0) 247 #define MLXPLAT_CPLD_PWR_BUTTON_MASK BIT(0) 248 #define MLXPLAT_CPLD_LATCH_RST_MASK BIT(6) 249 #define MLXPLAT_CPLD_THERMAL1_PDB_MASK BIT(3) 250 #define MLXPLAT_CPLD_THERMAL2_PDB_MASK BIT(4) 251 #define MLXPLAT_CPLD_INTRUSION_MASK BIT(6) 252 #define MLXPLAT_CPLD_PWM_PG_MASK BIT(7) 253 #define MLXPLAT_CPLD_L1_CHA_HEALTH_MASK (MLXPLAT_CPLD_THERMAL1_PDB_MASK | \ 254 MLXPLAT_CPLD_THERMAL2_PDB_MASK | \ 255 MLXPLAT_CPLD_INTRUSION_MASK |\ 256 MLXPLAT_CPLD_PWM_PG_MASK) 257 #define MLXPLAT_CPLD_I2C_CAP_BIT 0x04 258 #define MLXPLAT_CPLD_I2C_CAP_MASK GENMASK(5, MLXPLAT_CPLD_I2C_CAP_BIT) 259 #define MLXPLAT_CPLD_SYS_RESET_MASK BIT(0) 260 261 /* Masks for aggregation for comex carriers */ 262 #define MLXPLAT_CPLD_AGGR_MASK_CARRIER BIT(1) 263 #define MLXPLAT_CPLD_AGGR_MASK_CARR_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \ 264 MLXPLAT_CPLD_AGGR_MASK_CARRIER) 265 #define MLXPLAT_CPLD_LOW_AGGRCX_MASK 0xc1 266 267 /* Masks for aggregation for modular systems */ 268 #define MLXPLAT_CPLD_LPC_LC_MASK GENMASK(7, 0) 269 270 #define MLXPLAT_CPLD_HALT_MASK BIT(3) 271 #define MLXPLAT_CPLD_RESET_MASK GENMASK(7, 1) 272 273 /* Default I2C parent bus number */ 274 #define MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR 1 275 276 /* Maximum number of possible physical buses equipped on system */ 277 #define MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM 16 278 #define MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM 24 279 280 /* Number of channels in group */ 281 #define MLXPLAT_CPLD_GRP_CHNL_NUM 8 282 283 /* Start channel numbers */ 284 #define MLXPLAT_CPLD_CH1 2 285 #define MLXPLAT_CPLD_CH2 10 286 #define MLXPLAT_CPLD_CH3 18 287 #define MLXPLAT_CPLD_CH2_ETH_MODULAR 3 288 #define MLXPLAT_CPLD_CH3_ETH_MODULAR 43 289 #define MLXPLAT_CPLD_CH4_ETH_MODULAR 51 290 #define MLXPLAT_CPLD_CH2_RACK_SWITCH 18 291 #define MLXPLAT_CPLD_CH2_NG800 34 292 293 /* Number of LPC attached MUX platform devices */ 294 #define MLXPLAT_CPLD_LPC_MUX_DEVS 4 295 296 /* Hotplug devices adapter numbers */ 297 #define MLXPLAT_CPLD_NR_NONE -1 298 #define MLXPLAT_CPLD_PSU_DEFAULT_NR 10 299 #define MLXPLAT_CPLD_PSU_MSNXXXX_NR 4 300 #define MLXPLAT_CPLD_FAN1_DEFAULT_NR 11 301 #define MLXPLAT_CPLD_FAN2_DEFAULT_NR 12 302 #define MLXPLAT_CPLD_FAN3_DEFAULT_NR 13 303 #define MLXPLAT_CPLD_FAN4_DEFAULT_NR 14 304 #define MLXPLAT_CPLD_NR_ASIC 3 305 #define MLXPLAT_CPLD_NR_LC_BASE 34 306 307 #define MLXPLAT_CPLD_NR_LC_SET(nr) (MLXPLAT_CPLD_NR_LC_BASE + (nr)) 308 #define MLXPLAT_CPLD_LC_ADDR 0x32 309 310 /* Masks and default values for watchdogs */ 311 #define MLXPLAT_CPLD_WD1_CLEAR_MASK GENMASK(7, 1) 312 #define MLXPLAT_CPLD_WD2_CLEAR_MASK (GENMASK(7, 0) & ~BIT(1)) 313 314 #define MLXPLAT_CPLD_WD_TYPE1_TO_MASK GENMASK(7, 4) 315 #define MLXPLAT_CPLD_WD_TYPE2_TO_MASK 0 316 #define MLXPLAT_CPLD_WD_RESET_ACT_MASK GENMASK(7, 1) 317 #define MLXPLAT_CPLD_WD_FAN_ACT_MASK (GENMASK(7, 0) & ~BIT(4)) 318 #define MLXPLAT_CPLD_WD_COUNT_ACT_MASK (GENMASK(7, 0) & ~BIT(7)) 319 #define MLXPLAT_CPLD_WD_CPBLTY_MASK (GENMASK(7, 0) & ~BIT(6)) 320 #define MLXPLAT_CPLD_WD_DFLT_TIMEOUT 30 321 #define MLXPLAT_CPLD_WD3_DFLT_TIMEOUT 600 322 #define MLXPLAT_CPLD_WD_MAX_DEVS 2 323 324 #define MLXPLAT_CPLD_LPC_SYSIRQ 17 325 326 /* Minimum power required for turning on Ethernet modular system (WATT) */ 327 #define MLXPLAT_CPLD_ETH_MODULAR_PWR_MIN 50 328 329 /* Default value for PWM control register for rack switch system */ 330 #define MLXPLAT_REGMAP_NVSWITCH_PWM_DEFAULT 0xf4 331 332 #define MLXPLAT_I2C_MAIN_BUS_NOTIFIED 0x01 333 #define MLXPLAT_I2C_MAIN_BUS_HANDLE_CREATED 0x02 334 335 /* Lattice FPGA PCI configuration */ 336 #define PCI_VENDOR_ID_LATTICE 0x1204 337 #define PCI_DEVICE_ID_LATTICE_I2C_BRIDGE 0x9c2f 338 #define PCI_DEVICE_ID_LATTICE_JTAG_BRIDGE 0x9c30 339 #define PCI_DEVICE_ID_LATTICE_LPC_BRIDGE 0x9c32 340 341 /* mlxplat_priv - platform private data 342 * @pdev_i2c - i2c controller platform device 343 * @pdev_mux - array of mux platform devices 344 * @pdev_hotplug - hotplug platform devices 345 * @pdev_led - led platform devices 346 * @pdev_io_regs - register access platform devices 347 * @pdev_fan - FAN platform devices 348 * @pdev_wd - array of watchdog platform devices 349 * @regmap: device register map 350 * @hotplug_resources: system hotplug resources 351 * @hotplug_resources_size: size of system hotplug resources 352 * @hi2c_main_init_status: init status of I2C main bus 353 * @irq_fpga: FPGA IRQ number 354 */ 355 struct mlxplat_priv { 356 struct platform_device *pdev_i2c; 357 struct platform_device *pdev_mux[MLXPLAT_CPLD_LPC_MUX_DEVS]; 358 struct platform_device *pdev_hotplug; 359 struct platform_device *pdev_led; 360 struct platform_device *pdev_io_regs; 361 struct platform_device *pdev_fan; 362 struct platform_device *pdev_wd[MLXPLAT_CPLD_WD_MAX_DEVS]; 363 void *regmap; 364 struct resource *hotplug_resources; 365 unsigned int hotplug_resources_size; 366 u8 i2c_main_init_status; 367 int irq_fpga; 368 }; 369 370 static struct platform_device *mlxplat_dev; 371 static int mlxplat_i2c_main_completion_notify(void *handle, int id); 372 static void __iomem *i2c_bridge_addr, *jtag_bridge_addr; 373 374 /* Regions for LPC I2C controller and LPC base register space */ 375 static const struct resource mlxplat_lpc_resources[] = { 376 [0] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_I2C_BASE_ADRR, 377 MLXPLAT_CPLD_LPC_IO_RANGE, 378 "mlxplat_cpld_lpc_i2c_ctrl", IORESOURCE_IO), 379 [1] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_REG_BASE_ADRR, 380 MLXPLAT_CPLD_LPC_IO_RANGE, 381 "mlxplat_cpld_lpc_regs", 382 IORESOURCE_IO), 383 }; 384 385 /* Platform systems default i2c data */ 386 static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_i2c_default_data = { 387 .completion_notify = mlxplat_i2c_main_completion_notify, 388 }; 389 390 /* Platform i2c next generation systems data */ 391 static struct mlxreg_core_data mlxplat_mlxcpld_i2c_ng_items_data[] = { 392 { 393 .reg = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 394 .mask = MLXPLAT_CPLD_I2C_CAP_MASK, 395 .bit = MLXPLAT_CPLD_I2C_CAP_BIT, 396 }, 397 }; 398 399 static struct mlxreg_core_item mlxplat_mlxcpld_i2c_ng_items[] = { 400 { 401 .data = mlxplat_mlxcpld_i2c_ng_items_data, 402 }, 403 }; 404 405 /* Platform next generation systems i2c data */ 406 static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_i2c_ng_data = { 407 .items = mlxplat_mlxcpld_i2c_ng_items, 408 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 409 .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX, 410 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET, 411 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_I2C, 412 .completion_notify = mlxplat_i2c_main_completion_notify, 413 }; 414 415 /* Platform default channels */ 416 static const int mlxplat_default_channels[][MLXPLAT_CPLD_GRP_CHNL_NUM] = { 417 { 418 MLXPLAT_CPLD_CH1, MLXPLAT_CPLD_CH1 + 1, MLXPLAT_CPLD_CH1 + 2, 419 MLXPLAT_CPLD_CH1 + 3, MLXPLAT_CPLD_CH1 + 4, MLXPLAT_CPLD_CH1 + 420 5, MLXPLAT_CPLD_CH1 + 6, MLXPLAT_CPLD_CH1 + 7 421 }, 422 { 423 MLXPLAT_CPLD_CH2, MLXPLAT_CPLD_CH2 + 1, MLXPLAT_CPLD_CH2 + 2, 424 MLXPLAT_CPLD_CH2 + 3, MLXPLAT_CPLD_CH2 + 4, MLXPLAT_CPLD_CH2 + 425 5, MLXPLAT_CPLD_CH2 + 6, MLXPLAT_CPLD_CH2 + 7 426 }, 427 }; 428 429 /* Platform channels for MSN21xx system family */ 430 static const int mlxplat_msn21xx_channels[] = { 1, 2, 3, 4, 5, 6, 7, 8 }; 431 432 /* Platform mux data */ 433 static struct i2c_mux_reg_platform_data mlxplat_default_mux_data[] = { 434 { 435 .parent = 1, 436 .base_nr = MLXPLAT_CPLD_CH1, 437 .write_only = 1, 438 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 439 .reg_size = 1, 440 .idle_in_use = 1, 441 }, 442 { 443 .parent = 1, 444 .base_nr = MLXPLAT_CPLD_CH2, 445 .write_only = 1, 446 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 447 .reg_size = 1, 448 .idle_in_use = 1, 449 }, 450 451 }; 452 453 /* Platform mux configuration variables */ 454 static int mlxplat_max_adap_num; 455 static int mlxplat_mux_num; 456 static struct i2c_mux_reg_platform_data *mlxplat_mux_data; 457 static struct notifier_block *mlxplat_reboot_nb; 458 459 /* Platform extended mux data */ 460 static struct i2c_mux_reg_platform_data mlxplat_extended_mux_data[] = { 461 { 462 .parent = 1, 463 .base_nr = MLXPLAT_CPLD_CH1, 464 .write_only = 1, 465 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 466 .reg_size = 1, 467 .idle_in_use = 1, 468 }, 469 { 470 .parent = 1, 471 .base_nr = MLXPLAT_CPLD_CH2, 472 .write_only = 1, 473 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG3, 474 .reg_size = 1, 475 .idle_in_use = 1, 476 }, 477 { 478 .parent = 1, 479 .base_nr = MLXPLAT_CPLD_CH3, 480 .write_only = 1, 481 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 482 .reg_size = 1, 483 .idle_in_use = 1, 484 }, 485 486 }; 487 488 /* Platform channels for modular system family */ 489 static const int mlxplat_modular_upper_channel[] = { 1 }; 490 static const int mlxplat_modular_channels[] = { 491 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 492 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 493 38, 39, 40 494 }; 495 496 /* Platform modular mux data */ 497 static struct i2c_mux_reg_platform_data mlxplat_modular_mux_data[] = { 498 { 499 .parent = 1, 500 .base_nr = MLXPLAT_CPLD_CH1, 501 .write_only = 1, 502 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG4, 503 .reg_size = 1, 504 .idle_in_use = 1, 505 .values = mlxplat_modular_upper_channel, 506 .n_values = ARRAY_SIZE(mlxplat_modular_upper_channel), 507 }, 508 { 509 .parent = 1, 510 .base_nr = MLXPLAT_CPLD_CH2_ETH_MODULAR, 511 .write_only = 1, 512 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 513 .reg_size = 1, 514 .idle_in_use = 1, 515 .values = mlxplat_modular_channels, 516 .n_values = ARRAY_SIZE(mlxplat_modular_channels), 517 }, 518 { 519 .parent = MLXPLAT_CPLD_CH1, 520 .base_nr = MLXPLAT_CPLD_CH3_ETH_MODULAR, 521 .write_only = 1, 522 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG3, 523 .reg_size = 1, 524 .idle_in_use = 1, 525 .values = mlxplat_msn21xx_channels, 526 .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), 527 }, 528 { 529 .parent = 1, 530 .base_nr = MLXPLAT_CPLD_CH4_ETH_MODULAR, 531 .write_only = 1, 532 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 533 .reg_size = 1, 534 .idle_in_use = 1, 535 .values = mlxplat_msn21xx_channels, 536 .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), 537 }, 538 }; 539 540 /* Platform channels for rack switch system family */ 541 static const int mlxplat_rack_switch_channels[] = { 542 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 543 }; 544 545 /* Platform rack switch mux data */ 546 static struct i2c_mux_reg_platform_data mlxplat_rack_switch_mux_data[] = { 547 { 548 .parent = 1, 549 .base_nr = MLXPLAT_CPLD_CH1, 550 .write_only = 1, 551 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 552 .reg_size = 1, 553 .idle_in_use = 1, 554 .values = mlxplat_rack_switch_channels, 555 .n_values = ARRAY_SIZE(mlxplat_rack_switch_channels), 556 }, 557 { 558 .parent = 1, 559 .base_nr = MLXPLAT_CPLD_CH2_RACK_SWITCH, 560 .write_only = 1, 561 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 562 .reg_size = 1, 563 .idle_in_use = 1, 564 .values = mlxplat_msn21xx_channels, 565 .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), 566 }, 567 568 }; 569 570 /* Platform channels for ng800 system family */ 571 static const int mlxplat_ng800_channels[] = { 572 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 573 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 574 }; 575 576 /* Platform ng800 mux data */ 577 static struct i2c_mux_reg_platform_data mlxplat_ng800_mux_data[] = { 578 { 579 .parent = 1, 580 .base_nr = MLXPLAT_CPLD_CH1, 581 .write_only = 1, 582 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 583 .reg_size = 1, 584 .idle_in_use = 1, 585 .values = mlxplat_ng800_channels, 586 .n_values = ARRAY_SIZE(mlxplat_ng800_channels), 587 }, 588 { 589 .parent = 1, 590 .base_nr = MLXPLAT_CPLD_CH2_NG800, 591 .write_only = 1, 592 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 593 .reg_size = 1, 594 .idle_in_use = 1, 595 .values = mlxplat_msn21xx_channels, 596 .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), 597 }, 598 599 }; 600 601 /* Platform hotplug devices */ 602 static struct i2c_board_info mlxplat_mlxcpld_pwr[] = { 603 { 604 I2C_BOARD_INFO("dps460", 0x59), 605 }, 606 { 607 I2C_BOARD_INFO("dps460", 0x58), 608 }, 609 }; 610 611 static struct i2c_board_info mlxplat_mlxcpld_ext_pwr[] = { 612 { 613 I2C_BOARD_INFO("dps460", 0x5b), 614 }, 615 { 616 I2C_BOARD_INFO("dps460", 0x5a), 617 }, 618 }; 619 620 static struct i2c_board_info mlxplat_mlxcpld_pwr_ng800[] = { 621 { 622 I2C_BOARD_INFO("dps460", 0x59), 623 }, 624 { 625 I2C_BOARD_INFO("dps460", 0x5a), 626 }, 627 }; 628 629 static struct i2c_board_info mlxplat_mlxcpld_fan[] = { 630 { 631 I2C_BOARD_INFO("24c32", 0x50), 632 }, 633 { 634 I2C_BOARD_INFO("24c32", 0x50), 635 }, 636 { 637 I2C_BOARD_INFO("24c32", 0x50), 638 }, 639 { 640 I2C_BOARD_INFO("24c32", 0x50), 641 }, 642 }; 643 644 /* Platform hotplug comex carrier system family data */ 645 static struct mlxreg_core_data mlxplat_mlxcpld_comex_psu_items_data[] = { 646 { 647 .label = "psu1", 648 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 649 .mask = BIT(0), 650 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 651 }, 652 { 653 .label = "psu2", 654 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 655 .mask = BIT(1), 656 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 657 }, 658 }; 659 660 /* Platform hotplug default data */ 661 static struct mlxreg_core_data mlxplat_mlxcpld_default_psu_items_data[] = { 662 { 663 .label = "psu1", 664 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 665 .mask = BIT(0), 666 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 667 }, 668 { 669 .label = "psu2", 670 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 671 .mask = BIT(1), 672 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 673 }, 674 }; 675 676 static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_items_data[] = { 677 { 678 .label = "pwr1", 679 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 680 .mask = BIT(0), 681 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 682 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR, 683 }, 684 { 685 .label = "pwr2", 686 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 687 .mask = BIT(1), 688 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 689 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR, 690 }, 691 }; 692 693 static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_wc_items_data[] = { 694 { 695 .label = "pwr1", 696 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 697 .mask = BIT(0), 698 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 699 }, 700 { 701 .label = "pwr2", 702 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 703 .mask = BIT(1), 704 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 705 }, 706 }; 707 708 static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_ng800_items_data[] = { 709 { 710 .label = "pwr1", 711 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 712 .mask = BIT(0), 713 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr_ng800[0], 714 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 715 }, 716 { 717 .label = "pwr2", 718 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 719 .mask = BIT(1), 720 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr_ng800[1], 721 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 722 }, 723 }; 724 725 static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_items_data[] = { 726 { 727 .label = "fan1", 728 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 729 .mask = BIT(0), 730 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[0], 731 .hpdev.nr = MLXPLAT_CPLD_FAN1_DEFAULT_NR, 732 }, 733 { 734 .label = "fan2", 735 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 736 .mask = BIT(1), 737 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[1], 738 .hpdev.nr = MLXPLAT_CPLD_FAN2_DEFAULT_NR, 739 }, 740 { 741 .label = "fan3", 742 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 743 .mask = BIT(2), 744 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[2], 745 .hpdev.nr = MLXPLAT_CPLD_FAN3_DEFAULT_NR, 746 }, 747 { 748 .label = "fan4", 749 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 750 .mask = BIT(3), 751 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[3], 752 .hpdev.nr = MLXPLAT_CPLD_FAN4_DEFAULT_NR, 753 }, 754 }; 755 756 static struct mlxreg_core_data mlxplat_mlxcpld_default_asic_items_data[] = { 757 { 758 .label = "asic1", 759 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 760 .mask = MLXPLAT_CPLD_ASIC_MASK, 761 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 762 }, 763 }; 764 765 static struct mlxreg_core_data mlxplat_mlxcpld_default_asic2_items_data[] = { 766 { 767 .label = "asic2", 768 .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, 769 .mask = MLXPLAT_CPLD_ASIC_MASK, 770 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 771 }, 772 }; 773 774 static struct mlxreg_core_item mlxplat_mlxcpld_default_items[] = { 775 { 776 .data = mlxplat_mlxcpld_default_psu_items_data, 777 .aggr_mask = MLXPLAT_CPLD_AGGR_PSU_MASK_DEF, 778 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 779 .mask = MLXPLAT_CPLD_PSU_MASK, 780 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data), 781 .inversed = 1, 782 .health = false, 783 }, 784 { 785 .data = mlxplat_mlxcpld_default_pwr_items_data, 786 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 787 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 788 .mask = MLXPLAT_CPLD_PWR_MASK, 789 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data), 790 .inversed = 0, 791 .health = false, 792 }, 793 { 794 .data = mlxplat_mlxcpld_default_fan_items_data, 795 .aggr_mask = MLXPLAT_CPLD_AGGR_FAN_MASK_DEF, 796 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 797 .mask = MLXPLAT_CPLD_FAN_MASK, 798 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_items_data), 799 .inversed = 1, 800 .health = false, 801 }, 802 { 803 .data = mlxplat_mlxcpld_default_asic_items_data, 804 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 805 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 806 .mask = MLXPLAT_CPLD_ASIC_MASK, 807 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 808 .inversed = 0, 809 .health = true, 810 }, 811 }; 812 813 static struct mlxreg_core_item mlxplat_mlxcpld_comex_items[] = { 814 { 815 .data = mlxplat_mlxcpld_comex_psu_items_data, 816 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 817 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 818 .mask = MLXPLAT_CPLD_PSU_MASK, 819 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data), 820 .inversed = 1, 821 .health = false, 822 }, 823 { 824 .data = mlxplat_mlxcpld_default_pwr_items_data, 825 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 826 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 827 .mask = MLXPLAT_CPLD_PWR_MASK, 828 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data), 829 .inversed = 0, 830 .health = false, 831 }, 832 { 833 .data = mlxplat_mlxcpld_default_fan_items_data, 834 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 835 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 836 .mask = MLXPLAT_CPLD_FAN_MASK, 837 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_items_data), 838 .inversed = 1, 839 .health = false, 840 }, 841 { 842 .data = mlxplat_mlxcpld_default_asic_items_data, 843 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 844 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 845 .mask = MLXPLAT_CPLD_ASIC_MASK, 846 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 847 .inversed = 0, 848 .health = true, 849 }, 850 }; 851 852 static 853 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_data = { 854 .items = mlxplat_mlxcpld_default_items, 855 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_items), 856 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 857 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 858 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 859 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 860 }; 861 862 static struct mlxreg_core_item mlxplat_mlxcpld_default_wc_items[] = { 863 { 864 .data = mlxplat_mlxcpld_comex_psu_items_data, 865 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 866 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 867 .mask = MLXPLAT_CPLD_PSU_MASK, 868 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data), 869 .inversed = 1, 870 .health = false, 871 }, 872 { 873 .data = mlxplat_mlxcpld_default_pwr_wc_items_data, 874 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 875 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 876 .mask = MLXPLAT_CPLD_PWR_MASK, 877 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data), 878 .inversed = 0, 879 .health = false, 880 }, 881 { 882 .data = mlxplat_mlxcpld_default_asic_items_data, 883 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 884 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 885 .mask = MLXPLAT_CPLD_ASIC_MASK, 886 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 887 .inversed = 0, 888 .health = true, 889 }, 890 }; 891 892 static 893 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_wc_data = { 894 .items = mlxplat_mlxcpld_default_wc_items, 895 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_wc_items), 896 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 897 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 898 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 899 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 900 }; 901 902 static 903 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_comex_data = { 904 .items = mlxplat_mlxcpld_comex_items, 905 .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_items), 906 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 907 .mask = MLXPLAT_CPLD_AGGR_MASK_CARR_DEF, 908 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET, 909 .mask_low = MLXPLAT_CPLD_LOW_AGGRCX_MASK, 910 }; 911 912 static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_pwr_items_data[] = { 913 { 914 .label = "pwr1", 915 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 916 .mask = BIT(0), 917 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 918 }, 919 { 920 .label = "pwr2", 921 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 922 .mask = BIT(1), 923 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 924 }, 925 }; 926 927 /* Platform hotplug MSN21xx system family data */ 928 static struct mlxreg_core_item mlxplat_mlxcpld_msn21xx_items[] = { 929 { 930 .data = mlxplat_mlxcpld_msn21xx_pwr_items_data, 931 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 932 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 933 .mask = MLXPLAT_CPLD_PWR_MASK, 934 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_pwr_items_data), 935 .inversed = 0, 936 .health = false, 937 }, 938 { 939 .data = mlxplat_mlxcpld_default_asic_items_data, 940 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 941 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 942 .mask = MLXPLAT_CPLD_ASIC_MASK, 943 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 944 .inversed = 0, 945 .health = true, 946 }, 947 }; 948 949 static 950 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn21xx_data = { 951 .items = mlxplat_mlxcpld_msn21xx_items, 952 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_items), 953 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 954 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 955 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 956 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 957 }; 958 959 /* Platform hotplug msn274x system family data */ 960 static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_psu_items_data[] = { 961 { 962 .label = "psu1", 963 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 964 .mask = BIT(0), 965 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 966 }, 967 { 968 .label = "psu2", 969 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 970 .mask = BIT(1), 971 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 972 }, 973 }; 974 975 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_pwr_items_data[] = { 976 { 977 .label = "pwr1", 978 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 979 .mask = BIT(0), 980 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 981 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 982 }, 983 { 984 .label = "pwr2", 985 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 986 .mask = BIT(1), 987 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 988 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 989 }, 990 }; 991 992 static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_fan_items_data[] = { 993 { 994 .label = "fan1", 995 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 996 .mask = BIT(0), 997 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 998 }, 999 { 1000 .label = "fan2", 1001 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1002 .mask = BIT(1), 1003 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1004 }, 1005 { 1006 .label = "fan3", 1007 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1008 .mask = BIT(2), 1009 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1010 }, 1011 { 1012 .label = "fan4", 1013 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1014 .mask = BIT(3), 1015 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1016 }, 1017 }; 1018 1019 static struct mlxreg_core_item mlxplat_mlxcpld_msn274x_items[] = { 1020 { 1021 .data = mlxplat_mlxcpld_msn274x_psu_items_data, 1022 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1023 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1024 .mask = MLXPLAT_CPLD_PSU_MASK, 1025 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_psu_items_data), 1026 .inversed = 1, 1027 .health = false, 1028 }, 1029 { 1030 .data = mlxplat_mlxcpld_default_ng_pwr_items_data, 1031 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1032 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1033 .mask = MLXPLAT_CPLD_PWR_MASK, 1034 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_pwr_items_data), 1035 .inversed = 0, 1036 .health = false, 1037 }, 1038 { 1039 .data = mlxplat_mlxcpld_msn274x_fan_items_data, 1040 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1041 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1042 .mask = MLXPLAT_CPLD_FAN_MASK, 1043 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_fan_items_data), 1044 .inversed = 1, 1045 .health = false, 1046 }, 1047 { 1048 .data = mlxplat_mlxcpld_default_asic_items_data, 1049 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1050 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1051 .mask = MLXPLAT_CPLD_ASIC_MASK, 1052 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 1053 .inversed = 0, 1054 .health = true, 1055 }, 1056 }; 1057 1058 static 1059 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn274x_data = { 1060 .items = mlxplat_mlxcpld_msn274x_items, 1061 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_items), 1062 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1063 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1064 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1065 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 1066 }; 1067 1068 /* Platform hotplug MSN201x system family data */ 1069 static struct mlxreg_core_data mlxplat_mlxcpld_msn201x_pwr_items_data[] = { 1070 { 1071 .label = "pwr1", 1072 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1073 .mask = BIT(0), 1074 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1075 }, 1076 { 1077 .label = "pwr2", 1078 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1079 .mask = BIT(1), 1080 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1081 }, 1082 }; 1083 1084 static struct mlxreg_core_item mlxplat_mlxcpld_msn201x_items[] = { 1085 { 1086 .data = mlxplat_mlxcpld_msn201x_pwr_items_data, 1087 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 1088 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1089 .mask = MLXPLAT_CPLD_PWR_MASK, 1090 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_pwr_items_data), 1091 .inversed = 0, 1092 .health = false, 1093 }, 1094 { 1095 .data = mlxplat_mlxcpld_default_asic_items_data, 1096 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 1097 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1098 .mask = MLXPLAT_CPLD_ASIC_MASK, 1099 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 1100 .inversed = 0, 1101 .health = true, 1102 }, 1103 }; 1104 1105 static 1106 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn201x_data = { 1107 .items = mlxplat_mlxcpld_msn201x_items, 1108 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_items), 1109 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1110 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 1111 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1112 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 1113 }; 1114 1115 /* Platform hotplug next generation system family data */ 1116 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_psu_items_data[] = { 1117 { 1118 .label = "psu1", 1119 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1120 .mask = BIT(0), 1121 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1122 }, 1123 { 1124 .label = "psu2", 1125 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1126 .mask = BIT(1), 1127 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1128 }, 1129 }; 1130 1131 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_fan_items_data[] = { 1132 { 1133 .label = "fan1", 1134 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1135 .mask = BIT(0), 1136 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1137 .bit = BIT(0), 1138 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1139 }, 1140 { 1141 .label = "fan2", 1142 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1143 .mask = BIT(1), 1144 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1145 .bit = BIT(1), 1146 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1147 }, 1148 { 1149 .label = "fan3", 1150 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1151 .mask = BIT(2), 1152 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1153 .bit = BIT(2), 1154 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1155 }, 1156 { 1157 .label = "fan4", 1158 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1159 .mask = BIT(3), 1160 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1161 .bit = BIT(3), 1162 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1163 }, 1164 { 1165 .label = "fan5", 1166 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1167 .mask = BIT(4), 1168 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1169 .bit = BIT(4), 1170 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1171 }, 1172 { 1173 .label = "fan6", 1174 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1175 .mask = BIT(5), 1176 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1177 .bit = BIT(5), 1178 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1179 }, 1180 { 1181 .label = "fan7", 1182 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1183 .mask = BIT(6), 1184 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1185 .bit = BIT(6), 1186 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1187 }, 1188 }; 1189 1190 static struct mlxreg_core_item mlxplat_mlxcpld_default_ng_items[] = { 1191 { 1192 .data = mlxplat_mlxcpld_default_ng_psu_items_data, 1193 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1194 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1195 .mask = MLXPLAT_CPLD_PSU_MASK, 1196 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_psu_items_data), 1197 .inversed = 1, 1198 .health = false, 1199 }, 1200 { 1201 .data = mlxplat_mlxcpld_default_ng_pwr_items_data, 1202 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1203 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1204 .mask = MLXPLAT_CPLD_PWR_MASK, 1205 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_pwr_items_data), 1206 .inversed = 0, 1207 .health = false, 1208 }, 1209 { 1210 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 1211 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1212 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1213 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 1214 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 1215 .inversed = 1, 1216 .health = false, 1217 }, 1218 { 1219 .data = mlxplat_mlxcpld_default_asic_items_data, 1220 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1221 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1222 .mask = MLXPLAT_CPLD_ASIC_MASK, 1223 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 1224 .inversed = 0, 1225 .health = true, 1226 }, 1227 }; 1228 1229 static 1230 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_ng_data = { 1231 .items = mlxplat_mlxcpld_default_ng_items, 1232 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_items), 1233 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1234 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 1235 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1236 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 1237 }; 1238 1239 /* Platform hotplug extended system family data */ 1240 static struct mlxreg_core_data mlxplat_mlxcpld_ext_psu_items_data[] = { 1241 { 1242 .label = "psu1", 1243 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1244 .mask = BIT(0), 1245 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1246 }, 1247 { 1248 .label = "psu2", 1249 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1250 .mask = BIT(1), 1251 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1252 }, 1253 { 1254 .label = "psu3", 1255 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1256 .mask = BIT(2), 1257 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1258 }, 1259 { 1260 .label = "psu4", 1261 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1262 .mask = BIT(3), 1263 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1264 }, 1265 }; 1266 1267 static struct mlxreg_core_data mlxplat_mlxcpld_ext_pwr_items_data[] = { 1268 { 1269 .label = "pwr1", 1270 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1271 .mask = BIT(0), 1272 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 1273 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1274 }, 1275 { 1276 .label = "pwr2", 1277 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1278 .mask = BIT(1), 1279 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 1280 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1281 }, 1282 { 1283 .label = "pwr3", 1284 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1285 .mask = BIT(2), 1286 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0], 1287 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1288 }, 1289 { 1290 .label = "pwr4", 1291 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1292 .mask = BIT(3), 1293 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1], 1294 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1295 }, 1296 }; 1297 1298 static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = { 1299 { 1300 .data = mlxplat_mlxcpld_ext_psu_items_data, 1301 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1302 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1303 .mask = MLXPLAT_CPLD_PSU_EXT_MASK, 1304 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 1305 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data), 1306 .inversed = 1, 1307 .health = false, 1308 }, 1309 { 1310 .data = mlxplat_mlxcpld_ext_pwr_items_data, 1311 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1312 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1313 .mask = MLXPLAT_CPLD_PWR_EXT_MASK, 1314 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 1315 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data), 1316 .inversed = 0, 1317 .health = false, 1318 }, 1319 { 1320 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 1321 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1322 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1323 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 1324 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 1325 .inversed = 1, 1326 .health = false, 1327 }, 1328 { 1329 .data = mlxplat_mlxcpld_default_asic_items_data, 1330 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1331 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1332 .mask = MLXPLAT_CPLD_ASIC_MASK, 1333 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 1334 .inversed = 0, 1335 .health = true, 1336 }, 1337 { 1338 .data = mlxplat_mlxcpld_default_asic2_items_data, 1339 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1340 .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, 1341 .mask = MLXPLAT_CPLD_ASIC_MASK, 1342 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic2_items_data), 1343 .inversed = 0, 1344 .health = true, 1345 } 1346 }; 1347 1348 static struct mlxreg_core_item mlxplat_mlxcpld_ng800_items[] = { 1349 { 1350 .data = mlxplat_mlxcpld_default_ng_psu_items_data, 1351 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1352 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1353 .mask = MLXPLAT_CPLD_PSU_EXT_MASK, 1354 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 1355 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_psu_items_data), 1356 .inversed = 1, 1357 .health = false, 1358 }, 1359 { 1360 .data = mlxplat_mlxcpld_default_pwr_ng800_items_data, 1361 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1362 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1363 .mask = MLXPLAT_CPLD_PWR_EXT_MASK, 1364 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 1365 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_ng800_items_data), 1366 .inversed = 0, 1367 .health = false, 1368 }, 1369 { 1370 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 1371 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1372 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1373 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 1374 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 1375 .inversed = 1, 1376 .health = false, 1377 }, 1378 { 1379 .data = mlxplat_mlxcpld_default_asic_items_data, 1380 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1381 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1382 .mask = MLXPLAT_CPLD_ASIC_MASK, 1383 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 1384 .inversed = 0, 1385 .health = true, 1386 }, 1387 }; 1388 1389 static 1390 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = { 1391 .items = mlxplat_mlxcpld_ext_items, 1392 .counter = ARRAY_SIZE(mlxplat_mlxcpld_ext_items), 1393 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1394 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 1395 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1396 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2, 1397 }; 1398 1399 static 1400 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ng800_data = { 1401 .items = mlxplat_mlxcpld_ng800_items, 1402 .counter = ARRAY_SIZE(mlxplat_mlxcpld_ng800_items), 1403 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1404 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 1405 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1406 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2, 1407 }; 1408 1409 static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = { 1410 { 1411 .label = "pwr1", 1412 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1413 .mask = BIT(0), 1414 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 1415 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1416 }, 1417 { 1418 .label = "pwr2", 1419 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1420 .mask = BIT(1), 1421 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 1422 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1423 }, 1424 { 1425 .label = "pwr3", 1426 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1427 .mask = BIT(2), 1428 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0], 1429 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1430 }, 1431 { 1432 .label = "pwr4", 1433 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1434 .mask = BIT(3), 1435 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1], 1436 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1437 }, 1438 }; 1439 1440 static 1441 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_lc_act = { 1442 .irq = MLXPLAT_CPLD_LPC_SYSIRQ, 1443 }; 1444 1445 static struct mlxreg_core_data mlxplat_mlxcpld_modular_asic_items_data[] = { 1446 { 1447 .label = "asic1", 1448 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1449 .mask = MLXPLAT_CPLD_ASIC_MASK, 1450 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1451 }, 1452 }; 1453 1454 static struct i2c_board_info mlxplat_mlxcpld_lc_i2c_dev[] = { 1455 { 1456 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1457 .platform_data = &mlxplat_mlxcpld_lc_act, 1458 }, 1459 { 1460 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1461 .platform_data = &mlxplat_mlxcpld_lc_act, 1462 }, 1463 { 1464 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1465 .platform_data = &mlxplat_mlxcpld_lc_act, 1466 }, 1467 { 1468 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1469 .platform_data = &mlxplat_mlxcpld_lc_act, 1470 }, 1471 { 1472 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1473 .platform_data = &mlxplat_mlxcpld_lc_act, 1474 }, 1475 { 1476 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1477 .platform_data = &mlxplat_mlxcpld_lc_act, 1478 }, 1479 { 1480 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1481 .platform_data = &mlxplat_mlxcpld_lc_act, 1482 }, 1483 { 1484 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1485 .platform_data = &mlxplat_mlxcpld_lc_act, 1486 }, 1487 }; 1488 1489 static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_modular_lc_notifier[] = { 1490 { 1491 .identity = "lc1", 1492 }, 1493 { 1494 .identity = "lc2", 1495 }, 1496 { 1497 .identity = "lc3", 1498 }, 1499 { 1500 .identity = "lc4", 1501 }, 1502 { 1503 .identity = "lc5", 1504 }, 1505 { 1506 .identity = "lc6", 1507 }, 1508 { 1509 .identity = "lc7", 1510 }, 1511 { 1512 .identity = "lc8", 1513 }, 1514 }; 1515 1516 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pr_items_data[] = { 1517 { 1518 .label = "lc1_present", 1519 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1520 .mask = BIT(0), 1521 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1522 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1523 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1524 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1525 .slot = 1, 1526 }, 1527 { 1528 .label = "lc2_present", 1529 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1530 .mask = BIT(1), 1531 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1532 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1533 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1534 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1535 .slot = 2, 1536 }, 1537 { 1538 .label = "lc3_present", 1539 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1540 .mask = BIT(2), 1541 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1542 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1543 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1544 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1545 .slot = 3, 1546 }, 1547 { 1548 .label = "lc4_present", 1549 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1550 .mask = BIT(3), 1551 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1552 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1553 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1554 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1555 .slot = 4, 1556 }, 1557 { 1558 .label = "lc5_present", 1559 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1560 .mask = BIT(4), 1561 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1562 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1563 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1564 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1565 .slot = 5, 1566 }, 1567 { 1568 .label = "lc6_present", 1569 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1570 .mask = BIT(5), 1571 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1572 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1573 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1574 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1575 .slot = 6, 1576 }, 1577 { 1578 .label = "lc7_present", 1579 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1580 .mask = BIT(6), 1581 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1582 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1583 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1584 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1585 .slot = 7, 1586 }, 1587 { 1588 .label = "lc8_present", 1589 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1590 .mask = BIT(7), 1591 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1592 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1593 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1594 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1595 .slot = 8, 1596 }, 1597 }; 1598 1599 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ver_items_data[] = { 1600 { 1601 .label = "lc1_verified", 1602 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1603 .mask = BIT(0), 1604 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1605 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1606 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1607 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1608 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1609 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1610 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1611 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1612 .slot = 1, 1613 }, 1614 { 1615 .label = "lc2_verified", 1616 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1617 .mask = BIT(1), 1618 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1619 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1620 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1621 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1622 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1623 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1624 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1625 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1626 .slot = 2, 1627 }, 1628 { 1629 .label = "lc3_verified", 1630 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1631 .mask = BIT(2), 1632 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1633 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1634 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1635 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1636 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1637 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1638 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1639 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1640 .slot = 3, 1641 }, 1642 { 1643 .label = "lc4_verified", 1644 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1645 .mask = BIT(3), 1646 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1647 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1648 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1649 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1650 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1651 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1652 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1653 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1654 .slot = 4, 1655 }, 1656 { 1657 .label = "lc5_verified", 1658 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1659 .mask = BIT(4), 1660 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1661 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1662 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1663 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1664 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1665 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1666 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1667 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1668 .slot = 5, 1669 }, 1670 { 1671 .label = "lc6_verified", 1672 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1673 .mask = BIT(5), 1674 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1675 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1676 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1677 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1678 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1679 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1680 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1681 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1682 .slot = 6, 1683 }, 1684 { 1685 .label = "lc7_verified", 1686 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1687 .mask = BIT(6), 1688 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1689 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1690 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1691 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1692 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1693 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1694 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1695 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1696 .slot = 7, 1697 }, 1698 { 1699 .label = "lc8_verified", 1700 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1701 .mask = BIT(7), 1702 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1703 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1704 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1705 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1706 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1707 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1708 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1709 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1710 .slot = 8, 1711 }, 1712 }; 1713 1714 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pg_data[] = { 1715 { 1716 .label = "lc1_powered", 1717 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1718 .mask = BIT(0), 1719 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1720 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1721 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1722 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1723 .slot = 1, 1724 }, 1725 { 1726 .label = "lc2_powered", 1727 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1728 .mask = BIT(1), 1729 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1730 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1731 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1732 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1733 .slot = 2, 1734 }, 1735 { 1736 .label = "lc3_powered", 1737 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1738 .mask = BIT(2), 1739 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1740 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1741 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1742 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1743 .slot = 3, 1744 }, 1745 { 1746 .label = "lc4_powered", 1747 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1748 .mask = BIT(3), 1749 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1750 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1751 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1752 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1753 .slot = 4, 1754 }, 1755 { 1756 .label = "lc5_powered", 1757 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1758 .mask = BIT(4), 1759 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1760 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1761 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1762 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1763 .slot = 5, 1764 }, 1765 { 1766 .label = "lc6_powered", 1767 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1768 .mask = BIT(5), 1769 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1770 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1771 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1772 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1773 .slot = 6, 1774 }, 1775 { 1776 .label = "lc7_powered", 1777 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1778 .mask = BIT(6), 1779 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1780 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1781 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1782 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1783 .slot = 7, 1784 }, 1785 { 1786 .label = "lc8_powered", 1787 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1788 .mask = BIT(7), 1789 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1790 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1791 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1792 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1793 .slot = 8, 1794 }, 1795 }; 1796 1797 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ready_data[] = { 1798 { 1799 .label = "lc1_ready", 1800 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1801 .mask = BIT(0), 1802 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1803 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1804 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1805 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1806 .slot = 1, 1807 }, 1808 { 1809 .label = "lc2_ready", 1810 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1811 .mask = BIT(1), 1812 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1813 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1814 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1815 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1816 .slot = 2, 1817 }, 1818 { 1819 .label = "lc3_ready", 1820 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1821 .mask = BIT(2), 1822 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1823 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1824 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1825 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1826 .slot = 3, 1827 }, 1828 { 1829 .label = "lc4_ready", 1830 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1831 .mask = BIT(3), 1832 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1833 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1834 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1835 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1836 .slot = 4, 1837 }, 1838 { 1839 .label = "lc5_ready", 1840 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1841 .mask = BIT(4), 1842 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1843 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1844 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1845 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1846 .slot = 5, 1847 }, 1848 { 1849 .label = "lc6_ready", 1850 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1851 .mask = BIT(5), 1852 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1853 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1854 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1855 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1856 .slot = 6, 1857 }, 1858 { 1859 .label = "lc7_ready", 1860 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1861 .mask = BIT(6), 1862 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1863 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1864 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1865 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1866 .slot = 7, 1867 }, 1868 { 1869 .label = "lc8_ready", 1870 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1871 .mask = BIT(7), 1872 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1873 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1874 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1875 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1876 .slot = 8, 1877 }, 1878 }; 1879 1880 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_synced_data[] = { 1881 { 1882 .label = "lc1_synced", 1883 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1884 .mask = BIT(0), 1885 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1886 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1887 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1888 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1889 .slot = 1, 1890 }, 1891 { 1892 .label = "lc2_synced", 1893 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1894 .mask = BIT(1), 1895 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1896 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1897 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1898 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1899 .slot = 2, 1900 }, 1901 { 1902 .label = "lc3_synced", 1903 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1904 .mask = BIT(2), 1905 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1906 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1907 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1908 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1909 .slot = 3, 1910 }, 1911 { 1912 .label = "lc4_synced", 1913 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1914 .mask = BIT(3), 1915 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1916 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1917 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1918 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1919 .slot = 4, 1920 }, 1921 { 1922 .label = "lc5_synced", 1923 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1924 .mask = BIT(4), 1925 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1926 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1927 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1928 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1929 .slot = 5, 1930 }, 1931 { 1932 .label = "lc6_synced", 1933 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1934 .mask = BIT(5), 1935 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1936 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1937 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1938 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1939 .slot = 6, 1940 }, 1941 { 1942 .label = "lc7_synced", 1943 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1944 .mask = BIT(6), 1945 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1946 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1947 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1948 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1949 .slot = 7, 1950 }, 1951 { 1952 .label = "lc8_synced", 1953 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1954 .mask = BIT(7), 1955 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1956 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1957 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1958 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1959 .slot = 8, 1960 }, 1961 }; 1962 1963 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_act_data[] = { 1964 { 1965 .label = "lc1_active", 1966 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1967 .mask = BIT(0), 1968 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1969 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1970 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1971 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1972 .slot = 1, 1973 }, 1974 { 1975 .label = "lc2_active", 1976 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1977 .mask = BIT(1), 1978 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1979 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1980 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1981 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1982 .slot = 2, 1983 }, 1984 { 1985 .label = "lc3_active", 1986 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1987 .mask = BIT(2), 1988 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1989 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1990 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1991 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1992 .slot = 3, 1993 }, 1994 { 1995 .label = "lc4_active", 1996 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1997 .mask = BIT(3), 1998 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1999 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 2000 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2001 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 2002 .slot = 4, 2003 }, 2004 { 2005 .label = "lc5_active", 2006 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2007 .mask = BIT(4), 2008 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 2009 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 2010 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2011 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 2012 .slot = 5, 2013 }, 2014 { 2015 .label = "lc6_active", 2016 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2017 .mask = BIT(5), 2018 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 2019 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 2020 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2021 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 2022 .slot = 6, 2023 }, 2024 { 2025 .label = "lc7_active", 2026 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2027 .mask = BIT(6), 2028 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 2029 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 2030 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2031 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 2032 .slot = 7, 2033 }, 2034 { 2035 .label = "lc8_active", 2036 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2037 .mask = BIT(7), 2038 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 2039 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 2040 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2041 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 2042 .slot = 8, 2043 }, 2044 }; 2045 2046 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_sd_data[] = { 2047 { 2048 .label = "lc1_shutdown", 2049 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2050 .mask = BIT(0), 2051 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 2052 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 2053 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2054 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 2055 .slot = 1, 2056 }, 2057 { 2058 .label = "lc2_shutdown", 2059 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2060 .mask = BIT(1), 2061 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 2062 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 2063 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2064 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 2065 .slot = 2, 2066 }, 2067 { 2068 .label = "lc3_shutdown", 2069 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2070 .mask = BIT(2), 2071 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 2072 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 2073 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2074 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 2075 .slot = 3, 2076 }, 2077 { 2078 .label = "lc4_shutdown", 2079 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2080 .mask = BIT(3), 2081 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 2082 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 2083 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2084 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 2085 .slot = 4, 2086 }, 2087 { 2088 .label = "lc5_shutdown", 2089 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2090 .mask = BIT(4), 2091 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 2092 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 2093 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2094 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 2095 .slot = 5, 2096 }, 2097 { 2098 .label = "lc6_shutdown", 2099 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2100 .mask = BIT(5), 2101 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 2102 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 2103 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2104 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 2105 .slot = 6, 2106 }, 2107 { 2108 .label = "lc7_shutdown", 2109 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2110 .mask = BIT(6), 2111 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 2112 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 2113 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2114 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 2115 .slot = 7, 2116 }, 2117 { 2118 .label = "lc8_shutdown", 2119 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2120 .mask = BIT(7), 2121 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 2122 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 2123 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2124 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 2125 .slot = 8, 2126 }, 2127 }; 2128 2129 static struct mlxreg_core_item mlxplat_mlxcpld_modular_items[] = { 2130 { 2131 .data = mlxplat_mlxcpld_ext_psu_items_data, 2132 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2133 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 2134 .mask = MLXPLAT_CPLD_PSU_EXT_MASK, 2135 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2136 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data), 2137 .inversed = 1, 2138 .health = false, 2139 }, 2140 { 2141 .data = mlxplat_mlxcpld_modular_pwr_items_data, 2142 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2143 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 2144 .mask = MLXPLAT_CPLD_PWR_EXT_MASK, 2145 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2146 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data), 2147 .inversed = 0, 2148 .health = false, 2149 }, 2150 { 2151 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 2152 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2153 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2154 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 2155 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 2156 .inversed = 1, 2157 .health = false, 2158 }, 2159 { 2160 .data = mlxplat_mlxcpld_modular_asic_items_data, 2161 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2162 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 2163 .mask = MLXPLAT_CPLD_ASIC_MASK, 2164 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_asic_items_data), 2165 .inversed = 0, 2166 .health = true, 2167 }, 2168 { 2169 .data = mlxplat_mlxcpld_modular_lc_pr_items_data, 2170 .kind = MLXREG_HOTPLUG_LC_PRESENT, 2171 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2172 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 2173 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2174 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_pr_items_data), 2175 .inversed = 1, 2176 .health = false, 2177 }, 2178 { 2179 .data = mlxplat_mlxcpld_modular_lc_ver_items_data, 2180 .kind = MLXREG_HOTPLUG_LC_VERIFIED, 2181 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2182 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 2183 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2184 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_ver_items_data), 2185 .inversed = 0, 2186 .health = false, 2187 }, 2188 { 2189 .data = mlxplat_mlxcpld_modular_lc_pg_data, 2190 .kind = MLXREG_HOTPLUG_LC_POWERED, 2191 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2192 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 2193 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2194 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_pg_data), 2195 .inversed = 0, 2196 .health = false, 2197 }, 2198 { 2199 .data = mlxplat_mlxcpld_modular_lc_ready_data, 2200 .kind = MLXREG_HOTPLUG_LC_READY, 2201 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2202 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 2203 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2204 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_ready_data), 2205 .inversed = 0, 2206 .health = false, 2207 }, 2208 { 2209 .data = mlxplat_mlxcpld_modular_lc_synced_data, 2210 .kind = MLXREG_HOTPLUG_LC_SYNCED, 2211 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2212 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 2213 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2214 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_synced_data), 2215 .inversed = 0, 2216 .health = false, 2217 }, 2218 { 2219 .data = mlxplat_mlxcpld_modular_lc_act_data, 2220 .kind = MLXREG_HOTPLUG_LC_ACTIVE, 2221 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2222 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 2223 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2224 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_act_data), 2225 .inversed = 0, 2226 .health = false, 2227 }, 2228 { 2229 .data = mlxplat_mlxcpld_modular_lc_sd_data, 2230 .kind = MLXREG_HOTPLUG_LC_THERMAL, 2231 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 2232 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 2233 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 2234 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_sd_data), 2235 .inversed = 0, 2236 .health = false, 2237 }, 2238 }; 2239 2240 static 2241 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_modular_data = { 2242 .items = mlxplat_mlxcpld_modular_items, 2243 .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_items), 2244 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 2245 .mask = MLXPLAT_CPLD_AGGR_MASK_MODULAR, 2246 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 2247 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 2248 }; 2249 2250 /* Platform hotplug for NVLink blade systems family data */ 2251 static struct mlxreg_core_data mlxplat_mlxcpld_global_wp_items_data[] = { 2252 { 2253 .label = "global_wp_grant", 2254 .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET, 2255 .mask = MLXPLAT_CPLD_GWP_MASK, 2256 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2257 }, 2258 }; 2259 2260 static struct mlxreg_core_item mlxplat_mlxcpld_chassis_blade_items[] = { 2261 { 2262 .data = mlxplat_mlxcpld_global_wp_items_data, 2263 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2264 .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET, 2265 .mask = MLXPLAT_CPLD_GWP_MASK, 2266 .count = ARRAY_SIZE(mlxplat_mlxcpld_global_wp_items_data), 2267 .inversed = 0, 2268 .health = false, 2269 }, 2270 }; 2271 2272 static 2273 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_chassis_blade_data = { 2274 .items = mlxplat_mlxcpld_chassis_blade_items, 2275 .counter = ARRAY_SIZE(mlxplat_mlxcpld_chassis_blade_items), 2276 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 2277 .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX, 2278 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 2279 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 2280 }; 2281 2282 /* Platform hotplug for switch systems family data */ 2283 static struct mlxreg_core_data mlxplat_mlxcpld_erot_ap_items_data[] = { 2284 { 2285 .label = "erot1_ap", 2286 .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET, 2287 .mask = BIT(0), 2288 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2289 }, 2290 { 2291 .label = "erot2_ap", 2292 .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET, 2293 .mask = BIT(1), 2294 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2295 }, 2296 }; 2297 2298 static struct mlxreg_core_data mlxplat_mlxcpld_erot_error_items_data[] = { 2299 { 2300 .label = "erot1_error", 2301 .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET, 2302 .mask = BIT(0), 2303 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2304 }, 2305 { 2306 .label = "erot2_error", 2307 .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET, 2308 .mask = BIT(1), 2309 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2310 }, 2311 }; 2312 2313 static struct mlxreg_core_item mlxplat_mlxcpld_rack_switch_items[] = { 2314 { 2315 .data = mlxplat_mlxcpld_ext_psu_items_data, 2316 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2317 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 2318 .mask = MLXPLAT_CPLD_PSU_EXT_MASK, 2319 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2320 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data), 2321 .inversed = 1, 2322 .health = false, 2323 }, 2324 { 2325 .data = mlxplat_mlxcpld_ext_pwr_items_data, 2326 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2327 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 2328 .mask = MLXPLAT_CPLD_PWR_EXT_MASK, 2329 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 2330 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data), 2331 .inversed = 0, 2332 .health = false, 2333 }, 2334 { 2335 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 2336 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2337 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2338 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 2339 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 2340 .inversed = 1, 2341 .health = false, 2342 }, 2343 { 2344 .data = mlxplat_mlxcpld_erot_ap_items_data, 2345 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2346 .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET, 2347 .mask = MLXPLAT_CPLD_EROT_MASK, 2348 .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_ap_items_data), 2349 .inversed = 1, 2350 .health = false, 2351 }, 2352 { 2353 .data = mlxplat_mlxcpld_erot_error_items_data, 2354 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2355 .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET, 2356 .mask = MLXPLAT_CPLD_EROT_MASK, 2357 .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_error_items_data), 2358 .inversed = 1, 2359 .health = false, 2360 }, 2361 }; 2362 2363 static 2364 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_rack_switch_data = { 2365 .items = mlxplat_mlxcpld_rack_switch_items, 2366 .counter = ARRAY_SIZE(mlxplat_mlxcpld_rack_switch_items), 2367 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 2368 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 2369 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 2370 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 2371 }; 2372 2373 /* Callback performs graceful shutdown after notification about power button event */ 2374 static int 2375 mlxplat_mlxcpld_l1_switch_pwr_events_handler(void *handle, enum mlxreg_hotplug_kind kind, 2376 u8 action) 2377 { 2378 if (action) { 2379 dev_info(&mlxplat_dev->dev, "System shutdown due to short press of power button"); 2380 kernel_power_off(); 2381 } 2382 2383 return 0; 2384 } 2385 2386 static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_l1_switch_pwr_events_notifier = { 2387 .user_handler = mlxplat_mlxcpld_l1_switch_pwr_events_handler, 2388 }; 2389 2390 /* Platform hotplug for l1 switch systems family data */ 2391 static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_pwr_events_items_data[] = { 2392 { 2393 .label = "power_button", 2394 .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET, 2395 .mask = MLXPLAT_CPLD_PWR_BUTTON_MASK, 2396 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2397 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2398 .hpdev.notifier = &mlxplat_mlxcpld_l1_switch_pwr_events_notifier, 2399 }, 2400 }; 2401 2402 /* Callback activates latch reset flow after notification about intrusion event */ 2403 static int 2404 mlxplat_mlxcpld_l1_switch_intrusion_events_handler(void *handle, enum mlxreg_hotplug_kind kind, 2405 u8 action) 2406 { 2407 struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); 2408 u32 regval; 2409 int err; 2410 2411 err = regmap_read(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ®val); 2412 if (err) 2413 goto fail_regmap_read; 2414 2415 if (action) { 2416 dev_info(&mlxplat_dev->dev, "Detected intrusion - system latch is opened"); 2417 err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2418 regval | MLXPLAT_CPLD_LATCH_RST_MASK); 2419 } else { 2420 dev_info(&mlxplat_dev->dev, "System latch is properly closed"); 2421 err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2422 regval & ~MLXPLAT_CPLD_LATCH_RST_MASK); 2423 } 2424 2425 if (err) 2426 goto fail_regmap_write; 2427 2428 return 0; 2429 2430 fail_regmap_read: 2431 fail_regmap_write: 2432 dev_err(&mlxplat_dev->dev, "Register access failed"); 2433 return err; 2434 } 2435 2436 static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_l1_switch_intrusion_events_notifier = { 2437 .user_handler = mlxplat_mlxcpld_l1_switch_intrusion_events_handler, 2438 }; 2439 2440 static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_health_events_items_data[] = { 2441 { 2442 .label = "thermal1_pdb", 2443 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, 2444 .mask = MLXPLAT_CPLD_THERMAL1_PDB_MASK, 2445 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2446 }, 2447 { 2448 .label = "thermal2_pdb", 2449 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, 2450 .mask = MLXPLAT_CPLD_THERMAL2_PDB_MASK, 2451 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2452 }, 2453 { 2454 .label = "intrusion", 2455 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, 2456 .mask = MLXPLAT_CPLD_INTRUSION_MASK, 2457 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2458 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 2459 .hpdev.notifier = &mlxplat_mlxcpld_l1_switch_intrusion_events_notifier, 2460 }, 2461 { 2462 .label = "pwm_pg", 2463 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, 2464 .mask = MLXPLAT_CPLD_PWM_PG_MASK, 2465 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 2466 }, 2467 }; 2468 2469 static struct mlxreg_core_item mlxplat_mlxcpld_l1_switch_events_items[] = { 2470 { 2471 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 2472 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2473 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 2474 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 2475 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 2476 .inversed = 1, 2477 .health = false, 2478 }, 2479 { 2480 .data = mlxplat_mlxcpld_erot_ap_items_data, 2481 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2482 .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET, 2483 .mask = MLXPLAT_CPLD_EROT_MASK, 2484 .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_ap_items_data), 2485 .inversed = 1, 2486 .health = false, 2487 }, 2488 { 2489 .data = mlxplat_mlxcpld_erot_error_items_data, 2490 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2491 .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET, 2492 .mask = MLXPLAT_CPLD_EROT_MASK, 2493 .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_error_items_data), 2494 .inversed = 1, 2495 .health = false, 2496 }, 2497 { 2498 .data = mlxplat_mlxcpld_l1_switch_pwr_events_items_data, 2499 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2500 .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET, 2501 .mask = MLXPLAT_CPLD_PWR_BUTTON_MASK, 2502 .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_pwr_events_items_data), 2503 .inversed = 1, 2504 .health = false, 2505 }, 2506 { 2507 .data = mlxplat_mlxcpld_l1_switch_health_events_items_data, 2508 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 2509 .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, 2510 .mask = MLXPLAT_CPLD_L1_CHA_HEALTH_MASK, 2511 .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_health_events_items_data), 2512 .inversed = 1, 2513 .health = false, 2514 .ind = 8, 2515 }, 2516 }; 2517 2518 static 2519 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_l1_switch_data = { 2520 .items = mlxplat_mlxcpld_l1_switch_events_items, 2521 .counter = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_events_items), 2522 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 2523 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 2524 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 2525 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT, 2526 }; 2527 2528 /* Platform led default data */ 2529 static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = { 2530 { 2531 .label = "status:green", 2532 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2533 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2534 }, 2535 { 2536 .label = "status:red", 2537 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2538 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2539 }, 2540 { 2541 .label = "psu:green", 2542 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2543 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2544 }, 2545 { 2546 .label = "psu:red", 2547 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2548 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2549 }, 2550 { 2551 .label = "fan1:green", 2552 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2553 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2554 }, 2555 { 2556 .label = "fan1:red", 2557 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2558 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2559 }, 2560 { 2561 .label = "fan2:green", 2562 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2563 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2564 }, 2565 { 2566 .label = "fan2:red", 2567 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2568 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2569 }, 2570 { 2571 .label = "fan3:green", 2572 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2573 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2574 }, 2575 { 2576 .label = "fan3:red", 2577 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2578 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2579 }, 2580 { 2581 .label = "fan4:green", 2582 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2583 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2584 }, 2585 { 2586 .label = "fan4:red", 2587 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2588 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2589 }, 2590 }; 2591 2592 static struct mlxreg_core_platform_data mlxplat_default_led_data = { 2593 .data = mlxplat_mlxcpld_default_led_data, 2594 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_data), 2595 }; 2596 2597 /* Platform led default data for water cooling */ 2598 static struct mlxreg_core_data mlxplat_mlxcpld_default_led_wc_data[] = { 2599 { 2600 .label = "status:green", 2601 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2602 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2603 }, 2604 { 2605 .label = "status:red", 2606 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2607 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2608 }, 2609 { 2610 .label = "psu:green", 2611 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2612 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2613 }, 2614 { 2615 .label = "psu:red", 2616 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2617 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2618 }, 2619 }; 2620 2621 static struct mlxreg_core_platform_data mlxplat_default_led_wc_data = { 2622 .data = mlxplat_mlxcpld_default_led_wc_data, 2623 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_wc_data), 2624 }; 2625 2626 /* Platform led default data for water cooling Ethernet switch blade */ 2627 static struct mlxreg_core_data mlxplat_mlxcpld_default_led_eth_wc_blade_data[] = { 2628 { 2629 .label = "status:green", 2630 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2631 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2632 }, 2633 { 2634 .label = "status:red", 2635 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2636 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2637 }, 2638 }; 2639 2640 static struct mlxreg_core_platform_data mlxplat_default_led_eth_wc_blade_data = { 2641 .data = mlxplat_mlxcpld_default_led_eth_wc_blade_data, 2642 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_eth_wc_blade_data), 2643 }; 2644 2645 /* Platform led MSN21xx system family data */ 2646 static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_led_data[] = { 2647 { 2648 .label = "status:green", 2649 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2650 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2651 }, 2652 { 2653 .label = "status:red", 2654 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2655 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2656 }, 2657 { 2658 .label = "fan:green", 2659 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2660 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2661 }, 2662 { 2663 .label = "fan:red", 2664 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2665 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2666 }, 2667 { 2668 .label = "psu1:green", 2669 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2670 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2671 }, 2672 { 2673 .label = "psu1:red", 2674 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2675 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2676 }, 2677 { 2678 .label = "psu2:green", 2679 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2680 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2681 }, 2682 { 2683 .label = "psu2:red", 2684 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2685 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2686 }, 2687 { 2688 .label = "uid:blue", 2689 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 2690 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2691 }, 2692 }; 2693 2694 static struct mlxreg_core_platform_data mlxplat_msn21xx_led_data = { 2695 .data = mlxplat_mlxcpld_msn21xx_led_data, 2696 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_led_data), 2697 }; 2698 2699 /* Platform led for default data for 200GbE systems */ 2700 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_led_data[] = { 2701 { 2702 .label = "status:green", 2703 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2704 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2705 }, 2706 { 2707 .label = "status:orange", 2708 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2709 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2710 }, 2711 { 2712 .label = "psu:green", 2713 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2714 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2715 }, 2716 { 2717 .label = "psu:orange", 2718 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2719 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2720 }, 2721 { 2722 .label = "fan1:green", 2723 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2724 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2725 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2726 .bit = BIT(0), 2727 }, 2728 { 2729 .label = "fan1:orange", 2730 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2731 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2732 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2733 .bit = BIT(0), 2734 }, 2735 { 2736 .label = "fan2:green", 2737 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2738 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2739 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2740 .bit = BIT(1), 2741 }, 2742 { 2743 .label = "fan2:orange", 2744 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2745 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2746 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2747 .bit = BIT(1), 2748 }, 2749 { 2750 .label = "fan3:green", 2751 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2752 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2753 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2754 .bit = BIT(2), 2755 }, 2756 { 2757 .label = "fan3:orange", 2758 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2759 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2760 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2761 .bit = BIT(2), 2762 }, 2763 { 2764 .label = "fan4:green", 2765 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2766 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2767 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2768 .bit = BIT(3), 2769 }, 2770 { 2771 .label = "fan4:orange", 2772 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2773 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2774 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2775 .bit = BIT(3), 2776 }, 2777 { 2778 .label = "fan5:green", 2779 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2780 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2781 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2782 .bit = BIT(4), 2783 }, 2784 { 2785 .label = "fan5:orange", 2786 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2787 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2788 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2789 .bit = BIT(4), 2790 }, 2791 { 2792 .label = "fan6:green", 2793 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2794 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2795 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2796 .bit = BIT(5), 2797 }, 2798 { 2799 .label = "fan6:orange", 2800 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2801 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2802 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2803 .bit = BIT(5), 2804 }, 2805 { 2806 .label = "fan7:green", 2807 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 2808 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2809 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2810 .bit = BIT(6), 2811 }, 2812 { 2813 .label = "fan7:orange", 2814 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 2815 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2816 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2817 .bit = BIT(6), 2818 }, 2819 { 2820 .label = "uid:blue", 2821 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 2822 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2823 }, 2824 }; 2825 2826 static struct mlxreg_core_platform_data mlxplat_default_ng_led_data = { 2827 .data = mlxplat_mlxcpld_default_ng_led_data, 2828 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_led_data), 2829 }; 2830 2831 /* Platform led for Comex based 100GbE systems */ 2832 static struct mlxreg_core_data mlxplat_mlxcpld_comex_100G_led_data[] = { 2833 { 2834 .label = "status:green", 2835 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2836 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2837 }, 2838 { 2839 .label = "status:red", 2840 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2841 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2842 }, 2843 { 2844 .label = "psu:green", 2845 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2846 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2847 }, 2848 { 2849 .label = "psu:red", 2850 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2851 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2852 }, 2853 { 2854 .label = "fan1:green", 2855 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2856 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2857 }, 2858 { 2859 .label = "fan1:red", 2860 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2861 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2862 }, 2863 { 2864 .label = "fan2:green", 2865 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2866 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2867 }, 2868 { 2869 .label = "fan2:red", 2870 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2871 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2872 }, 2873 { 2874 .label = "fan3:green", 2875 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2876 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2877 }, 2878 { 2879 .label = "fan3:red", 2880 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2881 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2882 }, 2883 { 2884 .label = "fan4:green", 2885 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2886 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2887 }, 2888 { 2889 .label = "fan4:red", 2890 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2891 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2892 }, 2893 { 2894 .label = "uid:blue", 2895 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 2896 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2897 }, 2898 }; 2899 2900 static struct mlxreg_core_platform_data mlxplat_comex_100G_led_data = { 2901 .data = mlxplat_mlxcpld_comex_100G_led_data, 2902 .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_100G_led_data), 2903 }; 2904 2905 /* Platform led for data for modular systems */ 2906 static struct mlxreg_core_data mlxplat_mlxcpld_modular_led_data[] = { 2907 { 2908 .label = "status:green", 2909 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2910 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2911 }, 2912 { 2913 .label = "status:orange", 2914 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2915 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2916 }, 2917 { 2918 .label = "psu:green", 2919 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2920 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2921 }, 2922 { 2923 .label = "psu:orange", 2924 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2925 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2926 }, 2927 { 2928 .label = "fan1:green", 2929 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2930 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2931 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2932 .bit = BIT(0), 2933 }, 2934 { 2935 .label = "fan1:orange", 2936 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2937 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2938 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2939 .bit = BIT(0), 2940 }, 2941 { 2942 .label = "fan2:green", 2943 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2944 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2945 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2946 .bit = BIT(1), 2947 }, 2948 { 2949 .label = "fan2:orange", 2950 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2951 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2952 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2953 .bit = BIT(1), 2954 }, 2955 { 2956 .label = "fan3:green", 2957 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2958 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2959 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2960 .bit = BIT(2), 2961 }, 2962 { 2963 .label = "fan3:orange", 2964 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2965 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2966 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2967 .bit = BIT(2), 2968 }, 2969 { 2970 .label = "fan4:green", 2971 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2972 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2973 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2974 .bit = BIT(3), 2975 }, 2976 { 2977 .label = "fan4:orange", 2978 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2979 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2980 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2981 .bit = BIT(3), 2982 }, 2983 { 2984 .label = "fan5:green", 2985 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2986 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2987 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2988 .bit = BIT(4), 2989 }, 2990 { 2991 .label = "fan5:orange", 2992 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2993 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2994 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2995 .bit = BIT(4), 2996 }, 2997 { 2998 .label = "fan6:green", 2999 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3000 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3001 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3002 .bit = BIT(5), 3003 }, 3004 { 3005 .label = "fan6:orange", 3006 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3007 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3008 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3009 .bit = BIT(5), 3010 }, 3011 { 3012 .label = "fan7:green", 3013 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 3014 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3015 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3016 .bit = BIT(6), 3017 }, 3018 { 3019 .label = "fan7:orange", 3020 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 3021 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3022 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3023 .bit = BIT(6), 3024 }, 3025 { 3026 .label = "uid:blue", 3027 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 3028 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3029 }, 3030 { 3031 .label = "fan_front:green", 3032 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 3033 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3034 }, 3035 { 3036 .label = "fan_front:orange", 3037 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 3038 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3039 }, 3040 { 3041 .label = "mgmt:green", 3042 .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, 3043 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3044 }, 3045 { 3046 .label = "mgmt:orange", 3047 .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, 3048 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3049 }, 3050 }; 3051 3052 static struct mlxreg_core_platform_data mlxplat_modular_led_data = { 3053 .data = mlxplat_mlxcpld_modular_led_data, 3054 .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_led_data), 3055 }; 3056 3057 /* Platform led data for chassis system */ 3058 static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_led_data[] = { 3059 { 3060 .label = "status:green", 3061 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3062 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3063 }, 3064 { 3065 .label = "status:orange", 3066 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 3067 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 3068 }, 3069 { 3070 .label = "fan1:green", 3071 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3072 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3073 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3074 .bit = BIT(0), 3075 }, 3076 { 3077 .label = "fan1:orange", 3078 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3079 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3080 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3081 .bit = BIT(0), 3082 }, 3083 { 3084 .label = "fan2:green", 3085 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3086 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3087 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3088 .bit = BIT(1), 3089 }, 3090 { 3091 .label = "fan2:orange", 3092 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 3093 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3094 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3095 .bit = BIT(1), 3096 }, 3097 { 3098 .label = "fan3:green", 3099 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3100 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3101 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3102 .bit = BIT(2), 3103 }, 3104 { 3105 .label = "fan3:orange", 3106 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3107 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3108 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3109 .bit = BIT(2), 3110 }, 3111 { 3112 .label = "fan4:green", 3113 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3114 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3115 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3116 .bit = BIT(3), 3117 }, 3118 { 3119 .label = "fan4:orange", 3120 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 3121 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3122 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3123 .bit = BIT(3), 3124 }, 3125 { 3126 .label = "fan5:green", 3127 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3128 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3129 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3130 .bit = BIT(4), 3131 }, 3132 { 3133 .label = "fan5:orange", 3134 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3135 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3136 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3137 .bit = BIT(4), 3138 }, 3139 { 3140 .label = "fan6:green", 3141 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3142 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3143 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3144 .bit = BIT(5), 3145 }, 3146 { 3147 .label = "fan6:orange", 3148 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 3149 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 3150 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3151 .bit = BIT(5), 3152 }, 3153 { 3154 .label = "uid:blue", 3155 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 3156 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 3157 }, 3158 }; 3159 3160 static struct mlxreg_core_platform_data mlxplat_l1_switch_led_data = { 3161 .data = mlxplat_mlxcpld_l1_switch_led_data, 3162 .counter = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_led_data), 3163 }; 3164 3165 /* Platform register access default */ 3166 static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = { 3167 { 3168 .label = "cpld1_version", 3169 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 3170 .bit = GENMASK(7, 0), 3171 .mode = 0444, 3172 }, 3173 { 3174 .label = "cpld2_version", 3175 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 3176 .bit = GENMASK(7, 0), 3177 .mode = 0444, 3178 }, 3179 { 3180 .label = "cpld1_pn", 3181 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 3182 .bit = GENMASK(15, 0), 3183 .mode = 0444, 3184 .regnum = 2, 3185 }, 3186 { 3187 .label = "cpld2_pn", 3188 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 3189 .bit = GENMASK(15, 0), 3190 .mode = 0444, 3191 .regnum = 2, 3192 }, 3193 { 3194 .label = "cpld1_version_min", 3195 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 3196 .bit = GENMASK(7, 0), 3197 .mode = 0444, 3198 }, 3199 { 3200 .label = "cpld2_version_min", 3201 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 3202 .bit = GENMASK(7, 0), 3203 .mode = 0444, 3204 }, 3205 { 3206 .label = "reset_long_pb", 3207 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3208 .mask = GENMASK(7, 0) & ~BIT(0), 3209 .mode = 0444, 3210 }, 3211 { 3212 .label = "reset_short_pb", 3213 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3214 .mask = GENMASK(7, 0) & ~BIT(1), 3215 .mode = 0444, 3216 }, 3217 { 3218 .label = "reset_aux_pwr_or_ref", 3219 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3220 .mask = GENMASK(7, 0) & ~BIT(2), 3221 .mode = 0444, 3222 }, 3223 { 3224 .label = "reset_main_pwr_fail", 3225 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3226 .mask = GENMASK(7, 0) & ~BIT(3), 3227 .mode = 0444, 3228 }, 3229 { 3230 .label = "reset_sw_reset", 3231 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3232 .mask = GENMASK(7, 0) & ~BIT(4), 3233 .mode = 0444, 3234 }, 3235 { 3236 .label = "reset_fw_reset", 3237 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3238 .mask = GENMASK(7, 0) & ~BIT(5), 3239 .mode = 0444, 3240 }, 3241 { 3242 .label = "reset_hotswap_or_wd", 3243 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3244 .mask = GENMASK(7, 0) & ~BIT(6), 3245 .mode = 0444, 3246 }, 3247 { 3248 .label = "reset_asic_thermal", 3249 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3250 .mask = GENMASK(7, 0) & ~BIT(7), 3251 .mode = 0444, 3252 }, 3253 { 3254 .label = "psu1_on", 3255 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3256 .mask = GENMASK(7, 0) & ~BIT(0), 3257 .mode = 0200, 3258 }, 3259 { 3260 .label = "psu2_on", 3261 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3262 .mask = GENMASK(7, 0) & ~BIT(1), 3263 .mode = 0200, 3264 }, 3265 { 3266 .label = "pwr_cycle", 3267 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3268 .mask = GENMASK(7, 0) & ~BIT(2), 3269 .mode = 0200, 3270 }, 3271 { 3272 .label = "pwr_down", 3273 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3274 .mask = GENMASK(7, 0) & ~BIT(3), 3275 .mode = 0200, 3276 }, 3277 { 3278 .label = "select_iio", 3279 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 3280 .mask = GENMASK(7, 0) & ~BIT(6), 3281 .mode = 0644, 3282 }, 3283 { 3284 .label = "asic_health", 3285 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 3286 .mask = MLXPLAT_CPLD_ASIC_MASK, 3287 .bit = 1, 3288 .mode = 0444, 3289 }, 3290 }; 3291 3292 static struct mlxreg_core_platform_data mlxplat_default_regs_io_data = { 3293 .data = mlxplat_mlxcpld_default_regs_io_data, 3294 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_regs_io_data), 3295 }; 3296 3297 /* Platform register access MSN21xx, MSN201x, MSN274x systems families data */ 3298 static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = { 3299 { 3300 .label = "cpld1_version", 3301 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 3302 .bit = GENMASK(7, 0), 3303 .mode = 0444, 3304 }, 3305 { 3306 .label = "cpld2_version", 3307 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 3308 .bit = GENMASK(7, 0), 3309 .mode = 0444, 3310 }, 3311 { 3312 .label = "cpld1_pn", 3313 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 3314 .bit = GENMASK(15, 0), 3315 .mode = 0444, 3316 .regnum = 2, 3317 }, 3318 { 3319 .label = "cpld2_pn", 3320 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 3321 .bit = GENMASK(15, 0), 3322 .mode = 0444, 3323 .regnum = 2, 3324 }, 3325 { 3326 .label = "cpld1_version_min", 3327 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 3328 .bit = GENMASK(7, 0), 3329 .mode = 0444, 3330 }, 3331 { 3332 .label = "cpld2_version_min", 3333 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 3334 .bit = GENMASK(7, 0), 3335 .mode = 0444, 3336 }, 3337 { 3338 .label = "reset_long_pb", 3339 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3340 .mask = GENMASK(7, 0) & ~BIT(0), 3341 .mode = 0444, 3342 }, 3343 { 3344 .label = "reset_short_pb", 3345 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3346 .mask = GENMASK(7, 0) & ~BIT(1), 3347 .mode = 0444, 3348 }, 3349 { 3350 .label = "reset_aux_pwr_or_ref", 3351 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3352 .mask = GENMASK(7, 0) & ~BIT(2), 3353 .mode = 0444, 3354 }, 3355 { 3356 .label = "reset_sw_reset", 3357 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3358 .mask = GENMASK(7, 0) & ~BIT(3), 3359 .mode = 0444, 3360 }, 3361 { 3362 .label = "reset_main_pwr_fail", 3363 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3364 .mask = GENMASK(7, 0) & ~BIT(4), 3365 .mode = 0444, 3366 }, 3367 { 3368 .label = "reset_asic_thermal", 3369 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3370 .mask = GENMASK(7, 0) & ~BIT(5), 3371 .mode = 0444, 3372 }, 3373 { 3374 .label = "reset_hotswap_or_halt", 3375 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3376 .mask = GENMASK(7, 0) & ~BIT(6), 3377 .mode = 0444, 3378 }, 3379 { 3380 .label = "reset_sff_wd", 3381 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3382 .mask = GENMASK(7, 0) & ~BIT(6), 3383 .mode = 0444, 3384 }, 3385 { 3386 .label = "psu1_on", 3387 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3388 .mask = GENMASK(7, 0) & ~BIT(0), 3389 .mode = 0200, 3390 }, 3391 { 3392 .label = "psu2_on", 3393 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3394 .mask = GENMASK(7, 0) & ~BIT(1), 3395 .mode = 0200, 3396 }, 3397 { 3398 .label = "pwr_cycle", 3399 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3400 .mask = GENMASK(7, 0) & ~BIT(2), 3401 .mode = 0200, 3402 }, 3403 { 3404 .label = "pwr_down", 3405 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3406 .mask = GENMASK(7, 0) & ~BIT(3), 3407 .mode = 0200, 3408 }, 3409 { 3410 .label = "select_iio", 3411 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 3412 .mask = GENMASK(7, 0) & ~BIT(6), 3413 .mode = 0644, 3414 }, 3415 { 3416 .label = "asic_health", 3417 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 3418 .mask = MLXPLAT_CPLD_ASIC_MASK, 3419 .bit = 1, 3420 .mode = 0444, 3421 }, 3422 }; 3423 3424 static struct mlxreg_core_platform_data mlxplat_msn21xx_regs_io_data = { 3425 .data = mlxplat_mlxcpld_msn21xx_regs_io_data, 3426 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_regs_io_data), 3427 }; 3428 3429 /* Platform register access for next generation systems families data */ 3430 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { 3431 { 3432 .label = "cpld1_version", 3433 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 3434 .bit = GENMASK(7, 0), 3435 .mode = 0444, 3436 }, 3437 { 3438 .label = "cpld2_version", 3439 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 3440 .bit = GENMASK(7, 0), 3441 .mode = 0444, 3442 }, 3443 { 3444 .label = "cpld3_version", 3445 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, 3446 .bit = GENMASK(7, 0), 3447 .mode = 0444, 3448 }, 3449 { 3450 .label = "cpld4_version", 3451 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET, 3452 .bit = GENMASK(7, 0), 3453 .mode = 0444, 3454 }, 3455 { 3456 .label = "cpld5_version", 3457 .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET, 3458 .bit = GENMASK(7, 0), 3459 .mode = 0444, 3460 }, 3461 { 3462 .label = "cpld1_pn", 3463 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 3464 .bit = GENMASK(15, 0), 3465 .mode = 0444, 3466 .regnum = 2, 3467 }, 3468 { 3469 .label = "cpld2_pn", 3470 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 3471 .bit = GENMASK(15, 0), 3472 .mode = 0444, 3473 .regnum = 2, 3474 }, 3475 { 3476 .label = "cpld3_pn", 3477 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET, 3478 .bit = GENMASK(15, 0), 3479 .mode = 0444, 3480 .regnum = 2, 3481 }, 3482 { 3483 .label = "cpld4_pn", 3484 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET, 3485 .bit = GENMASK(15, 0), 3486 .mode = 0444, 3487 .regnum = 2, 3488 }, 3489 { 3490 .label = "cpld5_pn", 3491 .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET, 3492 .bit = GENMASK(15, 0), 3493 .mode = 0444, 3494 .regnum = 2, 3495 }, 3496 { 3497 .label = "cpld1_version_min", 3498 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 3499 .bit = GENMASK(7, 0), 3500 .mode = 0444, 3501 }, 3502 { 3503 .label = "cpld2_version_min", 3504 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 3505 .bit = GENMASK(7, 0), 3506 .mode = 0444, 3507 }, 3508 { 3509 .label = "cpld3_version_min", 3510 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET, 3511 .bit = GENMASK(7, 0), 3512 .mode = 0444, 3513 }, 3514 { 3515 .label = "cpld4_version_min", 3516 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET, 3517 .bit = GENMASK(7, 0), 3518 .mode = 0444, 3519 }, 3520 { 3521 .label = "cpld5_version_min", 3522 .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET, 3523 .bit = GENMASK(7, 0), 3524 .mode = 0444, 3525 }, 3526 { 3527 .label = "asic_reset", 3528 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, 3529 .mask = GENMASK(7, 0) & ~BIT(3), 3530 .mode = 0200, 3531 }, 3532 { 3533 .label = "asic2_reset", 3534 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, 3535 .mask = GENMASK(7, 0) & ~BIT(2), 3536 .mode = 0200, 3537 }, 3538 { 3539 .label = "erot1_reset", 3540 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, 3541 .mask = GENMASK(7, 0) & ~BIT(6), 3542 .mode = 0644, 3543 }, 3544 { 3545 .label = "erot2_reset", 3546 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, 3547 .mask = GENMASK(7, 0) & ~BIT(7), 3548 .mode = 0644, 3549 }, 3550 { 3551 .label = "clk_brd_prog_en", 3552 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 3553 .mask = GENMASK(7, 0) & ~BIT(1), 3554 .mode = 0644, 3555 .secured = 1, 3556 }, 3557 { 3558 .label = "erot1_recovery", 3559 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 3560 .mask = GENMASK(7, 0) & ~BIT(6), 3561 .mode = 0644, 3562 }, 3563 { 3564 .label = "erot2_recovery", 3565 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 3566 .mask = GENMASK(7, 0) & ~BIT(7), 3567 .mode = 0644, 3568 }, 3569 { 3570 .label = "erot1_wp", 3571 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 3572 .mask = GENMASK(7, 0) & ~BIT(4), 3573 .mode = 0644, 3574 .secured = 1, 3575 }, 3576 { 3577 .label = "erot2_wp", 3578 .reg = MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 3579 .mask = GENMASK(7, 0) & ~BIT(5), 3580 .mode = 0644, 3581 .secured = 1, 3582 }, 3583 { 3584 .label = "reset_long_pb", 3585 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3586 .mask = GENMASK(7, 0) & ~BIT(0), 3587 .mode = 0444, 3588 }, 3589 { 3590 .label = "reset_short_pb", 3591 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3592 .mask = GENMASK(7, 0) & ~BIT(1), 3593 .mode = 0444, 3594 }, 3595 { 3596 .label = "reset_aux_pwr_or_ref", 3597 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3598 .mask = GENMASK(7, 0) & ~BIT(2), 3599 .mode = 0444, 3600 }, 3601 { 3602 .label = "reset_swb_dc_dc_pwr_fail", 3603 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3604 .mask = GENMASK(7, 0) & ~BIT(3), 3605 .mode = 0444, 3606 }, 3607 { 3608 .label = "reset_from_asic", 3609 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3610 .mask = GENMASK(7, 0) & ~BIT(5), 3611 .mode = 0444, 3612 }, 3613 { 3614 .label = "reset_swb_wd", 3615 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3616 .mask = GENMASK(7, 0) & ~BIT(6), 3617 .mode = 0444, 3618 }, 3619 { 3620 .label = "reset_asic_thermal", 3621 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3622 .mask = GENMASK(7, 0) & ~BIT(7), 3623 .mode = 0444, 3624 }, 3625 { 3626 .label = "reset_sw_reset", 3627 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3628 .mask = GENMASK(7, 0) & ~BIT(0), 3629 .mode = 0444, 3630 }, 3631 { 3632 .label = "reset_comex_pwr_fail", 3633 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3634 .mask = GENMASK(7, 0) & ~BIT(3), 3635 .mode = 0444, 3636 }, 3637 { 3638 .label = "reset_platform", 3639 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3640 .mask = GENMASK(7, 0) & ~BIT(4), 3641 .mode = 0444, 3642 }, 3643 { 3644 .label = "reset_soc", 3645 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3646 .mask = GENMASK(7, 0) & ~BIT(5), 3647 .mode = 0444, 3648 }, 3649 { 3650 .label = "reset_comex_wd", 3651 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3652 .mask = GENMASK(7, 0) & ~BIT(6), 3653 .mode = 0444, 3654 }, 3655 { 3656 .label = "reset_pwr_converter_fail", 3657 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3658 .mask = GENMASK(7, 0) & ~BIT(0), 3659 .mode = 0444, 3660 }, 3661 { 3662 .label = "reset_system", 3663 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3664 .mask = GENMASK(7, 0) & ~BIT(1), 3665 .mode = 0444, 3666 }, 3667 { 3668 .label = "reset_sw_pwr_off", 3669 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3670 .mask = GENMASK(7, 0) & ~BIT(2), 3671 .mode = 0444, 3672 }, 3673 { 3674 .label = "reset_comex_thermal", 3675 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3676 .mask = GENMASK(7, 0) & ~BIT(3), 3677 .mode = 0444, 3678 }, 3679 { 3680 .label = "reset_reload_bios", 3681 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3682 .mask = GENMASK(7, 0) & ~BIT(5), 3683 .mode = 0444, 3684 }, 3685 { 3686 .label = "reset_ac_pwr_fail", 3687 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3688 .mask = GENMASK(7, 0) & ~BIT(6), 3689 .mode = 0444, 3690 }, 3691 { 3692 .label = "reset_ac_ok_fail", 3693 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3694 .mask = GENMASK(7, 0) & ~BIT(7), 3695 .mode = 0444, 3696 }, 3697 { 3698 .label = "psu1_on", 3699 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3700 .mask = GENMASK(7, 0) & ~BIT(0), 3701 .mode = 0200, 3702 }, 3703 { 3704 .label = "psu2_on", 3705 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3706 .mask = GENMASK(7, 0) & ~BIT(1), 3707 .mode = 0200, 3708 }, 3709 { 3710 .label = "pwr_cycle", 3711 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3712 .mask = GENMASK(7, 0) & ~BIT(2), 3713 .mode = 0200, 3714 }, 3715 { 3716 .label = "pwr_down", 3717 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3718 .mask = GENMASK(7, 0) & ~BIT(3), 3719 .mode = 0200, 3720 }, 3721 { 3722 .label = "deep_pwr_cycle", 3723 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3724 .mask = GENMASK(7, 0) & ~BIT(5), 3725 .mode = 0200, 3726 }, 3727 { 3728 .label = "latch_reset", 3729 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3730 .mask = GENMASK(7, 0) & ~BIT(6), 3731 .mode = 0200, 3732 }, 3733 { 3734 .label = "jtag_cap", 3735 .reg = MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET, 3736 .mask = MLXPLAT_CPLD_FU_CAP_MASK, 3737 .bit = 1, 3738 .mode = 0444, 3739 }, 3740 { 3741 .label = "jtag_enable", 3742 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 3743 .mask = GENMASK(7, 0) & ~BIT(4), 3744 .mode = 0644, 3745 }, 3746 { 3747 .label = "dbg1", 3748 .reg = MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET, 3749 .bit = GENMASK(7, 0), 3750 .mode = 0644, 3751 }, 3752 { 3753 .label = "dbg2", 3754 .reg = MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET, 3755 .bit = GENMASK(7, 0), 3756 .mode = 0644, 3757 }, 3758 { 3759 .label = "dbg3", 3760 .reg = MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET, 3761 .bit = GENMASK(7, 0), 3762 .mode = 0644, 3763 }, 3764 { 3765 .label = "dbg4", 3766 .reg = MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET, 3767 .bit = GENMASK(7, 0), 3768 .mode = 0644, 3769 }, 3770 { 3771 .label = "asic_health", 3772 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 3773 .mask = MLXPLAT_CPLD_ASIC_MASK, 3774 .bit = 1, 3775 .mode = 0444, 3776 }, 3777 { 3778 .label = "asic2_health", 3779 .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, 3780 .mask = MLXPLAT_CPLD_ASIC_MASK, 3781 .bit = 1, 3782 .mode = 0444, 3783 }, 3784 { 3785 .label = "fan_dir", 3786 .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, 3787 .bit = GENMASK(7, 0), 3788 .mode = 0444, 3789 }, 3790 { 3791 .label = "bios_safe_mode", 3792 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3793 .mask = GENMASK(7, 0) & ~BIT(4), 3794 .mode = 0444, 3795 }, 3796 { 3797 .label = "bios_active_image", 3798 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3799 .mask = GENMASK(7, 0) & ~BIT(5), 3800 .mode = 0444, 3801 }, 3802 { 3803 .label = "bios_auth_fail", 3804 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3805 .mask = GENMASK(7, 0) & ~BIT(6), 3806 .mode = 0444, 3807 }, 3808 { 3809 .label = "bios_upgrade_fail", 3810 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3811 .mask = GENMASK(7, 0) & ~BIT(7), 3812 .mode = 0444, 3813 }, 3814 { 3815 .label = "voltreg_update_status", 3816 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, 3817 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, 3818 .bit = 5, 3819 .mode = 0444, 3820 }, 3821 { 3822 .label = "pwr_converter_prog_en", 3823 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 3824 .mask = GENMASK(7, 0) & ~BIT(0), 3825 .mode = 0644, 3826 .secured = 1, 3827 }, 3828 { 3829 .label = "vpd_wp", 3830 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 3831 .mask = GENMASK(7, 0) & ~BIT(3), 3832 .mode = 0644, 3833 }, 3834 { 3835 .label = "pcie_asic_reset_dis", 3836 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 3837 .mask = GENMASK(7, 0) & ~BIT(4), 3838 .mode = 0644, 3839 }, 3840 { 3841 .label = "erot1_ap_reset", 3842 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 3843 .mask = GENMASK(7, 0) & ~BIT(0), 3844 .mode = 0444, 3845 }, 3846 { 3847 .label = "erot2_ap_reset", 3848 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 3849 .mask = GENMASK(7, 0) & ~BIT(1), 3850 .mode = 0444, 3851 }, 3852 { 3853 .label = "lid_open", 3854 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 3855 .mask = GENMASK(7, 0) & ~BIT(2), 3856 .mode = 0444, 3857 }, 3858 { 3859 .label = "clk_brd1_boot_fail", 3860 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 3861 .mask = GENMASK(7, 0) & ~BIT(4), 3862 .mode = 0444, 3863 }, 3864 { 3865 .label = "clk_brd2_boot_fail", 3866 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 3867 .mask = GENMASK(7, 0) & ~BIT(5), 3868 .mode = 0444, 3869 }, 3870 { 3871 .label = "clk_brd_fail", 3872 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 3873 .mask = GENMASK(7, 0) & ~BIT(6), 3874 .mode = 0444, 3875 }, 3876 { 3877 .label = "asic_pg_fail", 3878 .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, 3879 .mask = GENMASK(7, 0) & ~BIT(7), 3880 .mode = 0444, 3881 }, 3882 { 3883 .label = "spi_chnl_select", 3884 .reg = MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT, 3885 .mask = GENMASK(7, 0), 3886 .bit = 1, 3887 .mode = 0644, 3888 }, 3889 { 3890 .label = "config1", 3891 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, 3892 .bit = GENMASK(7, 0), 3893 .mode = 0444, 3894 }, 3895 { 3896 .label = "config2", 3897 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, 3898 .bit = GENMASK(7, 0), 3899 .mode = 0444, 3900 }, 3901 { 3902 .label = "config3", 3903 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, 3904 .bit = GENMASK(7, 0), 3905 .mode = 0444, 3906 }, 3907 { 3908 .label = "ufm_version", 3909 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, 3910 .bit = GENMASK(7, 0), 3911 .mode = 0444, 3912 }, 3913 }; 3914 3915 static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = { 3916 .data = mlxplat_mlxcpld_default_ng_regs_io_data, 3917 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_regs_io_data), 3918 }; 3919 3920 /* Platform register access for modular systems families data */ 3921 static struct mlxreg_core_data mlxplat_mlxcpld_modular_regs_io_data[] = { 3922 { 3923 .label = "cpld1_version", 3924 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 3925 .bit = GENMASK(7, 0), 3926 .mode = 0444, 3927 }, 3928 { 3929 .label = "cpld2_version", 3930 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 3931 .bit = GENMASK(7, 0), 3932 .mode = 0444, 3933 }, 3934 { 3935 .label = "cpld3_version", 3936 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, 3937 .bit = GENMASK(7, 0), 3938 .mode = 0444, 3939 }, 3940 { 3941 .label = "cpld4_version", 3942 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET, 3943 .bit = GENMASK(7, 0), 3944 .mode = 0444, 3945 }, 3946 { 3947 .label = "cpld1_pn", 3948 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 3949 .bit = GENMASK(15, 0), 3950 .mode = 0444, 3951 .regnum = 2, 3952 }, 3953 { 3954 .label = "cpld2_pn", 3955 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 3956 .bit = GENMASK(15, 0), 3957 .mode = 0444, 3958 .regnum = 2, 3959 }, 3960 { 3961 .label = "cpld3_pn", 3962 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET, 3963 .bit = GENMASK(15, 0), 3964 .mode = 0444, 3965 .regnum = 2, 3966 }, 3967 { 3968 .label = "cpld4_pn", 3969 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET, 3970 .bit = GENMASK(15, 0), 3971 .mode = 0444, 3972 .regnum = 2, 3973 }, 3974 { 3975 .label = "cpld1_version_min", 3976 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 3977 .bit = GENMASK(7, 0), 3978 .mode = 0444, 3979 }, 3980 { 3981 .label = "cpld2_version_min", 3982 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 3983 .bit = GENMASK(7, 0), 3984 .mode = 0444, 3985 }, 3986 { 3987 .label = "cpld3_version_min", 3988 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET, 3989 .bit = GENMASK(7, 0), 3990 .mode = 0444, 3991 }, 3992 { 3993 .label = "cpld4_version_min", 3994 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET, 3995 .bit = GENMASK(7, 0), 3996 .mode = 0444, 3997 }, 3998 { 3999 .label = "lc1_enable", 4000 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 4001 .mask = GENMASK(7, 0) & ~BIT(0), 4002 .mode = 0644, 4003 }, 4004 { 4005 .label = "lc2_enable", 4006 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 4007 .mask = GENMASK(7, 0) & ~BIT(1), 4008 .mode = 0644, 4009 }, 4010 { 4011 .label = "lc3_enable", 4012 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 4013 .mask = GENMASK(7, 0) & ~BIT(2), 4014 .mode = 0644, 4015 }, 4016 { 4017 .label = "lc4_enable", 4018 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 4019 .mask = GENMASK(7, 0) & ~BIT(3), 4020 .mode = 0644, 4021 }, 4022 { 4023 .label = "lc5_enable", 4024 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 4025 .mask = GENMASK(7, 0) & ~BIT(4), 4026 .mode = 0644, 4027 }, 4028 { 4029 .label = "lc6_enable", 4030 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 4031 .mask = GENMASK(7, 0) & ~BIT(5), 4032 .mode = 0644, 4033 }, 4034 { 4035 .label = "lc7_enable", 4036 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 4037 .mask = GENMASK(7, 0) & ~BIT(6), 4038 .mode = 0644, 4039 }, 4040 { 4041 .label = "lc8_enable", 4042 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 4043 .mask = GENMASK(7, 0) & ~BIT(7), 4044 .mode = 0644, 4045 }, 4046 { 4047 .label = "reset_long_pb", 4048 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4049 .mask = GENMASK(7, 0) & ~BIT(0), 4050 .mode = 0444, 4051 }, 4052 { 4053 .label = "reset_short_pb", 4054 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4055 .mask = GENMASK(7, 0) & ~BIT(1), 4056 .mode = 0444, 4057 }, 4058 { 4059 .label = "reset_aux_pwr_or_fu", 4060 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4061 .mask = GENMASK(7, 0) & ~BIT(2), 4062 .mode = 0444, 4063 }, 4064 { 4065 .label = "reset_mgmt_dc_dc_pwr_fail", 4066 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4067 .mask = GENMASK(7, 0) & ~BIT(3), 4068 .mode = 0444, 4069 }, 4070 { 4071 .label = "reset_sys_comex_bios", 4072 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4073 .mask = GENMASK(7, 0) & ~BIT(5), 4074 .mode = 0444, 4075 }, 4076 { 4077 .label = "reset_sw_reset", 4078 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4079 .mask = GENMASK(7, 0) & ~BIT(0), 4080 .mode = 0444, 4081 }, 4082 { 4083 .label = "reset_aux_pwr_or_reload", 4084 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4085 .mask = GENMASK(7, 0) & ~BIT(2), 4086 .mode = 0444, 4087 }, 4088 { 4089 .label = "reset_comex_pwr_fail", 4090 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4091 .mask = GENMASK(7, 0) & ~BIT(3), 4092 .mode = 0444, 4093 }, 4094 { 4095 .label = "reset_platform", 4096 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4097 .mask = GENMASK(7, 0) & ~BIT(4), 4098 .mode = 0444, 4099 }, 4100 { 4101 .label = "reset_soc", 4102 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4103 .mask = GENMASK(7, 0) & ~BIT(5), 4104 .mode = 0444, 4105 }, 4106 { 4107 .label = "reset_pwr_off_from_carrier", 4108 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4109 .mask = GENMASK(7, 0) & ~BIT(7), 4110 .mode = 0444, 4111 }, 4112 { 4113 .label = "reset_swb_wd", 4114 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4115 .mask = GENMASK(7, 0) & ~BIT(0), 4116 .mode = 0444, 4117 }, 4118 { 4119 .label = "reset_swb_aux_pwr_or_fu", 4120 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4121 .mask = GENMASK(7, 0) & ~BIT(2), 4122 .mode = 0444, 4123 }, 4124 { 4125 .label = "reset_swb_dc_dc_pwr_fail", 4126 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4127 .mask = GENMASK(7, 0) & ~BIT(3), 4128 .mode = 0444, 4129 }, 4130 { 4131 .label = "reset_swb_12v_fail", 4132 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4133 .mask = GENMASK(7, 0) & ~BIT(4), 4134 .mode = 0444, 4135 }, 4136 { 4137 .label = "reset_system", 4138 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4139 .mask = GENMASK(7, 0) & ~BIT(5), 4140 .mode = 0444, 4141 }, 4142 { 4143 .label = "reset_thermal_spc_or_pciesw", 4144 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4145 .mask = GENMASK(7, 0) & ~BIT(7), 4146 .mode = 0444, 4147 }, 4148 { 4149 .label = "bios_safe_mode", 4150 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4151 .mask = GENMASK(7, 0) & ~BIT(4), 4152 .mode = 0444, 4153 }, 4154 { 4155 .label = "bios_active_image", 4156 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4157 .mask = GENMASK(7, 0) & ~BIT(5), 4158 .mode = 0444, 4159 }, 4160 { 4161 .label = "bios_auth_fail", 4162 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4163 .mask = GENMASK(7, 0) & ~BIT(6), 4164 .mode = 0444, 4165 }, 4166 { 4167 .label = "bios_upgrade_fail", 4168 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4169 .mask = GENMASK(7, 0) & ~BIT(7), 4170 .mode = 0444, 4171 }, 4172 { 4173 .label = "voltreg_update_status", 4174 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, 4175 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, 4176 .bit = 5, 4177 .mode = 0444, 4178 }, 4179 { 4180 .label = "vpd_wp", 4181 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 4182 .mask = GENMASK(7, 0) & ~BIT(3), 4183 .mode = 0644, 4184 }, 4185 { 4186 .label = "pcie_asic_reset_dis", 4187 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 4188 .mask = GENMASK(7, 0) & ~BIT(4), 4189 .mode = 0644, 4190 }, 4191 { 4192 .label = "shutdown_unlock", 4193 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 4194 .mask = GENMASK(7, 0) & ~BIT(5), 4195 .mode = 0644, 4196 }, 4197 { 4198 .label = "lc1_rst_mask", 4199 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 4200 .mask = GENMASK(7, 0) & ~BIT(0), 4201 .mode = 0200, 4202 }, 4203 { 4204 .label = "lc2_rst_mask", 4205 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 4206 .mask = GENMASK(7, 0) & ~BIT(1), 4207 .mode = 0200, 4208 }, 4209 { 4210 .label = "lc3_rst_mask", 4211 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 4212 .mask = GENMASK(7, 0) & ~BIT(2), 4213 .mode = 0200, 4214 }, 4215 { 4216 .label = "lc4_rst_mask", 4217 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 4218 .mask = GENMASK(7, 0) & ~BIT(3), 4219 .mode = 0200, 4220 }, 4221 { 4222 .label = "lc5_rst_mask", 4223 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 4224 .mask = GENMASK(7, 0) & ~BIT(4), 4225 .mode = 0200, 4226 }, 4227 { 4228 .label = "lc6_rst_mask", 4229 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 4230 .mask = GENMASK(7, 0) & ~BIT(5), 4231 .mode = 0200, 4232 }, 4233 { 4234 .label = "lc7_rst_mask", 4235 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 4236 .mask = GENMASK(7, 0) & ~BIT(6), 4237 .mode = 0200, 4238 }, 4239 { 4240 .label = "lc8_rst_mask", 4241 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 4242 .mask = GENMASK(7, 0) & ~BIT(7), 4243 .mode = 0200, 4244 }, 4245 { 4246 .label = "psu1_on", 4247 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4248 .mask = GENMASK(7, 0) & ~BIT(0), 4249 .mode = 0200, 4250 }, 4251 { 4252 .label = "psu2_on", 4253 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4254 .mask = GENMASK(7, 0) & ~BIT(1), 4255 .mode = 0200, 4256 }, 4257 { 4258 .label = "pwr_cycle", 4259 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4260 .mask = GENMASK(7, 0) & ~BIT(2), 4261 .mode = 0200, 4262 }, 4263 { 4264 .label = "pwr_down", 4265 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4266 .mask = GENMASK(7, 0) & ~BIT(3), 4267 .mode = 0200, 4268 }, 4269 { 4270 .label = "psu3_on", 4271 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4272 .mask = GENMASK(7, 0) & ~BIT(4), 4273 .mode = 0200, 4274 }, 4275 { 4276 .label = "psu4_on", 4277 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4278 .mask = GENMASK(7, 0) & ~BIT(5), 4279 .mode = 0200, 4280 }, 4281 { 4282 .label = "auto_power_mode", 4283 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4284 .mask = GENMASK(7, 0) & ~BIT(6), 4285 .mode = 0644, 4286 }, 4287 { 4288 .label = "pm_mgmt_en", 4289 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4290 .mask = GENMASK(7, 0) & ~BIT(7), 4291 .mode = 0644, 4292 }, 4293 { 4294 .label = "jtag_enable", 4295 .reg = MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE, 4296 .mask = GENMASK(3, 0), 4297 .bit = 1, 4298 .mode = 0644, 4299 }, 4300 { 4301 .label = "safe_bios_dis", 4302 .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, 4303 .mask = GENMASK(7, 0) & ~BIT(5), 4304 .mode = 0644, 4305 }, 4306 { 4307 .label = "safe_bios_dis_wp", 4308 .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET, 4309 .mask = GENMASK(7, 0) & ~BIT(5), 4310 .mode = 0644, 4311 }, 4312 { 4313 .label = "asic_health", 4314 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 4315 .mask = MLXPLAT_CPLD_ASIC_MASK, 4316 .bit = 1, 4317 .mode = 0444, 4318 }, 4319 { 4320 .label = "fan_dir", 4321 .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, 4322 .bit = GENMASK(7, 0), 4323 .mode = 0444, 4324 }, 4325 { 4326 .label = "lc1_pwr", 4327 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 4328 .mask = GENMASK(7, 0) & ~BIT(0), 4329 .mode = 0644, 4330 }, 4331 { 4332 .label = "lc2_pwr", 4333 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 4334 .mask = GENMASK(7, 0) & ~BIT(1), 4335 .mode = 0644, 4336 }, 4337 { 4338 .label = "lc3_pwr", 4339 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 4340 .mask = GENMASK(7, 0) & ~BIT(2), 4341 .mode = 0644, 4342 }, 4343 { 4344 .label = "lc4_pwr", 4345 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 4346 .mask = GENMASK(7, 0) & ~BIT(3), 4347 .mode = 0644, 4348 }, 4349 { 4350 .label = "lc5_pwr", 4351 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 4352 .mask = GENMASK(7, 0) & ~BIT(4), 4353 .mode = 0644, 4354 }, 4355 { 4356 .label = "lc6_pwr", 4357 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 4358 .mask = GENMASK(7, 0) & ~BIT(5), 4359 .mode = 0644, 4360 }, 4361 { 4362 .label = "lc7_pwr", 4363 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 4364 .mask = GENMASK(7, 0) & ~BIT(6), 4365 .mode = 0644, 4366 }, 4367 { 4368 .label = "lc8_pwr", 4369 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 4370 .mask = GENMASK(7, 0) & ~BIT(7), 4371 .mode = 0644, 4372 }, 4373 { 4374 .label = "config1", 4375 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, 4376 .bit = GENMASK(7, 0), 4377 .mode = 0444, 4378 }, 4379 { 4380 .label = "config2", 4381 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, 4382 .bit = GENMASK(7, 0), 4383 .mode = 0444, 4384 }, 4385 { 4386 .label = "config3", 4387 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, 4388 .bit = GENMASK(7, 0), 4389 .mode = 0444, 4390 }, 4391 { 4392 .label = "ufm_version", 4393 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, 4394 .bit = GENMASK(7, 0), 4395 .mode = 0444, 4396 }, 4397 }; 4398 4399 static struct mlxreg_core_platform_data mlxplat_modular_regs_io_data = { 4400 .data = mlxplat_mlxcpld_modular_regs_io_data, 4401 .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_regs_io_data), 4402 }; 4403 4404 /* Platform register access for chassis blade systems family data */ 4405 static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = { 4406 { 4407 .label = "cpld1_version", 4408 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 4409 .bit = GENMASK(7, 0), 4410 .mode = 0444, 4411 }, 4412 { 4413 .label = "cpld1_pn", 4414 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 4415 .bit = GENMASK(15, 0), 4416 .mode = 0444, 4417 .regnum = 2, 4418 }, 4419 { 4420 .label = "cpld1_version_min", 4421 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 4422 .bit = GENMASK(7, 0), 4423 .mode = 0444, 4424 }, 4425 { 4426 .label = "reset_aux_pwr_or_ref", 4427 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4428 .mask = GENMASK(7, 0) & ~BIT(2), 4429 .mode = 0444, 4430 }, 4431 { 4432 .label = "reset_from_comex", 4433 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4434 .mask = GENMASK(7, 0) & ~BIT(4), 4435 .mode = 0444, 4436 }, 4437 { 4438 .label = "reset_comex_pwr_fail", 4439 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4440 .mask = GENMASK(7, 0) & ~BIT(3), 4441 .mode = 0444, 4442 }, 4443 { 4444 .label = "reset_platform", 4445 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4446 .mask = GENMASK(7, 0) & ~BIT(4), 4447 .mode = 0444, 4448 }, 4449 { 4450 .label = "reset_soc", 4451 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4452 .mask = GENMASK(7, 0) & ~BIT(5), 4453 .mode = 0444, 4454 }, 4455 { 4456 .label = "reset_comex_wd", 4457 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 4458 .mask = GENMASK(7, 0) & ~BIT(6), 4459 .mode = 0444, 4460 }, 4461 { 4462 .label = "reset_voltmon_upgrade_fail", 4463 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4464 .mask = GENMASK(7, 0) & ~BIT(0), 4465 .mode = 0444, 4466 }, 4467 { 4468 .label = "reset_system", 4469 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4470 .mask = GENMASK(7, 0) & ~BIT(1), 4471 .mode = 0444, 4472 }, 4473 { 4474 .label = "reset_sw_pwr_off", 4475 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4476 .mask = GENMASK(7, 0) & ~BIT(2), 4477 .mode = 0444, 4478 }, 4479 { 4480 .label = "reset_comex_thermal", 4481 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4482 .mask = GENMASK(7, 0) & ~BIT(3), 4483 .mode = 0444, 4484 }, 4485 { 4486 .label = "reset_reload_bios", 4487 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4488 .mask = GENMASK(7, 0) & ~BIT(5), 4489 .mode = 0444, 4490 }, 4491 { 4492 .label = "reset_ac_pwr_fail", 4493 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4494 .mask = GENMASK(7, 0) & ~BIT(6), 4495 .mode = 0444, 4496 }, 4497 { 4498 .label = "reset_long_pwr_pb", 4499 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 4500 .mask = GENMASK(7, 0) & ~BIT(7), 4501 .mode = 0444, 4502 }, 4503 { 4504 .label = "pwr_cycle", 4505 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4506 .mask = GENMASK(7, 0) & ~BIT(2), 4507 .mode = 0200, 4508 }, 4509 { 4510 .label = "pwr_down", 4511 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 4512 .mask = GENMASK(7, 0) & ~BIT(3), 4513 .mode = 0200, 4514 }, 4515 { 4516 .label = "global_wp_request", 4517 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 4518 .mask = GENMASK(7, 0) & ~BIT(0), 4519 .mode = 0644, 4520 }, 4521 { 4522 .label = "jtag_enable", 4523 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 4524 .mask = GENMASK(7, 0) & ~BIT(4), 4525 .mode = 0644, 4526 }, 4527 { 4528 .label = "comm_chnl_ready", 4529 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 4530 .mask = GENMASK(7, 0) & ~BIT(6), 4531 .mode = 0200, 4532 }, 4533 { 4534 .label = "bios_safe_mode", 4535 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4536 .mask = GENMASK(7, 0) & ~BIT(4), 4537 .mode = 0444, 4538 }, 4539 { 4540 .label = "bios_active_image", 4541 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4542 .mask = GENMASK(7, 0) & ~BIT(5), 4543 .mode = 0444, 4544 }, 4545 { 4546 .label = "bios_auth_fail", 4547 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4548 .mask = GENMASK(7, 0) & ~BIT(6), 4549 .mode = 0444, 4550 }, 4551 { 4552 .label = "bios_upgrade_fail", 4553 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 4554 .mask = GENMASK(7, 0) & ~BIT(7), 4555 .mode = 0444, 4556 }, 4557 { 4558 .label = "voltreg_update_status", 4559 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, 4560 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, 4561 .bit = 5, 4562 .mode = 0444, 4563 }, 4564 { 4565 .label = "vpd_wp", 4566 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 4567 .mask = GENMASK(7, 0) & ~BIT(3), 4568 .mode = 0644, 4569 }, 4570 { 4571 .label = "pcie_asic_reset_dis", 4572 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 4573 .mask = GENMASK(7, 0) & ~BIT(4), 4574 .mode = 0644, 4575 }, 4576 { 4577 .label = "global_wp_response", 4578 .reg = MLXPLAT_CPLD_LPC_REG_GWP_OFFSET, 4579 .mask = GENMASK(7, 0) & ~BIT(0), 4580 .mode = 0444, 4581 }, 4582 { 4583 .label = "config1", 4584 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, 4585 .bit = GENMASK(7, 0), 4586 .mode = 0444, 4587 }, 4588 { 4589 .label = "config2", 4590 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, 4591 .bit = GENMASK(7, 0), 4592 .mode = 0444, 4593 }, 4594 { 4595 .label = "config3", 4596 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET, 4597 .bit = GENMASK(7, 0), 4598 .mode = 0444, 4599 }, 4600 { 4601 .label = "ufm_version", 4602 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, 4603 .bit = GENMASK(7, 0), 4604 .mode = 0444, 4605 }, 4606 }; 4607 4608 static struct mlxreg_core_platform_data mlxplat_chassis_blade_regs_io_data = { 4609 .data = mlxplat_mlxcpld_chassis_blade_regs_io_data, 4610 .counter = ARRAY_SIZE(mlxplat_mlxcpld_chassis_blade_regs_io_data), 4611 }; 4612 4613 /* Platform FAN default */ 4614 static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = { 4615 { 4616 .label = "pwm1", 4617 .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET, 4618 }, 4619 { 4620 .label = "pwm2", 4621 .reg = MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET, 4622 }, 4623 { 4624 .label = "pwm3", 4625 .reg = MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET, 4626 }, 4627 { 4628 .label = "pwm4", 4629 .reg = MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET, 4630 }, 4631 { 4632 .label = "tacho1", 4633 .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET, 4634 .mask = GENMASK(7, 0), 4635 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 4636 .bit = BIT(0), 4637 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 4638 4639 }, 4640 { 4641 .label = "tacho2", 4642 .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET, 4643 .mask = GENMASK(7, 0), 4644 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 4645 .bit = BIT(1), 4646 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 4647 }, 4648 { 4649 .label = "tacho3", 4650 .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET, 4651 .mask = GENMASK(7, 0), 4652 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 4653 .bit = BIT(2), 4654 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 4655 }, 4656 { 4657 .label = "tacho4", 4658 .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET, 4659 .mask = GENMASK(7, 0), 4660 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 4661 .bit = BIT(3), 4662 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 4663 }, 4664 { 4665 .label = "tacho5", 4666 .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET, 4667 .mask = GENMASK(7, 0), 4668 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 4669 .bit = BIT(4), 4670 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 4671 }, 4672 { 4673 .label = "tacho6", 4674 .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET, 4675 .mask = GENMASK(7, 0), 4676 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 4677 .bit = BIT(5), 4678 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 4679 }, 4680 { 4681 .label = "tacho7", 4682 .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET, 4683 .mask = GENMASK(7, 0), 4684 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 4685 .bit = BIT(6), 4686 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 4687 }, 4688 { 4689 .label = "tacho8", 4690 .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET, 4691 .mask = GENMASK(7, 0), 4692 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 4693 .bit = BIT(7), 4694 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 4695 }, 4696 { 4697 .label = "tacho9", 4698 .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET, 4699 .mask = GENMASK(7, 0), 4700 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 4701 .bit = BIT(0), 4702 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 4703 }, 4704 { 4705 .label = "tacho10", 4706 .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET, 4707 .mask = GENMASK(7, 0), 4708 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 4709 .bit = BIT(1), 4710 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 4711 }, 4712 { 4713 .label = "tacho11", 4714 .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET, 4715 .mask = GENMASK(7, 0), 4716 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 4717 .bit = BIT(2), 4718 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 4719 }, 4720 { 4721 .label = "tacho12", 4722 .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET, 4723 .mask = GENMASK(7, 0), 4724 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 4725 .bit = BIT(3), 4726 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 4727 }, 4728 { 4729 .label = "tacho13", 4730 .reg = MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET, 4731 .mask = GENMASK(7, 0), 4732 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 4733 .bit = BIT(4), 4734 }, 4735 { 4736 .label = "tacho14", 4737 .reg = MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET, 4738 .mask = GENMASK(7, 0), 4739 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 4740 .bit = BIT(5), 4741 }, 4742 { 4743 .label = "conf", 4744 .capability = MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET, 4745 }, 4746 }; 4747 4748 static struct mlxreg_core_platform_data mlxplat_default_fan_data = { 4749 .data = mlxplat_mlxcpld_default_fan_data, 4750 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_data), 4751 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 4752 }; 4753 4754 /* Watchdog type1: hardware implementation version1 4755 * (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140 systems). 4756 */ 4757 static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type1[] = { 4758 { 4759 .label = "action", 4760 .reg = MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 4761 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 4762 .bit = 0, 4763 }, 4764 { 4765 .label = "timeout", 4766 .reg = MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET, 4767 .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK, 4768 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 4769 }, 4770 { 4771 .label = "ping", 4772 .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET, 4773 .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK, 4774 .bit = 0, 4775 }, 4776 { 4777 .label = "reset", 4778 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4779 .mask = GENMASK(7, 0) & ~BIT(6), 4780 .bit = 6, 4781 }, 4782 }; 4783 4784 static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type1[] = { 4785 { 4786 .label = "action", 4787 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 4788 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 4789 .bit = 4, 4790 }, 4791 { 4792 .label = "timeout", 4793 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 4794 .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK, 4795 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 4796 }, 4797 { 4798 .label = "ping", 4799 .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET, 4800 .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK, 4801 .bit = 1, 4802 }, 4803 }; 4804 4805 static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type1[] = { 4806 { 4807 .data = mlxplat_mlxcpld_wd_main_regs_type1, 4808 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type1), 4809 .version = MLX_WDT_TYPE1, 4810 .identity = "mlx-wdt-main", 4811 }, 4812 { 4813 .data = mlxplat_mlxcpld_wd_aux_regs_type1, 4814 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type1), 4815 .version = MLX_WDT_TYPE1, 4816 .identity = "mlx-wdt-aux", 4817 }, 4818 }; 4819 4820 /* Watchdog type2: hardware implementation version 2 4821 * (all systems except (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140). 4822 */ 4823 static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type2[] = { 4824 { 4825 .label = "action", 4826 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 4827 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 4828 .bit = 0, 4829 }, 4830 { 4831 .label = "timeout", 4832 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 4833 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 4834 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 4835 }, 4836 { 4837 .label = "timeleft", 4838 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET, 4839 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 4840 }, 4841 { 4842 .label = "ping", 4843 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 4844 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 4845 .bit = 0, 4846 }, 4847 { 4848 .label = "reset", 4849 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4850 .mask = GENMASK(7, 0) & ~BIT(6), 4851 .bit = 6, 4852 }, 4853 }; 4854 4855 static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type2[] = { 4856 { 4857 .label = "action", 4858 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 4859 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 4860 .bit = 4, 4861 }, 4862 { 4863 .label = "timeout", 4864 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET, 4865 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 4866 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 4867 }, 4868 { 4869 .label = "timeleft", 4870 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET, 4871 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 4872 }, 4873 { 4874 .label = "ping", 4875 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 4876 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 4877 .bit = 4, 4878 }, 4879 }; 4880 4881 static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type2[] = { 4882 { 4883 .data = mlxplat_mlxcpld_wd_main_regs_type2, 4884 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type2), 4885 .version = MLX_WDT_TYPE2, 4886 .identity = "mlx-wdt-main", 4887 }, 4888 { 4889 .data = mlxplat_mlxcpld_wd_aux_regs_type2, 4890 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type2), 4891 .version = MLX_WDT_TYPE2, 4892 .identity = "mlx-wdt-aux", 4893 }, 4894 }; 4895 4896 /* Watchdog type3: hardware implementation version 3 4897 * Can be on all systems. It's differentiated by WD capability bit. 4898 * Old systems (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140) 4899 * still have only one main watchdog. 4900 */ 4901 static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type3[] = { 4902 { 4903 .label = "action", 4904 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 4905 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 4906 .bit = 0, 4907 }, 4908 { 4909 .label = "timeout", 4910 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 4911 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 4912 .health_cntr = MLXPLAT_CPLD_WD3_DFLT_TIMEOUT, 4913 }, 4914 { 4915 .label = "timeleft", 4916 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 4917 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 4918 }, 4919 { 4920 .label = "ping", 4921 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 4922 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 4923 .bit = 0, 4924 }, 4925 { 4926 .label = "reset", 4927 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 4928 .mask = GENMASK(7, 0) & ~BIT(6), 4929 .bit = 6, 4930 }, 4931 }; 4932 4933 static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type3[] = { 4934 { 4935 .label = "action", 4936 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 4937 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 4938 .bit = 4, 4939 }, 4940 { 4941 .label = "timeout", 4942 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET, 4943 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 4944 .health_cntr = MLXPLAT_CPLD_WD3_DFLT_TIMEOUT, 4945 }, 4946 { 4947 .label = "timeleft", 4948 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET, 4949 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 4950 }, 4951 { 4952 .label = "ping", 4953 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 4954 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 4955 .bit = 4, 4956 }, 4957 }; 4958 4959 static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type3[] = { 4960 { 4961 .data = mlxplat_mlxcpld_wd_main_regs_type3, 4962 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type3), 4963 .version = MLX_WDT_TYPE3, 4964 .identity = "mlx-wdt-main", 4965 }, 4966 { 4967 .data = mlxplat_mlxcpld_wd_aux_regs_type3, 4968 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type3), 4969 .version = MLX_WDT_TYPE3, 4970 .identity = "mlx-wdt-aux", 4971 }, 4972 }; 4973 4974 static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) 4975 { 4976 switch (reg) { 4977 case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: 4978 case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: 4979 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 4980 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 4981 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 4982 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 4983 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 4984 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: 4985 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: 4986 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 4987 case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: 4988 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 4989 case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: 4990 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 4991 case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET: 4992 case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: 4993 case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: 4994 case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: 4995 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 4996 case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET: 4997 case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET: 4998 case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET: 4999 case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET: 5000 case MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET: 5001 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 5002 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 5003 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 5004 case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: 5005 case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: 5006 case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET: 5007 case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET: 5008 case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET: 5009 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 5010 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 5011 case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: 5012 case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: 5013 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 5014 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 5015 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 5016 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 5017 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 5018 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 5019 case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET: 5020 case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: 5021 case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET: 5022 case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET: 5023 case MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET: 5024 case MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET: 5025 case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: 5026 case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET: 5027 case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET: 5028 case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET: 5029 case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET: 5030 case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET: 5031 case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET: 5032 case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET: 5033 case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET: 5034 case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET: 5035 case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET: 5036 case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET: 5037 case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET: 5038 case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET: 5039 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: 5040 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: 5041 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: 5042 case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT: 5043 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET: 5044 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET: 5045 case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET: 5046 case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET: 5047 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 5048 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: 5049 case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET: 5050 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 5051 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: 5052 case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: 5053 case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: 5054 case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: 5055 case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: 5056 case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: 5057 case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET: 5058 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 5059 case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: 5060 case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: 5061 case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET: 5062 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 5063 return true; 5064 } 5065 return false; 5066 } 5067 5068 static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) 5069 { 5070 switch (reg) { 5071 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET: 5072 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET: 5073 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: 5074 case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: 5075 case MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET: 5076 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: 5077 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET: 5078 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: 5079 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET: 5080 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET: 5081 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET: 5082 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET: 5083 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET: 5084 case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET: 5085 case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET: 5086 case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: 5087 case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: 5088 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: 5089 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: 5090 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET: 5091 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 5092 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 5093 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 5094 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 5095 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 5096 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: 5097 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: 5098 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: 5099 case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: 5100 case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET: 5101 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 5102 case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: 5103 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 5104 case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: 5105 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 5106 case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET: 5107 case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: 5108 case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: 5109 case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: 5110 case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: 5111 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 5112 case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET: 5113 case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET: 5114 case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET: 5115 case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET: 5116 case MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET: 5117 case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET: 5118 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 5119 case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET: 5120 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 5121 case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET: 5122 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 5123 case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET: 5124 case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: 5125 case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: 5126 case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET: 5127 case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET: 5128 case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET: 5129 case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: 5130 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 5131 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 5132 case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET: 5133 case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: 5134 case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: 5135 case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: 5136 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 5137 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 5138 case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET: 5139 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 5140 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 5141 case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: 5142 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 5143 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 5144 case MLXPLAT_CPLD_LPC_REG_EROT_OFFSET: 5145 case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET: 5146 case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: 5147 case MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET: 5148 case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET: 5149 case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET: 5150 case MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET: 5151 case MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET: 5152 case MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET: 5153 case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET: 5154 case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: 5155 case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET: 5156 case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET: 5157 case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET: 5158 case MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET: 5159 case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET: 5160 case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET: 5161 case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET: 5162 case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET: 5163 case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET: 5164 case MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET: 5165 case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET: 5166 case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET: 5167 case MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET: 5168 case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET: 5169 case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET: 5170 case MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET: 5171 case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET: 5172 case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET: 5173 case MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET: 5174 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: 5175 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: 5176 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: 5177 case MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET: 5178 case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT: 5179 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET: 5180 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET: 5181 case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET: 5182 case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET: 5183 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 5184 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: 5185 case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET: 5186 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 5187 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: 5188 case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: 5189 case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: 5190 case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: 5191 case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: 5192 case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: 5193 case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET: 5194 case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: 5195 case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: 5196 case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: 5197 case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET: 5198 case MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET: 5199 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 5200 case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: 5201 case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: 5202 case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET: 5203 case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET: 5204 case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET: 5205 case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET: 5206 case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET: 5207 case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET: 5208 case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET: 5209 case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET: 5210 case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET: 5211 case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET: 5212 case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET: 5213 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET: 5214 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: 5215 case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET: 5216 case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET: 5217 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 5218 case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET: 5219 case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: 5220 case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET: 5221 case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET: 5222 case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET: 5223 case MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET: 5224 case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET: 5225 case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: 5226 case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET: 5227 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: 5228 return true; 5229 } 5230 return false; 5231 } 5232 5233 static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) 5234 { 5235 switch (reg) { 5236 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET: 5237 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET: 5238 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: 5239 case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: 5240 case MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET: 5241 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: 5242 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET: 5243 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: 5244 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET: 5245 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET: 5246 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET: 5247 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET: 5248 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET: 5249 case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET: 5250 case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET: 5251 case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: 5252 case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: 5253 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: 5254 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: 5255 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET: 5256 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 5257 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 5258 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 5259 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 5260 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 5261 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: 5262 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: 5263 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: 5264 case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: 5265 case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET: 5266 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 5267 case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: 5268 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 5269 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 5270 case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: 5271 case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: 5272 case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: 5273 case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: 5274 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 5275 case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET: 5276 case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET: 5277 case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET: 5278 case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET: 5279 case MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET: 5280 case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET: 5281 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 5282 case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET: 5283 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 5284 case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET: 5285 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 5286 case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET: 5287 case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: 5288 case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: 5289 case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET: 5290 case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET: 5291 case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET: 5292 case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: 5293 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 5294 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 5295 case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET: 5296 case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: 5297 case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: 5298 case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: 5299 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 5300 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 5301 case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET: 5302 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 5303 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 5304 case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: 5305 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 5306 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 5307 case MLXPLAT_CPLD_LPC_REG_EROT_OFFSET: 5308 case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET: 5309 case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: 5310 case MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET: 5311 case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET: 5312 case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET: 5313 case MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET: 5314 case MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET: 5315 case MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET: 5316 case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET: 5317 case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: 5318 case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET: 5319 case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET: 5320 case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET: 5321 case MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET: 5322 case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET: 5323 case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET: 5324 case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET: 5325 case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET: 5326 case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET: 5327 case MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET: 5328 case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET: 5329 case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET: 5330 case MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET: 5331 case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET: 5332 case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET: 5333 case MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET: 5334 case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET: 5335 case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET: 5336 case MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET: 5337 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: 5338 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: 5339 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: 5340 case MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET: 5341 case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT: 5342 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 5343 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: 5344 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 5345 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: 5346 case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: 5347 case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: 5348 case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: 5349 case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: 5350 case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET: 5351 case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: 5352 case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: 5353 case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: 5354 case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET: 5355 case MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET: 5356 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 5357 case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: 5358 case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: 5359 case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET: 5360 case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET: 5361 case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET: 5362 case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET: 5363 case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET: 5364 case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET: 5365 case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET: 5366 case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET: 5367 case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET: 5368 case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET: 5369 case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET: 5370 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET: 5371 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: 5372 case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET: 5373 case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET: 5374 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 5375 case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET: 5376 case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: 5377 case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET: 5378 case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET: 5379 case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET: 5380 case MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET: 5381 case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET: 5382 case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: 5383 case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET: 5384 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: 5385 return true; 5386 } 5387 return false; 5388 } 5389 5390 static const struct reg_default mlxplat_mlxcpld_regmap_default[] = { 5391 { MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, 0x00 }, 5392 { MLXPLAT_CPLD_LPC_REG_WP2_OFFSET, 0x00 }, 5393 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 5394 { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 }, 5395 }; 5396 5397 static const struct reg_default mlxplat_mlxcpld_regmap_ng[] = { 5398 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 5399 { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 }, 5400 }; 5401 5402 static const struct reg_default mlxplat_mlxcpld_regmap_comex_default[] = { 5403 { MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET, 5404 MLXPLAT_CPLD_LOW_AGGRCX_MASK }, 5405 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 5406 }; 5407 5408 static const struct reg_default mlxplat_mlxcpld_regmap_ng400[] = { 5409 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 5410 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, 5411 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, 5412 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, 5413 }; 5414 5415 static const struct reg_default mlxplat_mlxcpld_regmap_rack_switch[] = { 5416 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, MLXPLAT_REGMAP_NVSWITCH_PWM_DEFAULT }, 5417 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, 5418 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, 5419 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, 5420 }; 5421 5422 static const struct reg_default mlxplat_mlxcpld_regmap_eth_modular[] = { 5423 { MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 0x61 }, 5424 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 5425 { MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET, 0x00 }, 5426 { MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET, 0x00 }, 5427 { MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET, 0x00 }, 5428 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, 5429 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, 5430 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, 5431 { MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET, 5432 MLXPLAT_CPLD_AGGR_MASK_LC_LOW }, 5433 }; 5434 5435 struct mlxplat_mlxcpld_regmap_context { 5436 void __iomem *base; 5437 }; 5438 5439 static struct mlxplat_mlxcpld_regmap_context mlxplat_mlxcpld_regmap_ctx; 5440 5441 static int 5442 mlxplat_mlxcpld_reg_read(void *context, unsigned int reg, unsigned int *val) 5443 { 5444 struct mlxplat_mlxcpld_regmap_context *ctx = context; 5445 5446 *val = ioread8(ctx->base + reg); 5447 return 0; 5448 } 5449 5450 static int 5451 mlxplat_mlxcpld_reg_write(void *context, unsigned int reg, unsigned int val) 5452 { 5453 struct mlxplat_mlxcpld_regmap_context *ctx = context; 5454 5455 iowrite8(val, ctx->base + reg); 5456 return 0; 5457 } 5458 5459 static const struct regmap_config mlxplat_mlxcpld_regmap_config = { 5460 .reg_bits = 8, 5461 .val_bits = 8, 5462 .max_register = 255, 5463 .cache_type = REGCACHE_FLAT, 5464 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 5465 .readable_reg = mlxplat_mlxcpld_readable_reg, 5466 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 5467 .reg_defaults = mlxplat_mlxcpld_regmap_default, 5468 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_default), 5469 .reg_read = mlxplat_mlxcpld_reg_read, 5470 .reg_write = mlxplat_mlxcpld_reg_write, 5471 }; 5472 5473 static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng = { 5474 .reg_bits = 8, 5475 .val_bits = 8, 5476 .max_register = 255, 5477 .cache_type = REGCACHE_FLAT, 5478 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 5479 .readable_reg = mlxplat_mlxcpld_readable_reg, 5480 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 5481 .reg_defaults = mlxplat_mlxcpld_regmap_ng, 5482 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng), 5483 .reg_read = mlxplat_mlxcpld_reg_read, 5484 .reg_write = mlxplat_mlxcpld_reg_write, 5485 }; 5486 5487 static const struct regmap_config mlxplat_mlxcpld_regmap_config_comex = { 5488 .reg_bits = 8, 5489 .val_bits = 8, 5490 .max_register = 255, 5491 .cache_type = REGCACHE_FLAT, 5492 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 5493 .readable_reg = mlxplat_mlxcpld_readable_reg, 5494 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 5495 .reg_defaults = mlxplat_mlxcpld_regmap_comex_default, 5496 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_comex_default), 5497 .reg_read = mlxplat_mlxcpld_reg_read, 5498 .reg_write = mlxplat_mlxcpld_reg_write, 5499 }; 5500 5501 static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng400 = { 5502 .reg_bits = 8, 5503 .val_bits = 8, 5504 .max_register = 255, 5505 .cache_type = REGCACHE_FLAT, 5506 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 5507 .readable_reg = mlxplat_mlxcpld_readable_reg, 5508 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 5509 .reg_defaults = mlxplat_mlxcpld_regmap_ng400, 5510 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng400), 5511 .reg_read = mlxplat_mlxcpld_reg_read, 5512 .reg_write = mlxplat_mlxcpld_reg_write, 5513 }; 5514 5515 static const struct regmap_config mlxplat_mlxcpld_regmap_config_rack_switch = { 5516 .reg_bits = 8, 5517 .val_bits = 8, 5518 .max_register = 255, 5519 .cache_type = REGCACHE_FLAT, 5520 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 5521 .readable_reg = mlxplat_mlxcpld_readable_reg, 5522 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 5523 .reg_defaults = mlxplat_mlxcpld_regmap_rack_switch, 5524 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_rack_switch), 5525 .reg_read = mlxplat_mlxcpld_reg_read, 5526 .reg_write = mlxplat_mlxcpld_reg_write, 5527 }; 5528 5529 static const struct regmap_config mlxplat_mlxcpld_regmap_config_eth_modular = { 5530 .reg_bits = 8, 5531 .val_bits = 8, 5532 .max_register = 255, 5533 .cache_type = REGCACHE_FLAT, 5534 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 5535 .readable_reg = mlxplat_mlxcpld_readable_reg, 5536 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 5537 .reg_defaults = mlxplat_mlxcpld_regmap_eth_modular, 5538 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_eth_modular), 5539 .reg_read = mlxplat_mlxcpld_reg_read, 5540 .reg_write = mlxplat_mlxcpld_reg_write, 5541 }; 5542 5543 static struct resource mlxplat_mlxcpld_resources[] = { 5544 [0] = DEFINE_RES_IRQ_NAMED(MLXPLAT_CPLD_LPC_SYSIRQ, "mlxreg-hotplug"), 5545 }; 5546 5547 static struct mlxreg_core_hotplug_platform_data *mlxplat_i2c; 5548 static struct mlxreg_core_hotplug_platform_data *mlxplat_hotplug; 5549 static struct mlxreg_core_platform_data *mlxplat_led; 5550 static struct mlxreg_core_platform_data *mlxplat_regs_io; 5551 static struct mlxreg_core_platform_data *mlxplat_fan; 5552 static struct mlxreg_core_platform_data 5553 *mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS]; 5554 static const struct regmap_config *mlxplat_regmap_config; 5555 static struct pci_dev *lpc_bridge; 5556 static struct pci_dev *i2c_bridge; 5557 static struct pci_dev *jtag_bridge; 5558 5559 /* Platform default reset function */ 5560 static int mlxplat_reboot_notifier(struct notifier_block *nb, unsigned long action, void *unused) 5561 { 5562 struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); 5563 u32 regval; 5564 int ret; 5565 5566 ret = regmap_read(priv->regmap, MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET, ®val); 5567 5568 if (action == SYS_RESTART && !ret && regval & MLXPLAT_CPLD_SYS_RESET_MASK) 5569 regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET, 5570 MLXPLAT_CPLD_RESET_MASK); 5571 5572 return NOTIFY_DONE; 5573 } 5574 5575 static struct notifier_block mlxplat_reboot_default_nb = { 5576 .notifier_call = mlxplat_reboot_notifier, 5577 }; 5578 5579 /* Platform default poweroff function */ 5580 static void mlxplat_poweroff(void) 5581 { 5582 struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); 5583 5584 if (mlxplat_reboot_nb) 5585 unregister_reboot_notifier(mlxplat_reboot_nb); 5586 regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, MLXPLAT_CPLD_HALT_MASK); 5587 kernel_halt(); 5588 } 5589 5590 static int __init mlxplat_register_platform_device(void) 5591 { 5592 mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, -1, 5593 mlxplat_lpc_resources, 5594 ARRAY_SIZE(mlxplat_lpc_resources)); 5595 if (IS_ERR(mlxplat_dev)) 5596 return PTR_ERR(mlxplat_dev); 5597 else 5598 return 1; 5599 } 5600 5601 static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi) 5602 { 5603 int i; 5604 5605 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 5606 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 5607 mlxplat_mux_data = mlxplat_default_mux_data; 5608 for (i = 0; i < mlxplat_mux_num; i++) { 5609 mlxplat_mux_data[i].values = mlxplat_default_channels[i]; 5610 mlxplat_mux_data[i].n_values = 5611 ARRAY_SIZE(mlxplat_default_channels[i]); 5612 } 5613 mlxplat_hotplug = &mlxplat_mlxcpld_default_data; 5614 mlxplat_hotplug->deferred_nr = 5615 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 5616 mlxplat_led = &mlxplat_default_led_data; 5617 mlxplat_regs_io = &mlxplat_default_regs_io_data; 5618 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 5619 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; 5620 5621 return mlxplat_register_platform_device(); 5622 } 5623 5624 static int __init mlxplat_dmi_default_wc_matched(const struct dmi_system_id *dmi) 5625 { 5626 int i; 5627 5628 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 5629 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 5630 mlxplat_mux_data = mlxplat_default_mux_data; 5631 for (i = 0; i < mlxplat_mux_num; i++) { 5632 mlxplat_mux_data[i].values = mlxplat_default_channels[i]; 5633 mlxplat_mux_data[i].n_values = 5634 ARRAY_SIZE(mlxplat_default_channels[i]); 5635 } 5636 mlxplat_hotplug = &mlxplat_mlxcpld_default_wc_data; 5637 mlxplat_hotplug->deferred_nr = 5638 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 5639 mlxplat_led = &mlxplat_default_led_wc_data; 5640 mlxplat_regs_io = &mlxplat_default_regs_io_data; 5641 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 5642 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; 5643 5644 return mlxplat_register_platform_device(); 5645 } 5646 5647 static int __init mlxplat_dmi_default_eth_wc_blade_matched(const struct dmi_system_id *dmi) 5648 { 5649 int i; 5650 5651 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 5652 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 5653 mlxplat_mux_data = mlxplat_default_mux_data; 5654 for (i = 0; i < mlxplat_mux_num; i++) { 5655 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 5656 mlxplat_mux_data[i].n_values = 5657 ARRAY_SIZE(mlxplat_msn21xx_channels); 5658 } 5659 mlxplat_hotplug = &mlxplat_mlxcpld_default_wc_data; 5660 mlxplat_hotplug->deferred_nr = 5661 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 5662 mlxplat_led = &mlxplat_default_led_eth_wc_blade_data; 5663 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 5664 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 5665 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 5666 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 5667 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng; 5668 5669 return mlxplat_register_platform_device(); 5670 } 5671 5672 static int __init mlxplat_dmi_msn21xx_matched(const struct dmi_system_id *dmi) 5673 { 5674 int i; 5675 5676 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 5677 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 5678 mlxplat_mux_data = mlxplat_default_mux_data; 5679 for (i = 0; i < mlxplat_mux_num; i++) { 5680 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 5681 mlxplat_mux_data[i].n_values = 5682 ARRAY_SIZE(mlxplat_msn21xx_channels); 5683 } 5684 mlxplat_hotplug = &mlxplat_mlxcpld_msn21xx_data; 5685 mlxplat_hotplug->deferred_nr = 5686 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 5687 mlxplat_led = &mlxplat_msn21xx_led_data; 5688 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 5689 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 5690 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; 5691 5692 return mlxplat_register_platform_device(); 5693 } 5694 5695 static int __init mlxplat_dmi_msn274x_matched(const struct dmi_system_id *dmi) 5696 { 5697 int i; 5698 5699 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 5700 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 5701 mlxplat_mux_data = mlxplat_default_mux_data; 5702 for (i = 0; i < mlxplat_mux_num; i++) { 5703 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 5704 mlxplat_mux_data[i].n_values = 5705 ARRAY_SIZE(mlxplat_msn21xx_channels); 5706 } 5707 mlxplat_hotplug = &mlxplat_mlxcpld_msn274x_data; 5708 mlxplat_hotplug->deferred_nr = 5709 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 5710 mlxplat_led = &mlxplat_default_led_data; 5711 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 5712 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 5713 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; 5714 5715 return mlxplat_register_platform_device(); 5716 } 5717 5718 static int __init mlxplat_dmi_msn201x_matched(const struct dmi_system_id *dmi) 5719 { 5720 int i; 5721 5722 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 5723 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 5724 mlxplat_mux_data = mlxplat_default_mux_data; 5725 for (i = 0; i < mlxplat_mux_num; i++) { 5726 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 5727 mlxplat_mux_data[i].n_values = 5728 ARRAY_SIZE(mlxplat_msn21xx_channels); 5729 } 5730 mlxplat_hotplug = &mlxplat_mlxcpld_msn201x_data; 5731 mlxplat_hotplug->deferred_nr = 5732 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 5733 mlxplat_led = &mlxplat_msn21xx_led_data; 5734 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 5735 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 5736 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; 5737 5738 return mlxplat_register_platform_device(); 5739 } 5740 5741 static int __init mlxplat_dmi_qmb7xx_matched(const struct dmi_system_id *dmi) 5742 { 5743 int i; 5744 5745 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 5746 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 5747 mlxplat_mux_data = mlxplat_default_mux_data; 5748 for (i = 0; i < mlxplat_mux_num; i++) { 5749 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 5750 mlxplat_mux_data[i].n_values = 5751 ARRAY_SIZE(mlxplat_msn21xx_channels); 5752 } 5753 mlxplat_hotplug = &mlxplat_mlxcpld_default_ng_data; 5754 mlxplat_hotplug->deferred_nr = 5755 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 5756 mlxplat_led = &mlxplat_default_ng_led_data; 5757 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 5758 mlxplat_fan = &mlxplat_default_fan_data; 5759 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 5760 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 5761 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 5762 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng; 5763 5764 return mlxplat_register_platform_device(); 5765 } 5766 5767 static int __init mlxplat_dmi_comex_matched(const struct dmi_system_id *dmi) 5768 { 5769 int i; 5770 5771 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM; 5772 mlxplat_mux_num = ARRAY_SIZE(mlxplat_extended_mux_data); 5773 mlxplat_mux_data = mlxplat_extended_mux_data; 5774 for (i = 0; i < mlxplat_mux_num; i++) { 5775 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 5776 mlxplat_mux_data[i].n_values = 5777 ARRAY_SIZE(mlxplat_msn21xx_channels); 5778 } 5779 mlxplat_hotplug = &mlxplat_mlxcpld_comex_data; 5780 mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM; 5781 mlxplat_led = &mlxplat_comex_100G_led_data; 5782 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 5783 mlxplat_fan = &mlxplat_default_fan_data; 5784 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 5785 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 5786 mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; 5787 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_comex; 5788 5789 return mlxplat_register_platform_device(); 5790 } 5791 5792 static int __init mlxplat_dmi_ng400_matched(const struct dmi_system_id *dmi) 5793 { 5794 int i; 5795 5796 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 5797 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 5798 mlxplat_mux_data = mlxplat_default_mux_data; 5799 for (i = 0; i < mlxplat_mux_num; i++) { 5800 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 5801 mlxplat_mux_data[i].n_values = 5802 ARRAY_SIZE(mlxplat_msn21xx_channels); 5803 } 5804 mlxplat_hotplug = &mlxplat_mlxcpld_ext_data; 5805 mlxplat_hotplug->deferred_nr = 5806 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 5807 mlxplat_led = &mlxplat_default_ng_led_data; 5808 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 5809 mlxplat_fan = &mlxplat_default_fan_data; 5810 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 5811 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 5812 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 5813 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; 5814 5815 return mlxplat_register_platform_device(); 5816 } 5817 5818 static int __init mlxplat_dmi_modular_matched(const struct dmi_system_id *dmi) 5819 { 5820 int i; 5821 5822 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 5823 mlxplat_mux_num = ARRAY_SIZE(mlxplat_modular_mux_data); 5824 mlxplat_mux_data = mlxplat_modular_mux_data; 5825 mlxplat_hotplug = &mlxplat_mlxcpld_modular_data; 5826 mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_CH4_ETH_MODULAR; 5827 mlxplat_led = &mlxplat_modular_led_data; 5828 mlxplat_regs_io = &mlxplat_modular_regs_io_data; 5829 mlxplat_fan = &mlxplat_default_fan_data; 5830 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 5831 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 5832 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 5833 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_eth_modular; 5834 5835 return mlxplat_register_platform_device(); 5836 } 5837 5838 static int __init mlxplat_dmi_chassis_blade_matched(const struct dmi_system_id *dmi) 5839 { 5840 int i; 5841 5842 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 5843 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 5844 mlxplat_mux_data = mlxplat_default_mux_data; 5845 mlxplat_hotplug = &mlxplat_mlxcpld_chassis_blade_data; 5846 mlxplat_hotplug->deferred_nr = 5847 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 5848 for (i = 0; i < mlxplat_mux_num; i++) { 5849 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 5850 mlxplat_mux_data[i].n_values = 5851 ARRAY_SIZE(mlxplat_msn21xx_channels); 5852 } 5853 mlxplat_regs_io = &mlxplat_chassis_blade_regs_io_data; 5854 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 5855 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; 5856 5857 return mlxplat_register_platform_device(); 5858 } 5859 5860 static int __init mlxplat_dmi_rack_switch_matched(const struct dmi_system_id *dmi) 5861 { 5862 int i; 5863 5864 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 5865 mlxplat_mux_num = ARRAY_SIZE(mlxplat_rack_switch_mux_data); 5866 mlxplat_mux_data = mlxplat_rack_switch_mux_data; 5867 mlxplat_hotplug = &mlxplat_mlxcpld_rack_switch_data; 5868 mlxplat_hotplug->deferred_nr = 5869 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 5870 mlxplat_led = &mlxplat_default_ng_led_data; 5871 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 5872 mlxplat_fan = &mlxplat_default_fan_data; 5873 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 5874 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 5875 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 5876 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_rack_switch; 5877 5878 return mlxplat_register_platform_device(); 5879 } 5880 5881 static int __init mlxplat_dmi_ng800_matched(const struct dmi_system_id *dmi) 5882 { 5883 int i; 5884 5885 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 5886 mlxplat_mux_num = ARRAY_SIZE(mlxplat_ng800_mux_data); 5887 mlxplat_mux_data = mlxplat_ng800_mux_data; 5888 mlxplat_hotplug = &mlxplat_mlxcpld_ng800_data; 5889 mlxplat_hotplug->deferred_nr = 5890 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 5891 mlxplat_led = &mlxplat_default_ng_led_data; 5892 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 5893 mlxplat_fan = &mlxplat_default_fan_data; 5894 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 5895 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 5896 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 5897 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; 5898 5899 return mlxplat_register_platform_device(); 5900 } 5901 5902 static int __init mlxplat_dmi_l1_switch_matched(const struct dmi_system_id *dmi) 5903 { 5904 int i; 5905 5906 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 5907 mlxplat_mux_num = ARRAY_SIZE(mlxplat_rack_switch_mux_data); 5908 mlxplat_mux_data = mlxplat_rack_switch_mux_data; 5909 mlxplat_hotplug = &mlxplat_mlxcpld_l1_switch_data; 5910 mlxplat_hotplug->deferred_nr = 5911 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 5912 mlxplat_led = &mlxplat_l1_switch_led_data; 5913 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 5914 mlxplat_fan = &mlxplat_default_fan_data; 5915 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 5916 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 5917 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 5918 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_rack_switch; 5919 pm_power_off = mlxplat_poweroff; 5920 mlxplat_reboot_nb = &mlxplat_reboot_default_nb; 5921 5922 return mlxplat_register_platform_device(); 5923 } 5924 5925 static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { 5926 { 5927 .callback = mlxplat_dmi_default_wc_matched, 5928 .matches = { 5929 DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"), 5930 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI138"), 5931 }, 5932 }, 5933 { 5934 .callback = mlxplat_dmi_default_matched, 5935 .matches = { 5936 DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"), 5937 }, 5938 }, 5939 { 5940 .callback = mlxplat_dmi_msn21xx_matched, 5941 .matches = { 5942 DMI_MATCH(DMI_BOARD_NAME, "VMOD0002"), 5943 }, 5944 }, 5945 { 5946 .callback = mlxplat_dmi_msn274x_matched, 5947 .matches = { 5948 DMI_MATCH(DMI_BOARD_NAME, "VMOD0003"), 5949 }, 5950 }, 5951 { 5952 .callback = mlxplat_dmi_msn201x_matched, 5953 .matches = { 5954 DMI_MATCH(DMI_BOARD_NAME, "VMOD0004"), 5955 }, 5956 }, 5957 { 5958 .callback = mlxplat_dmi_default_eth_wc_blade_matched, 5959 .matches = { 5960 DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"), 5961 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI139"), 5962 }, 5963 }, 5964 { 5965 .callback = mlxplat_dmi_qmb7xx_matched, 5966 .matches = { 5967 DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"), 5968 }, 5969 }, 5970 { 5971 .callback = mlxplat_dmi_qmb7xx_matched, 5972 .matches = { 5973 DMI_MATCH(DMI_BOARD_NAME, "VMOD0007"), 5974 }, 5975 }, 5976 { 5977 .callback = mlxplat_dmi_comex_matched, 5978 .matches = { 5979 DMI_MATCH(DMI_BOARD_NAME, "VMOD0009"), 5980 }, 5981 }, 5982 { 5983 .callback = mlxplat_dmi_rack_switch_matched, 5984 .matches = { 5985 DMI_MATCH(DMI_BOARD_NAME, "VMOD0010"), 5986 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI142"), 5987 }, 5988 }, 5989 { 5990 .callback = mlxplat_dmi_ng400_matched, 5991 .matches = { 5992 DMI_MATCH(DMI_BOARD_NAME, "VMOD0010"), 5993 }, 5994 }, 5995 { 5996 .callback = mlxplat_dmi_modular_matched, 5997 .matches = { 5998 DMI_MATCH(DMI_BOARD_NAME, "VMOD0011"), 5999 }, 6000 }, 6001 { 6002 .callback = mlxplat_dmi_ng800_matched, 6003 .matches = { 6004 DMI_MATCH(DMI_BOARD_NAME, "VMOD0013"), 6005 }, 6006 }, 6007 { 6008 .callback = mlxplat_dmi_chassis_blade_matched, 6009 .matches = { 6010 DMI_MATCH(DMI_BOARD_NAME, "VMOD0015"), 6011 }, 6012 }, 6013 { 6014 .callback = mlxplat_dmi_l1_switch_matched, 6015 .matches = { 6016 DMI_MATCH(DMI_BOARD_NAME, "VMOD0017"), 6017 }, 6018 }, 6019 { 6020 .callback = mlxplat_dmi_msn274x_matched, 6021 .matches = { 6022 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 6023 DMI_MATCH(DMI_PRODUCT_NAME, "MSN274"), 6024 }, 6025 }, 6026 { 6027 .callback = mlxplat_dmi_default_matched, 6028 .matches = { 6029 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 6030 DMI_MATCH(DMI_PRODUCT_NAME, "MSN24"), 6031 }, 6032 }, 6033 { 6034 .callback = mlxplat_dmi_default_matched, 6035 .matches = { 6036 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 6037 DMI_MATCH(DMI_PRODUCT_NAME, "MSN27"), 6038 }, 6039 }, 6040 { 6041 .callback = mlxplat_dmi_default_matched, 6042 .matches = { 6043 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 6044 DMI_MATCH(DMI_PRODUCT_NAME, "MSB"), 6045 }, 6046 }, 6047 { 6048 .callback = mlxplat_dmi_default_matched, 6049 .matches = { 6050 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 6051 DMI_MATCH(DMI_PRODUCT_NAME, "MSX"), 6052 }, 6053 }, 6054 { 6055 .callback = mlxplat_dmi_msn21xx_matched, 6056 .matches = { 6057 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 6058 DMI_MATCH(DMI_PRODUCT_NAME, "MSN21"), 6059 }, 6060 }, 6061 { 6062 .callback = mlxplat_dmi_msn201x_matched, 6063 .matches = { 6064 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 6065 DMI_MATCH(DMI_PRODUCT_NAME, "MSN201"), 6066 }, 6067 }, 6068 { 6069 .callback = mlxplat_dmi_qmb7xx_matched, 6070 .matches = { 6071 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 6072 DMI_MATCH(DMI_PRODUCT_NAME, "MQM87"), 6073 }, 6074 }, 6075 { 6076 .callback = mlxplat_dmi_qmb7xx_matched, 6077 .matches = { 6078 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 6079 DMI_MATCH(DMI_PRODUCT_NAME, "MSN37"), 6080 }, 6081 }, 6082 { 6083 .callback = mlxplat_dmi_qmb7xx_matched, 6084 .matches = { 6085 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 6086 DMI_MATCH(DMI_PRODUCT_NAME, "MSN34"), 6087 }, 6088 }, 6089 { 6090 .callback = mlxplat_dmi_qmb7xx_matched, 6091 .matches = { 6092 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 6093 DMI_MATCH(DMI_PRODUCT_NAME, "MSN38"), 6094 }, 6095 }, 6096 { } 6097 }; 6098 6099 MODULE_DEVICE_TABLE(dmi, mlxplat_dmi_table); 6100 6101 static int mlxplat_mlxcpld_verify_bus_topology(int *nr) 6102 { 6103 struct i2c_adapter *search_adap; 6104 int i, shift = 0; 6105 6106 /* Scan adapters from expected id to verify it is free. */ 6107 *nr = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; 6108 for (i = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; i < 6109 mlxplat_max_adap_num; i++) { 6110 search_adap = i2c_get_adapter(i); 6111 if (search_adap) { 6112 i2c_put_adapter(search_adap); 6113 continue; 6114 } 6115 6116 /* Return if expected parent adapter is free. */ 6117 if (i == MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR) 6118 return 0; 6119 break; 6120 } 6121 6122 /* Return with error if free id for adapter is not found. */ 6123 if (i == mlxplat_max_adap_num) 6124 return -ENODEV; 6125 6126 /* Shift adapter ids, since expected parent adapter is not free. */ 6127 *nr = i; 6128 for (i = 0; i < mlxplat_mux_num; i++) { 6129 shift = *nr - mlxplat_mux_data[i].parent; 6130 mlxplat_mux_data[i].parent = *nr; 6131 mlxplat_mux_data[i].base_nr += shift; 6132 } 6133 6134 if (shift > 0) 6135 mlxplat_hotplug->shift_nr = shift; 6136 6137 return 0; 6138 } 6139 6140 static int mlxplat_mlxcpld_check_wd_capability(void *regmap) 6141 { 6142 u32 regval; 6143 int i, rc; 6144 6145 rc = regmap_read(regmap, MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 6146 ®val); 6147 if (rc) 6148 return rc; 6149 6150 if (!(regval & ~MLXPLAT_CPLD_WD_CPBLTY_MASK)) { 6151 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type3); i++) { 6152 if (mlxplat_wd_data[i]) 6153 mlxplat_wd_data[i] = 6154 &mlxplat_mlxcpld_wd_set_type3[i]; 6155 } 6156 } 6157 6158 return 0; 6159 } 6160 6161 static int mlxplat_lpc_cpld_device_init(struct resource **hotplug_resources, 6162 unsigned int *hotplug_resources_size) 6163 { 6164 int err; 6165 6166 mlxplat_mlxcpld_regmap_ctx.base = devm_ioport_map(&mlxplat_dev->dev, 6167 mlxplat_lpc_resources[1].start, 1); 6168 if (!mlxplat_mlxcpld_regmap_ctx.base) { 6169 err = -ENOMEM; 6170 goto fail_devm_ioport_map; 6171 } 6172 6173 *hotplug_resources = mlxplat_mlxcpld_resources; 6174 *hotplug_resources_size = ARRAY_SIZE(mlxplat_mlxcpld_resources); 6175 6176 return 0; 6177 6178 fail_devm_ioport_map: 6179 return err; 6180 } 6181 6182 static void mlxplat_lpc_cpld_device_exit(void) 6183 { 6184 } 6185 6186 static int 6187 mlxplat_pci_fpga_device_init(unsigned int device, const char *res_name, struct pci_dev **pci_bridge, 6188 void __iomem **pci_bridge_addr) 6189 { 6190 void __iomem *pci_mem_addr; 6191 struct pci_dev *pci_dev; 6192 int err; 6193 6194 pci_dev = pci_get_device(PCI_VENDOR_ID_LATTICE, device, NULL); 6195 if (!pci_dev) 6196 return -ENODEV; 6197 6198 err = pci_enable_device(pci_dev); 6199 if (err) { 6200 dev_err(&pci_dev->dev, "pci_enable_device failed with error %d\n", err); 6201 goto fail_pci_enable_device; 6202 } 6203 6204 err = pci_request_region(pci_dev, 0, res_name); 6205 if (err) { 6206 dev_err(&pci_dev->dev, "pci_request_regions failed with error %d\n", err); 6207 goto fail_pci_request_regions; 6208 } 6209 6210 err = dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(64)); 6211 if (err) { 6212 err = dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32)); 6213 if (err) { 6214 dev_err(&pci_dev->dev, "dma_set_mask failed with error %d\n", err); 6215 goto fail_pci_set_dma_mask; 6216 } 6217 } 6218 6219 pci_set_master(pci_dev); 6220 6221 pci_mem_addr = devm_ioremap(&pci_dev->dev, pci_resource_start(pci_dev, 0), 6222 pci_resource_len(pci_dev, 0)); 6223 if (!pci_mem_addr) { 6224 dev_err(&mlxplat_dev->dev, "ioremap failed\n"); 6225 err = -EIO; 6226 goto fail_ioremap; 6227 } 6228 6229 *pci_bridge = pci_dev; 6230 *pci_bridge_addr = pci_mem_addr; 6231 6232 return 0; 6233 6234 fail_ioremap: 6235 fail_pci_set_dma_mask: 6236 pci_release_regions(pci_dev); 6237 fail_pci_request_regions: 6238 pci_disable_device(pci_dev); 6239 fail_pci_enable_device: 6240 return err; 6241 } 6242 6243 static void 6244 mlxplat_pci_fpga_device_exit(struct pci_dev *pci_bridge, 6245 void __iomem *pci_bridge_addr) 6246 { 6247 iounmap(pci_bridge_addr); 6248 pci_release_regions(pci_bridge); 6249 pci_disable_device(pci_bridge); 6250 } 6251 6252 static int 6253 mlxplat_pci_fpga_devices_init(struct resource **hotplug_resources, 6254 unsigned int *hotplug_resources_size) 6255 { 6256 int err; 6257 6258 err = mlxplat_pci_fpga_device_init(PCI_DEVICE_ID_LATTICE_LPC_BRIDGE, 6259 "mlxplat_lpc_bridge", &lpc_bridge, 6260 &mlxplat_mlxcpld_regmap_ctx.base); 6261 if (err) 6262 goto mlxplat_pci_fpga_device_init_lpc_fail; 6263 6264 err = mlxplat_pci_fpga_device_init(PCI_DEVICE_ID_LATTICE_I2C_BRIDGE, 6265 "mlxplat_i2c_bridge", &i2c_bridge, 6266 &i2c_bridge_addr); 6267 if (err) 6268 goto mlxplat_pci_fpga_device_init_i2c_fail; 6269 6270 err = mlxplat_pci_fpga_device_init(PCI_DEVICE_ID_LATTICE_JTAG_BRIDGE, 6271 "mlxplat_jtag_bridge", &jtag_bridge, 6272 &jtag_bridge_addr); 6273 if (err) 6274 goto mlxplat_pci_fpga_device_init_jtag_fail; 6275 6276 return 0; 6277 6278 mlxplat_pci_fpga_device_init_jtag_fail: 6279 mlxplat_pci_fpga_device_exit(i2c_bridge, i2c_bridge_addr); 6280 mlxplat_pci_fpga_device_init_i2c_fail: 6281 mlxplat_pci_fpga_device_exit(lpc_bridge, mlxplat_mlxcpld_regmap_ctx.base); 6282 mlxplat_pci_fpga_device_init_lpc_fail: 6283 return err; 6284 } 6285 6286 static void mlxplat_pci_fpga_devices_exit(void) 6287 { 6288 mlxplat_pci_fpga_device_exit(jtag_bridge, jtag_bridge_addr); 6289 mlxplat_pci_fpga_device_exit(i2c_bridge, i2c_bridge_addr); 6290 mlxplat_pci_fpga_device_exit(lpc_bridge, mlxplat_mlxcpld_regmap_ctx.base); 6291 } 6292 6293 static int 6294 mlxplat_logicdev_init(struct resource **hotplug_resources, unsigned int *hotplug_resources_size) 6295 { 6296 int err; 6297 6298 err = mlxplat_pci_fpga_devices_init(hotplug_resources, hotplug_resources_size); 6299 if (err == -ENODEV) 6300 return mlxplat_lpc_cpld_device_init(hotplug_resources, hotplug_resources_size); 6301 6302 return err; 6303 } 6304 6305 static void mlxplat_logicdev_exit(void) 6306 { 6307 if (lpc_bridge) 6308 mlxplat_pci_fpga_devices_exit(); 6309 else 6310 mlxplat_lpc_cpld_device_exit(); 6311 } 6312 6313 static int mlxplat_platdevs_init(struct mlxplat_priv *priv) 6314 { 6315 int i = 0, err; 6316 6317 /* Add hotplug driver */ 6318 if (mlxplat_hotplug) { 6319 mlxplat_hotplug->regmap = priv->regmap; 6320 if (priv->irq_fpga) 6321 mlxplat_hotplug->irq = priv->irq_fpga; 6322 priv->pdev_hotplug = 6323 platform_device_register_resndata(&mlxplat_dev->dev, 6324 "mlxreg-hotplug", PLATFORM_DEVID_NONE, 6325 priv->hotplug_resources, 6326 priv->hotplug_resources_size, 6327 mlxplat_hotplug, sizeof(*mlxplat_hotplug)); 6328 if (IS_ERR(priv->pdev_hotplug)) { 6329 err = PTR_ERR(priv->pdev_hotplug); 6330 goto fail_platform_hotplug_register; 6331 } 6332 } 6333 6334 /* Add LED driver. */ 6335 if (mlxplat_led) { 6336 mlxplat_led->regmap = priv->regmap; 6337 priv->pdev_led = 6338 platform_device_register_resndata(&mlxplat_dev->dev, "leds-mlxreg", 6339 PLATFORM_DEVID_NONE, NULL, 0, mlxplat_led, 6340 sizeof(*mlxplat_led)); 6341 if (IS_ERR(priv->pdev_led)) { 6342 err = PTR_ERR(priv->pdev_led); 6343 goto fail_platform_leds_register; 6344 } 6345 } 6346 6347 /* Add registers io access driver. */ 6348 if (mlxplat_regs_io) { 6349 mlxplat_regs_io->regmap = priv->regmap; 6350 priv->pdev_io_regs = platform_device_register_resndata(&mlxplat_dev->dev, 6351 "mlxreg-io", 6352 PLATFORM_DEVID_NONE, NULL, 6353 0, mlxplat_regs_io, 6354 sizeof(*mlxplat_regs_io)); 6355 if (IS_ERR(priv->pdev_io_regs)) { 6356 err = PTR_ERR(priv->pdev_io_regs); 6357 goto fail_platform_io_register; 6358 } 6359 } 6360 6361 /* Add FAN driver. */ 6362 if (mlxplat_fan) { 6363 mlxplat_fan->regmap = priv->regmap; 6364 priv->pdev_fan = platform_device_register_resndata(&mlxplat_dev->dev, "mlxreg-fan", 6365 PLATFORM_DEVID_NONE, NULL, 0, 6366 mlxplat_fan, 6367 sizeof(*mlxplat_fan)); 6368 if (IS_ERR(priv->pdev_fan)) { 6369 err = PTR_ERR(priv->pdev_fan); 6370 goto fail_platform_fan_register; 6371 } 6372 } 6373 6374 /* Add WD drivers. */ 6375 err = mlxplat_mlxcpld_check_wd_capability(priv->regmap); 6376 if (err) 6377 goto fail_platform_wd_register; 6378 for (i = 0; i < MLXPLAT_CPLD_WD_MAX_DEVS; i++) { 6379 if (mlxplat_wd_data[i]) { 6380 mlxplat_wd_data[i]->regmap = priv->regmap; 6381 priv->pdev_wd[i] = 6382 platform_device_register_resndata(&mlxplat_dev->dev, "mlx-wdt", i, 6383 NULL, 0, mlxplat_wd_data[i], 6384 sizeof(*mlxplat_wd_data[i])); 6385 if (IS_ERR(priv->pdev_wd[i])) { 6386 err = PTR_ERR(priv->pdev_wd[i]); 6387 goto fail_platform_wd_register; 6388 } 6389 } 6390 } 6391 6392 return 0; 6393 6394 fail_platform_wd_register: 6395 while (--i >= 0) 6396 platform_device_unregister(priv->pdev_wd[i]); 6397 fail_platform_fan_register: 6398 if (mlxplat_regs_io) 6399 platform_device_unregister(priv->pdev_io_regs); 6400 fail_platform_io_register: 6401 if (mlxplat_led) 6402 platform_device_unregister(priv->pdev_led); 6403 fail_platform_leds_register: 6404 if (mlxplat_hotplug) 6405 platform_device_unregister(priv->pdev_hotplug); 6406 fail_platform_hotplug_register: 6407 return err; 6408 } 6409 6410 static void mlxplat_platdevs_exit(struct mlxplat_priv *priv) 6411 { 6412 int i; 6413 6414 for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0 ; i--) 6415 platform_device_unregister(priv->pdev_wd[i]); 6416 if (priv->pdev_fan) 6417 platform_device_unregister(priv->pdev_fan); 6418 if (priv->pdev_io_regs) 6419 platform_device_unregister(priv->pdev_io_regs); 6420 if (priv->pdev_led) 6421 platform_device_unregister(priv->pdev_led); 6422 if (priv->pdev_hotplug) 6423 platform_device_unregister(priv->pdev_hotplug); 6424 } 6425 6426 static int 6427 mlxplat_i2c_mux_complition_notify(void *handle, struct i2c_adapter *parent, 6428 struct i2c_adapter *adapters[]) 6429 { 6430 struct mlxplat_priv *priv = handle; 6431 6432 return mlxplat_platdevs_init(priv); 6433 } 6434 6435 static int mlxplat_i2c_mux_topology_init(struct mlxplat_priv *priv) 6436 { 6437 int i, err; 6438 6439 if (!priv->pdev_i2c) { 6440 priv->i2c_main_init_status = MLXPLAT_I2C_MAIN_BUS_NOTIFIED; 6441 return 0; 6442 } 6443 6444 priv->i2c_main_init_status = MLXPLAT_I2C_MAIN_BUS_HANDLE_CREATED; 6445 for (i = 0; i < mlxplat_mux_num; i++) { 6446 priv->pdev_mux[i] = platform_device_register_resndata(&priv->pdev_i2c->dev, 6447 "i2c-mux-reg", i, NULL, 0, 6448 &mlxplat_mux_data[i], 6449 sizeof(mlxplat_mux_data[i])); 6450 if (IS_ERR(priv->pdev_mux[i])) { 6451 err = PTR_ERR(priv->pdev_mux[i]); 6452 goto fail_platform_mux_register; 6453 } 6454 } 6455 6456 return mlxplat_i2c_mux_complition_notify(priv, NULL, NULL); 6457 6458 fail_platform_mux_register: 6459 while (--i >= 0) 6460 platform_device_unregister(priv->pdev_mux[i]); 6461 return err; 6462 } 6463 6464 static void mlxplat_i2c_mux_topology_exit(struct mlxplat_priv *priv) 6465 { 6466 int i; 6467 6468 for (i = mlxplat_mux_num - 1; i >= 0 ; i--) { 6469 if (priv->pdev_mux[i]) 6470 platform_device_unregister(priv->pdev_mux[i]); 6471 } 6472 } 6473 6474 static int mlxplat_i2c_main_completion_notify(void *handle, int id) 6475 { 6476 struct mlxplat_priv *priv = handle; 6477 6478 return mlxplat_i2c_mux_topology_init(priv); 6479 } 6480 6481 static int mlxplat_i2c_main_init(struct mlxplat_priv *priv) 6482 { 6483 int nr, err; 6484 6485 if (!mlxplat_i2c) 6486 return 0; 6487 6488 err = mlxplat_mlxcpld_verify_bus_topology(&nr); 6489 if (nr < 0) 6490 goto fail_mlxplat_mlxcpld_verify_bus_topology; 6491 6492 nr = (nr == mlxplat_max_adap_num) ? -1 : nr; 6493 mlxplat_i2c->regmap = priv->regmap; 6494 mlxplat_i2c->handle = priv; 6495 6496 /* Set mapped base address of I2C-LPC bridge over PCIe */ 6497 if (lpc_bridge) 6498 mlxplat_i2c->addr = i2c_bridge_addr; 6499 priv->pdev_i2c = platform_device_register_resndata(&mlxplat_dev->dev, "i2c_mlxcpld", 6500 nr, priv->hotplug_resources, 6501 priv->hotplug_resources_size, 6502 mlxplat_i2c, sizeof(*mlxplat_i2c)); 6503 if (IS_ERR(priv->pdev_i2c)) { 6504 err = PTR_ERR(priv->pdev_i2c); 6505 goto fail_platform_i2c_register; 6506 } 6507 6508 if (priv->i2c_main_init_status == MLXPLAT_I2C_MAIN_BUS_NOTIFIED) { 6509 err = mlxplat_i2c_mux_topology_init(priv); 6510 if (err) 6511 goto fail_mlxplat_i2c_mux_topology_init; 6512 } 6513 6514 return 0; 6515 6516 fail_mlxplat_i2c_mux_topology_init: 6517 platform_device_unregister(priv->pdev_i2c); 6518 fail_platform_i2c_register: 6519 fail_mlxplat_mlxcpld_verify_bus_topology: 6520 return err; 6521 } 6522 6523 static void mlxplat_i2c_main_exit(struct mlxplat_priv *priv) 6524 { 6525 mlxplat_platdevs_exit(priv); 6526 mlxplat_i2c_mux_topology_exit(priv); 6527 if (priv->pdev_i2c) 6528 platform_device_unregister(priv->pdev_i2c); 6529 } 6530 6531 static int mlxplat_probe(struct platform_device *pdev) 6532 { 6533 unsigned int hotplug_resources_size = 0; 6534 struct resource *hotplug_resources = NULL; 6535 struct acpi_device *acpi_dev; 6536 struct mlxplat_priv *priv; 6537 int irq_fpga = 0, i, err; 6538 6539 acpi_dev = ACPI_COMPANION(&pdev->dev); 6540 if (acpi_dev) { 6541 irq_fpga = acpi_dev_gpio_irq_get(acpi_dev, 0); 6542 if (irq_fpga < 0) 6543 return -ENODEV; 6544 mlxplat_dev = pdev; 6545 } 6546 6547 err = mlxplat_logicdev_init(&hotplug_resources, &hotplug_resources_size); 6548 if (err) 6549 return err; 6550 6551 priv = devm_kzalloc(&mlxplat_dev->dev, sizeof(struct mlxplat_priv), 6552 GFP_KERNEL); 6553 if (!priv) { 6554 err = -ENOMEM; 6555 goto fail_alloc; 6556 } 6557 platform_set_drvdata(mlxplat_dev, priv); 6558 priv->hotplug_resources = hotplug_resources; 6559 priv->hotplug_resources_size = hotplug_resources_size; 6560 priv->irq_fpga = irq_fpga; 6561 6562 if (!mlxplat_regmap_config) 6563 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config; 6564 6565 priv->regmap = devm_regmap_init(&mlxplat_dev->dev, NULL, 6566 &mlxplat_mlxcpld_regmap_ctx, 6567 mlxplat_regmap_config); 6568 if (IS_ERR(priv->regmap)) { 6569 err = PTR_ERR(priv->regmap); 6570 goto fail_alloc; 6571 } 6572 6573 /* Set default registers. */ 6574 for (i = 0; i < mlxplat_regmap_config->num_reg_defaults; i++) { 6575 err = regmap_write(priv->regmap, 6576 mlxplat_regmap_config->reg_defaults[i].reg, 6577 mlxplat_regmap_config->reg_defaults[i].def); 6578 if (err) 6579 goto fail_regmap_write; 6580 } 6581 6582 err = mlxplat_i2c_main_init(priv); 6583 if (err) 6584 goto fail_mlxplat_i2c_main_init; 6585 6586 /* Sync registers with hardware. */ 6587 regcache_mark_dirty(priv->regmap); 6588 err = regcache_sync(priv->regmap); 6589 if (err) 6590 goto fail_regcache_sync; 6591 6592 if (mlxplat_reboot_nb) { 6593 err = register_reboot_notifier(mlxplat_reboot_nb); 6594 if (err) 6595 goto fail_register_reboot_notifier; 6596 } 6597 6598 return 0; 6599 6600 fail_register_reboot_notifier: 6601 fail_regcache_sync: 6602 mlxplat_i2c_main_exit(priv); 6603 fail_mlxplat_i2c_main_init: 6604 fail_regmap_write: 6605 fail_alloc: 6606 mlxplat_logicdev_exit(); 6607 6608 return err; 6609 } 6610 6611 static void mlxplat_remove(struct platform_device *pdev) 6612 { 6613 struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); 6614 6615 if (pm_power_off) 6616 pm_power_off = NULL; 6617 if (mlxplat_reboot_nb) 6618 unregister_reboot_notifier(mlxplat_reboot_nb); 6619 mlxplat_i2c_main_exit(priv); 6620 mlxplat_logicdev_exit(); 6621 } 6622 6623 static const struct acpi_device_id mlxplat_acpi_table[] = { 6624 { "MLNXBF49", 0 }, 6625 {} 6626 }; 6627 MODULE_DEVICE_TABLE(acpi, mlxplat_acpi_table); 6628 6629 static struct platform_driver mlxplat_driver = { 6630 .driver = { 6631 .name = "mlxplat", 6632 .acpi_match_table = mlxplat_acpi_table, 6633 .probe_type = PROBE_FORCE_SYNCHRONOUS, 6634 }, 6635 .probe = mlxplat_probe, 6636 .remove_new = mlxplat_remove, 6637 }; 6638 6639 static int __init mlxplat_init(void) 6640 { 6641 int err; 6642 6643 if (!dmi_check_system(mlxplat_dmi_table)) 6644 return -ENODEV; 6645 6646 err = platform_driver_register(&mlxplat_driver); 6647 if (err) 6648 return err; 6649 return 0; 6650 } 6651 module_init(mlxplat_init); 6652 6653 static void __exit mlxplat_exit(void) 6654 { 6655 if (mlxplat_dev) 6656 platform_device_unregister(mlxplat_dev); 6657 6658 platform_driver_unregister(&mlxplat_driver); 6659 } 6660 module_exit(mlxplat_exit); 6661 6662 MODULE_AUTHOR("Vadim Pasternak (vadimp@mellanox.com)"); 6663 MODULE_DESCRIPTION("Mellanox platform driver"); 6664 MODULE_LICENSE("Dual BSD/GPL"); 6665