1 // SPDX-License-Identifier: GPL-2.0+ 2 3 /* 4 * Copyright 2021 Pengutronix, Lucas Stach <kernel@pengutronix.de> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/device.h> 9 #include <linux/interconnect.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_platform.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_domain.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/clk.h> 18 19 #include <dt-bindings/power/imx8mm-power.h> 20 #include <dt-bindings/power/imx8mn-power.h> 21 #include <dt-bindings/power/imx8mp-power.h> 22 #include <dt-bindings/power/imx8mq-power.h> 23 24 #define BLK_SFT_RSTN 0x0 25 #define BLK_CLK_EN 0x4 26 #define BLK_MIPI_RESET_DIV 0x8 /* Mini/Nano/Plus DISPLAY_BLK_CTRL only */ 27 28 struct imx8m_blk_ctrl_domain; 29 30 struct imx8m_blk_ctrl { 31 struct device *dev; 32 struct notifier_block power_nb; 33 struct device *bus_power_dev; 34 struct regmap *regmap; 35 struct imx8m_blk_ctrl_domain *domains; 36 struct genpd_onecell_data onecell_data; 37 }; 38 39 struct imx8m_blk_ctrl_domain_data { 40 const char *name; 41 const char * const *clk_names; 42 const char * const *path_names; 43 const char *gpc_name; 44 int num_clks; 45 int num_paths; 46 u32 rst_mask; 47 u32 clk_mask; 48 49 /* 50 * i.MX8M Mini, Nano and Plus have a third DISPLAY_BLK_CTRL register 51 * which is used to control the reset for the MIPI Phy. 52 * Since it's only present in certain circumstances, 53 * an if-statement should be used before setting and clearing this 54 * register. 55 */ 56 u32 mipi_phy_rst_mask; 57 }; 58 59 #define DOMAIN_MAX_CLKS 4 60 #define DOMAIN_MAX_PATHS 4 61 62 struct imx8m_blk_ctrl_domain { 63 struct generic_pm_domain genpd; 64 const struct imx8m_blk_ctrl_domain_data *data; 65 struct clk_bulk_data clks[DOMAIN_MAX_CLKS]; 66 struct icc_bulk_data paths[DOMAIN_MAX_PATHS]; 67 struct device *power_dev; 68 struct imx8m_blk_ctrl *bc; 69 int num_paths; 70 }; 71 72 struct imx8m_blk_ctrl_data { 73 int max_reg; 74 notifier_fn_t power_notifier_fn; 75 const struct imx8m_blk_ctrl_domain_data *domains; 76 int num_domains; 77 }; 78 79 static inline struct imx8m_blk_ctrl_domain * 80 to_imx8m_blk_ctrl_domain(struct generic_pm_domain *genpd) 81 { 82 return container_of(genpd, struct imx8m_blk_ctrl_domain, genpd); 83 } 84 85 static int imx8m_blk_ctrl_power_on(struct generic_pm_domain *genpd) 86 { 87 struct imx8m_blk_ctrl_domain *domain = to_imx8m_blk_ctrl_domain(genpd); 88 const struct imx8m_blk_ctrl_domain_data *data = domain->data; 89 struct imx8m_blk_ctrl *bc = domain->bc; 90 int ret; 91 92 /* make sure bus domain is awake */ 93 ret = pm_runtime_get_sync(bc->bus_power_dev); 94 if (ret < 0) { 95 pm_runtime_put_noidle(bc->bus_power_dev); 96 dev_err(bc->dev, "failed to power up bus domain\n"); 97 return ret; 98 } 99 100 /* put devices into reset */ 101 regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask); 102 if (data->mipi_phy_rst_mask) 103 regmap_clear_bits(bc->regmap, BLK_MIPI_RESET_DIV, data->mipi_phy_rst_mask); 104 105 /* enable upstream and blk-ctrl clocks to allow reset to propagate */ 106 ret = clk_bulk_prepare_enable(data->num_clks, domain->clks); 107 if (ret) { 108 dev_err(bc->dev, "failed to enable clocks\n"); 109 goto bus_put; 110 } 111 regmap_set_bits(bc->regmap, BLK_CLK_EN, data->clk_mask); 112 113 /* power up upstream GPC domain */ 114 ret = pm_runtime_get_sync(domain->power_dev); 115 if (ret < 0) { 116 dev_err(bc->dev, "failed to power up peripheral domain\n"); 117 goto clk_disable; 118 } 119 120 /* wait for reset to propagate */ 121 udelay(5); 122 123 /* release reset */ 124 regmap_set_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask); 125 if (data->mipi_phy_rst_mask) 126 regmap_set_bits(bc->regmap, BLK_MIPI_RESET_DIV, data->mipi_phy_rst_mask); 127 128 ret = icc_bulk_set_bw(domain->num_paths, domain->paths); 129 if (ret) 130 dev_err(bc->dev, "failed to set icc bw\n"); 131 132 /* disable upstream clocks */ 133 clk_bulk_disable_unprepare(data->num_clks, domain->clks); 134 135 return 0; 136 137 clk_disable: 138 clk_bulk_disable_unprepare(data->num_clks, domain->clks); 139 bus_put: 140 pm_runtime_put(bc->bus_power_dev); 141 142 return ret; 143 } 144 145 static int imx8m_blk_ctrl_power_off(struct generic_pm_domain *genpd) 146 { 147 struct imx8m_blk_ctrl_domain *domain = to_imx8m_blk_ctrl_domain(genpd); 148 const struct imx8m_blk_ctrl_domain_data *data = domain->data; 149 struct imx8m_blk_ctrl *bc = domain->bc; 150 151 /* put devices into reset and disable clocks */ 152 if (data->mipi_phy_rst_mask) 153 regmap_clear_bits(bc->regmap, BLK_MIPI_RESET_DIV, data->mipi_phy_rst_mask); 154 155 regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask); 156 regmap_clear_bits(bc->regmap, BLK_CLK_EN, data->clk_mask); 157 158 /* power down upstream GPC domain */ 159 pm_runtime_put(domain->power_dev); 160 161 /* allow bus domain to suspend */ 162 pm_runtime_put(bc->bus_power_dev); 163 164 return 0; 165 } 166 167 static struct lock_class_key blk_ctrl_genpd_lock_class; 168 169 static int imx8m_blk_ctrl_probe(struct platform_device *pdev) 170 { 171 const struct imx8m_blk_ctrl_data *bc_data; 172 struct device *dev = &pdev->dev; 173 struct imx8m_blk_ctrl *bc; 174 void __iomem *base; 175 int i, ret; 176 177 struct regmap_config regmap_config = { 178 .reg_bits = 32, 179 .val_bits = 32, 180 .reg_stride = 4, 181 }; 182 183 bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL); 184 if (!bc) 185 return -ENOMEM; 186 187 bc->dev = dev; 188 189 bc_data = of_device_get_match_data(dev); 190 191 base = devm_platform_ioremap_resource(pdev, 0); 192 if (IS_ERR(base)) 193 return PTR_ERR(base); 194 195 regmap_config.max_register = bc_data->max_reg; 196 bc->regmap = devm_regmap_init_mmio(dev, base, ®map_config); 197 if (IS_ERR(bc->regmap)) 198 return dev_err_probe(dev, PTR_ERR(bc->regmap), 199 "failed to init regmap\n"); 200 201 bc->domains = devm_kcalloc(dev, bc_data->num_domains, 202 sizeof(struct imx8m_blk_ctrl_domain), 203 GFP_KERNEL); 204 if (!bc->domains) 205 return -ENOMEM; 206 207 bc->onecell_data.num_domains = bc_data->num_domains; 208 bc->onecell_data.domains = 209 devm_kcalloc(dev, bc_data->num_domains, 210 sizeof(struct generic_pm_domain *), GFP_KERNEL); 211 if (!bc->onecell_data.domains) 212 return -ENOMEM; 213 214 bc->bus_power_dev = dev_pm_domain_attach_by_name(dev, "bus"); 215 if (IS_ERR(bc->bus_power_dev)) { 216 if (PTR_ERR(bc->bus_power_dev) == -ENODEV) 217 return dev_err_probe(dev, -EPROBE_DEFER, 218 "failed to attach power domain \"bus\"\n"); 219 else 220 return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev), 221 "failed to attach power domain \"bus\"\n"); 222 } 223 224 for (i = 0; i < bc_data->num_domains; i++) { 225 const struct imx8m_blk_ctrl_domain_data *data = &bc_data->domains[i]; 226 struct imx8m_blk_ctrl_domain *domain = &bc->domains[i]; 227 int j; 228 229 domain->data = data; 230 domain->num_paths = data->num_paths; 231 232 for (j = 0; j < data->num_clks; j++) 233 domain->clks[j].id = data->clk_names[j]; 234 235 for (j = 0; j < data->num_paths; j++) { 236 domain->paths[j].name = data->path_names[j]; 237 /* Fake value for now, just let ICC could configure NoC mode/priority */ 238 domain->paths[j].avg_bw = 1; 239 domain->paths[j].peak_bw = 1; 240 } 241 242 ret = devm_of_icc_bulk_get(dev, data->num_paths, domain->paths); 243 if (ret) { 244 if (ret != -EPROBE_DEFER) { 245 dev_warn_once(dev, "Could not get interconnect paths, NoC will stay unconfigured!\n"); 246 domain->num_paths = 0; 247 } else { 248 dev_err_probe(dev, ret, "failed to get noc entries\n"); 249 goto cleanup_pds; 250 } 251 } 252 253 ret = devm_clk_bulk_get(dev, data->num_clks, domain->clks); 254 if (ret) { 255 dev_err_probe(dev, ret, "failed to get clock\n"); 256 goto cleanup_pds; 257 } 258 259 domain->power_dev = 260 dev_pm_domain_attach_by_name(dev, data->gpc_name); 261 if (IS_ERR(domain->power_dev)) { 262 dev_err_probe(dev, PTR_ERR(domain->power_dev), 263 "failed to attach power domain \"%s\"\n", 264 data->gpc_name); 265 ret = PTR_ERR(domain->power_dev); 266 goto cleanup_pds; 267 } 268 269 domain->genpd.name = data->name; 270 domain->genpd.power_on = imx8m_blk_ctrl_power_on; 271 domain->genpd.power_off = imx8m_blk_ctrl_power_off; 272 domain->bc = bc; 273 274 ret = pm_genpd_init(&domain->genpd, NULL, true); 275 if (ret) { 276 dev_err_probe(dev, ret, 277 "failed to init power domain \"%s\"\n", 278 data->gpc_name); 279 dev_pm_domain_detach(domain->power_dev, true); 280 goto cleanup_pds; 281 } 282 283 /* 284 * We use runtime PM to trigger power on/off of the upstream GPC 285 * domain, as a strict hierarchical parent/child power domain 286 * setup doesn't allow us to meet the sequencing requirements. 287 * This means we have nested locking of genpd locks, without the 288 * nesting being visible at the genpd level, so we need a 289 * separate lock class to make lockdep aware of the fact that 290 * this are separate domain locks that can be nested without a 291 * self-deadlock. 292 */ 293 lockdep_set_class(&domain->genpd.mlock, 294 &blk_ctrl_genpd_lock_class); 295 296 bc->onecell_data.domains[i] = &domain->genpd; 297 } 298 299 ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data); 300 if (ret) { 301 dev_err_probe(dev, ret, "failed to add power domain provider\n"); 302 goto cleanup_pds; 303 } 304 305 bc->power_nb.notifier_call = bc_data->power_notifier_fn; 306 ret = dev_pm_genpd_add_notifier(bc->bus_power_dev, &bc->power_nb); 307 if (ret) { 308 dev_err_probe(dev, ret, "failed to add power notifier\n"); 309 goto cleanup_provider; 310 } 311 312 dev_set_drvdata(dev, bc); 313 314 ret = devm_of_platform_populate(dev); 315 if (ret) 316 goto cleanup_provider; 317 318 return 0; 319 320 cleanup_provider: 321 of_genpd_del_provider(dev->of_node); 322 cleanup_pds: 323 for (i--; i >= 0; i--) { 324 pm_genpd_remove(&bc->domains[i].genpd); 325 dev_pm_domain_detach(bc->domains[i].power_dev, true); 326 } 327 328 dev_pm_domain_detach(bc->bus_power_dev, true); 329 330 return ret; 331 } 332 333 static int imx8m_blk_ctrl_remove(struct platform_device *pdev) 334 { 335 struct imx8m_blk_ctrl *bc = dev_get_drvdata(&pdev->dev); 336 int i; 337 338 of_genpd_del_provider(pdev->dev.of_node); 339 340 for (i = 0; bc->onecell_data.num_domains; i++) { 341 struct imx8m_blk_ctrl_domain *domain = &bc->domains[i]; 342 343 pm_genpd_remove(&domain->genpd); 344 dev_pm_domain_detach(domain->power_dev, true); 345 } 346 347 dev_pm_genpd_remove_notifier(bc->bus_power_dev); 348 349 dev_pm_domain_detach(bc->bus_power_dev, true); 350 351 return 0; 352 } 353 354 #ifdef CONFIG_PM_SLEEP 355 static int imx8m_blk_ctrl_suspend(struct device *dev) 356 { 357 struct imx8m_blk_ctrl *bc = dev_get_drvdata(dev); 358 int ret, i; 359 360 /* 361 * This may look strange, but is done so the generic PM_SLEEP code 362 * can power down our domains and more importantly power them up again 363 * after resume, without tripping over our usage of runtime PM to 364 * control the upstream GPC domains. Things happen in the right order 365 * in the system suspend/resume paths due to the device parent/child 366 * hierarchy. 367 */ 368 ret = pm_runtime_get_sync(bc->bus_power_dev); 369 if (ret < 0) { 370 pm_runtime_put_noidle(bc->bus_power_dev); 371 return ret; 372 } 373 374 for (i = 0; i < bc->onecell_data.num_domains; i++) { 375 struct imx8m_blk_ctrl_domain *domain = &bc->domains[i]; 376 377 ret = pm_runtime_get_sync(domain->power_dev); 378 if (ret < 0) { 379 pm_runtime_put_noidle(domain->power_dev); 380 goto out_fail; 381 } 382 } 383 384 return 0; 385 386 out_fail: 387 for (i--; i >= 0; i--) 388 pm_runtime_put(bc->domains[i].power_dev); 389 390 pm_runtime_put(bc->bus_power_dev); 391 392 return ret; 393 } 394 395 static int imx8m_blk_ctrl_resume(struct device *dev) 396 { 397 struct imx8m_blk_ctrl *bc = dev_get_drvdata(dev); 398 int i; 399 400 for (i = 0; i < bc->onecell_data.num_domains; i++) 401 pm_runtime_put(bc->domains[i].power_dev); 402 403 pm_runtime_put(bc->bus_power_dev); 404 405 return 0; 406 } 407 #endif 408 409 static const struct dev_pm_ops imx8m_blk_ctrl_pm_ops = { 410 SET_SYSTEM_SLEEP_PM_OPS(imx8m_blk_ctrl_suspend, imx8m_blk_ctrl_resume) 411 }; 412 413 static int imx8mm_vpu_power_notifier(struct notifier_block *nb, 414 unsigned long action, void *data) 415 { 416 struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, 417 power_nb); 418 419 if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) 420 return NOTIFY_OK; 421 422 /* 423 * The ADB in the VPUMIX domain has no separate reset and clock 424 * enable bits, but is ungated together with the VPU clocks. To 425 * allow the handshake with the GPC to progress we put the VPUs 426 * in reset and ungate the clocks. 427 */ 428 regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, BIT(0) | BIT(1) | BIT(2)); 429 regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(0) | BIT(1) | BIT(2)); 430 431 if (action == GENPD_NOTIFY_ON) { 432 /* 433 * On power up we have no software backchannel to the GPC to 434 * wait for the ADB handshake to happen, so we just delay for a 435 * bit. On power down the GPC driver waits for the handshake. 436 */ 437 udelay(5); 438 439 /* set "fuse" bits to enable the VPUs */ 440 regmap_set_bits(bc->regmap, 0x8, 0xffffffff); 441 regmap_set_bits(bc->regmap, 0xc, 0xffffffff); 442 regmap_set_bits(bc->regmap, 0x10, 0xffffffff); 443 regmap_set_bits(bc->regmap, 0x14, 0xffffffff); 444 } 445 446 return NOTIFY_OK; 447 } 448 449 static const struct imx8m_blk_ctrl_domain_data imx8mm_vpu_blk_ctl_domain_data[] = { 450 [IMX8MM_VPUBLK_PD_G1] = { 451 .name = "vpublk-g1", 452 .clk_names = (const char *[]){ "g1", }, 453 .num_clks = 1, 454 .gpc_name = "g1", 455 .rst_mask = BIT(1), 456 .clk_mask = BIT(1), 457 }, 458 [IMX8MM_VPUBLK_PD_G2] = { 459 .name = "vpublk-g2", 460 .clk_names = (const char *[]){ "g2", }, 461 .num_clks = 1, 462 .gpc_name = "g2", 463 .rst_mask = BIT(0), 464 .clk_mask = BIT(0), 465 }, 466 [IMX8MM_VPUBLK_PD_H1] = { 467 .name = "vpublk-h1", 468 .clk_names = (const char *[]){ "h1", }, 469 .num_clks = 1, 470 .gpc_name = "h1", 471 .rst_mask = BIT(2), 472 .clk_mask = BIT(2), 473 }, 474 }; 475 476 static const struct imx8m_blk_ctrl_data imx8mm_vpu_blk_ctl_dev_data = { 477 .max_reg = 0x18, 478 .power_notifier_fn = imx8mm_vpu_power_notifier, 479 .domains = imx8mm_vpu_blk_ctl_domain_data, 480 .num_domains = ARRAY_SIZE(imx8mm_vpu_blk_ctl_domain_data), 481 }; 482 483 static const struct imx8m_blk_ctrl_domain_data imx8mp_vpu_blk_ctl_domain_data[] = { 484 [IMX8MP_VPUBLK_PD_G1] = { 485 .name = "vpublk-g1", 486 .clk_names = (const char *[]){ "g1", }, 487 .num_clks = 1, 488 .gpc_name = "g1", 489 .rst_mask = BIT(1), 490 .clk_mask = BIT(1), 491 .path_names = (const char *[]){"g1"}, 492 .num_paths = 1, 493 }, 494 [IMX8MP_VPUBLK_PD_G2] = { 495 .name = "vpublk-g2", 496 .clk_names = (const char *[]){ "g2", }, 497 .num_clks = 1, 498 .gpc_name = "g2", 499 .rst_mask = BIT(0), 500 .clk_mask = BIT(0), 501 .path_names = (const char *[]){"g2"}, 502 .num_paths = 1, 503 }, 504 [IMX8MP_VPUBLK_PD_VC8000E] = { 505 .name = "vpublk-vc8000e", 506 .clk_names = (const char *[]){ "vc8000e", }, 507 .num_clks = 1, 508 .gpc_name = "vc8000e", 509 .rst_mask = BIT(2), 510 .clk_mask = BIT(2), 511 .path_names = (const char *[]){"vc8000e"}, 512 .num_paths = 1, 513 }, 514 }; 515 516 static const struct imx8m_blk_ctrl_data imx8mp_vpu_blk_ctl_dev_data = { 517 .max_reg = 0x18, 518 .power_notifier_fn = imx8mm_vpu_power_notifier, 519 .domains = imx8mp_vpu_blk_ctl_domain_data, 520 .num_domains = ARRAY_SIZE(imx8mp_vpu_blk_ctl_domain_data), 521 }; 522 523 static int imx8mm_disp_power_notifier(struct notifier_block *nb, 524 unsigned long action, void *data) 525 { 526 struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, 527 power_nb); 528 529 if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) 530 return NOTIFY_OK; 531 532 /* Enable bus clock and deassert bus reset */ 533 regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(12)); 534 regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(6)); 535 536 /* 537 * On power up we have no software backchannel to the GPC to 538 * wait for the ADB handshake to happen, so we just delay for a 539 * bit. On power down the GPC driver waits for the handshake. 540 */ 541 if (action == GENPD_NOTIFY_ON) 542 udelay(5); 543 544 545 return NOTIFY_OK; 546 } 547 548 static const struct imx8m_blk_ctrl_domain_data imx8mm_disp_blk_ctl_domain_data[] = { 549 [IMX8MM_DISPBLK_PD_CSI_BRIDGE] = { 550 .name = "dispblk-csi-bridge", 551 .clk_names = (const char *[]){ "csi-bridge-axi", "csi-bridge-apb", 552 "csi-bridge-core", }, 553 .num_clks = 3, 554 .gpc_name = "csi-bridge", 555 .rst_mask = BIT(0) | BIT(1) | BIT(2), 556 .clk_mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5), 557 }, 558 [IMX8MM_DISPBLK_PD_LCDIF] = { 559 .name = "dispblk-lcdif", 560 .clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", }, 561 .num_clks = 3, 562 .gpc_name = "lcdif", 563 .clk_mask = BIT(6) | BIT(7), 564 }, 565 [IMX8MM_DISPBLK_PD_MIPI_DSI] = { 566 .name = "dispblk-mipi-dsi", 567 .clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", }, 568 .num_clks = 2, 569 .gpc_name = "mipi-dsi", 570 .rst_mask = BIT(5), 571 .clk_mask = BIT(8) | BIT(9), 572 .mipi_phy_rst_mask = BIT(17), 573 }, 574 [IMX8MM_DISPBLK_PD_MIPI_CSI] = { 575 .name = "dispblk-mipi-csi", 576 .clk_names = (const char *[]){ "csi-aclk", "csi-pclk" }, 577 .num_clks = 2, 578 .gpc_name = "mipi-csi", 579 .rst_mask = BIT(3) | BIT(4), 580 .clk_mask = BIT(10) | BIT(11), 581 .mipi_phy_rst_mask = BIT(16), 582 }, 583 }; 584 585 static const struct imx8m_blk_ctrl_data imx8mm_disp_blk_ctl_dev_data = { 586 .max_reg = 0x2c, 587 .power_notifier_fn = imx8mm_disp_power_notifier, 588 .domains = imx8mm_disp_blk_ctl_domain_data, 589 .num_domains = ARRAY_SIZE(imx8mm_disp_blk_ctl_domain_data), 590 }; 591 592 593 static int imx8mn_disp_power_notifier(struct notifier_block *nb, 594 unsigned long action, void *data) 595 { 596 struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, 597 power_nb); 598 599 if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) 600 return NOTIFY_OK; 601 602 /* Enable bus clock and deassert bus reset */ 603 regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8)); 604 regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8)); 605 606 /* 607 * On power up we have no software backchannel to the GPC to 608 * wait for the ADB handshake to happen, so we just delay for a 609 * bit. On power down the GPC driver waits for the handshake. 610 */ 611 if (action == GENPD_NOTIFY_ON) 612 udelay(5); 613 614 615 return NOTIFY_OK; 616 } 617 618 static const struct imx8m_blk_ctrl_domain_data imx8mn_disp_blk_ctl_domain_data[] = { 619 [IMX8MN_DISPBLK_PD_MIPI_DSI] = { 620 .name = "dispblk-mipi-dsi", 621 .clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", }, 622 .num_clks = 2, 623 .gpc_name = "mipi-dsi", 624 .rst_mask = BIT(0) | BIT(1), 625 .clk_mask = BIT(0) | BIT(1), 626 .mipi_phy_rst_mask = BIT(17), 627 }, 628 [IMX8MN_DISPBLK_PD_MIPI_CSI] = { 629 .name = "dispblk-mipi-csi", 630 .clk_names = (const char *[]){ "csi-aclk", "csi-pclk" }, 631 .num_clks = 2, 632 .gpc_name = "mipi-csi", 633 .rst_mask = BIT(2) | BIT(3), 634 .clk_mask = BIT(2) | BIT(3), 635 .mipi_phy_rst_mask = BIT(16), 636 }, 637 [IMX8MN_DISPBLK_PD_LCDIF] = { 638 .name = "dispblk-lcdif", 639 .clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", }, 640 .num_clks = 3, 641 .gpc_name = "lcdif", 642 .rst_mask = BIT(4) | BIT(5), 643 .clk_mask = BIT(4) | BIT(5), 644 }, 645 [IMX8MN_DISPBLK_PD_ISI] = { 646 .name = "dispblk-isi", 647 .clk_names = (const char *[]){ "disp_axi", "disp_apb", "disp_axi_root", 648 "disp_apb_root"}, 649 .num_clks = 4, 650 .gpc_name = "isi", 651 .rst_mask = BIT(6) | BIT(7), 652 .clk_mask = BIT(6) | BIT(7), 653 }, 654 }; 655 656 static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = { 657 .max_reg = 0x84, 658 .power_notifier_fn = imx8mn_disp_power_notifier, 659 .domains = imx8mn_disp_blk_ctl_domain_data, 660 .num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data), 661 }; 662 663 #define LCDIF_ARCACHE_CTRL 0x4c 664 #define LCDIF_1_RD_HURRY GENMASK(15, 13) 665 #define LCDIF_0_RD_HURRY GENMASK(12, 10) 666 667 static int imx8mp_media_power_notifier(struct notifier_block *nb, 668 unsigned long action, void *data) 669 { 670 struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, 671 power_nb); 672 673 if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) 674 return NOTIFY_OK; 675 676 /* Enable bus clock and deassert bus reset */ 677 regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8)); 678 regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8)); 679 680 if (action == GENPD_NOTIFY_ON) { 681 /* 682 * On power up we have no software backchannel to the GPC to 683 * wait for the ADB handshake to happen, so we just delay for a 684 * bit. On power down the GPC driver waits for the handshake. 685 */ 686 udelay(5); 687 688 /* 689 * Set panic read hurry level for both LCDIF interfaces to 690 * maximum priority to minimize chances of display FIFO 691 * underflow. 692 */ 693 regmap_set_bits(bc->regmap, LCDIF_ARCACHE_CTRL, 694 FIELD_PREP(LCDIF_1_RD_HURRY, 7) | 695 FIELD_PREP(LCDIF_0_RD_HURRY, 7)); 696 } 697 698 return NOTIFY_OK; 699 } 700 701 /* 702 * From i.MX 8M Plus Applications Processor Reference Manual, Rev. 1, 703 * section 13.2.2, 13.2.3 704 * isp-ahb and dwe are not in Figure 13-5. Media BLK_CTRL Clocks 705 */ 706 static const struct imx8m_blk_ctrl_domain_data imx8mp_media_blk_ctl_domain_data[] = { 707 [IMX8MP_MEDIABLK_PD_MIPI_DSI_1] = { 708 .name = "mediablk-mipi-dsi-1", 709 .clk_names = (const char *[]){ "apb", "phy", }, 710 .num_clks = 2, 711 .gpc_name = "mipi-dsi1", 712 .rst_mask = BIT(0) | BIT(1), 713 .clk_mask = BIT(0) | BIT(1), 714 .mipi_phy_rst_mask = BIT(17), 715 }, 716 [IMX8MP_MEDIABLK_PD_MIPI_CSI2_1] = { 717 .name = "mediablk-mipi-csi2-1", 718 .clk_names = (const char *[]){ "apb", "cam1" }, 719 .num_clks = 2, 720 .gpc_name = "mipi-csi1", 721 .rst_mask = BIT(2) | BIT(3), 722 .clk_mask = BIT(2) | BIT(3), 723 .mipi_phy_rst_mask = BIT(16), 724 }, 725 [IMX8MP_MEDIABLK_PD_LCDIF_1] = { 726 .name = "mediablk-lcdif-1", 727 .clk_names = (const char *[]){ "disp1", "apb", "axi", }, 728 .num_clks = 3, 729 .gpc_name = "lcdif1", 730 .rst_mask = BIT(4) | BIT(5) | BIT(23), 731 .clk_mask = BIT(4) | BIT(5) | BIT(23), 732 .path_names = (const char *[]){"lcdif-rd", "lcdif-wr"}, 733 .num_paths = 2, 734 }, 735 [IMX8MP_MEDIABLK_PD_ISI] = { 736 .name = "mediablk-isi", 737 .clk_names = (const char *[]){ "axi", "apb" }, 738 .num_clks = 2, 739 .gpc_name = "isi", 740 .rst_mask = BIT(6) | BIT(7), 741 .clk_mask = BIT(6) | BIT(7), 742 .path_names = (const char *[]){"isi0", "isi1", "isi2"}, 743 .num_paths = 3, 744 }, 745 [IMX8MP_MEDIABLK_PD_MIPI_CSI2_2] = { 746 .name = "mediablk-mipi-csi2-2", 747 .clk_names = (const char *[]){ "apb", "cam2" }, 748 .num_clks = 2, 749 .gpc_name = "mipi-csi2", 750 .rst_mask = BIT(9) | BIT(10), 751 .clk_mask = BIT(9) | BIT(10), 752 .mipi_phy_rst_mask = BIT(30), 753 }, 754 [IMX8MP_MEDIABLK_PD_LCDIF_2] = { 755 .name = "mediablk-lcdif-2", 756 .clk_names = (const char *[]){ "disp2", "apb", "axi", }, 757 .num_clks = 3, 758 .gpc_name = "lcdif2", 759 .rst_mask = BIT(11) | BIT(12) | BIT(24), 760 .clk_mask = BIT(11) | BIT(12) | BIT(24), 761 .path_names = (const char *[]){"lcdif-rd", "lcdif-wr"}, 762 .num_paths = 2, 763 }, 764 [IMX8MP_MEDIABLK_PD_ISP] = { 765 .name = "mediablk-isp", 766 .clk_names = (const char *[]){ "isp", "axi", "apb" }, 767 .num_clks = 3, 768 .gpc_name = "isp", 769 .rst_mask = BIT(16) | BIT(17) | BIT(18), 770 .clk_mask = BIT(16) | BIT(17) | BIT(18), 771 .path_names = (const char *[]){"isp0", "isp1"}, 772 .num_paths = 2, 773 }, 774 [IMX8MP_MEDIABLK_PD_DWE] = { 775 .name = "mediablk-dwe", 776 .clk_names = (const char *[]){ "axi", "apb" }, 777 .num_clks = 2, 778 .gpc_name = "dwe", 779 .rst_mask = BIT(19) | BIT(20) | BIT(21), 780 .clk_mask = BIT(19) | BIT(20) | BIT(21), 781 .path_names = (const char *[]){"dwe"}, 782 .num_paths = 1, 783 }, 784 [IMX8MP_MEDIABLK_PD_MIPI_DSI_2] = { 785 .name = "mediablk-mipi-dsi-2", 786 .clk_names = (const char *[]){ "phy", }, 787 .num_clks = 1, 788 .gpc_name = "mipi-dsi2", 789 .rst_mask = BIT(22), 790 .clk_mask = BIT(22), 791 .mipi_phy_rst_mask = BIT(29), 792 }, 793 }; 794 795 static const struct imx8m_blk_ctrl_data imx8mp_media_blk_ctl_dev_data = { 796 .max_reg = 0x138, 797 .power_notifier_fn = imx8mp_media_power_notifier, 798 .domains = imx8mp_media_blk_ctl_domain_data, 799 .num_domains = ARRAY_SIZE(imx8mp_media_blk_ctl_domain_data), 800 }; 801 802 static int imx8mq_vpu_power_notifier(struct notifier_block *nb, 803 unsigned long action, void *data) 804 { 805 struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, 806 power_nb); 807 808 if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) 809 return NOTIFY_OK; 810 811 /* 812 * The ADB in the VPUMIX domain has no separate reset and clock 813 * enable bits, but is ungated and reset together with the VPUs. The 814 * reset and clock enable inputs to the ADB is a logical OR of the 815 * VPU bits. In order to set the G2 fuse bits, the G2 clock must 816 * also be enabled. 817 */ 818 regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(0) | BIT(1)); 819 regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(0) | BIT(1)); 820 821 if (action == GENPD_NOTIFY_ON) { 822 /* 823 * On power up we have no software backchannel to the GPC to 824 * wait for the ADB handshake to happen, so we just delay for a 825 * bit. On power down the GPC driver waits for the handshake. 826 */ 827 udelay(5); 828 829 /* set "fuse" bits to enable the VPUs */ 830 regmap_set_bits(bc->regmap, 0x8, 0xffffffff); 831 regmap_set_bits(bc->regmap, 0xc, 0xffffffff); 832 regmap_set_bits(bc->regmap, 0x10, 0xffffffff); 833 } 834 835 return NOTIFY_OK; 836 } 837 838 static const struct imx8m_blk_ctrl_domain_data imx8mq_vpu_blk_ctl_domain_data[] = { 839 [IMX8MQ_VPUBLK_PD_G1] = { 840 .name = "vpublk-g1", 841 .clk_names = (const char *[]){ "g1", }, 842 .num_clks = 1, 843 .gpc_name = "g1", 844 .rst_mask = BIT(1), 845 .clk_mask = BIT(1), 846 }, 847 [IMX8MQ_VPUBLK_PD_G2] = { 848 .name = "vpublk-g2", 849 .clk_names = (const char *[]){ "g2", }, 850 .num_clks = 1, 851 .gpc_name = "g2", 852 .rst_mask = BIT(0), 853 .clk_mask = BIT(0), 854 }, 855 }; 856 857 static const struct imx8m_blk_ctrl_data imx8mq_vpu_blk_ctl_dev_data = { 858 .max_reg = 0x14, 859 .power_notifier_fn = imx8mq_vpu_power_notifier, 860 .domains = imx8mq_vpu_blk_ctl_domain_data, 861 .num_domains = ARRAY_SIZE(imx8mq_vpu_blk_ctl_domain_data), 862 }; 863 864 static const struct of_device_id imx8m_blk_ctrl_of_match[] = { 865 { 866 .compatible = "fsl,imx8mm-vpu-blk-ctrl", 867 .data = &imx8mm_vpu_blk_ctl_dev_data 868 }, { 869 .compatible = "fsl,imx8mm-disp-blk-ctrl", 870 .data = &imx8mm_disp_blk_ctl_dev_data 871 }, { 872 .compatible = "fsl,imx8mn-disp-blk-ctrl", 873 .data = &imx8mn_disp_blk_ctl_dev_data 874 }, { 875 .compatible = "fsl,imx8mp-media-blk-ctrl", 876 .data = &imx8mp_media_blk_ctl_dev_data 877 }, { 878 .compatible = "fsl,imx8mq-vpu-blk-ctrl", 879 .data = &imx8mq_vpu_blk_ctl_dev_data 880 }, { 881 .compatible = "fsl,imx8mp-vpu-blk-ctrl", 882 .data = &imx8mp_vpu_blk_ctl_dev_data 883 }, { 884 /* Sentinel */ 885 } 886 }; 887 MODULE_DEVICE_TABLE(of, imx8m_blk_ctrl_of_match); 888 889 static struct platform_driver imx8m_blk_ctrl_driver = { 890 .probe = imx8m_blk_ctrl_probe, 891 .remove = imx8m_blk_ctrl_remove, 892 .driver = { 893 .name = "imx8m-blk-ctrl", 894 .pm = &imx8m_blk_ctrl_pm_ops, 895 .of_match_table = imx8m_blk_ctrl_of_match, 896 }, 897 }; 898 module_platform_driver(imx8m_blk_ctrl_driver); 899 MODULE_LICENSE("GPL"); 900