1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Freescale FlexTimer Module (FTM) PWM Driver 4 * 5 * Copyright 2012-2013 Freescale Semiconductor, Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/of_address.h> 15 #include <linux/of_device.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm.h> 18 #include <linux/pwm.h> 19 #include <linux/regmap.h> 20 #include <linux/slab.h> 21 #include <linux/fsl/ftm.h> 22 23 #define FTM_SC_CLK(c) (((c) + 1) << FTM_SC_CLK_MASK_SHIFT) 24 25 enum fsl_pwm_clk { 26 FSL_PWM_CLK_SYS, 27 FSL_PWM_CLK_FIX, 28 FSL_PWM_CLK_EXT, 29 FSL_PWM_CLK_CNTEN, 30 FSL_PWM_CLK_MAX 31 }; 32 33 struct fsl_ftm_soc { 34 bool has_enable_bits; 35 }; 36 37 struct fsl_pwm_chip { 38 struct pwm_chip chip; 39 40 struct mutex lock; 41 42 unsigned int cnt_select; 43 unsigned int clk_ps; 44 45 struct regmap *regmap; 46 47 int period_ns; 48 49 struct clk *ipg_clk; 50 struct clk *clk[FSL_PWM_CLK_MAX]; 51 52 const struct fsl_ftm_soc *soc; 53 }; 54 55 static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip) 56 { 57 return container_of(chip, struct fsl_pwm_chip, chip); 58 } 59 60 static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 61 { 62 int ret; 63 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 64 65 ret = clk_prepare_enable(fpc->ipg_clk); 66 if (!ret && fpc->soc->has_enable_bits) { 67 mutex_lock(&fpc->lock); 68 regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16), 69 BIT(pwm->hwpwm + 16)); 70 mutex_unlock(&fpc->lock); 71 } 72 73 return ret; 74 } 75 76 static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 77 { 78 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 79 80 if (fpc->soc->has_enable_bits) { 81 mutex_lock(&fpc->lock); 82 regmap_update_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16), 83 0); 84 mutex_unlock(&fpc->lock); 85 } 86 87 clk_disable_unprepare(fpc->ipg_clk); 88 } 89 90 static int fsl_pwm_calculate_default_ps(struct fsl_pwm_chip *fpc, 91 enum fsl_pwm_clk index) 92 { 93 unsigned long sys_rate, cnt_rate; 94 unsigned long long ratio; 95 96 sys_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_SYS]); 97 if (!sys_rate) 98 return -EINVAL; 99 100 cnt_rate = clk_get_rate(fpc->clk[fpc->cnt_select]); 101 if (!cnt_rate) 102 return -EINVAL; 103 104 switch (index) { 105 case FSL_PWM_CLK_SYS: 106 fpc->clk_ps = 1; 107 break; 108 case FSL_PWM_CLK_FIX: 109 ratio = 2 * cnt_rate - 1; 110 do_div(ratio, sys_rate); 111 fpc->clk_ps = ratio; 112 break; 113 case FSL_PWM_CLK_EXT: 114 ratio = 4 * cnt_rate - 1; 115 do_div(ratio, sys_rate); 116 fpc->clk_ps = ratio; 117 break; 118 default: 119 return -EINVAL; 120 } 121 122 return 0; 123 } 124 125 static unsigned long fsl_pwm_calculate_cycles(struct fsl_pwm_chip *fpc, 126 unsigned long period_ns) 127 { 128 unsigned long long c, c0; 129 130 c = clk_get_rate(fpc->clk[fpc->cnt_select]); 131 c = c * period_ns; 132 do_div(c, 1000000000UL); 133 134 do { 135 c0 = c; 136 do_div(c0, (1 << fpc->clk_ps)); 137 if (c0 <= 0xFFFF) 138 return (unsigned long)c0; 139 } while (++fpc->clk_ps < 8); 140 141 return 0; 142 } 143 144 static unsigned long fsl_pwm_calculate_period_cycles(struct fsl_pwm_chip *fpc, 145 unsigned long period_ns, 146 enum fsl_pwm_clk index) 147 { 148 int ret; 149 150 ret = fsl_pwm_calculate_default_ps(fpc, index); 151 if (ret) { 152 dev_err(fpc->chip.dev, 153 "failed to calculate default prescaler: %d\n", 154 ret); 155 return 0; 156 } 157 158 return fsl_pwm_calculate_cycles(fpc, period_ns); 159 } 160 161 static unsigned long fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc, 162 unsigned long period_ns) 163 { 164 enum fsl_pwm_clk m0, m1; 165 unsigned long fix_rate, ext_rate, cycles; 166 167 cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns, 168 FSL_PWM_CLK_SYS); 169 if (cycles) { 170 fpc->cnt_select = FSL_PWM_CLK_SYS; 171 return cycles; 172 } 173 174 fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]); 175 ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]); 176 177 if (fix_rate > ext_rate) { 178 m0 = FSL_PWM_CLK_FIX; 179 m1 = FSL_PWM_CLK_EXT; 180 } else { 181 m0 = FSL_PWM_CLK_EXT; 182 m1 = FSL_PWM_CLK_FIX; 183 } 184 185 cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns, m0); 186 if (cycles) { 187 fpc->cnt_select = m0; 188 return cycles; 189 } 190 191 fpc->cnt_select = m1; 192 193 return fsl_pwm_calculate_period_cycles(fpc, period_ns, m1); 194 } 195 196 static unsigned long fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc, 197 unsigned long period_ns, 198 unsigned long duty_ns) 199 { 200 unsigned long long duty; 201 u32 val; 202 203 regmap_read(fpc->regmap, FTM_MOD, &val); 204 duty = (unsigned long long)duty_ns * (val + 1); 205 do_div(duty, period_ns); 206 207 return (unsigned long)duty; 208 } 209 210 static int fsl_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 211 int duty_ns, int period_ns) 212 { 213 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 214 u32 period, duty; 215 216 mutex_lock(&fpc->lock); 217 218 /* 219 * The Freescale FTM controller supports only a single period for 220 * all PWM channels, therefore incompatible changes need to be 221 * refused. 222 */ 223 if (fpc->period_ns && fpc->period_ns != period_ns) { 224 dev_err(fpc->chip.dev, 225 "conflicting period requested for PWM %u\n", 226 pwm->hwpwm); 227 mutex_unlock(&fpc->lock); 228 return -EBUSY; 229 } 230 231 if (!fpc->period_ns && duty_ns) { 232 period = fsl_pwm_calculate_period(fpc, period_ns); 233 if (!period) { 234 dev_err(fpc->chip.dev, "failed to calculate period\n"); 235 mutex_unlock(&fpc->lock); 236 return -EINVAL; 237 } 238 239 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK, 240 fpc->clk_ps); 241 regmap_write(fpc->regmap, FTM_MOD, period - 1); 242 243 fpc->period_ns = period_ns; 244 } 245 246 mutex_unlock(&fpc->lock); 247 248 duty = fsl_pwm_calculate_duty(fpc, period_ns, duty_ns); 249 250 regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm), 251 FTM_CSC_MSB | FTM_CSC_ELSB); 252 regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty); 253 254 return 0; 255 } 256 257 static int fsl_pwm_set_polarity(struct pwm_chip *chip, 258 struct pwm_device *pwm, 259 enum pwm_polarity polarity) 260 { 261 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 262 u32 val; 263 264 regmap_read(fpc->regmap, FTM_POL, &val); 265 266 if (polarity == PWM_POLARITY_INVERSED) 267 val |= BIT(pwm->hwpwm); 268 else 269 val &= ~BIT(pwm->hwpwm); 270 271 regmap_write(fpc->regmap, FTM_POL, val); 272 273 return 0; 274 } 275 276 static int fsl_counter_clock_enable(struct fsl_pwm_chip *fpc) 277 { 278 int ret; 279 280 /* select counter clock source */ 281 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK, 282 FTM_SC_CLK(fpc->cnt_select)); 283 284 ret = clk_prepare_enable(fpc->clk[fpc->cnt_select]); 285 if (ret) 286 return ret; 287 288 ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]); 289 if (ret) { 290 clk_disable_unprepare(fpc->clk[fpc->cnt_select]); 291 return ret; 292 } 293 294 return 0; 295 } 296 297 static int fsl_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 298 { 299 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 300 int ret; 301 302 mutex_lock(&fpc->lock); 303 regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm), 0); 304 305 ret = fsl_counter_clock_enable(fpc); 306 mutex_unlock(&fpc->lock); 307 308 return ret; 309 } 310 311 static void fsl_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 312 { 313 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 314 u32 val; 315 316 mutex_lock(&fpc->lock); 317 regmap_update_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm), 318 BIT(pwm->hwpwm)); 319 320 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]); 321 clk_disable_unprepare(fpc->clk[fpc->cnt_select]); 322 323 regmap_read(fpc->regmap, FTM_OUTMASK, &val); 324 if ((val & 0xFF) == 0xFF) 325 fpc->period_ns = 0; 326 327 mutex_unlock(&fpc->lock); 328 } 329 330 static const struct pwm_ops fsl_pwm_ops = { 331 .request = fsl_pwm_request, 332 .free = fsl_pwm_free, 333 .config = fsl_pwm_config, 334 .set_polarity = fsl_pwm_set_polarity, 335 .enable = fsl_pwm_enable, 336 .disable = fsl_pwm_disable, 337 .owner = THIS_MODULE, 338 }; 339 340 static int fsl_pwm_init(struct fsl_pwm_chip *fpc) 341 { 342 int ret; 343 344 ret = clk_prepare_enable(fpc->ipg_clk); 345 if (ret) 346 return ret; 347 348 regmap_write(fpc->regmap, FTM_CNTIN, 0x00); 349 regmap_write(fpc->regmap, FTM_OUTINIT, 0x00); 350 regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF); 351 352 clk_disable_unprepare(fpc->ipg_clk); 353 354 return 0; 355 } 356 357 static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg) 358 { 359 switch (reg) { 360 case FTM_CNT: 361 return true; 362 } 363 return false; 364 } 365 366 static const struct regmap_config fsl_pwm_regmap_config = { 367 .reg_bits = 32, 368 .reg_stride = 4, 369 .val_bits = 32, 370 371 .max_register = FTM_PWMLOAD, 372 .volatile_reg = fsl_pwm_volatile_reg, 373 .cache_type = REGCACHE_FLAT, 374 }; 375 376 static int fsl_pwm_probe(struct platform_device *pdev) 377 { 378 struct fsl_pwm_chip *fpc; 379 struct resource *res; 380 void __iomem *base; 381 int ret; 382 383 fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL); 384 if (!fpc) 385 return -ENOMEM; 386 387 mutex_init(&fpc->lock); 388 389 fpc->soc = of_device_get_match_data(&pdev->dev); 390 fpc->chip.dev = &pdev->dev; 391 392 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 393 base = devm_ioremap_resource(&pdev->dev, res); 394 if (IS_ERR(base)) 395 return PTR_ERR(base); 396 397 fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base, 398 &fsl_pwm_regmap_config); 399 if (IS_ERR(fpc->regmap)) { 400 dev_err(&pdev->dev, "regmap init failed\n"); 401 return PTR_ERR(fpc->regmap); 402 } 403 404 fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys"); 405 if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) { 406 dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n"); 407 return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]); 408 } 409 410 fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix"); 411 if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX])) 412 return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]); 413 414 fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext"); 415 if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT])) 416 return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]); 417 418 fpc->clk[FSL_PWM_CLK_CNTEN] = 419 devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en"); 420 if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN])) 421 return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]); 422 423 /* 424 * ipg_clk is the interface clock for the IP. If not provided, use the 425 * ftm_sys clock as the default. 426 */ 427 fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 428 if (IS_ERR(fpc->ipg_clk)) 429 fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS]; 430 431 432 fpc->chip.ops = &fsl_pwm_ops; 433 fpc->chip.of_xlate = of_pwm_xlate_with_flags; 434 fpc->chip.of_pwm_n_cells = 3; 435 fpc->chip.base = -1; 436 fpc->chip.npwm = 8; 437 438 ret = pwmchip_add(&fpc->chip); 439 if (ret < 0) { 440 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); 441 return ret; 442 } 443 444 platform_set_drvdata(pdev, fpc); 445 446 return fsl_pwm_init(fpc); 447 } 448 449 static int fsl_pwm_remove(struct platform_device *pdev) 450 { 451 struct fsl_pwm_chip *fpc = platform_get_drvdata(pdev); 452 453 return pwmchip_remove(&fpc->chip); 454 } 455 456 #ifdef CONFIG_PM_SLEEP 457 static int fsl_pwm_suspend(struct device *dev) 458 { 459 struct fsl_pwm_chip *fpc = dev_get_drvdata(dev); 460 int i; 461 462 regcache_cache_only(fpc->regmap, true); 463 regcache_mark_dirty(fpc->regmap); 464 465 for (i = 0; i < fpc->chip.npwm; i++) { 466 struct pwm_device *pwm = &fpc->chip.pwms[i]; 467 468 if (!test_bit(PWMF_REQUESTED, &pwm->flags)) 469 continue; 470 471 clk_disable_unprepare(fpc->ipg_clk); 472 473 if (!pwm_is_enabled(pwm)) 474 continue; 475 476 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]); 477 clk_disable_unprepare(fpc->clk[fpc->cnt_select]); 478 } 479 480 return 0; 481 } 482 483 static int fsl_pwm_resume(struct device *dev) 484 { 485 struct fsl_pwm_chip *fpc = dev_get_drvdata(dev); 486 int i; 487 488 for (i = 0; i < fpc->chip.npwm; i++) { 489 struct pwm_device *pwm = &fpc->chip.pwms[i]; 490 491 if (!test_bit(PWMF_REQUESTED, &pwm->flags)) 492 continue; 493 494 clk_prepare_enable(fpc->ipg_clk); 495 496 if (!pwm_is_enabled(pwm)) 497 continue; 498 499 clk_prepare_enable(fpc->clk[fpc->cnt_select]); 500 clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]); 501 } 502 503 /* restore all registers from cache */ 504 regcache_cache_only(fpc->regmap, false); 505 regcache_sync(fpc->regmap); 506 507 return 0; 508 } 509 #endif 510 511 static const struct dev_pm_ops fsl_pwm_pm_ops = { 512 SET_SYSTEM_SLEEP_PM_OPS(fsl_pwm_suspend, fsl_pwm_resume) 513 }; 514 515 static const struct fsl_ftm_soc vf610_ftm_pwm = { 516 .has_enable_bits = false, 517 }; 518 519 static const struct fsl_ftm_soc imx8qm_ftm_pwm = { 520 .has_enable_bits = true, 521 }; 522 523 static const struct of_device_id fsl_pwm_dt_ids[] = { 524 { .compatible = "fsl,vf610-ftm-pwm", .data = &vf610_ftm_pwm }, 525 { .compatible = "fsl,imx8qm-ftm-pwm", .data = &imx8qm_ftm_pwm }, 526 { /* sentinel */ } 527 }; 528 MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids); 529 530 static struct platform_driver fsl_pwm_driver = { 531 .driver = { 532 .name = "fsl-ftm-pwm", 533 .of_match_table = fsl_pwm_dt_ids, 534 .pm = &fsl_pwm_pm_ops, 535 }, 536 .probe = fsl_pwm_probe, 537 .remove = fsl_pwm_remove, 538 }; 539 module_platform_driver(fsl_pwm_driver); 540 541 MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver"); 542 MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>"); 543 MODULE_ALIAS("platform:fsl-ftm-pwm"); 544 MODULE_LICENSE("GPL"); 545