1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2020 Intel Corporation. 4 * 5 * Limitations: 6 * - The hardware supports fixed period & configures only 2-wire mode. 7 * - Supports normal polarity. Does not support changing polarity. 8 * - When PWM is disabled, output of PWM will become 0(inactive). It doesn't 9 * keep track of running period. 10 * - When duty cycle is changed, PWM output may be a mix of previous setting 11 * and new setting for the first period. From second period, the output is 12 * based on new setting. 13 * - It is a dedicated PWM fan controller. There are no other consumers for 14 * this PWM controller. 15 */ 16 #include <linux/bitfield.h> 17 #include <linux/clk.h> 18 #include <linux/module.h> 19 #include <linux/platform_device.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/pwm.h> 22 #include <linux/regmap.h> 23 #include <linux/reset.h> 24 25 #define LGM_PWM_FAN_CON0 0x0 26 #define LGM_PWM_FAN_EN_EN BIT(0) 27 #define LGM_PWM_FAN_EN_DIS 0x0 28 #define LGM_PWM_FAN_EN_MSK BIT(0) 29 #define LGM_PWM_FAN_MODE_2WIRE 0x0 30 #define LGM_PWM_FAN_MODE_MSK BIT(1) 31 #define LGM_PWM_FAN_DC_MSK GENMASK(23, 16) 32 33 #define LGM_PWM_FAN_CON1 0x4 34 #define LGM_PWM_FAN_MAX_RPM_MSK GENMASK(15, 0) 35 36 #define LGM_PWM_MAX_RPM (BIT(16) - 1) 37 #define LGM_PWM_DEFAULT_RPM 4000 38 #define LGM_PWM_MAX_DUTY_CYCLE (BIT(8) - 1) 39 40 #define LGM_PWM_DC_BITS 8 41 42 #define LGM_PWM_PERIOD_2WIRE_NS (40 * NSEC_PER_MSEC) 43 44 struct lgm_pwm_chip { 45 struct pwm_chip chip; 46 struct regmap *regmap; 47 u32 period; 48 }; 49 50 static inline struct lgm_pwm_chip *to_lgm_pwm_chip(struct pwm_chip *chip) 51 { 52 return container_of(chip, struct lgm_pwm_chip, chip); 53 } 54 55 static int lgm_pwm_enable(struct pwm_chip *chip, bool enable) 56 { 57 struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip); 58 struct regmap *regmap = pc->regmap; 59 60 return regmap_update_bits(regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_EN_MSK, 61 enable ? LGM_PWM_FAN_EN_EN : LGM_PWM_FAN_EN_DIS); 62 } 63 64 static int lgm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 65 const struct pwm_state *state) 66 { 67 struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip); 68 u32 duty_cycle, val; 69 int ret; 70 71 /* The hardware only supports normal polarity and fixed period. */ 72 if (state->polarity != PWM_POLARITY_NORMAL || state->period < pc->period) 73 return -EINVAL; 74 75 if (!state->enabled) 76 return lgm_pwm_enable(chip, 0); 77 78 duty_cycle = min_t(u64, state->duty_cycle, pc->period); 79 val = duty_cycle * LGM_PWM_MAX_DUTY_CYCLE / pc->period; 80 81 ret = regmap_update_bits(pc->regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_DC_MSK, 82 FIELD_PREP(LGM_PWM_FAN_DC_MSK, val)); 83 if (ret) 84 return ret; 85 86 return lgm_pwm_enable(chip, 1); 87 } 88 89 static int lgm_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 90 struct pwm_state *state) 91 { 92 struct lgm_pwm_chip *pc = to_lgm_pwm_chip(chip); 93 u32 duty, val; 94 95 state->enabled = regmap_test_bits(pc->regmap, LGM_PWM_FAN_CON0, 96 LGM_PWM_FAN_EN_EN); 97 state->polarity = PWM_POLARITY_NORMAL; 98 state->period = pc->period; /* fixed period */ 99 100 regmap_read(pc->regmap, LGM_PWM_FAN_CON0, &val); 101 duty = FIELD_GET(LGM_PWM_FAN_DC_MSK, val); 102 state->duty_cycle = DIV_ROUND_UP(duty * pc->period, LGM_PWM_MAX_DUTY_CYCLE); 103 104 return 0; 105 } 106 107 static const struct pwm_ops lgm_pwm_ops = { 108 .get_state = lgm_pwm_get_state, 109 .apply = lgm_pwm_apply, 110 }; 111 112 static void lgm_pwm_init(struct lgm_pwm_chip *pc) 113 { 114 struct regmap *regmap = pc->regmap; 115 u32 con0_val; 116 117 con0_val = FIELD_PREP(LGM_PWM_FAN_MODE_MSK, LGM_PWM_FAN_MODE_2WIRE); 118 pc->period = LGM_PWM_PERIOD_2WIRE_NS; 119 regmap_update_bits(regmap, LGM_PWM_FAN_CON1, LGM_PWM_FAN_MAX_RPM_MSK, 120 LGM_PWM_DEFAULT_RPM); 121 regmap_update_bits(regmap, LGM_PWM_FAN_CON0, LGM_PWM_FAN_MODE_MSK, 122 con0_val); 123 } 124 125 static const struct regmap_config lgm_pwm_regmap_config = { 126 .reg_bits = 32, 127 .reg_stride = 4, 128 .val_bits = 32, 129 }; 130 131 static void lgm_clk_release(void *data) 132 { 133 struct clk *clk = data; 134 135 clk_disable_unprepare(clk); 136 } 137 138 static int lgm_clk_enable(struct device *dev, struct clk *clk) 139 { 140 int ret; 141 142 ret = clk_prepare_enable(clk); 143 if (ret) 144 return ret; 145 146 return devm_add_action_or_reset(dev, lgm_clk_release, clk); 147 } 148 149 static void lgm_reset_control_release(void *data) 150 { 151 struct reset_control *rst = data; 152 153 reset_control_assert(rst); 154 } 155 156 static int lgm_reset_control_deassert(struct device *dev, struct reset_control *rst) 157 { 158 int ret; 159 160 ret = reset_control_deassert(rst); 161 if (ret) 162 return ret; 163 164 return devm_add_action_or_reset(dev, lgm_reset_control_release, rst); 165 } 166 167 static int lgm_pwm_probe(struct platform_device *pdev) 168 { 169 struct device *dev = &pdev->dev; 170 struct reset_control *rst; 171 struct lgm_pwm_chip *pc; 172 void __iomem *io_base; 173 struct clk *clk; 174 int ret; 175 176 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL); 177 if (!pc) 178 return -ENOMEM; 179 180 io_base = devm_platform_ioremap_resource(pdev, 0); 181 if (IS_ERR(io_base)) 182 return PTR_ERR(io_base); 183 184 pc->regmap = devm_regmap_init_mmio(dev, io_base, &lgm_pwm_regmap_config); 185 if (IS_ERR(pc->regmap)) 186 return dev_err_probe(dev, PTR_ERR(pc->regmap), 187 "failed to init register map\n"); 188 189 clk = devm_clk_get(dev, NULL); 190 if (IS_ERR(clk)) 191 return dev_err_probe(dev, PTR_ERR(clk), "failed to get clock\n"); 192 193 ret = lgm_clk_enable(dev, clk); 194 if (ret) 195 return dev_err_probe(dev, ret, "failed to enable clock\n"); 196 197 rst = devm_reset_control_get_exclusive(dev, NULL); 198 if (IS_ERR(rst)) 199 return dev_err_probe(dev, PTR_ERR(rst), 200 "failed to get reset control\n"); 201 202 ret = lgm_reset_control_deassert(dev, rst); 203 if (ret) 204 return dev_err_probe(dev, ret, "cannot deassert reset control\n"); 205 206 pc->chip.dev = dev; 207 pc->chip.ops = &lgm_pwm_ops; 208 pc->chip.npwm = 1; 209 210 lgm_pwm_init(pc); 211 212 ret = devm_pwmchip_add(dev, &pc->chip); 213 if (ret < 0) 214 return dev_err_probe(dev, ret, "failed to add PWM chip\n"); 215 216 return 0; 217 } 218 219 static const struct of_device_id lgm_pwm_of_match[] = { 220 { .compatible = "intel,lgm-pwm" }, 221 { } 222 }; 223 MODULE_DEVICE_TABLE(of, lgm_pwm_of_match); 224 225 static struct platform_driver lgm_pwm_driver = { 226 .driver = { 227 .name = "intel-pwm", 228 .of_match_table = lgm_pwm_of_match, 229 }, 230 .probe = lgm_pwm_probe, 231 }; 232 module_platform_driver(lgm_pwm_driver); 233 234 MODULE_LICENSE("GPL v2"); 235