1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * PWM driver for Rockchip SoCs 4 * 5 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> 6 * Copyright (C) 2014 ROCKCHIP, Inc. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_device.h> 14 #include <linux/platform_device.h> 15 #include <linux/pwm.h> 16 #include <linux/time.h> 17 18 #define PWM_CTRL_TIMER_EN (1 << 0) 19 #define PWM_CTRL_OUTPUT_EN (1 << 3) 20 21 #define PWM_ENABLE (1 << 0) 22 #define PWM_CONTINUOUS (1 << 1) 23 #define PWM_DUTY_POSITIVE (1 << 3) 24 #define PWM_DUTY_NEGATIVE (0 << 3) 25 #define PWM_INACTIVE_NEGATIVE (0 << 4) 26 #define PWM_INACTIVE_POSITIVE (1 << 4) 27 #define PWM_POLARITY_MASK (PWM_DUTY_POSITIVE | PWM_INACTIVE_POSITIVE) 28 #define PWM_OUTPUT_LEFT (0 << 5) 29 #define PWM_LOCK_EN (1 << 6) 30 #define PWM_LP_DISABLE (0 << 8) 31 32 struct rockchip_pwm_chip { 33 struct pwm_chip chip; 34 struct clk *clk; 35 struct clk *pclk; 36 const struct rockchip_pwm_data *data; 37 void __iomem *base; 38 }; 39 40 struct rockchip_pwm_regs { 41 unsigned long duty; 42 unsigned long period; 43 unsigned long cntr; 44 unsigned long ctrl; 45 }; 46 47 struct rockchip_pwm_data { 48 struct rockchip_pwm_regs regs; 49 unsigned int prescaler; 50 bool supports_polarity; 51 bool supports_lock; 52 u32 enable_conf; 53 }; 54 55 static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c) 56 { 57 return container_of(c, struct rockchip_pwm_chip, chip); 58 } 59 60 static void rockchip_pwm_get_state(struct pwm_chip *chip, 61 struct pwm_device *pwm, 62 struct pwm_state *state) 63 { 64 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 65 u32 enable_conf = pc->data->enable_conf; 66 unsigned long clk_rate; 67 u64 tmp; 68 u32 val; 69 int ret; 70 71 ret = clk_enable(pc->pclk); 72 if (ret) 73 return; 74 75 ret = clk_enable(pc->clk); 76 if (ret) 77 return; 78 79 clk_rate = clk_get_rate(pc->clk); 80 81 tmp = readl_relaxed(pc->base + pc->data->regs.period); 82 tmp *= pc->data->prescaler * NSEC_PER_SEC; 83 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); 84 85 tmp = readl_relaxed(pc->base + pc->data->regs.duty); 86 tmp *= pc->data->prescaler * NSEC_PER_SEC; 87 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); 88 89 val = readl_relaxed(pc->base + pc->data->regs.ctrl); 90 state->enabled = (val & enable_conf) == enable_conf; 91 92 if (pc->data->supports_polarity && !(val & PWM_DUTY_POSITIVE)) 93 state->polarity = PWM_POLARITY_INVERSED; 94 else 95 state->polarity = PWM_POLARITY_NORMAL; 96 97 clk_disable(pc->clk); 98 clk_disable(pc->pclk); 99 } 100 101 static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 102 const struct pwm_state *state) 103 { 104 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 105 unsigned long period, duty; 106 u64 clk_rate, div; 107 u32 ctrl; 108 109 clk_rate = clk_get_rate(pc->clk); 110 111 /* 112 * Since period and duty cycle registers have a width of 32 113 * bits, every possible input period can be obtained using the 114 * default prescaler value for all practical clock rate values. 115 */ 116 div = clk_rate * state->period; 117 period = DIV_ROUND_CLOSEST_ULL(div, 118 pc->data->prescaler * NSEC_PER_SEC); 119 120 div = clk_rate * state->duty_cycle; 121 duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC); 122 123 /* 124 * Lock the period and duty of previous configuration, then 125 * change the duty and period, that would not be effective. 126 */ 127 ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl); 128 if (pc->data->supports_lock) { 129 ctrl |= PWM_LOCK_EN; 130 writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl); 131 } 132 133 writel(period, pc->base + pc->data->regs.period); 134 writel(duty, pc->base + pc->data->regs.duty); 135 136 if (pc->data->supports_polarity) { 137 ctrl &= ~PWM_POLARITY_MASK; 138 if (state->polarity == PWM_POLARITY_INVERSED) 139 ctrl |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE; 140 else 141 ctrl |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE; 142 } 143 144 /* 145 * Unlock and set polarity at the same time, 146 * the configuration of duty, period and polarity 147 * would be effective together at next period. 148 */ 149 if (pc->data->supports_lock) 150 ctrl &= ~PWM_LOCK_EN; 151 152 writel(ctrl, pc->base + pc->data->regs.ctrl); 153 } 154 155 static int rockchip_pwm_enable(struct pwm_chip *chip, 156 struct pwm_device *pwm, 157 bool enable) 158 { 159 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 160 u32 enable_conf = pc->data->enable_conf; 161 int ret; 162 u32 val; 163 164 if (enable) { 165 ret = clk_enable(pc->clk); 166 if (ret) 167 return ret; 168 } 169 170 val = readl_relaxed(pc->base + pc->data->regs.ctrl); 171 172 if (enable) 173 val |= enable_conf; 174 else 175 val &= ~enable_conf; 176 177 writel_relaxed(val, pc->base + pc->data->regs.ctrl); 178 179 if (!enable) 180 clk_disable(pc->clk); 181 182 return 0; 183 } 184 185 static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 186 const struct pwm_state *state) 187 { 188 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 189 struct pwm_state curstate; 190 bool enabled; 191 int ret = 0; 192 193 ret = clk_enable(pc->pclk); 194 if (ret) 195 return ret; 196 197 ret = clk_enable(pc->clk); 198 if (ret) 199 return ret; 200 201 pwm_get_state(pwm, &curstate); 202 enabled = curstate.enabled; 203 204 if (state->polarity != curstate.polarity && enabled && 205 !pc->data->supports_lock) { 206 ret = rockchip_pwm_enable(chip, pwm, false); 207 if (ret) 208 goto out; 209 enabled = false; 210 } 211 212 rockchip_pwm_config(chip, pwm, state); 213 if (state->enabled != enabled) { 214 ret = rockchip_pwm_enable(chip, pwm, state->enabled); 215 if (ret) 216 goto out; 217 } 218 219 out: 220 clk_disable(pc->clk); 221 clk_disable(pc->pclk); 222 223 return ret; 224 } 225 226 static const struct pwm_ops rockchip_pwm_ops = { 227 .get_state = rockchip_pwm_get_state, 228 .apply = rockchip_pwm_apply, 229 .owner = THIS_MODULE, 230 }; 231 232 static const struct rockchip_pwm_data pwm_data_v1 = { 233 .regs = { 234 .duty = 0x04, 235 .period = 0x08, 236 .cntr = 0x00, 237 .ctrl = 0x0c, 238 }, 239 .prescaler = 2, 240 .supports_polarity = false, 241 .supports_lock = false, 242 .enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN, 243 }; 244 245 static const struct rockchip_pwm_data pwm_data_v2 = { 246 .regs = { 247 .duty = 0x08, 248 .period = 0x04, 249 .cntr = 0x00, 250 .ctrl = 0x0c, 251 }, 252 .prescaler = 1, 253 .supports_polarity = true, 254 .supports_lock = false, 255 .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | 256 PWM_CONTINUOUS, 257 }; 258 259 static const struct rockchip_pwm_data pwm_data_vop = { 260 .regs = { 261 .duty = 0x08, 262 .period = 0x04, 263 .cntr = 0x0c, 264 .ctrl = 0x00, 265 }, 266 .prescaler = 1, 267 .supports_polarity = true, 268 .supports_lock = false, 269 .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | 270 PWM_CONTINUOUS, 271 }; 272 273 static const struct rockchip_pwm_data pwm_data_v3 = { 274 .regs = { 275 .duty = 0x08, 276 .period = 0x04, 277 .cntr = 0x00, 278 .ctrl = 0x0c, 279 }, 280 .prescaler = 1, 281 .supports_polarity = true, 282 .supports_lock = true, 283 .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | 284 PWM_CONTINUOUS, 285 }; 286 287 static const struct of_device_id rockchip_pwm_dt_ids[] = { 288 { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1}, 289 { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2}, 290 { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop}, 291 { .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3}, 292 { /* sentinel */ } 293 }; 294 MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids); 295 296 static int rockchip_pwm_probe(struct platform_device *pdev) 297 { 298 const struct of_device_id *id; 299 struct rockchip_pwm_chip *pc; 300 u32 enable_conf, ctrl; 301 bool enabled; 302 int ret, count; 303 304 id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev); 305 if (!id) 306 return -EINVAL; 307 308 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); 309 if (!pc) 310 return -ENOMEM; 311 312 pc->base = devm_platform_ioremap_resource(pdev, 0); 313 if (IS_ERR(pc->base)) 314 return PTR_ERR(pc->base); 315 316 pc->clk = devm_clk_get(&pdev->dev, "pwm"); 317 if (IS_ERR(pc->clk)) { 318 pc->clk = devm_clk_get(&pdev->dev, NULL); 319 if (IS_ERR(pc->clk)) 320 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk), 321 "Can't get PWM clk\n"); 322 } 323 324 count = of_count_phandle_with_args(pdev->dev.of_node, 325 "clocks", "#clock-cells"); 326 if (count == 2) 327 pc->pclk = devm_clk_get(&pdev->dev, "pclk"); 328 else 329 pc->pclk = pc->clk; 330 331 if (IS_ERR(pc->pclk)) 332 return dev_err_probe(&pdev->dev, PTR_ERR(pc->pclk), "Can't get APB clk\n"); 333 334 ret = clk_prepare_enable(pc->clk); 335 if (ret) 336 return dev_err_probe(&pdev->dev, ret, "Can't prepare enable PWM clk\n"); 337 338 ret = clk_prepare_enable(pc->pclk); 339 if (ret) { 340 dev_err_probe(&pdev->dev, ret, "Can't prepare enable APB clk\n"); 341 goto err_clk; 342 } 343 344 platform_set_drvdata(pdev, pc); 345 346 pc->data = id->data; 347 pc->chip.dev = &pdev->dev; 348 pc->chip.ops = &rockchip_pwm_ops; 349 pc->chip.npwm = 1; 350 351 enable_conf = pc->data->enable_conf; 352 ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl); 353 enabled = (ctrl & enable_conf) == enable_conf; 354 355 ret = pwmchip_add(&pc->chip); 356 if (ret < 0) { 357 dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n"); 358 goto err_pclk; 359 } 360 361 /* Keep the PWM clk enabled if the PWM appears to be up and running. */ 362 if (!enabled) 363 clk_disable(pc->clk); 364 365 clk_disable(pc->pclk); 366 367 return 0; 368 369 err_pclk: 370 clk_disable_unprepare(pc->pclk); 371 err_clk: 372 clk_disable_unprepare(pc->clk); 373 374 return ret; 375 } 376 377 static int rockchip_pwm_remove(struct platform_device *pdev) 378 { 379 struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev); 380 381 pwmchip_remove(&pc->chip); 382 383 clk_unprepare(pc->pclk); 384 clk_unprepare(pc->clk); 385 386 return 0; 387 } 388 389 static struct platform_driver rockchip_pwm_driver = { 390 .driver = { 391 .name = "rockchip-pwm", 392 .of_match_table = rockchip_pwm_dt_ids, 393 }, 394 .probe = rockchip_pwm_probe, 395 .remove = rockchip_pwm_remove, 396 }; 397 module_platform_driver(rockchip_pwm_driver); 398 399 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>"); 400 MODULE_DESCRIPTION("Rockchip SoC PWM driver"); 401 MODULE_LICENSE("GPL v2"); 402