1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright 2021 NXP */ 3 4 #include <dt-bindings/firmware/imx/rsrc.h> 5 #include <linux/arm-smccc.h> 6 #include <linux/clk.h> 7 #include <linux/err.h> 8 #include <linux/firmware.h> 9 #include <linux/firmware/imx/sci.h> 10 #include <linux/interrupt.h> 11 #include <linux/kernel.h> 12 #include <linux/mailbox_client.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_reserved_mem.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_domain.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/regmap.h> 21 #include <linux/remoteproc.h> 22 #include <linux/slab.h> 23 24 #include "imx_rproc.h" 25 #include "remoteproc_elf_helpers.h" 26 #include "remoteproc_internal.h" 27 28 #define DSP_RPROC_CLK_MAX 5 29 30 /* 31 * Module parameters 32 */ 33 static unsigned int no_mailboxes; 34 module_param_named(no_mailboxes, no_mailboxes, int, 0644); 35 MODULE_PARM_DESC(no_mailboxes, 36 "There is no mailbox between cores, so ignore remote proc reply after start, default is 0 (off)."); 37 38 #define REMOTE_IS_READY BIT(0) 39 #define REMOTE_READY_WAIT_MAX_RETRIES 500 40 41 /* att flags */ 42 /* DSP own area */ 43 #define ATT_OWN BIT(31) 44 /* DSP instruction area */ 45 #define ATT_IRAM BIT(30) 46 47 /* Definitions for i.MX8MP */ 48 /* DAP registers */ 49 #define IMX8M_DAP_DEBUG 0x28800000 50 #define IMX8M_DAP_DEBUG_SIZE (64 * 1024) 51 #define IMX8M_DAP_PWRCTL (0x4000 + 0x3020) 52 #define IMX8M_PWRCTL_CORERESET BIT(16) 53 54 /* DSP audio mix registers */ 55 #define IMX8M_AudioDSP_REG0 0x100 56 #define IMX8M_AudioDSP_REG1 0x104 57 #define IMX8M_AudioDSP_REG2 0x108 58 #define IMX8M_AudioDSP_REG3 0x10c 59 60 #define IMX8M_AudioDSP_REG2_RUNSTALL BIT(5) 61 #define IMX8M_AudioDSP_REG2_PWAITMODE BIT(1) 62 63 /* Definitions for i.MX8ULP */ 64 #define IMX8ULP_SIM_LPAV_REG_SYSCTRL0 0x8 65 #define IMX8ULP_SYSCTRL0_DSP_DBG_RST BIT(25) 66 #define IMX8ULP_SYSCTRL0_DSP_PLAT_CLK_EN BIT(19) 67 #define IMX8ULP_SYSCTRL0_DSP_PBCLK_EN BIT(18) 68 #define IMX8ULP_SYSCTRL0_DSP_CLK_EN BIT(17) 69 #define IMX8ULP_SYSCTRL0_DSP_RST BIT(16) 70 #define IMX8ULP_SYSCTRL0_DSP_OCD_HALT BIT(14) 71 #define IMX8ULP_SYSCTRL0_DSP_STALL BIT(13) 72 73 #define IMX8ULP_SIP_HIFI_XRDC 0xc200000e 74 75 /* 76 * enum - Predefined Mailbox Messages 77 * 78 * @RP_MBOX_SUSPEND_SYSTEM: system suspend request for the remote processor 79 * 80 * @RP_MBOX_SUSPEND_ACK: successful response from remote processor for a 81 * suspend request 82 * 83 * @RP_MBOX_RESUME_SYSTEM: system resume request for the remote processor 84 * 85 * @RP_MBOX_RESUME_ACK: successful response from remote processor for a 86 * resume request 87 */ 88 enum imx_dsp_rp_mbox_messages { 89 RP_MBOX_SUSPEND_SYSTEM = 0xFF11, 90 RP_MBOX_SUSPEND_ACK = 0xFF12, 91 RP_MBOX_RESUME_SYSTEM = 0xFF13, 92 RP_MBOX_RESUME_ACK = 0xFF14, 93 }; 94 95 /** 96 * struct imx_dsp_rproc - DSP remote processor state 97 * @regmap: regmap handler 98 * @rproc: rproc handler 99 * @dsp_dcfg: device configuration pointer 100 * @clks: clocks needed by this device 101 * @cl: mailbox client to request the mailbox channel 102 * @cl_rxdb: mailbox client to request the mailbox channel for doorbell 103 * @tx_ch: mailbox tx channel handle 104 * @rx_ch: mailbox rx channel handle 105 * @rxdb_ch: mailbox rx doorbell channel handle 106 * @pd_dev: power domain device 107 * @pd_dev_link: power domain device link 108 * @ipc_handle: System Control Unit ipc handle 109 * @rproc_work: work for processing virtio interrupts 110 * @pm_comp: completion primitive to sync for suspend response 111 * @num_domains: power domain number 112 * @flags: control flags 113 */ 114 struct imx_dsp_rproc { 115 struct regmap *regmap; 116 struct rproc *rproc; 117 const struct imx_dsp_rproc_dcfg *dsp_dcfg; 118 struct clk_bulk_data clks[DSP_RPROC_CLK_MAX]; 119 struct mbox_client cl; 120 struct mbox_client cl_rxdb; 121 struct mbox_chan *tx_ch; 122 struct mbox_chan *rx_ch; 123 struct mbox_chan *rxdb_ch; 124 struct device **pd_dev; 125 struct device_link **pd_dev_link; 126 struct imx_sc_ipc *ipc_handle; 127 struct work_struct rproc_work; 128 struct completion pm_comp; 129 int num_domains; 130 u32 flags; 131 }; 132 133 /** 134 * struct imx_dsp_rproc_dcfg - DSP remote processor configuration 135 * @dcfg: imx_rproc_dcfg handler 136 * @reset: reset callback function 137 */ 138 struct imx_dsp_rproc_dcfg { 139 const struct imx_rproc_dcfg *dcfg; 140 int (*reset)(struct imx_dsp_rproc *priv); 141 }; 142 143 static const struct imx_rproc_att imx_dsp_rproc_att_imx8qm[] = { 144 /* dev addr , sys addr , size , flags */ 145 { 0x596e8000, 0x556e8000, 0x00008000, ATT_OWN }, 146 { 0x596f0000, 0x556f0000, 0x00008000, ATT_OWN }, 147 { 0x596f8000, 0x556f8000, 0x00000800, ATT_OWN | ATT_IRAM}, 148 { 0x55700000, 0x55700000, 0x00070000, ATT_OWN }, 149 /* DDR (Data) */ 150 { 0x80000000, 0x80000000, 0x60000000, 0}, 151 }; 152 153 static const struct imx_rproc_att imx_dsp_rproc_att_imx8qxp[] = { 154 /* dev addr , sys addr , size , flags */ 155 { 0x596e8000, 0x596e8000, 0x00008000, ATT_OWN }, 156 { 0x596f0000, 0x596f0000, 0x00008000, ATT_OWN }, 157 { 0x596f8000, 0x596f8000, 0x00000800, ATT_OWN | ATT_IRAM}, 158 { 0x59700000, 0x59700000, 0x00070000, ATT_OWN }, 159 /* DDR (Data) */ 160 { 0x80000000, 0x80000000, 0x60000000, 0}, 161 }; 162 163 static const struct imx_rproc_att imx_dsp_rproc_att_imx8mp[] = { 164 /* dev addr , sys addr , size , flags */ 165 { 0x3b6e8000, 0x3b6e8000, 0x00008000, ATT_OWN }, 166 { 0x3b6f0000, 0x3b6f0000, 0x00008000, ATT_OWN }, 167 { 0x3b6f8000, 0x3b6f8000, 0x00000800, ATT_OWN | ATT_IRAM}, 168 { 0x3b700000, 0x3b700000, 0x00040000, ATT_OWN }, 169 /* DDR (Data) */ 170 { 0x40000000, 0x40000000, 0x80000000, 0}, 171 }; 172 173 static const struct imx_rproc_att imx_dsp_rproc_att_imx8ulp[] = { 174 /* dev addr , sys addr , size , flags */ 175 { 0x21170000, 0x21170000, 0x00010000, ATT_OWN | ATT_IRAM}, 176 { 0x21180000, 0x21180000, 0x00010000, ATT_OWN }, 177 /* DDR (Data) */ 178 { 0x0c000000, 0x80000000, 0x10000000, 0}, 179 { 0x30000000, 0x90000000, 0x10000000, 0}, 180 }; 181 182 /* Initialize the mailboxes between cores, if exists */ 183 static int (*imx_dsp_rproc_mbox_init)(struct imx_dsp_rproc *priv); 184 185 /* Reset function for DSP on i.MX8MP */ 186 static int imx8mp_dsp_reset(struct imx_dsp_rproc *priv) 187 { 188 void __iomem *dap = ioremap_wc(IMX8M_DAP_DEBUG, IMX8M_DAP_DEBUG_SIZE); 189 int pwrctl; 190 191 /* Put DSP into reset and stall */ 192 pwrctl = readl(dap + IMX8M_DAP_PWRCTL); 193 pwrctl |= IMX8M_PWRCTL_CORERESET; 194 writel(pwrctl, dap + IMX8M_DAP_PWRCTL); 195 196 /* Keep reset asserted for 10 cycles */ 197 usleep_range(1, 2); 198 199 regmap_update_bits(priv->regmap, IMX8M_AudioDSP_REG2, 200 IMX8M_AudioDSP_REG2_RUNSTALL, 201 IMX8M_AudioDSP_REG2_RUNSTALL); 202 203 /* Take the DSP out of reset and keep stalled for FW loading */ 204 pwrctl = readl(dap + IMX8M_DAP_PWRCTL); 205 pwrctl &= ~IMX8M_PWRCTL_CORERESET; 206 writel(pwrctl, dap + IMX8M_DAP_PWRCTL); 207 208 iounmap(dap); 209 return 0; 210 } 211 212 /* Reset function for DSP on i.MX8ULP */ 213 static int imx8ulp_dsp_reset(struct imx_dsp_rproc *priv) 214 { 215 struct arm_smccc_res res; 216 217 /* Put DSP into reset and stall */ 218 regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0, 219 IMX8ULP_SYSCTRL0_DSP_RST, IMX8ULP_SYSCTRL0_DSP_RST); 220 regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0, 221 IMX8ULP_SYSCTRL0_DSP_STALL, 222 IMX8ULP_SYSCTRL0_DSP_STALL); 223 224 /* Configure resources of DSP through TFA */ 225 arm_smccc_smc(IMX8ULP_SIP_HIFI_XRDC, 0, 0, 0, 0, 0, 0, 0, &res); 226 227 /* Take the DSP out of reset and keep stalled for FW loading */ 228 regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0, 229 IMX8ULP_SYSCTRL0_DSP_RST, 0); 230 regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0, 231 IMX8ULP_SYSCTRL0_DSP_DBG_RST, 0); 232 233 return 0; 234 } 235 236 /* Specific configuration for i.MX8MP */ 237 static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8mp = { 238 .src_reg = IMX8M_AudioDSP_REG2, 239 .src_mask = IMX8M_AudioDSP_REG2_RUNSTALL, 240 .src_start = 0, 241 .src_stop = IMX8M_AudioDSP_REG2_RUNSTALL, 242 .att = imx_dsp_rproc_att_imx8mp, 243 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8mp), 244 .method = IMX_RPROC_MMIO, 245 }; 246 247 static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8mp = { 248 .dcfg = &dsp_rproc_cfg_imx8mp, 249 .reset = imx8mp_dsp_reset, 250 }; 251 252 /* Specific configuration for i.MX8ULP */ 253 static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8ulp = { 254 .src_reg = IMX8ULP_SIM_LPAV_REG_SYSCTRL0, 255 .src_mask = IMX8ULP_SYSCTRL0_DSP_STALL, 256 .src_start = 0, 257 .src_stop = IMX8ULP_SYSCTRL0_DSP_STALL, 258 .att = imx_dsp_rproc_att_imx8ulp, 259 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8ulp), 260 .method = IMX_RPROC_MMIO, 261 }; 262 263 static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8ulp = { 264 .dcfg = &dsp_rproc_cfg_imx8ulp, 265 .reset = imx8ulp_dsp_reset, 266 }; 267 268 /* Specific configuration for i.MX8QXP */ 269 static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8qxp = { 270 .att = imx_dsp_rproc_att_imx8qxp, 271 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8qxp), 272 .method = IMX_RPROC_SCU_API, 273 }; 274 275 static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8qxp = { 276 .dcfg = &dsp_rproc_cfg_imx8qxp, 277 }; 278 279 /* Specific configuration for i.MX8QM */ 280 static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8qm = { 281 .att = imx_dsp_rproc_att_imx8qm, 282 .att_size = ARRAY_SIZE(imx_dsp_rproc_att_imx8qm), 283 .method = IMX_RPROC_SCU_API, 284 }; 285 286 static const struct imx_dsp_rproc_dcfg imx_dsp_rproc_cfg_imx8qm = { 287 .dcfg = &dsp_rproc_cfg_imx8qm, 288 }; 289 290 static int imx_dsp_rproc_ready(struct rproc *rproc) 291 { 292 struct imx_dsp_rproc *priv = rproc->priv; 293 int i; 294 295 if (!priv->rxdb_ch) 296 return 0; 297 298 for (i = 0; i < REMOTE_READY_WAIT_MAX_RETRIES; i++) { 299 if (priv->flags & REMOTE_IS_READY) 300 return 0; 301 usleep_range(100, 200); 302 } 303 304 return -ETIMEDOUT; 305 } 306 307 /* 308 * Start function for rproc_ops 309 * 310 * There is a handshake for start procedure: when DSP starts, it 311 * will send a doorbell message to this driver, then the 312 * REMOTE_IS_READY flags is set, then driver will kick 313 * a message to DSP. 314 */ 315 static int imx_dsp_rproc_start(struct rproc *rproc) 316 { 317 struct imx_dsp_rproc *priv = rproc->priv; 318 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg; 319 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg; 320 struct device *dev = rproc->dev.parent; 321 int ret; 322 323 switch (dcfg->method) { 324 case IMX_RPROC_MMIO: 325 ret = regmap_update_bits(priv->regmap, 326 dcfg->src_reg, 327 dcfg->src_mask, 328 dcfg->src_start); 329 break; 330 case IMX_RPROC_SCU_API: 331 ret = imx_sc_pm_cpu_start(priv->ipc_handle, 332 IMX_SC_R_DSP, 333 true, 334 rproc->bootaddr); 335 break; 336 default: 337 return -EOPNOTSUPP; 338 } 339 340 if (ret) 341 dev_err(dev, "Failed to enable remote core!\n"); 342 else 343 ret = imx_dsp_rproc_ready(rproc); 344 345 return ret; 346 } 347 348 /* 349 * Stop function for rproc_ops 350 * It clears the REMOTE_IS_READY flags 351 */ 352 static int imx_dsp_rproc_stop(struct rproc *rproc) 353 { 354 struct imx_dsp_rproc *priv = rproc->priv; 355 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg; 356 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg; 357 struct device *dev = rproc->dev.parent; 358 int ret = 0; 359 360 if (rproc->state == RPROC_CRASHED) { 361 priv->flags &= ~REMOTE_IS_READY; 362 return 0; 363 } 364 365 switch (dcfg->method) { 366 case IMX_RPROC_MMIO: 367 ret = regmap_update_bits(priv->regmap, dcfg->src_reg, dcfg->src_mask, 368 dcfg->src_stop); 369 break; 370 case IMX_RPROC_SCU_API: 371 ret = imx_sc_pm_cpu_start(priv->ipc_handle, 372 IMX_SC_R_DSP, 373 false, 374 rproc->bootaddr); 375 break; 376 default: 377 return -EOPNOTSUPP; 378 } 379 380 if (ret) 381 dev_err(dev, "Failed to stop remote core\n"); 382 else 383 priv->flags &= ~REMOTE_IS_READY; 384 385 return ret; 386 } 387 388 /** 389 * imx_dsp_rproc_sys_to_da() - internal memory translation helper 390 * @priv: private data pointer 391 * @sys: system address (DDR address) 392 * @len: length of the memory buffer 393 * @da: device address to translate 394 * 395 * Convert system address (DDR address) to device address (DSP) 396 * for there may be memory remap for device. 397 */ 398 static int imx_dsp_rproc_sys_to_da(struct imx_dsp_rproc *priv, u64 sys, 399 size_t len, u64 *da) 400 { 401 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg; 402 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg; 403 int i; 404 405 /* Parse address translation table */ 406 for (i = 0; i < dcfg->att_size; i++) { 407 const struct imx_rproc_att *att = &dcfg->att[i]; 408 409 if (sys >= att->sa && sys + len <= att->sa + att->size) { 410 unsigned int offset = sys - att->sa; 411 412 *da = att->da + offset; 413 return 0; 414 } 415 } 416 417 return -ENOENT; 418 } 419 420 /* Main virtqueue message work function 421 * 422 * This function is executed upon scheduling of the i.MX DSP remoteproc 423 * driver's workqueue. The workqueue is scheduled by the mailbox rx 424 * handler. 425 * 426 * This work function processes both the Tx and Rx virtqueue indices on 427 * every invocation. The rproc_vq_interrupt function can detect if there 428 * are new unprocessed messages or not (returns IRQ_NONE vs IRQ_HANDLED), 429 * but there is no need to check for these return values. The index 0 430 * triggering will process all pending Rx buffers, and the index 1 triggering 431 * will process all newly available Tx buffers and will wakeup any potentially 432 * blocked senders. 433 * 434 * NOTE: 435 * The current logic is based on an inherent design assumption of supporting 436 * only 2 vrings, but this can be changed if needed. 437 */ 438 static void imx_dsp_rproc_vq_work(struct work_struct *work) 439 { 440 struct imx_dsp_rproc *priv = container_of(work, struct imx_dsp_rproc, 441 rproc_work); 442 struct rproc *rproc = priv->rproc; 443 444 mutex_lock(&rproc->lock); 445 446 if (rproc->state != RPROC_RUNNING) 447 goto unlock_mutex; 448 449 rproc_vq_interrupt(priv->rproc, 0); 450 rproc_vq_interrupt(priv->rproc, 1); 451 452 unlock_mutex: 453 mutex_unlock(&rproc->lock); 454 } 455 456 /** 457 * imx_dsp_rproc_rx_tx_callback() - inbound mailbox message handler 458 * @cl: mailbox client pointer used for requesting the mailbox channel 459 * @data: mailbox payload 460 * 461 * This handler is invoked by mailbox driver whenever a mailbox 462 * message is received. Usually, the SUSPEND and RESUME related messages 463 * are handled in this function, other messages are handled by remoteproc core 464 */ 465 static void imx_dsp_rproc_rx_tx_callback(struct mbox_client *cl, void *data) 466 { 467 struct rproc *rproc = dev_get_drvdata(cl->dev); 468 struct imx_dsp_rproc *priv = rproc->priv; 469 struct device *dev = rproc->dev.parent; 470 u32 message = (u32)(*(u32 *)data); 471 472 dev_dbg(dev, "mbox msg: 0x%x\n", message); 473 474 switch (message) { 475 case RP_MBOX_SUSPEND_ACK: 476 complete(&priv->pm_comp); 477 break; 478 case RP_MBOX_RESUME_ACK: 479 complete(&priv->pm_comp); 480 break; 481 default: 482 schedule_work(&priv->rproc_work); 483 break; 484 } 485 } 486 487 /** 488 * imx_dsp_rproc_rxdb_callback() - inbound mailbox message handler 489 * @cl: mailbox client pointer used for requesting the mailbox channel 490 * @data: mailbox payload 491 * 492 * For doorbell, there is no message specified, just set REMOTE_IS_READY 493 * flag. 494 */ 495 static void imx_dsp_rproc_rxdb_callback(struct mbox_client *cl, void *data) 496 { 497 struct rproc *rproc = dev_get_drvdata(cl->dev); 498 struct imx_dsp_rproc *priv = rproc->priv; 499 500 /* Remote is ready after firmware is loaded and running */ 501 priv->flags |= REMOTE_IS_READY; 502 } 503 504 /** 505 * imx_dsp_rproc_mbox_alloc() - request mailbox channels 506 * @priv: private data pointer 507 * 508 * Request three mailbox channels (tx, rx, rxdb). 509 */ 510 static int imx_dsp_rproc_mbox_alloc(struct imx_dsp_rproc *priv) 511 { 512 struct device *dev = priv->rproc->dev.parent; 513 struct mbox_client *cl; 514 int ret; 515 516 if (!of_get_property(dev->of_node, "mbox-names", NULL)) 517 return 0; 518 519 cl = &priv->cl; 520 cl->dev = dev; 521 cl->tx_block = true; 522 cl->tx_tout = 100; 523 cl->knows_txdone = false; 524 cl->rx_callback = imx_dsp_rproc_rx_tx_callback; 525 526 /* Channel for sending message */ 527 priv->tx_ch = mbox_request_channel_byname(cl, "tx"); 528 if (IS_ERR(priv->tx_ch)) { 529 ret = PTR_ERR(priv->tx_ch); 530 dev_dbg(cl->dev, "failed to request tx mailbox channel: %d\n", 531 ret); 532 return ret; 533 } 534 535 /* Channel for receiving message */ 536 priv->rx_ch = mbox_request_channel_byname(cl, "rx"); 537 if (IS_ERR(priv->rx_ch)) { 538 ret = PTR_ERR(priv->rx_ch); 539 dev_dbg(cl->dev, "failed to request rx mailbox channel: %d\n", 540 ret); 541 goto free_channel_tx; 542 } 543 544 cl = &priv->cl_rxdb; 545 cl->dev = dev; 546 cl->rx_callback = imx_dsp_rproc_rxdb_callback; 547 548 /* 549 * RX door bell is used to receive the ready signal from remote 550 * after firmware loaded. 551 */ 552 priv->rxdb_ch = mbox_request_channel_byname(cl, "rxdb"); 553 if (IS_ERR(priv->rxdb_ch)) { 554 ret = PTR_ERR(priv->rxdb_ch); 555 dev_dbg(cl->dev, "failed to request mbox chan rxdb, ret %d\n", 556 ret); 557 goto free_channel_rx; 558 } 559 560 return 0; 561 562 free_channel_rx: 563 mbox_free_channel(priv->rx_ch); 564 free_channel_tx: 565 mbox_free_channel(priv->tx_ch); 566 return ret; 567 } 568 569 /* 570 * imx_dsp_rproc_mbox_no_alloc() 571 * 572 * Empty function for no mailbox between cores 573 * 574 * Always return 0 575 */ 576 static int imx_dsp_rproc_mbox_no_alloc(struct imx_dsp_rproc *priv) 577 { 578 return 0; 579 } 580 581 static void imx_dsp_rproc_free_mbox(struct imx_dsp_rproc *priv) 582 { 583 mbox_free_channel(priv->tx_ch); 584 mbox_free_channel(priv->rx_ch); 585 mbox_free_channel(priv->rxdb_ch); 586 } 587 588 /** 589 * imx_dsp_rproc_add_carveout() - request mailbox channels 590 * @priv: private data pointer 591 * 592 * This function registers specified memory entry in @rproc carveouts list 593 * The carveouts can help to mapping the memory address for DSP. 594 */ 595 static int imx_dsp_rproc_add_carveout(struct imx_dsp_rproc *priv) 596 { 597 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg; 598 const struct imx_rproc_dcfg *dcfg = dsp_dcfg->dcfg; 599 struct rproc *rproc = priv->rproc; 600 struct device *dev = rproc->dev.parent; 601 struct device_node *np = dev->of_node; 602 struct of_phandle_iterator it; 603 struct rproc_mem_entry *mem; 604 struct reserved_mem *rmem; 605 void __iomem *cpu_addr; 606 int a; 607 u64 da; 608 609 /* Remap required addresses */ 610 for (a = 0; a < dcfg->att_size; a++) { 611 const struct imx_rproc_att *att = &dcfg->att[a]; 612 613 if (!(att->flags & ATT_OWN)) 614 continue; 615 616 if (imx_dsp_rproc_sys_to_da(priv, att->sa, att->size, &da)) 617 return -EINVAL; 618 619 cpu_addr = devm_ioremap_wc(dev, att->sa, att->size); 620 if (!cpu_addr) { 621 dev_err(dev, "failed to map memory %p\n", &att->sa); 622 return -ENOMEM; 623 } 624 625 /* Register memory region */ 626 mem = rproc_mem_entry_init(dev, (void __force *)cpu_addr, (dma_addr_t)att->sa, 627 att->size, da, NULL, NULL, "dsp_mem"); 628 629 if (mem) 630 rproc_coredump_add_segment(rproc, da, att->size); 631 else 632 return -ENOMEM; 633 634 rproc_add_carveout(rproc, mem); 635 } 636 637 of_phandle_iterator_init(&it, np, "memory-region", NULL, 0); 638 while (of_phandle_iterator_next(&it) == 0) { 639 /* 640 * Ignore the first memory region which will be used vdev buffer. 641 * No need to do extra handlings, rproc_add_virtio_dev will handle it. 642 */ 643 if (!strcmp(it.node->name, "vdev0buffer")) 644 continue; 645 646 rmem = of_reserved_mem_lookup(it.node); 647 if (!rmem) { 648 of_node_put(it.node); 649 dev_err(dev, "unable to acquire memory-region\n"); 650 return -EINVAL; 651 } 652 653 if (imx_dsp_rproc_sys_to_da(priv, rmem->base, rmem->size, &da)) { 654 of_node_put(it.node); 655 return -EINVAL; 656 } 657 658 cpu_addr = devm_ioremap_wc(dev, rmem->base, rmem->size); 659 if (!cpu_addr) { 660 of_node_put(it.node); 661 dev_err(dev, "failed to map memory %p\n", &rmem->base); 662 return -ENOMEM; 663 } 664 665 /* Register memory region */ 666 mem = rproc_mem_entry_init(dev, (void __force *)cpu_addr, (dma_addr_t)rmem->base, 667 rmem->size, da, NULL, NULL, it.node->name); 668 669 if (mem) { 670 rproc_coredump_add_segment(rproc, da, rmem->size); 671 } else { 672 of_node_put(it.node); 673 return -ENOMEM; 674 } 675 676 rproc_add_carveout(rproc, mem); 677 } 678 679 return 0; 680 } 681 682 /* Prepare function for rproc_ops */ 683 static int imx_dsp_rproc_prepare(struct rproc *rproc) 684 { 685 struct imx_dsp_rproc *priv = rproc->priv; 686 struct device *dev = rproc->dev.parent; 687 struct rproc_mem_entry *carveout; 688 int ret; 689 690 ret = imx_dsp_rproc_add_carveout(priv); 691 if (ret) { 692 dev_err(dev, "failed on imx_dsp_rproc_add_carveout\n"); 693 return ret; 694 } 695 696 pm_runtime_get_sync(dev); 697 698 /* 699 * Clear buffers after pm rumtime for internal ocram is not 700 * accessible if power and clock are not enabled. 701 */ 702 list_for_each_entry(carveout, &rproc->carveouts, node) { 703 if (carveout->va) 704 memset(carveout->va, 0, carveout->len); 705 } 706 707 return 0; 708 } 709 710 /* Unprepare function for rproc_ops */ 711 static int imx_dsp_rproc_unprepare(struct rproc *rproc) 712 { 713 pm_runtime_put_sync(rproc->dev.parent); 714 715 return 0; 716 } 717 718 /* Kick function for rproc_ops */ 719 static void imx_dsp_rproc_kick(struct rproc *rproc, int vqid) 720 { 721 struct imx_dsp_rproc *priv = rproc->priv; 722 struct device *dev = rproc->dev.parent; 723 int err; 724 __u32 mmsg; 725 726 if (!priv->tx_ch) { 727 dev_err(dev, "No initialized mbox tx channel\n"); 728 return; 729 } 730 731 /* 732 * Send the index of the triggered virtqueue as the mu payload. 733 * Let remote processor know which virtqueue is used. 734 */ 735 mmsg = vqid; 736 737 err = mbox_send_message(priv->tx_ch, (void *)&mmsg); 738 if (err < 0) 739 dev_err(dev, "%s: failed (%d, err:%d)\n", __func__, vqid, err); 740 } 741 742 /* 743 * Custom memory copy implementation for i.MX DSP Cores 744 * 745 * The IRAM is part of the HiFi DSP. 746 * According to hw specs only 32-bits writes are allowed. 747 */ 748 static int imx_dsp_rproc_memcpy(void *dst, const void *src, size_t size) 749 { 750 void __iomem *dest = (void __iomem *)dst; 751 const u8 *src_byte = src; 752 const u32 *source = src; 753 u32 affected_mask; 754 int i, q, r; 755 u32 tmp; 756 757 /* destination must be 32bit aligned */ 758 if (!IS_ALIGNED((uintptr_t)dest, 4)) 759 return -EINVAL; 760 761 q = size / 4; 762 r = size % 4; 763 764 /* copy data in units of 32 bits at a time */ 765 for (i = 0; i < q; i++) 766 writel(source[i], dest + i * 4); 767 768 if (r) { 769 affected_mask = GENMASK(8 * r, 0); 770 771 /* 772 * first read the 32bit data of dest, then change affected 773 * bytes, and write back to dest. 774 * For unaffected bytes, it should not be changed 775 */ 776 tmp = readl(dest + q * 4); 777 tmp &= ~affected_mask; 778 779 /* avoid reading after end of source */ 780 for (i = 0; i < r; i++) 781 tmp |= (src_byte[q * 4 + i] << (8 * i)); 782 783 writel(tmp, dest + q * 4); 784 } 785 786 return 0; 787 } 788 789 /* 790 * Custom memset implementation for i.MX DSP Cores 791 * 792 * The IRAM is part of the HiFi DSP. 793 * According to hw specs only 32-bits writes are allowed. 794 */ 795 static int imx_dsp_rproc_memset(void *addr, u8 value, size_t size) 796 { 797 void __iomem *tmp_dst = (void __iomem *)addr; 798 u32 tmp_val = value; 799 u32 affected_mask; 800 int q, r; 801 u32 tmp; 802 803 /* destination must be 32bit aligned */ 804 if (!IS_ALIGNED((uintptr_t)addr, 4)) 805 return -EINVAL; 806 807 tmp_val |= tmp_val << 8; 808 tmp_val |= tmp_val << 16; 809 810 q = size / 4; 811 r = size % 4; 812 813 while (q--) 814 writel(tmp_val, tmp_dst++); 815 816 if (r) { 817 affected_mask = GENMASK(8 * r, 0); 818 819 /* 820 * first read the 32bit data of addr, then change affected 821 * bytes, and write back to addr. 822 * For unaffected bytes, it should not be changed 823 */ 824 tmp = readl(tmp_dst); 825 tmp &= ~affected_mask; 826 827 tmp |= (tmp_val & affected_mask); 828 writel(tmp, tmp_dst); 829 } 830 831 return 0; 832 } 833 834 /* 835 * imx_dsp_rproc_elf_load_segments() - load firmware segments to memory 836 * @rproc: remote processor which will be booted using these fw segments 837 * @fw: the ELF firmware image 838 * 839 * This function loads the firmware segments to memory, where the remote 840 * processor expects them. 841 * 842 * Return: 0 on success and an appropriate error code otherwise 843 */ 844 static int imx_dsp_rproc_elf_load_segments(struct rproc *rproc, const struct firmware *fw) 845 { 846 struct device *dev = &rproc->dev; 847 const void *ehdr, *phdr; 848 int i, ret = 0; 849 u16 phnum; 850 const u8 *elf_data = fw->data; 851 u8 class = fw_elf_get_class(fw); 852 u32 elf_phdr_get_size = elf_size_of_phdr(class); 853 854 ehdr = elf_data; 855 phnum = elf_hdr_get_e_phnum(class, ehdr); 856 phdr = elf_data + elf_hdr_get_e_phoff(class, ehdr); 857 858 /* go through the available ELF segments */ 859 for (i = 0; i < phnum; i++, phdr += elf_phdr_get_size) { 860 u64 da = elf_phdr_get_p_paddr(class, phdr); 861 u64 memsz = elf_phdr_get_p_memsz(class, phdr); 862 u64 filesz = elf_phdr_get_p_filesz(class, phdr); 863 u64 offset = elf_phdr_get_p_offset(class, phdr); 864 u32 type = elf_phdr_get_p_type(class, phdr); 865 void *ptr; 866 867 if (type != PT_LOAD || !memsz) 868 continue; 869 870 dev_dbg(dev, "phdr: type %d da 0x%llx memsz 0x%llx filesz 0x%llx\n", 871 type, da, memsz, filesz); 872 873 if (filesz > memsz) { 874 dev_err(dev, "bad phdr filesz 0x%llx memsz 0x%llx\n", 875 filesz, memsz); 876 ret = -EINVAL; 877 break; 878 } 879 880 if (offset + filesz > fw->size) { 881 dev_err(dev, "truncated fw: need 0x%llx avail 0x%zx\n", 882 offset + filesz, fw->size); 883 ret = -EINVAL; 884 break; 885 } 886 887 if (!rproc_u64_fit_in_size_t(memsz)) { 888 dev_err(dev, "size (%llx) does not fit in size_t type\n", 889 memsz); 890 ret = -EOVERFLOW; 891 break; 892 } 893 894 /* grab the kernel address for this device address */ 895 ptr = rproc_da_to_va(rproc, da, memsz, NULL); 896 if (!ptr) { 897 dev_err(dev, "bad phdr da 0x%llx mem 0x%llx\n", da, 898 memsz); 899 ret = -EINVAL; 900 break; 901 } 902 903 /* put the segment where the remote processor expects it */ 904 if (filesz) { 905 ret = imx_dsp_rproc_memcpy(ptr, elf_data + offset, filesz); 906 if (ret) { 907 dev_err(dev, "memory copy failed for da 0x%llx memsz 0x%llx\n", 908 da, memsz); 909 break; 910 } 911 } 912 913 /* zero out remaining memory for this segment */ 914 if (memsz > filesz) { 915 ret = imx_dsp_rproc_memset(ptr + filesz, 0, memsz - filesz); 916 if (ret) { 917 dev_err(dev, "memset failed for da 0x%llx memsz 0x%llx\n", 918 da, memsz); 919 break; 920 } 921 } 922 } 923 924 return ret; 925 } 926 927 static int imx_dsp_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw) 928 { 929 if (rproc_elf_load_rsc_table(rproc, fw)) 930 dev_warn(&rproc->dev, "no resource table found for this firmware\n"); 931 932 return 0; 933 } 934 935 static const struct rproc_ops imx_dsp_rproc_ops = { 936 .prepare = imx_dsp_rproc_prepare, 937 .unprepare = imx_dsp_rproc_unprepare, 938 .start = imx_dsp_rproc_start, 939 .stop = imx_dsp_rproc_stop, 940 .kick = imx_dsp_rproc_kick, 941 .load = imx_dsp_rproc_elf_load_segments, 942 .parse_fw = imx_dsp_rproc_parse_fw, 943 .find_loaded_rsc_table = rproc_elf_find_loaded_rsc_table, 944 .sanity_check = rproc_elf_sanity_check, 945 .get_boot_addr = rproc_elf_get_boot_addr, 946 }; 947 948 /** 949 * imx_dsp_attach_pm_domains() - attach the power domains 950 * @priv: private data pointer 951 * 952 * On i.MX8QM and i.MX8QXP there is multiple power domains 953 * required, so need to link them. 954 */ 955 static int imx_dsp_attach_pm_domains(struct imx_dsp_rproc *priv) 956 { 957 struct device *dev = priv->rproc->dev.parent; 958 int ret, i; 959 960 priv->num_domains = of_count_phandle_with_args(dev->of_node, 961 "power-domains", 962 "#power-domain-cells"); 963 964 /* If only one domain, then no need to link the device */ 965 if (priv->num_domains <= 1) 966 return 0; 967 968 priv->pd_dev = devm_kmalloc_array(dev, priv->num_domains, 969 sizeof(*priv->pd_dev), 970 GFP_KERNEL); 971 if (!priv->pd_dev) 972 return -ENOMEM; 973 974 priv->pd_dev_link = devm_kmalloc_array(dev, priv->num_domains, 975 sizeof(*priv->pd_dev_link), 976 GFP_KERNEL); 977 if (!priv->pd_dev_link) 978 return -ENOMEM; 979 980 for (i = 0; i < priv->num_domains; i++) { 981 priv->pd_dev[i] = dev_pm_domain_attach_by_id(dev, i); 982 if (IS_ERR(priv->pd_dev[i])) { 983 ret = PTR_ERR(priv->pd_dev[i]); 984 goto detach_pm; 985 } 986 987 /* 988 * device_link_add will check priv->pd_dev[i], if it is 989 * NULL, then will break. 990 */ 991 priv->pd_dev_link[i] = device_link_add(dev, 992 priv->pd_dev[i], 993 DL_FLAG_STATELESS | 994 DL_FLAG_PM_RUNTIME); 995 if (!priv->pd_dev_link[i]) { 996 dev_pm_domain_detach(priv->pd_dev[i], false); 997 ret = -EINVAL; 998 goto detach_pm; 999 } 1000 } 1001 1002 return 0; 1003 1004 detach_pm: 1005 while (--i >= 0) { 1006 device_link_del(priv->pd_dev_link[i]); 1007 dev_pm_domain_detach(priv->pd_dev[i], false); 1008 } 1009 1010 return ret; 1011 } 1012 1013 static int imx_dsp_detach_pm_domains(struct imx_dsp_rproc *priv) 1014 { 1015 int i; 1016 1017 if (priv->num_domains <= 1) 1018 return 0; 1019 1020 for (i = 0; i < priv->num_domains; i++) { 1021 device_link_del(priv->pd_dev_link[i]); 1022 dev_pm_domain_detach(priv->pd_dev[i], false); 1023 } 1024 1025 return 0; 1026 } 1027 1028 /** 1029 * imx_dsp_rproc_detect_mode() - detect DSP control mode 1030 * @priv: private data pointer 1031 * 1032 * Different platform has different control method for DSP, which depends 1033 * on how the DSP is integrated in platform. 1034 * 1035 * For i.MX8QXP and i.MX8QM, DSP should be started and stopped by System 1036 * Control Unit. 1037 * For i.MX8MP and i.MX8ULP, DSP should be started and stopped by system 1038 * integration module. 1039 */ 1040 static int imx_dsp_rproc_detect_mode(struct imx_dsp_rproc *priv) 1041 { 1042 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg; 1043 struct device *dev = priv->rproc->dev.parent; 1044 struct regmap *regmap; 1045 int ret = 0; 1046 1047 switch (dsp_dcfg->dcfg->method) { 1048 case IMX_RPROC_SCU_API: 1049 ret = imx_scu_get_handle(&priv->ipc_handle); 1050 if (ret) 1051 return ret; 1052 break; 1053 case IMX_RPROC_MMIO: 1054 regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,dsp-ctrl"); 1055 if (IS_ERR(regmap)) { 1056 dev_err(dev, "failed to find syscon\n"); 1057 return PTR_ERR(regmap); 1058 } 1059 1060 priv->regmap = regmap; 1061 break; 1062 default: 1063 ret = -EOPNOTSUPP; 1064 break; 1065 } 1066 1067 return ret; 1068 } 1069 1070 static const char *imx_dsp_clks_names[DSP_RPROC_CLK_MAX] = { 1071 /* DSP clocks */ 1072 "core", "ocram", "debug", "ipg", "mu", 1073 }; 1074 1075 static int imx_dsp_rproc_clk_get(struct imx_dsp_rproc *priv) 1076 { 1077 struct device *dev = priv->rproc->dev.parent; 1078 struct clk_bulk_data *clks = priv->clks; 1079 int i; 1080 1081 for (i = 0; i < DSP_RPROC_CLK_MAX; i++) 1082 clks[i].id = imx_dsp_clks_names[i]; 1083 1084 return devm_clk_bulk_get_optional(dev, DSP_RPROC_CLK_MAX, clks); 1085 } 1086 1087 static int imx_dsp_rproc_probe(struct platform_device *pdev) 1088 { 1089 const struct imx_dsp_rproc_dcfg *dsp_dcfg; 1090 struct device *dev = &pdev->dev; 1091 struct imx_dsp_rproc *priv; 1092 struct rproc *rproc; 1093 const char *fw_name; 1094 int ret; 1095 1096 dsp_dcfg = of_device_get_match_data(dev); 1097 if (!dsp_dcfg) 1098 return -ENODEV; 1099 1100 ret = rproc_of_parse_firmware(dev, 0, &fw_name); 1101 if (ret) { 1102 dev_err(dev, "failed to parse firmware-name property, ret = %d\n", 1103 ret); 1104 return ret; 1105 } 1106 1107 rproc = rproc_alloc(dev, "imx-dsp-rproc", &imx_dsp_rproc_ops, fw_name, 1108 sizeof(*priv)); 1109 if (!rproc) 1110 return -ENOMEM; 1111 1112 priv = rproc->priv; 1113 priv->rproc = rproc; 1114 priv->dsp_dcfg = dsp_dcfg; 1115 1116 if (no_mailboxes) 1117 imx_dsp_rproc_mbox_init = imx_dsp_rproc_mbox_no_alloc; 1118 else 1119 imx_dsp_rproc_mbox_init = imx_dsp_rproc_mbox_alloc; 1120 1121 dev_set_drvdata(dev, rproc); 1122 1123 INIT_WORK(&priv->rproc_work, imx_dsp_rproc_vq_work); 1124 1125 ret = imx_dsp_rproc_detect_mode(priv); 1126 if (ret) { 1127 dev_err(dev, "failed on imx_dsp_rproc_detect_mode\n"); 1128 goto err_put_rproc; 1129 } 1130 1131 /* There are multiple power domains required by DSP on some platform */ 1132 ret = imx_dsp_attach_pm_domains(priv); 1133 if (ret) { 1134 dev_err(dev, "failed on imx_dsp_attach_pm_domains\n"); 1135 goto err_put_rproc; 1136 } 1137 /* Get clocks */ 1138 ret = imx_dsp_rproc_clk_get(priv); 1139 if (ret) { 1140 dev_err(dev, "failed on imx_dsp_rproc_clk_get\n"); 1141 goto err_detach_domains; 1142 } 1143 1144 init_completion(&priv->pm_comp); 1145 rproc->auto_boot = false; 1146 ret = rproc_add(rproc); 1147 if (ret) { 1148 dev_err(dev, "rproc_add failed\n"); 1149 goto err_detach_domains; 1150 } 1151 1152 pm_runtime_enable(dev); 1153 1154 return 0; 1155 1156 err_detach_domains: 1157 imx_dsp_detach_pm_domains(priv); 1158 err_put_rproc: 1159 rproc_free(rproc); 1160 1161 return ret; 1162 } 1163 1164 static void imx_dsp_rproc_remove(struct platform_device *pdev) 1165 { 1166 struct rproc *rproc = platform_get_drvdata(pdev); 1167 struct imx_dsp_rproc *priv = rproc->priv; 1168 1169 pm_runtime_disable(&pdev->dev); 1170 rproc_del(rproc); 1171 imx_dsp_detach_pm_domains(priv); 1172 rproc_free(rproc); 1173 } 1174 1175 /* pm runtime functions */ 1176 static int imx_dsp_runtime_resume(struct device *dev) 1177 { 1178 struct rproc *rproc = dev_get_drvdata(dev); 1179 struct imx_dsp_rproc *priv = rproc->priv; 1180 const struct imx_dsp_rproc_dcfg *dsp_dcfg = priv->dsp_dcfg; 1181 int ret; 1182 1183 /* 1184 * There is power domain attached with mailbox, if setup mailbox 1185 * in probe(), then the power of mailbox is always enabled, 1186 * the power can't be saved. 1187 * So move setup of mailbox to runtime resume. 1188 */ 1189 ret = imx_dsp_rproc_mbox_init(priv); 1190 if (ret) { 1191 dev_err(dev, "failed on imx_dsp_rproc_mbox_init\n"); 1192 return ret; 1193 } 1194 1195 ret = clk_bulk_prepare_enable(DSP_RPROC_CLK_MAX, priv->clks); 1196 if (ret) { 1197 dev_err(dev, "failed on clk_bulk_prepare_enable\n"); 1198 return ret; 1199 } 1200 1201 /* Reset DSP if needed */ 1202 if (dsp_dcfg->reset) 1203 dsp_dcfg->reset(priv); 1204 1205 return 0; 1206 } 1207 1208 static int imx_dsp_runtime_suspend(struct device *dev) 1209 { 1210 struct rproc *rproc = dev_get_drvdata(dev); 1211 struct imx_dsp_rproc *priv = rproc->priv; 1212 1213 clk_bulk_disable_unprepare(DSP_RPROC_CLK_MAX, priv->clks); 1214 1215 imx_dsp_rproc_free_mbox(priv); 1216 1217 return 0; 1218 } 1219 1220 static void imx_dsp_load_firmware(const struct firmware *fw, void *context) 1221 { 1222 struct rproc *rproc = context; 1223 int ret; 1224 1225 /* 1226 * Same flow as start procedure. 1227 * Load the ELF segments to memory firstly. 1228 */ 1229 ret = rproc_load_segments(rproc, fw); 1230 if (ret) 1231 goto out; 1232 1233 /* Start the remote processor */ 1234 ret = rproc->ops->start(rproc); 1235 if (ret) 1236 goto out; 1237 1238 rproc->ops->kick(rproc, 0); 1239 1240 out: 1241 release_firmware(fw); 1242 } 1243 1244 static int imx_dsp_suspend(struct device *dev) 1245 { 1246 struct rproc *rproc = dev_get_drvdata(dev); 1247 struct imx_dsp_rproc *priv = rproc->priv; 1248 __u32 mmsg = RP_MBOX_SUSPEND_SYSTEM; 1249 int ret; 1250 1251 if (rproc->state != RPROC_RUNNING) 1252 goto out; 1253 1254 reinit_completion(&priv->pm_comp); 1255 1256 /* Tell DSP that suspend is happening */ 1257 ret = mbox_send_message(priv->tx_ch, (void *)&mmsg); 1258 if (ret < 0) { 1259 dev_err(dev, "PM mbox_send_message failed: %d\n", ret); 1260 return ret; 1261 } 1262 1263 /* 1264 * DSP need to save the context at suspend. 1265 * Here waiting the response for DSP, then power can be disabled. 1266 */ 1267 if (!wait_for_completion_timeout(&priv->pm_comp, msecs_to_jiffies(100))) 1268 return -EBUSY; 1269 1270 out: 1271 /* 1272 * The power of DSP is disabled in suspend, so force pm runtime 1273 * to be suspend, then we can reenable the power and clocks at 1274 * resume stage. 1275 */ 1276 return pm_runtime_force_suspend(dev); 1277 } 1278 1279 static int imx_dsp_resume(struct device *dev) 1280 { 1281 struct rproc *rproc = dev_get_drvdata(dev); 1282 int ret = 0; 1283 1284 ret = pm_runtime_force_resume(dev); 1285 if (ret) 1286 return ret; 1287 1288 if (rproc->state != RPROC_RUNNING) 1289 return 0; 1290 1291 /* 1292 * The power of DSP is disabled at suspend, the memory of dsp 1293 * is reset, the image segments are lost. So need to reload 1294 * firmware and restart the DSP if it is in running state. 1295 */ 1296 ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT, 1297 rproc->firmware, dev, GFP_KERNEL, 1298 rproc, imx_dsp_load_firmware); 1299 if (ret < 0) { 1300 dev_err(dev, "load firmware failed: %d\n", ret); 1301 goto err; 1302 } 1303 1304 return 0; 1305 1306 err: 1307 pm_runtime_force_suspend(dev); 1308 1309 return ret; 1310 } 1311 1312 static const struct dev_pm_ops imx_dsp_rproc_pm_ops = { 1313 SYSTEM_SLEEP_PM_OPS(imx_dsp_suspend, imx_dsp_resume) 1314 RUNTIME_PM_OPS(imx_dsp_runtime_suspend, imx_dsp_runtime_resume, NULL) 1315 }; 1316 1317 static const struct of_device_id imx_dsp_rproc_of_match[] = { 1318 { .compatible = "fsl,imx8qxp-hifi4", .data = &imx_dsp_rproc_cfg_imx8qxp }, 1319 { .compatible = "fsl,imx8qm-hifi4", .data = &imx_dsp_rproc_cfg_imx8qm }, 1320 { .compatible = "fsl,imx8mp-hifi4", .data = &imx_dsp_rproc_cfg_imx8mp }, 1321 { .compatible = "fsl,imx8ulp-hifi4", .data = &imx_dsp_rproc_cfg_imx8ulp }, 1322 {}, 1323 }; 1324 MODULE_DEVICE_TABLE(of, imx_dsp_rproc_of_match); 1325 1326 static struct platform_driver imx_dsp_rproc_driver = { 1327 .probe = imx_dsp_rproc_probe, 1328 .remove_new = imx_dsp_rproc_remove, 1329 .driver = { 1330 .name = "imx-dsp-rproc", 1331 .of_match_table = imx_dsp_rproc_of_match, 1332 .pm = pm_ptr(&imx_dsp_rproc_pm_ops), 1333 }, 1334 }; 1335 module_platform_driver(imx_dsp_rproc_driver); 1336 1337 MODULE_LICENSE("GPL v2"); 1338 MODULE_DESCRIPTION("i.MX HiFi Core Remote Processor Control Driver"); 1339 MODULE_AUTHOR("Shengjiu Wang <shengjiu.wang@nxp.com>"); 1340