1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * An I2C driver for the PCF85063 RTC 4 * Copyright 2014 Rose Technology 5 * 6 * Author: Søren Andersen <san@rosetechnology.dk> 7 * Maintainers: http://www.nslu2-linux.org/ 8 * 9 * Copyright (C) 2019 Micro Crystal AG 10 * Author: Alexandre Belloni <alexandre.belloni@bootlin.com> 11 */ 12 #include <linux/i2c.h> 13 #include <linux/bcd.h> 14 #include <linux/rtc.h> 15 #include <linux/module.h> 16 #include <linux/of_device.h> 17 #include <linux/pm_wakeirq.h> 18 #include <linux/regmap.h> 19 20 /* 21 * Information for this driver was pulled from the following datasheets. 22 * 23 * http://www.nxp.com/documents/data_sheet/PCF85063A.pdf 24 * http://www.nxp.com/documents/data_sheet/PCF85063TP.pdf 25 * 26 * PCF85063A -- Rev. 6 — 18 November 2015 27 * PCF85063TP -- Rev. 4 — 6 May 2015 28 * 29 * https://www.microcrystal.com/fileadmin/Media/Products/RTC/App.Manual/RV-8263-C7_App-Manual.pdf 30 * RV8263 -- Rev. 1.0 — January 2019 31 */ 32 33 #define PCF85063_REG_CTRL1 0x00 /* status */ 34 #define PCF85063_REG_CTRL1_CAP_SEL BIT(0) 35 #define PCF85063_REG_CTRL1_STOP BIT(5) 36 37 #define PCF85063_REG_CTRL2 0x01 38 #define PCF85063_CTRL2_AF BIT(6) 39 #define PCF85063_CTRL2_AIE BIT(7) 40 41 #define PCF85063_REG_OFFSET 0x02 42 #define PCF85063_OFFSET_SIGN_BIT 6 /* 2's complement sign bit */ 43 #define PCF85063_OFFSET_MODE BIT(7) 44 #define PCF85063_OFFSET_STEP0 4340 45 #define PCF85063_OFFSET_STEP1 4069 46 47 #define PCF85063_REG_RAM 0x03 48 49 #define PCF85063_REG_SC 0x04 /* datetime */ 50 #define PCF85063_REG_SC_OS 0x80 51 52 #define PCF85063_REG_ALM_S 0x0b 53 #define PCF85063_AEN BIT(7) 54 55 struct pcf85063_config { 56 struct regmap_config regmap; 57 unsigned has_alarms:1; 58 unsigned force_cap_7000:1; 59 }; 60 61 struct pcf85063 { 62 struct rtc_device *rtc; 63 struct regmap *regmap; 64 }; 65 66 static int pcf85063_rtc_read_time(struct device *dev, struct rtc_time *tm) 67 { 68 struct pcf85063 *pcf85063 = dev_get_drvdata(dev); 69 int rc; 70 u8 regs[7]; 71 72 /* 73 * while reading, the time/date registers are blocked and not updated 74 * anymore until the access is finished. To not lose a second 75 * event, the access must be finished within one second. So, read all 76 * time/date registers in one turn. 77 */ 78 rc = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_SC, regs, 79 sizeof(regs)); 80 if (rc) 81 return rc; 82 83 /* if the clock has lost its power it makes no sense to use its time */ 84 if (regs[0] & PCF85063_REG_SC_OS) { 85 dev_warn(&pcf85063->rtc->dev, "Power loss detected, invalid time\n"); 86 return -EINVAL; 87 } 88 89 tm->tm_sec = bcd2bin(regs[0] & 0x7F); 90 tm->tm_min = bcd2bin(regs[1] & 0x7F); 91 tm->tm_hour = bcd2bin(regs[2] & 0x3F); /* rtc hr 0-23 */ 92 tm->tm_mday = bcd2bin(regs[3] & 0x3F); 93 tm->tm_wday = regs[4] & 0x07; 94 tm->tm_mon = bcd2bin(regs[5] & 0x1F) - 1; /* rtc mn 1-12 */ 95 tm->tm_year = bcd2bin(regs[6]); 96 tm->tm_year += 100; 97 98 return 0; 99 } 100 101 static int pcf85063_rtc_set_time(struct device *dev, struct rtc_time *tm) 102 { 103 struct pcf85063 *pcf85063 = dev_get_drvdata(dev); 104 int rc; 105 u8 regs[7]; 106 107 /* 108 * to accurately set the time, reset the divider chain and keep it in 109 * reset state until all time/date registers are written 110 */ 111 rc = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1, 112 PCF85063_REG_CTRL1_STOP, 113 PCF85063_REG_CTRL1_STOP); 114 if (rc) 115 return rc; 116 117 /* hours, minutes and seconds */ 118 regs[0] = bin2bcd(tm->tm_sec) & 0x7F; /* clear OS flag */ 119 120 regs[1] = bin2bcd(tm->tm_min); 121 regs[2] = bin2bcd(tm->tm_hour); 122 123 /* Day of month, 1 - 31 */ 124 regs[3] = bin2bcd(tm->tm_mday); 125 126 /* Day, 0 - 6 */ 127 regs[4] = tm->tm_wday & 0x07; 128 129 /* month, 1 - 12 */ 130 regs[5] = bin2bcd(tm->tm_mon + 1); 131 132 /* year and century */ 133 regs[6] = bin2bcd(tm->tm_year - 100); 134 135 /* write all registers at once */ 136 rc = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_SC, 137 regs, sizeof(regs)); 138 if (rc) 139 return rc; 140 141 /* 142 * Write the control register as a separate action since the size of 143 * the register space is different between the PCF85063TP and 144 * PCF85063A devices. The rollover point can not be used. 145 */ 146 return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1, 147 PCF85063_REG_CTRL1_STOP, 0); 148 } 149 150 static int pcf85063_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 151 { 152 struct pcf85063 *pcf85063 = dev_get_drvdata(dev); 153 u8 buf[4]; 154 unsigned int val; 155 int ret; 156 157 ret = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_ALM_S, 158 buf, sizeof(buf)); 159 if (ret) 160 return ret; 161 162 alrm->time.tm_sec = bcd2bin(buf[0]); 163 alrm->time.tm_min = bcd2bin(buf[1]); 164 alrm->time.tm_hour = bcd2bin(buf[2]); 165 alrm->time.tm_mday = bcd2bin(buf[3]); 166 167 ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val); 168 if (ret) 169 return ret; 170 171 alrm->enabled = !!(val & PCF85063_CTRL2_AIE); 172 173 return 0; 174 } 175 176 static int pcf85063_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 177 { 178 struct pcf85063 *pcf85063 = dev_get_drvdata(dev); 179 u8 buf[5]; 180 int ret; 181 182 buf[0] = bin2bcd(alrm->time.tm_sec); 183 buf[1] = bin2bcd(alrm->time.tm_min); 184 buf[2] = bin2bcd(alrm->time.tm_hour); 185 buf[3] = bin2bcd(alrm->time.tm_mday); 186 buf[4] = PCF85063_AEN; /* Do not match on week day */ 187 188 ret = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2, 189 PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF, 0); 190 if (ret) 191 return ret; 192 193 ret = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_ALM_S, 194 buf, sizeof(buf)); 195 if (ret) 196 return ret; 197 198 return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2, 199 PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF, 200 alrm->enabled ? PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF : PCF85063_CTRL2_AF); 201 } 202 203 static int pcf85063_rtc_alarm_irq_enable(struct device *dev, 204 unsigned int enabled) 205 { 206 struct pcf85063 *pcf85063 = dev_get_drvdata(dev); 207 208 return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2, 209 PCF85063_CTRL2_AIE, 210 enabled ? PCF85063_CTRL2_AIE : 0); 211 } 212 213 static irqreturn_t pcf85063_rtc_handle_irq(int irq, void *dev_id) 214 { 215 struct pcf85063 *pcf85063 = dev_id; 216 unsigned int val; 217 int err; 218 219 err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val); 220 if (err) 221 return IRQ_NONE; 222 223 if (val & PCF85063_CTRL2_AF) { 224 rtc_update_irq(pcf85063->rtc, 1, RTC_IRQF | RTC_AF); 225 regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2, 226 PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF, 227 0); 228 return IRQ_HANDLED; 229 } 230 231 return IRQ_NONE; 232 } 233 234 static int pcf85063_read_offset(struct device *dev, long *offset) 235 { 236 struct pcf85063 *pcf85063 = dev_get_drvdata(dev); 237 long val; 238 u32 reg; 239 int ret; 240 241 ret = regmap_read(pcf85063->regmap, PCF85063_REG_OFFSET, ®); 242 if (ret < 0) 243 return ret; 244 245 val = sign_extend32(reg & ~PCF85063_OFFSET_MODE, 246 PCF85063_OFFSET_SIGN_BIT); 247 248 if (reg & PCF85063_OFFSET_MODE) 249 *offset = val * PCF85063_OFFSET_STEP1; 250 else 251 *offset = val * PCF85063_OFFSET_STEP0; 252 253 return 0; 254 } 255 256 static int pcf85063_set_offset(struct device *dev, long offset) 257 { 258 struct pcf85063 *pcf85063 = dev_get_drvdata(dev); 259 s8 mode0, mode1, reg; 260 unsigned int error0, error1; 261 262 if (offset > PCF85063_OFFSET_STEP0 * 63) 263 return -ERANGE; 264 if (offset < PCF85063_OFFSET_STEP0 * -64) 265 return -ERANGE; 266 267 mode0 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP0); 268 mode1 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP1); 269 270 error0 = abs(offset - (mode0 * PCF85063_OFFSET_STEP0)); 271 error1 = abs(offset - (mode1 * PCF85063_OFFSET_STEP1)); 272 if (mode1 > 63 || mode1 < -64 || error0 < error1) 273 reg = mode0 & ~PCF85063_OFFSET_MODE; 274 else 275 reg = mode1 | PCF85063_OFFSET_MODE; 276 277 return regmap_write(pcf85063->regmap, PCF85063_REG_OFFSET, reg); 278 } 279 280 static int pcf85063_ioctl(struct device *dev, unsigned int cmd, 281 unsigned long arg) 282 { 283 struct pcf85063 *pcf85063 = dev_get_drvdata(dev); 284 int status, ret = 0; 285 286 switch (cmd) { 287 case RTC_VL_READ: 288 ret = regmap_read(pcf85063->regmap, PCF85063_REG_SC, &status); 289 if (ret < 0) 290 return ret; 291 292 status = status & PCF85063_REG_SC_OS ? RTC_VL_DATA_INVALID : 0; 293 294 return put_user(status, (unsigned int __user *)arg); 295 296 default: 297 return -ENOIOCTLCMD; 298 } 299 } 300 301 static const struct rtc_class_ops pcf85063_rtc_ops = { 302 .read_time = pcf85063_rtc_read_time, 303 .set_time = pcf85063_rtc_set_time, 304 .read_offset = pcf85063_read_offset, 305 .set_offset = pcf85063_set_offset, 306 .ioctl = pcf85063_ioctl, 307 }; 308 309 static const struct rtc_class_ops pcf85063_rtc_ops_alarm = { 310 .read_time = pcf85063_rtc_read_time, 311 .set_time = pcf85063_rtc_set_time, 312 .read_offset = pcf85063_read_offset, 313 .set_offset = pcf85063_set_offset, 314 .read_alarm = pcf85063_rtc_read_alarm, 315 .set_alarm = pcf85063_rtc_set_alarm, 316 .alarm_irq_enable = pcf85063_rtc_alarm_irq_enable, 317 .ioctl = pcf85063_ioctl, 318 }; 319 320 static int pcf85063_nvmem_read(void *priv, unsigned int offset, 321 void *val, size_t bytes) 322 { 323 return regmap_read(priv, PCF85063_REG_RAM, val); 324 } 325 326 static int pcf85063_nvmem_write(void *priv, unsigned int offset, 327 void *val, size_t bytes) 328 { 329 return regmap_write(priv, PCF85063_REG_RAM, *(u8 *)val); 330 } 331 332 static int pcf85063_load_capacitance(struct pcf85063 *pcf85063, 333 const struct device_node *np, 334 unsigned int force_cap) 335 { 336 u32 load = 7000; 337 u8 reg = 0; 338 339 if (force_cap) 340 load = force_cap; 341 else 342 of_property_read_u32(np, "quartz-load-femtofarads", &load); 343 344 switch (load) { 345 default: 346 dev_warn(&pcf85063->rtc->dev, "Unknown quartz-load-femtofarads value: %d. Assuming 7000", 347 load); 348 /* fall through */ 349 case 7000: 350 break; 351 case 12500: 352 reg = PCF85063_REG_CTRL1_CAP_SEL; 353 break; 354 } 355 356 return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1, 357 PCF85063_REG_CTRL1_CAP_SEL, reg); 358 } 359 360 static const struct pcf85063_config pcf85063a_config = { 361 .regmap = { 362 .reg_bits = 8, 363 .val_bits = 8, 364 .max_register = 0x11, 365 }, 366 .has_alarms = 1, 367 }; 368 369 static const struct pcf85063_config pcf85063tp_config = { 370 .regmap = { 371 .reg_bits = 8, 372 .val_bits = 8, 373 .max_register = 0x0a, 374 }, 375 }; 376 377 static const struct pcf85063_config rv8263_config = { 378 .regmap = { 379 .reg_bits = 8, 380 .val_bits = 8, 381 .max_register = 0x11, 382 }, 383 .has_alarms = 1, 384 .force_cap_7000 = 1, 385 }; 386 387 static int pcf85063_probe(struct i2c_client *client) 388 { 389 struct pcf85063 *pcf85063; 390 unsigned int tmp; 391 int err; 392 const struct pcf85063_config *config = &pcf85063tp_config; 393 const void *data = of_device_get_match_data(&client->dev); 394 struct nvmem_config nvmem_cfg = { 395 .name = "pcf85063_nvram", 396 .reg_read = pcf85063_nvmem_read, 397 .reg_write = pcf85063_nvmem_write, 398 .type = NVMEM_TYPE_BATTERY_BACKED, 399 .size = 1, 400 }; 401 402 dev_dbg(&client->dev, "%s\n", __func__); 403 404 pcf85063 = devm_kzalloc(&client->dev, sizeof(struct pcf85063), 405 GFP_KERNEL); 406 if (!pcf85063) 407 return -ENOMEM; 408 409 if (data) 410 config = data; 411 412 pcf85063->regmap = devm_regmap_init_i2c(client, &config->regmap); 413 if (IS_ERR(pcf85063->regmap)) 414 return PTR_ERR(pcf85063->regmap); 415 416 i2c_set_clientdata(client, pcf85063); 417 418 err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL1, &tmp); 419 if (err) { 420 dev_err(&client->dev, "RTC chip is not present\n"); 421 return err; 422 } 423 424 pcf85063->rtc = devm_rtc_allocate_device(&client->dev); 425 if (IS_ERR(pcf85063->rtc)) 426 return PTR_ERR(pcf85063->rtc); 427 428 err = pcf85063_load_capacitance(pcf85063, client->dev.of_node, 429 config->force_cap_7000 ? 7000 : 0); 430 if (err < 0) 431 dev_warn(&client->dev, "failed to set xtal load capacitance: %d", 432 err); 433 434 pcf85063->rtc->ops = &pcf85063_rtc_ops; 435 pcf85063->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; 436 pcf85063->rtc->range_max = RTC_TIMESTAMP_END_2099; 437 pcf85063->rtc->uie_unsupported = 1; 438 439 if (config->has_alarms && client->irq > 0) { 440 err = devm_request_threaded_irq(&client->dev, client->irq, 441 NULL, pcf85063_rtc_handle_irq, 442 IRQF_TRIGGER_LOW | IRQF_ONESHOT, 443 "pcf85063", pcf85063); 444 if (err) { 445 dev_warn(&pcf85063->rtc->dev, 446 "unable to request IRQ, alarms disabled\n"); 447 } else { 448 pcf85063->rtc->ops = &pcf85063_rtc_ops_alarm; 449 device_init_wakeup(&client->dev, true); 450 err = dev_pm_set_wake_irq(&client->dev, client->irq); 451 if (err) 452 dev_err(&pcf85063->rtc->dev, 453 "failed to enable irq wake\n"); 454 } 455 } 456 457 nvmem_cfg.priv = pcf85063->regmap; 458 rtc_nvmem_register(pcf85063->rtc, &nvmem_cfg); 459 460 return rtc_register_device(pcf85063->rtc); 461 } 462 463 #ifdef CONFIG_OF 464 static const struct of_device_id pcf85063_of_match[] = { 465 { .compatible = "nxp,pcf85063", .data = &pcf85063tp_config }, 466 { .compatible = "nxp,pcf85063tp", .data = &pcf85063tp_config }, 467 { .compatible = "nxp,pcf85063a", .data = &pcf85063a_config }, 468 { .compatible = "microcrystal,rv8263", .data = &rv8263_config }, 469 {} 470 }; 471 MODULE_DEVICE_TABLE(of, pcf85063_of_match); 472 #endif 473 474 static struct i2c_driver pcf85063_driver = { 475 .driver = { 476 .name = "rtc-pcf85063", 477 .of_match_table = of_match_ptr(pcf85063_of_match), 478 }, 479 .probe_new = pcf85063_probe, 480 }; 481 482 module_i2c_driver(pcf85063_driver); 483 484 MODULE_AUTHOR("Søren Andersen <san@rosetechnology.dk>"); 485 MODULE_DESCRIPTION("PCF85063 RTC driver"); 486 MODULE_LICENSE("GPL"); 487