1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Linux MegaRAID driver for SAS based RAID controllers 4 * 5 * Copyright (c) 2003-2013 LSI Corporation 6 * Copyright (c) 2013-2016 Avago Technologies 7 * Copyright (c) 2016-2018 Broadcom Inc. 8 * 9 * FILE: megaraid_sas.h 10 * 11 * Authors: Broadcom Inc. 12 * Kashyap Desai <kashyap.desai@broadcom.com> 13 * Sumit Saxena <sumit.saxena@broadcom.com> 14 * 15 * Send feedback to: megaraidlinux.pdl@broadcom.com 16 */ 17 18 #ifndef LSI_MEGARAID_SAS_H 19 #define LSI_MEGARAID_SAS_H 20 21 /* 22 * MegaRAID SAS Driver meta data 23 */ 24 #define MEGASAS_VERSION "07.707.51.00-rc1" 25 #define MEGASAS_RELDATE "February 7, 2019" 26 27 /* 28 * Device IDs 29 */ 30 #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060 31 #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C 32 #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413 33 #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078 34 #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079 35 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073 36 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071 37 #define PCI_DEVICE_ID_LSI_FUSION 0x005b 38 #define PCI_DEVICE_ID_LSI_PLASMA 0x002f 39 #define PCI_DEVICE_ID_LSI_INVADER 0x005d 40 #define PCI_DEVICE_ID_LSI_FURY 0x005f 41 #define PCI_DEVICE_ID_LSI_INTRUDER 0x00ce 42 #define PCI_DEVICE_ID_LSI_INTRUDER_24 0x00cf 43 #define PCI_DEVICE_ID_LSI_CUTLASS_52 0x0052 44 #define PCI_DEVICE_ID_LSI_CUTLASS_53 0x0053 45 #define PCI_DEVICE_ID_LSI_VENTURA 0x0014 46 #define PCI_DEVICE_ID_LSI_CRUSADER 0x0015 47 #define PCI_DEVICE_ID_LSI_HARPOON 0x0016 48 #define PCI_DEVICE_ID_LSI_TOMCAT 0x0017 49 #define PCI_DEVICE_ID_LSI_VENTURA_4PORT 0x001B 50 #define PCI_DEVICE_ID_LSI_CRUSADER_4PORT 0x001C 51 #define PCI_DEVICE_ID_LSI_AERO_10E1 0x10e1 52 #define PCI_DEVICE_ID_LSI_AERO_10E2 0x10e2 53 #define PCI_DEVICE_ID_LSI_AERO_10E5 0x10e5 54 #define PCI_DEVICE_ID_LSI_AERO_10E6 0x10e6 55 56 /* 57 * Intel HBA SSDIDs 58 */ 59 #define MEGARAID_INTEL_RS3DC080_SSDID 0x9360 60 #define MEGARAID_INTEL_RS3DC040_SSDID 0x9362 61 #define MEGARAID_INTEL_RS3SC008_SSDID 0x9380 62 #define MEGARAID_INTEL_RS3MC044_SSDID 0x9381 63 #define MEGARAID_INTEL_RS3WC080_SSDID 0x9341 64 #define MEGARAID_INTEL_RS3WC040_SSDID 0x9343 65 #define MEGARAID_INTEL_RMS3BC160_SSDID 0x352B 66 67 /* 68 * Intruder HBA SSDIDs 69 */ 70 #define MEGARAID_INTRUDER_SSDID1 0x9371 71 #define MEGARAID_INTRUDER_SSDID2 0x9390 72 #define MEGARAID_INTRUDER_SSDID3 0x9370 73 74 /* 75 * Intel HBA branding 76 */ 77 #define MEGARAID_INTEL_RS3DC080_BRANDING \ 78 "Intel(R) RAID Controller RS3DC080" 79 #define MEGARAID_INTEL_RS3DC040_BRANDING \ 80 "Intel(R) RAID Controller RS3DC040" 81 #define MEGARAID_INTEL_RS3SC008_BRANDING \ 82 "Intel(R) RAID Controller RS3SC008" 83 #define MEGARAID_INTEL_RS3MC044_BRANDING \ 84 "Intel(R) RAID Controller RS3MC044" 85 #define MEGARAID_INTEL_RS3WC080_BRANDING \ 86 "Intel(R) RAID Controller RS3WC080" 87 #define MEGARAID_INTEL_RS3WC040_BRANDING \ 88 "Intel(R) RAID Controller RS3WC040" 89 #define MEGARAID_INTEL_RMS3BC160_BRANDING \ 90 "Intel(R) Integrated RAID Module RMS3BC160" 91 92 /* 93 * ===================================== 94 * MegaRAID SAS MFI firmware definitions 95 * ===================================== 96 */ 97 98 /* 99 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for 100 * protocol between the software and firmware. Commands are issued using 101 * "message frames" 102 */ 103 104 /* 105 * FW posts its state in upper 4 bits of outbound_msg_0 register 106 */ 107 #define MFI_STATE_MASK 0xF0000000 108 #define MFI_STATE_UNDEFINED 0x00000000 109 #define MFI_STATE_BB_INIT 0x10000000 110 #define MFI_STATE_FW_INIT 0x40000000 111 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 112 #define MFI_STATE_FW_INIT_2 0x70000000 113 #define MFI_STATE_DEVICE_SCAN 0x80000000 114 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 115 #define MFI_STATE_FLUSH_CACHE 0xA0000000 116 #define MFI_STATE_READY 0xB0000000 117 #define MFI_STATE_OPERATIONAL 0xC0000000 118 #define MFI_STATE_FAULT 0xF0000000 119 #define MFI_STATE_FORCE_OCR 0x00000080 120 #define MFI_STATE_DMADONE 0x00000008 121 #define MFI_STATE_CRASH_DUMP_DONE 0x00000004 122 #define MFI_RESET_REQUIRED 0x00000001 123 #define MFI_RESET_ADAPTER 0x00000002 124 #define MEGAMFI_FRAME_SIZE 64 125 126 /* 127 * During FW init, clear pending cmds & reset state using inbound_msg_0 128 * 129 * ABORT : Abort all pending cmds 130 * READY : Move from OPERATIONAL to READY state; discard queue info 131 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 132 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 133 * HOTPLUG : Resume from Hotplug 134 * MFI_STOP_ADP : Send signal to FW to stop processing 135 * MFI_ADP_TRIGGER_SNAP_DUMP: Inform firmware to initiate snap dump 136 */ 137 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */ 138 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */ 139 #define DIAG_WRITE_ENABLE (0x00000080) 140 #define DIAG_RESET_ADAPTER (0x00000004) 141 142 #define MFI_ADP_RESET 0x00000040 143 #define MFI_INIT_ABORT 0x00000001 144 #define MFI_INIT_READY 0x00000002 145 #define MFI_INIT_MFIMODE 0x00000004 146 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 147 #define MFI_INIT_HOTPLUG 0x00000010 148 #define MFI_STOP_ADP 0x00000020 149 #define MFI_RESET_FLAGS MFI_INIT_READY| \ 150 MFI_INIT_MFIMODE| \ 151 MFI_INIT_ABORT 152 #define MFI_ADP_TRIGGER_SNAP_DUMP 0x00000100 153 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01) 154 155 /* 156 * MFI frame flags 157 */ 158 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 159 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 160 #define MFI_FRAME_SGL32 0x0000 161 #define MFI_FRAME_SGL64 0x0002 162 #define MFI_FRAME_SENSE32 0x0000 163 #define MFI_FRAME_SENSE64 0x0004 164 #define MFI_FRAME_DIR_NONE 0x0000 165 #define MFI_FRAME_DIR_WRITE 0x0008 166 #define MFI_FRAME_DIR_READ 0x0010 167 #define MFI_FRAME_DIR_BOTH 0x0018 168 #define MFI_FRAME_IEEE 0x0020 169 170 /* Driver internal */ 171 #define DRV_DCMD_POLLED_MODE 0x1 172 #define DRV_DCMD_SKIP_REFIRE 0x2 173 174 /* 175 * Definition for cmd_status 176 */ 177 #define MFI_CMD_STATUS_POLL_MODE 0xFF 178 179 /* 180 * MFI command opcodes 181 */ 182 enum MFI_CMD_OP { 183 MFI_CMD_INIT = 0x0, 184 MFI_CMD_LD_READ = 0x1, 185 MFI_CMD_LD_WRITE = 0x2, 186 MFI_CMD_LD_SCSI_IO = 0x3, 187 MFI_CMD_PD_SCSI_IO = 0x4, 188 MFI_CMD_DCMD = 0x5, 189 MFI_CMD_ABORT = 0x6, 190 MFI_CMD_SMP = 0x7, 191 MFI_CMD_STP = 0x8, 192 MFI_CMD_NVME = 0x9, 193 MFI_CMD_OP_COUNT, 194 MFI_CMD_INVALID = 0xff 195 }; 196 197 #define MR_DCMD_CTRL_GET_INFO 0x01010000 198 #define MR_DCMD_LD_GET_LIST 0x03010000 199 #define MR_DCMD_LD_LIST_QUERY 0x03010100 200 201 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 202 #define MR_FLUSH_CTRL_CACHE 0x01 203 #define MR_FLUSH_DISK_CACHE 0x02 204 205 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 206 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 207 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 208 209 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 210 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 211 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 212 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 213 214 #define MR_DCMD_CLUSTER 0x08000000 215 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 216 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 217 #define MR_DCMD_PD_LIST_QUERY 0x02010100 218 219 #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS 0x01190100 220 #define MR_DRIVER_SET_APP_CRASHDUMP_MODE (0xF0010000 | 0x0600) 221 #define MR_DCMD_PD_GET_INFO 0x02020000 222 223 /* 224 * Global functions 225 */ 226 extern u8 MR_ValidateMapInfo(struct megasas_instance *instance, u64 map_id); 227 228 229 /* 230 * MFI command completion codes 231 */ 232 enum MFI_STAT { 233 MFI_STAT_OK = 0x00, 234 MFI_STAT_INVALID_CMD = 0x01, 235 MFI_STAT_INVALID_DCMD = 0x02, 236 MFI_STAT_INVALID_PARAMETER = 0x03, 237 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 238 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 239 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 240 MFI_STAT_APP_IN_USE = 0x07, 241 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 242 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 243 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 244 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 245 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 246 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 247 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 248 MFI_STAT_FLASH_BUSY = 0x0f, 249 MFI_STAT_FLASH_ERROR = 0x10, 250 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 251 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 252 MFI_STAT_FLASH_NOT_OPEN = 0x13, 253 MFI_STAT_FLASH_NOT_STARTED = 0x14, 254 MFI_STAT_FLUSH_FAILED = 0x15, 255 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 256 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 257 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 258 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 259 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 260 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 261 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 262 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 263 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 264 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 265 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 266 MFI_STAT_MFC_HW_ERROR = 0x21, 267 MFI_STAT_NO_HW_PRESENT = 0x22, 268 MFI_STAT_NOT_FOUND = 0x23, 269 MFI_STAT_NOT_IN_ENCL = 0x24, 270 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 271 MFI_STAT_PD_TYPE_WRONG = 0x26, 272 MFI_STAT_PR_DISABLED = 0x27, 273 MFI_STAT_ROW_INDEX_INVALID = 0x28, 274 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 275 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 276 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 277 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 278 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 279 MFI_STAT_SCSI_IO_FAILED = 0x2e, 280 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 281 MFI_STAT_SHUTDOWN_FAILED = 0x30, 282 MFI_STAT_TIME_NOT_SET = 0x31, 283 MFI_STAT_WRONG_STATE = 0x32, 284 MFI_STAT_LD_OFFLINE = 0x33, 285 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 286 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 287 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 288 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 289 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 290 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67, 291 292 MFI_STAT_INVALID_STATUS = 0xFF 293 }; 294 295 enum mfi_evt_class { 296 MFI_EVT_CLASS_DEBUG = -2, 297 MFI_EVT_CLASS_PROGRESS = -1, 298 MFI_EVT_CLASS_INFO = 0, 299 MFI_EVT_CLASS_WARNING = 1, 300 MFI_EVT_CLASS_CRITICAL = 2, 301 MFI_EVT_CLASS_FATAL = 3, 302 MFI_EVT_CLASS_DEAD = 4 303 }; 304 305 /* 306 * Crash dump related defines 307 */ 308 #define MAX_CRASH_DUMP_SIZE 512 309 #define CRASH_DMA_BUF_SIZE (1024 * 1024) 310 311 enum MR_FW_CRASH_DUMP_STATE { 312 UNAVAILABLE = 0, 313 AVAILABLE = 1, 314 COPYING = 2, 315 COPIED = 3, 316 COPY_ERROR = 4, 317 }; 318 319 enum _MR_CRASH_BUF_STATUS { 320 MR_CRASH_BUF_TURN_OFF = 0, 321 MR_CRASH_BUF_TURN_ON = 1, 322 }; 323 324 /* 325 * Number of mailbox bytes in DCMD message frame 326 */ 327 #define MFI_MBOX_SIZE 12 328 329 enum MR_EVT_CLASS { 330 331 MR_EVT_CLASS_DEBUG = -2, 332 MR_EVT_CLASS_PROGRESS = -1, 333 MR_EVT_CLASS_INFO = 0, 334 MR_EVT_CLASS_WARNING = 1, 335 MR_EVT_CLASS_CRITICAL = 2, 336 MR_EVT_CLASS_FATAL = 3, 337 MR_EVT_CLASS_DEAD = 4, 338 339 }; 340 341 enum MR_EVT_LOCALE { 342 343 MR_EVT_LOCALE_LD = 0x0001, 344 MR_EVT_LOCALE_PD = 0x0002, 345 MR_EVT_LOCALE_ENCL = 0x0004, 346 MR_EVT_LOCALE_BBU = 0x0008, 347 MR_EVT_LOCALE_SAS = 0x0010, 348 MR_EVT_LOCALE_CTRL = 0x0020, 349 MR_EVT_LOCALE_CONFIG = 0x0040, 350 MR_EVT_LOCALE_CLUSTER = 0x0080, 351 MR_EVT_LOCALE_ALL = 0xffff, 352 353 }; 354 355 enum MR_EVT_ARGS { 356 357 MR_EVT_ARGS_NONE, 358 MR_EVT_ARGS_CDB_SENSE, 359 MR_EVT_ARGS_LD, 360 MR_EVT_ARGS_LD_COUNT, 361 MR_EVT_ARGS_LD_LBA, 362 MR_EVT_ARGS_LD_OWNER, 363 MR_EVT_ARGS_LD_LBA_PD_LBA, 364 MR_EVT_ARGS_LD_PROG, 365 MR_EVT_ARGS_LD_STATE, 366 MR_EVT_ARGS_LD_STRIP, 367 MR_EVT_ARGS_PD, 368 MR_EVT_ARGS_PD_ERR, 369 MR_EVT_ARGS_PD_LBA, 370 MR_EVT_ARGS_PD_LBA_LD, 371 MR_EVT_ARGS_PD_PROG, 372 MR_EVT_ARGS_PD_STATE, 373 MR_EVT_ARGS_PCI, 374 MR_EVT_ARGS_RATE, 375 MR_EVT_ARGS_STR, 376 MR_EVT_ARGS_TIME, 377 MR_EVT_ARGS_ECC, 378 MR_EVT_ARGS_LD_PROP, 379 MR_EVT_ARGS_PD_SPARE, 380 MR_EVT_ARGS_PD_INDEX, 381 MR_EVT_ARGS_DIAG_PASS, 382 MR_EVT_ARGS_DIAG_FAIL, 383 MR_EVT_ARGS_PD_LBA_LBA, 384 MR_EVT_ARGS_PORT_PHY, 385 MR_EVT_ARGS_PD_MISSING, 386 MR_EVT_ARGS_PD_ADDRESS, 387 MR_EVT_ARGS_BITMAP, 388 MR_EVT_ARGS_CONNECTOR, 389 MR_EVT_ARGS_PD_PD, 390 MR_EVT_ARGS_PD_FRU, 391 MR_EVT_ARGS_PD_PATHINFO, 392 MR_EVT_ARGS_PD_POWER_STATE, 393 MR_EVT_ARGS_GENERIC, 394 }; 395 396 397 #define SGE_BUFFER_SIZE 4096 398 #define MEGASAS_CLUSTER_ID_SIZE 16 399 /* 400 * define constants for device list query options 401 */ 402 enum MR_PD_QUERY_TYPE { 403 MR_PD_QUERY_TYPE_ALL = 0, 404 MR_PD_QUERY_TYPE_STATE = 1, 405 MR_PD_QUERY_TYPE_POWER_STATE = 2, 406 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 407 MR_PD_QUERY_TYPE_SPEED = 4, 408 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, 409 }; 410 411 enum MR_LD_QUERY_TYPE { 412 MR_LD_QUERY_TYPE_ALL = 0, 413 MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1, 414 MR_LD_QUERY_TYPE_USED_TGT_IDS = 2, 415 MR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3, 416 MR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4, 417 }; 418 419 420 #define MR_EVT_CFG_CLEARED 0x0004 421 #define MR_EVT_LD_STATE_CHANGE 0x0051 422 #define MR_EVT_PD_INSERTED 0x005b 423 #define MR_EVT_PD_REMOVED 0x0070 424 #define MR_EVT_LD_CREATED 0x008a 425 #define MR_EVT_LD_DELETED 0x008b 426 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 427 #define MR_EVT_LD_OFFLINE 0x00fc 428 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 429 #define MR_EVT_CTRL_PROP_CHANGED 0x012f 430 431 enum MR_PD_STATE { 432 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, 433 MR_PD_STATE_UNCONFIGURED_BAD = 0x01, 434 MR_PD_STATE_HOT_SPARE = 0x02, 435 MR_PD_STATE_OFFLINE = 0x10, 436 MR_PD_STATE_FAILED = 0x11, 437 MR_PD_STATE_REBUILD = 0x14, 438 MR_PD_STATE_ONLINE = 0x18, 439 MR_PD_STATE_COPYBACK = 0x20, 440 MR_PD_STATE_SYSTEM = 0x40, 441 }; 442 443 union MR_PD_REF { 444 struct { 445 u16 deviceId; 446 u16 seqNum; 447 } mrPdRef; 448 u32 ref; 449 }; 450 451 /* 452 * define the DDF Type bit structure 453 */ 454 union MR_PD_DDF_TYPE { 455 struct { 456 union { 457 struct { 458 #ifndef __BIG_ENDIAN_BITFIELD 459 u16 forcedPDGUID:1; 460 u16 inVD:1; 461 u16 isGlobalSpare:1; 462 u16 isSpare:1; 463 u16 isForeign:1; 464 u16 reserved:7; 465 u16 intf:4; 466 #else 467 u16 intf:4; 468 u16 reserved:7; 469 u16 isForeign:1; 470 u16 isSpare:1; 471 u16 isGlobalSpare:1; 472 u16 inVD:1; 473 u16 forcedPDGUID:1; 474 #endif 475 } pdType; 476 u16 type; 477 }; 478 u16 reserved; 479 } ddf; 480 struct { 481 u32 reserved; 482 } nonDisk; 483 u32 type; 484 } __packed; 485 486 /* 487 * defines the progress structure 488 */ 489 union MR_PROGRESS { 490 struct { 491 u16 progress; 492 union { 493 u16 elapsedSecs; 494 u16 elapsedSecsForLastPercent; 495 }; 496 } mrProgress; 497 u32 w; 498 } __packed; 499 500 /* 501 * defines the physical drive progress structure 502 */ 503 struct MR_PD_PROGRESS { 504 struct { 505 #ifndef MFI_BIG_ENDIAN 506 u32 rbld:1; 507 u32 patrol:1; 508 u32 clear:1; 509 u32 copyBack:1; 510 u32 erase:1; 511 u32 locate:1; 512 u32 reserved:26; 513 #else 514 u32 reserved:26; 515 u32 locate:1; 516 u32 erase:1; 517 u32 copyBack:1; 518 u32 clear:1; 519 u32 patrol:1; 520 u32 rbld:1; 521 #endif 522 } active; 523 union MR_PROGRESS rbld; 524 union MR_PROGRESS patrol; 525 union { 526 union MR_PROGRESS clear; 527 union MR_PROGRESS erase; 528 }; 529 530 struct { 531 #ifndef MFI_BIG_ENDIAN 532 u32 rbld:1; 533 u32 patrol:1; 534 u32 clear:1; 535 u32 copyBack:1; 536 u32 erase:1; 537 u32 reserved:27; 538 #else 539 u32 reserved:27; 540 u32 erase:1; 541 u32 copyBack:1; 542 u32 clear:1; 543 u32 patrol:1; 544 u32 rbld:1; 545 #endif 546 } pause; 547 548 union MR_PROGRESS reserved[3]; 549 } __packed; 550 551 struct MR_PD_INFO { 552 union MR_PD_REF ref; 553 u8 inquiryData[96]; 554 u8 vpdPage83[64]; 555 u8 notSupported; 556 u8 scsiDevType; 557 558 union { 559 u8 connectedPortBitmap; 560 u8 connectedPortNumbers; 561 }; 562 563 u8 deviceSpeed; 564 u32 mediaErrCount; 565 u32 otherErrCount; 566 u32 predFailCount; 567 u32 lastPredFailEventSeqNum; 568 569 u16 fwState; 570 u8 disabledForRemoval; 571 u8 linkSpeed; 572 union MR_PD_DDF_TYPE state; 573 574 struct { 575 u8 count; 576 #ifndef __BIG_ENDIAN_BITFIELD 577 u8 isPathBroken:4; 578 u8 reserved3:3; 579 u8 widePortCapable:1; 580 #else 581 u8 widePortCapable:1; 582 u8 reserved3:3; 583 u8 isPathBroken:4; 584 #endif 585 586 u8 connectorIndex[2]; 587 u8 reserved[4]; 588 u64 sasAddr[2]; 589 u8 reserved2[16]; 590 } pathInfo; 591 592 u64 rawSize; 593 u64 nonCoercedSize; 594 u64 coercedSize; 595 u16 enclDeviceId; 596 u8 enclIndex; 597 598 union { 599 u8 slotNumber; 600 u8 enclConnectorIndex; 601 }; 602 603 struct MR_PD_PROGRESS progInfo; 604 u8 badBlockTableFull; 605 u8 unusableInCurrentConfig; 606 u8 vpdPage83Ext[64]; 607 u8 powerState; 608 u8 enclPosition; 609 u32 allowedOps; 610 u16 copyBackPartnerId; 611 u16 enclPartnerDeviceId; 612 struct { 613 #ifndef __BIG_ENDIAN_BITFIELD 614 u16 fdeCapable:1; 615 u16 fdeEnabled:1; 616 u16 secured:1; 617 u16 locked:1; 618 u16 foreign:1; 619 u16 needsEKM:1; 620 u16 reserved:10; 621 #else 622 u16 reserved:10; 623 u16 needsEKM:1; 624 u16 foreign:1; 625 u16 locked:1; 626 u16 secured:1; 627 u16 fdeEnabled:1; 628 u16 fdeCapable:1; 629 #endif 630 } security; 631 u8 mediaType; 632 u8 notCertified; 633 u8 bridgeVendor[8]; 634 u8 bridgeProductIdentification[16]; 635 u8 bridgeProductRevisionLevel[4]; 636 u8 satBridgeExists; 637 638 u8 interfaceType; 639 u8 temperature; 640 u8 emulatedBlockSize; 641 u16 userDataBlockSize; 642 u16 reserved2; 643 644 struct { 645 #ifndef __BIG_ENDIAN_BITFIELD 646 u32 piType:3; 647 u32 piFormatted:1; 648 u32 piEligible:1; 649 u32 NCQ:1; 650 u32 WCE:1; 651 u32 commissionedSpare:1; 652 u32 emergencySpare:1; 653 u32 ineligibleForSSCD:1; 654 u32 ineligibleForLd:1; 655 u32 useSSEraseType:1; 656 u32 wceUnchanged:1; 657 u32 supportScsiUnmap:1; 658 u32 reserved:18; 659 #else 660 u32 reserved:18; 661 u32 supportScsiUnmap:1; 662 u32 wceUnchanged:1; 663 u32 useSSEraseType:1; 664 u32 ineligibleForLd:1; 665 u32 ineligibleForSSCD:1; 666 u32 emergencySpare:1; 667 u32 commissionedSpare:1; 668 u32 WCE:1; 669 u32 NCQ:1; 670 u32 piEligible:1; 671 u32 piFormatted:1; 672 u32 piType:3; 673 #endif 674 } properties; 675 676 u64 shieldDiagCompletionTime; 677 u8 shieldCounter; 678 679 u8 linkSpeedOther; 680 u8 reserved4[2]; 681 682 struct { 683 #ifndef __BIG_ENDIAN_BITFIELD 684 u32 bbmErrCountSupported:1; 685 u32 bbmErrCount:31; 686 #else 687 u32 bbmErrCount:31; 688 u32 bbmErrCountSupported:1; 689 #endif 690 } bbmErr; 691 692 u8 reserved1[512-428]; 693 } __packed; 694 695 /* 696 * Definition of structure used to expose attributes of VD or JBOD 697 * (this structure is to be filled by firmware when MR_DCMD_DRV_GET_TARGET_PROP 698 * is fired by driver) 699 */ 700 struct MR_TARGET_PROPERTIES { 701 u32 max_io_size_kb; 702 u32 device_qdepth; 703 u32 sector_size; 704 u8 reset_tmo; 705 u8 reserved[499]; 706 } __packed; 707 708 /* 709 * defines the physical drive address structure 710 */ 711 struct MR_PD_ADDRESS { 712 __le16 deviceId; 713 u16 enclDeviceId; 714 715 union { 716 struct { 717 u8 enclIndex; 718 u8 slotNumber; 719 } mrPdAddress; 720 struct { 721 u8 enclPosition; 722 u8 enclConnectorIndex; 723 } mrEnclAddress; 724 }; 725 u8 scsiDevType; 726 union { 727 u8 connectedPortBitmap; 728 u8 connectedPortNumbers; 729 }; 730 u64 sasAddr[2]; 731 } __packed; 732 733 /* 734 * defines the physical drive list structure 735 */ 736 struct MR_PD_LIST { 737 __le32 size; 738 __le32 count; 739 struct MR_PD_ADDRESS addr[1]; 740 } __packed; 741 742 struct megasas_pd_list { 743 u16 tid; 744 u8 driveType; 745 u8 driveState; 746 } __packed; 747 748 /* 749 * defines the logical drive reference structure 750 */ 751 union MR_LD_REF { 752 struct { 753 u8 targetId; 754 u8 reserved; 755 __le16 seqNum; 756 }; 757 __le32 ref; 758 } __packed; 759 760 /* 761 * defines the logical drive list structure 762 */ 763 struct MR_LD_LIST { 764 __le32 ldCount; 765 __le32 reserved; 766 struct { 767 union MR_LD_REF ref; 768 u8 state; 769 u8 reserved[3]; 770 __le64 size; 771 } ldList[MAX_LOGICAL_DRIVES_EXT]; 772 } __packed; 773 774 struct MR_LD_TARGETID_LIST { 775 __le32 size; 776 __le32 count; 777 u8 pad[3]; 778 u8 targetId[MAX_LOGICAL_DRIVES_EXT]; 779 }; 780 781 struct MR_HOST_DEVICE_LIST_ENTRY { 782 struct { 783 union { 784 struct { 785 #if defined(__BIG_ENDIAN_BITFIELD) 786 u8 reserved:7; 787 u8 is_sys_pd:1; 788 #else 789 u8 is_sys_pd:1; 790 u8 reserved:7; 791 #endif 792 } bits; 793 u8 byte; 794 } u; 795 } flags; 796 u8 scsi_type; 797 __le16 target_id; 798 u8 reserved[4]; 799 __le64 sas_addr[2]; 800 } __packed; 801 802 struct MR_HOST_DEVICE_LIST { 803 __le32 size; 804 __le32 count; 805 __le32 reserved[2]; 806 struct MR_HOST_DEVICE_LIST_ENTRY host_device_list[1]; 807 } __packed; 808 809 #define HOST_DEVICE_LIST_SZ (sizeof(struct MR_HOST_DEVICE_LIST) + \ 810 (sizeof(struct MR_HOST_DEVICE_LIST_ENTRY) * \ 811 (MEGASAS_MAX_PD + MAX_LOGICAL_DRIVES_EXT - 1))) 812 813 814 /* 815 * SAS controller properties 816 */ 817 struct megasas_ctrl_prop { 818 819 u16 seq_num; 820 u16 pred_fail_poll_interval; 821 u16 intr_throttle_count; 822 u16 intr_throttle_timeouts; 823 u8 rebuild_rate; 824 u8 patrol_read_rate; 825 u8 bgi_rate; 826 u8 cc_rate; 827 u8 recon_rate; 828 u8 cache_flush_interval; 829 u8 spinup_drv_count; 830 u8 spinup_delay; 831 u8 cluster_enable; 832 u8 coercion_mode; 833 u8 alarm_enable; 834 u8 disable_auto_rebuild; 835 u8 disable_battery_warn; 836 u8 ecc_bucket_size; 837 u16 ecc_bucket_leak_rate; 838 u8 restore_hotspare_on_insertion; 839 u8 expose_encl_devices; 840 u8 maintainPdFailHistory; 841 u8 disallowHostRequestReordering; 842 u8 abortCCOnError; 843 u8 loadBalanceMode; 844 u8 disableAutoDetectBackplane; 845 846 u8 snapVDSpace; 847 848 /* 849 * Add properties that can be controlled by 850 * a bit in the following structure. 851 */ 852 struct { 853 #if defined(__BIG_ENDIAN_BITFIELD) 854 u32 reserved:18; 855 u32 enableJBOD:1; 856 u32 disableSpinDownHS:1; 857 u32 allowBootWithPinnedCache:1; 858 u32 disableOnlineCtrlReset:1; 859 u32 enableSecretKeyControl:1; 860 u32 autoEnhancedImport:1; 861 u32 enableSpinDownUnconfigured:1; 862 u32 SSDPatrolReadEnabled:1; 863 u32 SSDSMARTerEnabled:1; 864 u32 disableNCQ:1; 865 u32 useFdeOnly:1; 866 u32 prCorrectUnconfiguredAreas:1; 867 u32 SMARTerEnabled:1; 868 u32 copyBackDisabled:1; 869 #else 870 u32 copyBackDisabled:1; 871 u32 SMARTerEnabled:1; 872 u32 prCorrectUnconfiguredAreas:1; 873 u32 useFdeOnly:1; 874 u32 disableNCQ:1; 875 u32 SSDSMARTerEnabled:1; 876 u32 SSDPatrolReadEnabled:1; 877 u32 enableSpinDownUnconfigured:1; 878 u32 autoEnhancedImport:1; 879 u32 enableSecretKeyControl:1; 880 u32 disableOnlineCtrlReset:1; 881 u32 allowBootWithPinnedCache:1; 882 u32 disableSpinDownHS:1; 883 u32 enableJBOD:1; 884 u32 reserved:18; 885 #endif 886 } OnOffProperties; 887 888 union { 889 u8 autoSnapVDSpace; 890 u8 viewSpace; 891 struct { 892 #if defined(__BIG_ENDIAN_BITFIELD) 893 u16 reserved3:9; 894 u16 enable_fw_dev_list:1; 895 u16 reserved2:1; 896 u16 enable_snap_dump:1; 897 u16 reserved1:4; 898 #else 899 u16 reserved1:4; 900 u16 enable_snap_dump:1; 901 u16 reserved2:1; 902 u16 enable_fw_dev_list:1; 903 u16 reserved3:9; 904 #endif 905 } on_off_properties2; 906 }; 907 __le16 spinDownTime; 908 u8 reserved[24]; 909 } __packed; 910 911 /* 912 * SAS controller information 913 */ 914 struct megasas_ctrl_info { 915 916 /* 917 * PCI device information 918 */ 919 struct { 920 921 __le16 vendor_id; 922 __le16 device_id; 923 __le16 sub_vendor_id; 924 __le16 sub_device_id; 925 u8 reserved[24]; 926 927 } __attribute__ ((packed)) pci; 928 929 /* 930 * Host interface information 931 */ 932 struct { 933 934 u8 PCIX:1; 935 u8 PCIE:1; 936 u8 iSCSI:1; 937 u8 SAS_3G:1; 938 u8 SRIOV:1; 939 u8 reserved_0:3; 940 u8 reserved_1[6]; 941 u8 port_count; 942 u64 port_addr[8]; 943 944 } __attribute__ ((packed)) host_interface; 945 946 /* 947 * Device (backend) interface information 948 */ 949 struct { 950 951 u8 SPI:1; 952 u8 SAS_3G:1; 953 u8 SATA_1_5G:1; 954 u8 SATA_3G:1; 955 u8 reserved_0:4; 956 u8 reserved_1[6]; 957 u8 port_count; 958 u64 port_addr[8]; 959 960 } __attribute__ ((packed)) device_interface; 961 962 /* 963 * List of components residing in flash. All str are null terminated 964 */ 965 __le32 image_check_word; 966 __le32 image_component_count; 967 968 struct { 969 970 char name[8]; 971 char version[32]; 972 char build_date[16]; 973 char built_time[16]; 974 975 } __attribute__ ((packed)) image_component[8]; 976 977 /* 978 * List of flash components that have been flashed on the card, but 979 * are not in use, pending reset of the adapter. This list will be 980 * empty if a flash operation has not occurred. All stings are null 981 * terminated 982 */ 983 __le32 pending_image_component_count; 984 985 struct { 986 987 char name[8]; 988 char version[32]; 989 char build_date[16]; 990 char build_time[16]; 991 992 } __attribute__ ((packed)) pending_image_component[8]; 993 994 u8 max_arms; 995 u8 max_spans; 996 u8 max_arrays; 997 u8 max_lds; 998 999 char product_name[80]; 1000 char serial_no[32]; 1001 1002 /* 1003 * Other physical/controller/operation information. Indicates the 1004 * presence of the hardware 1005 */ 1006 struct { 1007 1008 u32 bbu:1; 1009 u32 alarm:1; 1010 u32 nvram:1; 1011 u32 uart:1; 1012 u32 reserved:28; 1013 1014 } __attribute__ ((packed)) hw_present; 1015 1016 __le32 current_fw_time; 1017 1018 /* 1019 * Maximum data transfer sizes 1020 */ 1021 __le16 max_concurrent_cmds; 1022 __le16 max_sge_count; 1023 __le32 max_request_size; 1024 1025 /* 1026 * Logical and physical device counts 1027 */ 1028 __le16 ld_present_count; 1029 __le16 ld_degraded_count; 1030 __le16 ld_offline_count; 1031 1032 __le16 pd_present_count; 1033 __le16 pd_disk_present_count; 1034 __le16 pd_disk_pred_failure_count; 1035 __le16 pd_disk_failed_count; 1036 1037 /* 1038 * Memory size information 1039 */ 1040 __le16 nvram_size; 1041 __le16 memory_size; 1042 __le16 flash_size; 1043 1044 /* 1045 * Error counters 1046 */ 1047 __le16 mem_correctable_error_count; 1048 __le16 mem_uncorrectable_error_count; 1049 1050 /* 1051 * Cluster information 1052 */ 1053 u8 cluster_permitted; 1054 u8 cluster_active; 1055 1056 /* 1057 * Additional max data transfer sizes 1058 */ 1059 __le16 max_strips_per_io; 1060 1061 /* 1062 * Controller capabilities structures 1063 */ 1064 struct { 1065 1066 u32 raid_level_0:1; 1067 u32 raid_level_1:1; 1068 u32 raid_level_5:1; 1069 u32 raid_level_1E:1; 1070 u32 raid_level_6:1; 1071 u32 reserved:27; 1072 1073 } __attribute__ ((packed)) raid_levels; 1074 1075 struct { 1076 1077 u32 rbld_rate:1; 1078 u32 cc_rate:1; 1079 u32 bgi_rate:1; 1080 u32 recon_rate:1; 1081 u32 patrol_rate:1; 1082 u32 alarm_control:1; 1083 u32 cluster_supported:1; 1084 u32 bbu:1; 1085 u32 spanning_allowed:1; 1086 u32 dedicated_hotspares:1; 1087 u32 revertible_hotspares:1; 1088 u32 foreign_config_import:1; 1089 u32 self_diagnostic:1; 1090 u32 mixed_redundancy_arr:1; 1091 u32 global_hot_spares:1; 1092 u32 reserved:17; 1093 1094 } __attribute__ ((packed)) adapter_operations; 1095 1096 struct { 1097 1098 u32 read_policy:1; 1099 u32 write_policy:1; 1100 u32 io_policy:1; 1101 u32 access_policy:1; 1102 u32 disk_cache_policy:1; 1103 u32 reserved:27; 1104 1105 } __attribute__ ((packed)) ld_operations; 1106 1107 struct { 1108 1109 u8 min; 1110 u8 max; 1111 u8 reserved[2]; 1112 1113 } __attribute__ ((packed)) stripe_sz_ops; 1114 1115 struct { 1116 1117 u32 force_online:1; 1118 u32 force_offline:1; 1119 u32 force_rebuild:1; 1120 u32 reserved:29; 1121 1122 } __attribute__ ((packed)) pd_operations; 1123 1124 struct { 1125 1126 u32 ctrl_supports_sas:1; 1127 u32 ctrl_supports_sata:1; 1128 u32 allow_mix_in_encl:1; 1129 u32 allow_mix_in_ld:1; 1130 u32 allow_sata_in_cluster:1; 1131 u32 reserved:27; 1132 1133 } __attribute__ ((packed)) pd_mix_support; 1134 1135 /* 1136 * Define ECC single-bit-error bucket information 1137 */ 1138 u8 ecc_bucket_count; 1139 u8 reserved_2[11]; 1140 1141 /* 1142 * Include the controller properties (changeable items) 1143 */ 1144 struct megasas_ctrl_prop properties; 1145 1146 /* 1147 * Define FW pkg version (set in envt v'bles on OEM basis) 1148 */ 1149 char package_version[0x60]; 1150 1151 1152 /* 1153 * If adapterOperations.supportMoreThan8Phys is set, 1154 * and deviceInterface.portCount is greater than 8, 1155 * SAS Addrs for first 8 ports shall be populated in 1156 * deviceInterface.portAddr, and the rest shall be 1157 * populated in deviceInterfacePortAddr2. 1158 */ 1159 __le64 deviceInterfacePortAddr2[8]; /*6a0h */ 1160 u8 reserved3[128]; /*6e0h */ 1161 1162 struct { /*760h */ 1163 u16 minPdRaidLevel_0:4; 1164 u16 maxPdRaidLevel_0:12; 1165 1166 u16 minPdRaidLevel_1:4; 1167 u16 maxPdRaidLevel_1:12; 1168 1169 u16 minPdRaidLevel_5:4; 1170 u16 maxPdRaidLevel_5:12; 1171 1172 u16 minPdRaidLevel_1E:4; 1173 u16 maxPdRaidLevel_1E:12; 1174 1175 u16 minPdRaidLevel_6:4; 1176 u16 maxPdRaidLevel_6:12; 1177 1178 u16 minPdRaidLevel_10:4; 1179 u16 maxPdRaidLevel_10:12; 1180 1181 u16 minPdRaidLevel_50:4; 1182 u16 maxPdRaidLevel_50:12; 1183 1184 u16 minPdRaidLevel_60:4; 1185 u16 maxPdRaidLevel_60:12; 1186 1187 u16 minPdRaidLevel_1E_RLQ0:4; 1188 u16 maxPdRaidLevel_1E_RLQ0:12; 1189 1190 u16 minPdRaidLevel_1E0_RLQ0:4; 1191 u16 maxPdRaidLevel_1E0_RLQ0:12; 1192 1193 u16 reserved[6]; 1194 } pdsForRaidLevels; 1195 1196 __le16 maxPds; /*780h */ 1197 __le16 maxDedHSPs; /*782h */ 1198 __le16 maxGlobalHSP; /*784h */ 1199 __le16 ddfSize; /*786h */ 1200 u8 maxLdsPerArray; /*788h */ 1201 u8 partitionsInDDF; /*789h */ 1202 u8 lockKeyBinding; /*78ah */ 1203 u8 maxPITsPerLd; /*78bh */ 1204 u8 maxViewsPerLd; /*78ch */ 1205 u8 maxTargetId; /*78dh */ 1206 __le16 maxBvlVdSize; /*78eh */ 1207 1208 __le16 maxConfigurableSSCSize; /*790h */ 1209 __le16 currentSSCsize; /*792h */ 1210 1211 char expanderFwVersion[12]; /*794h */ 1212 1213 __le16 PFKTrialTimeRemaining; /*7A0h */ 1214 1215 __le16 cacheMemorySize; /*7A2h */ 1216 1217 struct { /*7A4h */ 1218 #if defined(__BIG_ENDIAN_BITFIELD) 1219 u32 reserved:5; 1220 u32 activePassive:2; 1221 u32 supportConfigAutoBalance:1; 1222 u32 mpio:1; 1223 u32 supportDataLDonSSCArray:1; 1224 u32 supportPointInTimeProgress:1; 1225 u32 supportUnevenSpans:1; 1226 u32 dedicatedHotSparesLimited:1; 1227 u32 headlessMode:1; 1228 u32 supportEmulatedDrives:1; 1229 u32 supportResetNow:1; 1230 u32 realTimeScheduler:1; 1231 u32 supportSSDPatrolRead:1; 1232 u32 supportPerfTuning:1; 1233 u32 disableOnlinePFKChange:1; 1234 u32 supportJBOD:1; 1235 u32 supportBootTimePFKChange:1; 1236 u32 supportSetLinkSpeed:1; 1237 u32 supportEmergencySpares:1; 1238 u32 supportSuspendResumeBGops:1; 1239 u32 blockSSDWriteCacheChange:1; 1240 u32 supportShieldState:1; 1241 u32 supportLdBBMInfo:1; 1242 u32 supportLdPIType3:1; 1243 u32 supportLdPIType2:1; 1244 u32 supportLdPIType1:1; 1245 u32 supportPIcontroller:1; 1246 #else 1247 u32 supportPIcontroller:1; 1248 u32 supportLdPIType1:1; 1249 u32 supportLdPIType2:1; 1250 u32 supportLdPIType3:1; 1251 u32 supportLdBBMInfo:1; 1252 u32 supportShieldState:1; 1253 u32 blockSSDWriteCacheChange:1; 1254 u32 supportSuspendResumeBGops:1; 1255 u32 supportEmergencySpares:1; 1256 u32 supportSetLinkSpeed:1; 1257 u32 supportBootTimePFKChange:1; 1258 u32 supportJBOD:1; 1259 u32 disableOnlinePFKChange:1; 1260 u32 supportPerfTuning:1; 1261 u32 supportSSDPatrolRead:1; 1262 u32 realTimeScheduler:1; 1263 1264 u32 supportResetNow:1; 1265 u32 supportEmulatedDrives:1; 1266 u32 headlessMode:1; 1267 u32 dedicatedHotSparesLimited:1; 1268 1269 1270 u32 supportUnevenSpans:1; 1271 u32 supportPointInTimeProgress:1; 1272 u32 supportDataLDonSSCArray:1; 1273 u32 mpio:1; 1274 u32 supportConfigAutoBalance:1; 1275 u32 activePassive:2; 1276 u32 reserved:5; 1277 #endif 1278 } adapterOperations2; 1279 1280 u8 driverVersion[32]; /*7A8h */ 1281 u8 maxDAPdCountSpinup60; /*7C8h */ 1282 u8 temperatureROC; /*7C9h */ 1283 u8 temperatureCtrl; /*7CAh */ 1284 u8 reserved4; /*7CBh */ 1285 __le16 maxConfigurablePds; /*7CCh */ 1286 1287 1288 u8 reserved5[2]; /*0x7CDh */ 1289 1290 /* 1291 * HA cluster information 1292 */ 1293 struct { 1294 #if defined(__BIG_ENDIAN_BITFIELD) 1295 u32 reserved:25; 1296 u32 passive:1; 1297 u32 premiumFeatureMismatch:1; 1298 u32 ctrlPropIncompatible:1; 1299 u32 fwVersionMismatch:1; 1300 u32 hwIncompatible:1; 1301 u32 peerIsIncompatible:1; 1302 u32 peerIsPresent:1; 1303 #else 1304 u32 peerIsPresent:1; 1305 u32 peerIsIncompatible:1; 1306 u32 hwIncompatible:1; 1307 u32 fwVersionMismatch:1; 1308 u32 ctrlPropIncompatible:1; 1309 u32 premiumFeatureMismatch:1; 1310 u32 passive:1; 1311 u32 reserved:25; 1312 #endif 1313 } cluster; 1314 1315 char clusterId[MEGASAS_CLUSTER_ID_SIZE]; /*0x7D4 */ 1316 struct { 1317 u8 maxVFsSupported; /*0x7E4*/ 1318 u8 numVFsEnabled; /*0x7E5*/ 1319 u8 requestorId; /*0x7E6 0:PF, 1:VF1, 2:VF2*/ 1320 u8 reserved; /*0x7E7*/ 1321 } iov; 1322 1323 struct { 1324 #if defined(__BIG_ENDIAN_BITFIELD) 1325 u32 reserved:7; 1326 u32 useSeqNumJbodFP:1; 1327 u32 supportExtendedSSCSize:1; 1328 u32 supportDiskCacheSettingForSysPDs:1; 1329 u32 supportCPLDUpdate:1; 1330 u32 supportTTYLogCompression:1; 1331 u32 discardCacheDuringLDDelete:1; 1332 u32 supportSecurityonJBOD:1; 1333 u32 supportCacheBypassModes:1; 1334 u32 supportDisableSESMonitoring:1; 1335 u32 supportForceFlash:1; 1336 u32 supportNVDRAM:1; 1337 u32 supportDrvActivityLEDSetting:1; 1338 u32 supportAllowedOpsforDrvRemoval:1; 1339 u32 supportHOQRebuild:1; 1340 u32 supportForceTo512e:1; 1341 u32 supportNVCacheErase:1; 1342 u32 supportDebugQueue:1; 1343 u32 supportSwZone:1; 1344 u32 supportCrashDump:1; 1345 u32 supportMaxExtLDs:1; 1346 u32 supportT10RebuildAssist:1; 1347 u32 supportDisableImmediateIO:1; 1348 u32 supportThermalPollInterval:1; 1349 u32 supportPersonalityChange:2; 1350 #else 1351 u32 supportPersonalityChange:2; 1352 u32 supportThermalPollInterval:1; 1353 u32 supportDisableImmediateIO:1; 1354 u32 supportT10RebuildAssist:1; 1355 u32 supportMaxExtLDs:1; 1356 u32 supportCrashDump:1; 1357 u32 supportSwZone:1; 1358 u32 supportDebugQueue:1; 1359 u32 supportNVCacheErase:1; 1360 u32 supportForceTo512e:1; 1361 u32 supportHOQRebuild:1; 1362 u32 supportAllowedOpsforDrvRemoval:1; 1363 u32 supportDrvActivityLEDSetting:1; 1364 u32 supportNVDRAM:1; 1365 u32 supportForceFlash:1; 1366 u32 supportDisableSESMonitoring:1; 1367 u32 supportCacheBypassModes:1; 1368 u32 supportSecurityonJBOD:1; 1369 u32 discardCacheDuringLDDelete:1; 1370 u32 supportTTYLogCompression:1; 1371 u32 supportCPLDUpdate:1; 1372 u32 supportDiskCacheSettingForSysPDs:1; 1373 u32 supportExtendedSSCSize:1; 1374 u32 useSeqNumJbodFP:1; 1375 u32 reserved:7; 1376 #endif 1377 } adapterOperations3; 1378 1379 struct { 1380 #if defined(__BIG_ENDIAN_BITFIELD) 1381 u8 reserved:7; 1382 /* Indicates whether the CPLD image is part of 1383 * the package and stored in flash 1384 */ 1385 u8 cpld_in_flash:1; 1386 #else 1387 u8 cpld_in_flash:1; 1388 u8 reserved:7; 1389 #endif 1390 u8 reserved1[3]; 1391 /* Null terminated string. Has the version 1392 * information if cpld_in_flash = FALSE 1393 */ 1394 u8 userCodeDefinition[12]; 1395 } cpld; /* Valid only if upgradableCPLD is TRUE */ 1396 1397 struct { 1398 #if defined(__BIG_ENDIAN_BITFIELD) 1399 u16 reserved:2; 1400 u16 support_nvme_passthru:1; 1401 u16 support_pl_debug_info:1; 1402 u16 support_flash_comp_info:1; 1403 u16 support_host_info:1; 1404 u16 support_dual_fw_update:1; 1405 u16 support_ssc_rev3:1; 1406 u16 fw_swaps_bbu_vpd_info:1; 1407 u16 support_pd_map_target_id:1; 1408 u16 support_ses_ctrl_in_multipathcfg:1; 1409 u16 image_upload_supported:1; 1410 u16 support_encrypted_mfc:1; 1411 u16 supported_enc_algo:1; 1412 u16 support_ibutton_less:1; 1413 u16 ctrl_info_ext_supported:1; 1414 #else 1415 1416 u16 ctrl_info_ext_supported:1; 1417 u16 support_ibutton_less:1; 1418 u16 supported_enc_algo:1; 1419 u16 support_encrypted_mfc:1; 1420 u16 image_upload_supported:1; 1421 /* FW supports LUN based association and target port based */ 1422 u16 support_ses_ctrl_in_multipathcfg:1; 1423 /* association for the SES device connected in multipath mode */ 1424 /* FW defines Jbod target Id within MR_PD_CFG_SEQ */ 1425 u16 support_pd_map_target_id:1; 1426 /* FW swaps relevant fields in MR_BBU_VPD_INFO_FIXED to 1427 * provide the data in little endian order 1428 */ 1429 u16 fw_swaps_bbu_vpd_info:1; 1430 u16 support_ssc_rev3:1; 1431 /* FW supports CacheCade 3.0, only one SSCD creation allowed */ 1432 u16 support_dual_fw_update:1; 1433 /* FW supports dual firmware update feature */ 1434 u16 support_host_info:1; 1435 /* FW supports MR_DCMD_CTRL_HOST_INFO_SET/GET */ 1436 u16 support_flash_comp_info:1; 1437 /* FW supports MR_DCMD_CTRL_FLASH_COMP_INFO_GET */ 1438 u16 support_pl_debug_info:1; 1439 /* FW supports retrieval of PL debug information through apps */ 1440 u16 support_nvme_passthru:1; 1441 /* FW supports NVMe passthru commands */ 1442 u16 reserved:2; 1443 #endif 1444 } adapter_operations4; 1445 u8 pad[0x800 - 0x7FE]; /* 0x7FE pad to 2K for expansion */ 1446 1447 u32 size; 1448 u32 pad1; 1449 1450 u8 reserved6[64]; 1451 1452 u32 rsvdForAdptOp[64]; 1453 1454 u8 reserved7[3]; 1455 1456 u8 TaskAbortTO; /* Timeout value in seconds used by Abort Task TM */ 1457 u8 MaxResetTO; /* Max Supported Reset timeout in seconds. */ 1458 u8 reserved8[3]; 1459 } __packed; 1460 1461 /* 1462 * =============================== 1463 * MegaRAID SAS driver definitions 1464 * =============================== 1465 */ 1466 #define MEGASAS_MAX_PD_CHANNELS 2 1467 #define MEGASAS_MAX_LD_CHANNELS 2 1468 #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \ 1469 MEGASAS_MAX_LD_CHANNELS) 1470 #define MEGASAS_MAX_DEV_PER_CHANNEL 128 1471 #define MEGASAS_DEFAULT_INIT_ID -1 1472 #define MEGASAS_MAX_LUN 8 1473 #define MEGASAS_DEFAULT_CMD_PER_LUN 256 1474 #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \ 1475 MEGASAS_MAX_DEV_PER_CHANNEL) 1476 #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \ 1477 MEGASAS_MAX_DEV_PER_CHANNEL) 1478 1479 #define MEGASAS_MAX_SECTORS (2*1024) 1480 #define MEGASAS_MAX_SECTORS_IEEE (2*128) 1481 #define MEGASAS_DBG_LVL 1 1482 1483 #define MEGASAS_FW_BUSY 1 1484 1485 /* Driver's internal Logging levels*/ 1486 #define OCR_LOGS (1 << 0) 1487 1488 #define SCAN_PD_CHANNEL 0x1 1489 #define SCAN_VD_CHANNEL 0x2 1490 1491 #define MEGASAS_KDUMP_QUEUE_DEPTH 100 1492 #define MR_LARGE_IO_MIN_SIZE (32 * 1024) 1493 #define MR_R1_LDIO_PIGGYBACK_DEFAULT 4 1494 1495 enum MR_SCSI_CMD_TYPE { 1496 READ_WRITE_LDIO = 0, 1497 NON_READ_WRITE_LDIO = 1, 1498 READ_WRITE_SYSPDIO = 2, 1499 NON_READ_WRITE_SYSPDIO = 3, 1500 }; 1501 1502 enum DCMD_TIMEOUT_ACTION { 1503 INITIATE_OCR = 0, 1504 KILL_ADAPTER = 1, 1505 IGNORE_TIMEOUT = 2, 1506 }; 1507 1508 enum FW_BOOT_CONTEXT { 1509 PROBE_CONTEXT = 0, 1510 OCR_CONTEXT = 1, 1511 }; 1512 1513 /* Frame Type */ 1514 #define IO_FRAME 0 1515 #define PTHRU_FRAME 1 1516 1517 /* 1518 * When SCSI mid-layer calls driver's reset routine, driver waits for 1519 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 1520 * that the driver cannot _actually_ abort or reset pending commands. While 1521 * it is waiting for the commands to complete, it prints a diagnostic message 1522 * every MEGASAS_RESET_NOTICE_INTERVAL seconds 1523 */ 1524 #define MEGASAS_RESET_WAIT_TIME 180 1525 #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180 1526 #define MEGASAS_RESET_NOTICE_INTERVAL 5 1527 #define MEGASAS_IOCTL_CMD 0 1528 #define MEGASAS_DEFAULT_CMD_TIMEOUT 90 1529 #define MEGASAS_THROTTLE_QUEUE_DEPTH 16 1530 #define MEGASAS_DEFAULT_TM_TIMEOUT 50 1531 /* 1532 * FW reports the maximum of number of commands that it can accept (maximum 1533 * commands that can be outstanding) at any time. The driver must report a 1534 * lower number to the mid layer because it can issue a few internal commands 1535 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 1536 * is shown below 1537 */ 1538 #define MEGASAS_INT_CMDS 32 1539 #define MEGASAS_SKINNY_INT_CMDS 5 1540 #define MEGASAS_FUSION_INTERNAL_CMDS 8 1541 #define MEGASAS_FUSION_IOCTL_CMDS 3 1542 #define MEGASAS_MFI_IOCTL_CMDS 27 1543 1544 #define MEGASAS_MAX_MSIX_QUEUES 128 1545 /* 1546 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 1547 * SGLs based on the size of dma_addr_t 1548 */ 1549 #define IS_DMA64 (sizeof(dma_addr_t) == 8) 1550 1551 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 1552 1553 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 1554 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 1555 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 1556 1557 #define MFI_OB_INTR_STATUS_MASK 0x00000002 1558 #define MFI_POLL_TIMEOUT_SECS 60 1559 #define MFI_IO_TIMEOUT_SECS 180 1560 #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF (5 * HZ) 1561 #define MEGASAS_OCR_SETTLE_TIME_VF (1000 * 30) 1562 #define MEGASAS_ROUTINE_WAIT_TIME_VF 300 1563 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 1564 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 1565 #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004) 1566 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 1567 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 1568 1569 #define MFI_1068_PCSR_OFFSET 0x84 1570 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 1571 #define MFI_1068_FW_READY 0xDDDD0000 1572 1573 #define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F 1574 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000 1575 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14 1576 #define MR_MAX_MSIX_REG_ARRAY 16 1577 #define MR_RDPQ_MODE_OFFSET 0X00800000 1578 1579 #define MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT 16 1580 #define MR_MAX_RAID_MAP_SIZE_MASK 0x1FF 1581 #define MR_MIN_MAP_SIZE 0x10000 1582 /* 64k */ 1583 1584 #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET 0X01000000 1585 1586 #define MR_CAN_HANDLE_64_BIT_DMA_OFFSET (1 << 25) 1587 1588 #define MEGASAS_WATCHDOG_THREAD_INTERVAL 1000 1589 #define MEGASAS_WAIT_FOR_NEXT_DMA_MSECS 20 1590 #define MEGASAS_WATCHDOG_WAIT_COUNT 50 1591 1592 enum MR_ADAPTER_TYPE { 1593 MFI_SERIES = 1, 1594 THUNDERBOLT_SERIES = 2, 1595 INVADER_SERIES = 3, 1596 VENTURA_SERIES = 4, 1597 AERO_SERIES = 5, 1598 }; 1599 1600 /* 1601 * register set for both 1068 and 1078 controllers 1602 * structure extended for 1078 registers 1603 */ 1604 1605 struct megasas_register_set { 1606 u32 doorbell; /*0000h*/ 1607 u32 fusion_seq_offset; /*0004h*/ 1608 u32 fusion_host_diag; /*0008h*/ 1609 u32 reserved_01; /*000Ch*/ 1610 1611 u32 inbound_msg_0; /*0010h*/ 1612 u32 inbound_msg_1; /*0014h*/ 1613 u32 outbound_msg_0; /*0018h*/ 1614 u32 outbound_msg_1; /*001Ch*/ 1615 1616 u32 inbound_doorbell; /*0020h*/ 1617 u32 inbound_intr_status; /*0024h*/ 1618 u32 inbound_intr_mask; /*0028h*/ 1619 1620 u32 outbound_doorbell; /*002Ch*/ 1621 u32 outbound_intr_status; /*0030h*/ 1622 u32 outbound_intr_mask; /*0034h*/ 1623 1624 u32 reserved_1[2]; /*0038h*/ 1625 1626 u32 inbound_queue_port; /*0040h*/ 1627 u32 outbound_queue_port; /*0044h*/ 1628 1629 u32 reserved_2[9]; /*0048h*/ 1630 u32 reply_post_host_index; /*006Ch*/ 1631 u32 reserved_2_2[12]; /*0070h*/ 1632 1633 u32 outbound_doorbell_clear; /*00A0h*/ 1634 1635 u32 reserved_3[3]; /*00A4h*/ 1636 1637 u32 outbound_scratch_pad_0; /*00B0h*/ 1638 u32 outbound_scratch_pad_1; /*00B4h*/ 1639 u32 outbound_scratch_pad_2; /*00B8h*/ 1640 u32 outbound_scratch_pad_3; /*00BCh*/ 1641 1642 u32 inbound_low_queue_port ; /*00C0h*/ 1643 1644 u32 inbound_high_queue_port ; /*00C4h*/ 1645 1646 u32 inbound_single_queue_port; /*00C8h*/ 1647 u32 res_6[11]; /*CCh*/ 1648 u32 host_diag; 1649 u32 seq_offset; 1650 u32 index_registers[807]; /*00CCh*/ 1651 } __attribute__ ((packed)); 1652 1653 struct megasas_sge32 { 1654 1655 __le32 phys_addr; 1656 __le32 length; 1657 1658 } __attribute__ ((packed)); 1659 1660 struct megasas_sge64 { 1661 1662 __le64 phys_addr; 1663 __le32 length; 1664 1665 } __attribute__ ((packed)); 1666 1667 struct megasas_sge_skinny { 1668 __le64 phys_addr; 1669 __le32 length; 1670 __le32 flag; 1671 } __packed; 1672 1673 union megasas_sgl { 1674 1675 struct megasas_sge32 sge32[1]; 1676 struct megasas_sge64 sge64[1]; 1677 struct megasas_sge_skinny sge_skinny[1]; 1678 1679 } __attribute__ ((packed)); 1680 1681 struct megasas_header { 1682 1683 u8 cmd; /*00h */ 1684 u8 sense_len; /*01h */ 1685 u8 cmd_status; /*02h */ 1686 u8 scsi_status; /*03h */ 1687 1688 u8 target_id; /*04h */ 1689 u8 lun; /*05h */ 1690 u8 cdb_len; /*06h */ 1691 u8 sge_count; /*07h */ 1692 1693 __le32 context; /*08h */ 1694 __le32 pad_0; /*0Ch */ 1695 1696 __le16 flags; /*10h */ 1697 __le16 timeout; /*12h */ 1698 __le32 data_xferlen; /*14h */ 1699 1700 } __attribute__ ((packed)); 1701 1702 union megasas_sgl_frame { 1703 1704 struct megasas_sge32 sge32[8]; 1705 struct megasas_sge64 sge64[5]; 1706 1707 } __attribute__ ((packed)); 1708 1709 typedef union _MFI_CAPABILITIES { 1710 struct { 1711 #if defined(__BIG_ENDIAN_BITFIELD) 1712 u32 reserved:16; 1713 u32 support_fw_exposed_dev_list:1; 1714 u32 support_nvme_passthru:1; 1715 u32 support_64bit_mode:1; 1716 u32 support_pd_map_target_id:1; 1717 u32 support_qd_throttling:1; 1718 u32 support_fp_rlbypass:1; 1719 u32 support_vfid_in_ioframe:1; 1720 u32 support_ext_io_size:1; 1721 u32 support_ext_queue_depth:1; 1722 u32 security_protocol_cmds_fw:1; 1723 u32 support_core_affinity:1; 1724 u32 support_ndrive_r1_lb:1; 1725 u32 support_max_255lds:1; 1726 u32 support_fastpath_wb:1; 1727 u32 support_additional_msix:1; 1728 u32 support_fp_remote_lun:1; 1729 #else 1730 u32 support_fp_remote_lun:1; 1731 u32 support_additional_msix:1; 1732 u32 support_fastpath_wb:1; 1733 u32 support_max_255lds:1; 1734 u32 support_ndrive_r1_lb:1; 1735 u32 support_core_affinity:1; 1736 u32 security_protocol_cmds_fw:1; 1737 u32 support_ext_queue_depth:1; 1738 u32 support_ext_io_size:1; 1739 u32 support_vfid_in_ioframe:1; 1740 u32 support_fp_rlbypass:1; 1741 u32 support_qd_throttling:1; 1742 u32 support_pd_map_target_id:1; 1743 u32 support_64bit_mode:1; 1744 u32 support_nvme_passthru:1; 1745 u32 support_fw_exposed_dev_list:1; 1746 u32 reserved:16; 1747 #endif 1748 } mfi_capabilities; 1749 __le32 reg; 1750 } MFI_CAPABILITIES; 1751 1752 struct megasas_init_frame { 1753 1754 u8 cmd; /*00h */ 1755 u8 reserved_0; /*01h */ 1756 u8 cmd_status; /*02h */ 1757 1758 u8 reserved_1; /*03h */ 1759 MFI_CAPABILITIES driver_operations; /*04h*/ 1760 1761 __le32 context; /*08h */ 1762 __le32 pad_0; /*0Ch */ 1763 1764 __le16 flags; /*10h */ 1765 __le16 reserved_3; /*12h */ 1766 __le32 data_xfer_len; /*14h */ 1767 1768 __le32 queue_info_new_phys_addr_lo; /*18h */ 1769 __le32 queue_info_new_phys_addr_hi; /*1Ch */ 1770 __le32 queue_info_old_phys_addr_lo; /*20h */ 1771 __le32 queue_info_old_phys_addr_hi; /*24h */ 1772 __le32 reserved_4[2]; /*28h */ 1773 __le32 system_info_lo; /*30h */ 1774 __le32 system_info_hi; /*34h */ 1775 __le32 reserved_5[2]; /*38h */ 1776 1777 } __attribute__ ((packed)); 1778 1779 struct megasas_init_queue_info { 1780 1781 __le32 init_flags; /*00h */ 1782 __le32 reply_queue_entries; /*04h */ 1783 1784 __le32 reply_queue_start_phys_addr_lo; /*08h */ 1785 __le32 reply_queue_start_phys_addr_hi; /*0Ch */ 1786 __le32 producer_index_phys_addr_lo; /*10h */ 1787 __le32 producer_index_phys_addr_hi; /*14h */ 1788 __le32 consumer_index_phys_addr_lo; /*18h */ 1789 __le32 consumer_index_phys_addr_hi; /*1Ch */ 1790 1791 } __attribute__ ((packed)); 1792 1793 struct megasas_io_frame { 1794 1795 u8 cmd; /*00h */ 1796 u8 sense_len; /*01h */ 1797 u8 cmd_status; /*02h */ 1798 u8 scsi_status; /*03h */ 1799 1800 u8 target_id; /*04h */ 1801 u8 access_byte; /*05h */ 1802 u8 reserved_0; /*06h */ 1803 u8 sge_count; /*07h */ 1804 1805 __le32 context; /*08h */ 1806 __le32 pad_0; /*0Ch */ 1807 1808 __le16 flags; /*10h */ 1809 __le16 timeout; /*12h */ 1810 __le32 lba_count; /*14h */ 1811 1812 __le32 sense_buf_phys_addr_lo; /*18h */ 1813 __le32 sense_buf_phys_addr_hi; /*1Ch */ 1814 1815 __le32 start_lba_lo; /*20h */ 1816 __le32 start_lba_hi; /*24h */ 1817 1818 union megasas_sgl sgl; /*28h */ 1819 1820 } __attribute__ ((packed)); 1821 1822 struct megasas_pthru_frame { 1823 1824 u8 cmd; /*00h */ 1825 u8 sense_len; /*01h */ 1826 u8 cmd_status; /*02h */ 1827 u8 scsi_status; /*03h */ 1828 1829 u8 target_id; /*04h */ 1830 u8 lun; /*05h */ 1831 u8 cdb_len; /*06h */ 1832 u8 sge_count; /*07h */ 1833 1834 __le32 context; /*08h */ 1835 __le32 pad_0; /*0Ch */ 1836 1837 __le16 flags; /*10h */ 1838 __le16 timeout; /*12h */ 1839 __le32 data_xfer_len; /*14h */ 1840 1841 __le32 sense_buf_phys_addr_lo; /*18h */ 1842 __le32 sense_buf_phys_addr_hi; /*1Ch */ 1843 1844 u8 cdb[16]; /*20h */ 1845 union megasas_sgl sgl; /*30h */ 1846 1847 } __attribute__ ((packed)); 1848 1849 struct megasas_dcmd_frame { 1850 1851 u8 cmd; /*00h */ 1852 u8 reserved_0; /*01h */ 1853 u8 cmd_status; /*02h */ 1854 u8 reserved_1[4]; /*03h */ 1855 u8 sge_count; /*07h */ 1856 1857 __le32 context; /*08h */ 1858 __le32 pad_0; /*0Ch */ 1859 1860 __le16 flags; /*10h */ 1861 __le16 timeout; /*12h */ 1862 1863 __le32 data_xfer_len; /*14h */ 1864 __le32 opcode; /*18h */ 1865 1866 union { /*1Ch */ 1867 u8 b[12]; 1868 __le16 s[6]; 1869 __le32 w[3]; 1870 } mbox; 1871 1872 union megasas_sgl sgl; /*28h */ 1873 1874 } __attribute__ ((packed)); 1875 1876 struct megasas_abort_frame { 1877 1878 u8 cmd; /*00h */ 1879 u8 reserved_0; /*01h */ 1880 u8 cmd_status; /*02h */ 1881 1882 u8 reserved_1; /*03h */ 1883 __le32 reserved_2; /*04h */ 1884 1885 __le32 context; /*08h */ 1886 __le32 pad_0; /*0Ch */ 1887 1888 __le16 flags; /*10h */ 1889 __le16 reserved_3; /*12h */ 1890 __le32 reserved_4; /*14h */ 1891 1892 __le32 abort_context; /*18h */ 1893 __le32 pad_1; /*1Ch */ 1894 1895 __le32 abort_mfi_phys_addr_lo; /*20h */ 1896 __le32 abort_mfi_phys_addr_hi; /*24h */ 1897 1898 __le32 reserved_5[6]; /*28h */ 1899 1900 } __attribute__ ((packed)); 1901 1902 struct megasas_smp_frame { 1903 1904 u8 cmd; /*00h */ 1905 u8 reserved_1; /*01h */ 1906 u8 cmd_status; /*02h */ 1907 u8 connection_status; /*03h */ 1908 1909 u8 reserved_2[3]; /*04h */ 1910 u8 sge_count; /*07h */ 1911 1912 __le32 context; /*08h */ 1913 __le32 pad_0; /*0Ch */ 1914 1915 __le16 flags; /*10h */ 1916 __le16 timeout; /*12h */ 1917 1918 __le32 data_xfer_len; /*14h */ 1919 __le64 sas_addr; /*18h */ 1920 1921 union { 1922 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */ 1923 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */ 1924 } sgl; 1925 1926 } __attribute__ ((packed)); 1927 1928 struct megasas_stp_frame { 1929 1930 u8 cmd; /*00h */ 1931 u8 reserved_1; /*01h */ 1932 u8 cmd_status; /*02h */ 1933 u8 reserved_2; /*03h */ 1934 1935 u8 target_id; /*04h */ 1936 u8 reserved_3[2]; /*05h */ 1937 u8 sge_count; /*07h */ 1938 1939 __le32 context; /*08h */ 1940 __le32 pad_0; /*0Ch */ 1941 1942 __le16 flags; /*10h */ 1943 __le16 timeout; /*12h */ 1944 1945 __le32 data_xfer_len; /*14h */ 1946 1947 __le16 fis[10]; /*18h */ 1948 __le32 stp_flags; 1949 1950 union { 1951 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */ 1952 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */ 1953 } sgl; 1954 1955 } __attribute__ ((packed)); 1956 1957 union megasas_frame { 1958 1959 struct megasas_header hdr; 1960 struct megasas_init_frame init; 1961 struct megasas_io_frame io; 1962 struct megasas_pthru_frame pthru; 1963 struct megasas_dcmd_frame dcmd; 1964 struct megasas_abort_frame abort; 1965 struct megasas_smp_frame smp; 1966 struct megasas_stp_frame stp; 1967 1968 u8 raw_bytes[64]; 1969 }; 1970 1971 /** 1972 * struct MR_PRIV_DEVICE - sdev private hostdata 1973 * @is_tm_capable: firmware managed tm_capable flag 1974 * @tm_busy: TM request is in progress 1975 */ 1976 struct MR_PRIV_DEVICE { 1977 bool is_tm_capable; 1978 bool tm_busy; 1979 atomic_t r1_ldio_hint; 1980 u8 interface_type; 1981 u8 task_abort_tmo; 1982 u8 target_reset_tmo; 1983 }; 1984 struct megasas_cmd; 1985 1986 union megasas_evt_class_locale { 1987 1988 struct { 1989 #ifndef __BIG_ENDIAN_BITFIELD 1990 u16 locale; 1991 u8 reserved; 1992 s8 class; 1993 #else 1994 s8 class; 1995 u8 reserved; 1996 u16 locale; 1997 #endif 1998 } __attribute__ ((packed)) members; 1999 2000 u32 word; 2001 2002 } __attribute__ ((packed)); 2003 2004 struct megasas_evt_log_info { 2005 __le32 newest_seq_num; 2006 __le32 oldest_seq_num; 2007 __le32 clear_seq_num; 2008 __le32 shutdown_seq_num; 2009 __le32 boot_seq_num; 2010 2011 } __attribute__ ((packed)); 2012 2013 struct megasas_progress { 2014 2015 __le16 progress; 2016 __le16 elapsed_seconds; 2017 2018 } __attribute__ ((packed)); 2019 2020 struct megasas_evtarg_ld { 2021 2022 u16 target_id; 2023 u8 ld_index; 2024 u8 reserved; 2025 2026 } __attribute__ ((packed)); 2027 2028 struct megasas_evtarg_pd { 2029 u16 device_id; 2030 u8 encl_index; 2031 u8 slot_number; 2032 2033 } __attribute__ ((packed)); 2034 2035 struct megasas_evt_detail { 2036 2037 __le32 seq_num; 2038 __le32 time_stamp; 2039 __le32 code; 2040 union megasas_evt_class_locale cl; 2041 u8 arg_type; 2042 u8 reserved1[15]; 2043 2044 union { 2045 struct { 2046 struct megasas_evtarg_pd pd; 2047 u8 cdb_length; 2048 u8 sense_length; 2049 u8 reserved[2]; 2050 u8 cdb[16]; 2051 u8 sense[64]; 2052 } __attribute__ ((packed)) cdbSense; 2053 2054 struct megasas_evtarg_ld ld; 2055 2056 struct { 2057 struct megasas_evtarg_ld ld; 2058 __le64 count; 2059 } __attribute__ ((packed)) ld_count; 2060 2061 struct { 2062 __le64 lba; 2063 struct megasas_evtarg_ld ld; 2064 } __attribute__ ((packed)) ld_lba; 2065 2066 struct { 2067 struct megasas_evtarg_ld ld; 2068 __le32 prevOwner; 2069 __le32 newOwner; 2070 } __attribute__ ((packed)) ld_owner; 2071 2072 struct { 2073 u64 ld_lba; 2074 u64 pd_lba; 2075 struct megasas_evtarg_ld ld; 2076 struct megasas_evtarg_pd pd; 2077 } __attribute__ ((packed)) ld_lba_pd_lba; 2078 2079 struct { 2080 struct megasas_evtarg_ld ld; 2081 struct megasas_progress prog; 2082 } __attribute__ ((packed)) ld_prog; 2083 2084 struct { 2085 struct megasas_evtarg_ld ld; 2086 u32 prev_state; 2087 u32 new_state; 2088 } __attribute__ ((packed)) ld_state; 2089 2090 struct { 2091 u64 strip; 2092 struct megasas_evtarg_ld ld; 2093 } __attribute__ ((packed)) ld_strip; 2094 2095 struct megasas_evtarg_pd pd; 2096 2097 struct { 2098 struct megasas_evtarg_pd pd; 2099 u32 err; 2100 } __attribute__ ((packed)) pd_err; 2101 2102 struct { 2103 u64 lba; 2104 struct megasas_evtarg_pd pd; 2105 } __attribute__ ((packed)) pd_lba; 2106 2107 struct { 2108 u64 lba; 2109 struct megasas_evtarg_pd pd; 2110 struct megasas_evtarg_ld ld; 2111 } __attribute__ ((packed)) pd_lba_ld; 2112 2113 struct { 2114 struct megasas_evtarg_pd pd; 2115 struct megasas_progress prog; 2116 } __attribute__ ((packed)) pd_prog; 2117 2118 struct { 2119 struct megasas_evtarg_pd pd; 2120 u32 prevState; 2121 u32 newState; 2122 } __attribute__ ((packed)) pd_state; 2123 2124 struct { 2125 u16 vendorId; 2126 __le16 deviceId; 2127 u16 subVendorId; 2128 u16 subDeviceId; 2129 } __attribute__ ((packed)) pci; 2130 2131 u32 rate; 2132 char str[96]; 2133 2134 struct { 2135 u32 rtc; 2136 u32 elapsedSeconds; 2137 } __attribute__ ((packed)) time; 2138 2139 struct { 2140 u32 ecar; 2141 u32 elog; 2142 char str[64]; 2143 } __attribute__ ((packed)) ecc; 2144 2145 u8 b[96]; 2146 __le16 s[48]; 2147 __le32 w[24]; 2148 __le64 d[12]; 2149 } args; 2150 2151 char description[128]; 2152 2153 } __attribute__ ((packed)); 2154 2155 struct megasas_aen_event { 2156 struct delayed_work hotplug_work; 2157 struct megasas_instance *instance; 2158 }; 2159 2160 struct megasas_irq_context { 2161 struct megasas_instance *instance; 2162 u32 MSIxIndex; 2163 }; 2164 2165 struct MR_DRV_SYSTEM_INFO { 2166 u8 infoVersion; 2167 u8 systemIdLength; 2168 u16 reserved0; 2169 u8 systemId[64]; 2170 u8 reserved[1980]; 2171 }; 2172 2173 enum MR_PD_TYPE { 2174 UNKNOWN_DRIVE = 0, 2175 PARALLEL_SCSI = 1, 2176 SAS_PD = 2, 2177 SATA_PD = 3, 2178 FC_PD = 4, 2179 NVME_PD = 5, 2180 }; 2181 2182 /* JBOD Queue depth definitions */ 2183 #define MEGASAS_SATA_QD 32 2184 #define MEGASAS_SAS_QD 64 2185 #define MEGASAS_DEFAULT_PD_QD 64 2186 #define MEGASAS_NVME_QD 32 2187 2188 #define MR_DEFAULT_NVME_PAGE_SIZE 4096 2189 #define MR_DEFAULT_NVME_PAGE_SHIFT 12 2190 #define MR_DEFAULT_NVME_MDTS_KB 128 2191 #define MR_NVME_PAGE_SIZE_MASK 0x000000FF 2192 2193 struct megasas_instance { 2194 2195 unsigned int *reply_map; 2196 __le32 *producer; 2197 dma_addr_t producer_h; 2198 __le32 *consumer; 2199 dma_addr_t consumer_h; 2200 struct MR_DRV_SYSTEM_INFO *system_info_buf; 2201 dma_addr_t system_info_h; 2202 struct MR_LD_VF_AFFILIATION *vf_affiliation; 2203 dma_addr_t vf_affiliation_h; 2204 struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111; 2205 dma_addr_t vf_affiliation_111_h; 2206 struct MR_CTRL_HB_HOST_MEM *hb_host_mem; 2207 dma_addr_t hb_host_mem_h; 2208 struct MR_PD_INFO *pd_info; 2209 dma_addr_t pd_info_h; 2210 struct MR_TARGET_PROPERTIES *tgt_prop; 2211 dma_addr_t tgt_prop_h; 2212 2213 __le32 *reply_queue; 2214 dma_addr_t reply_queue_h; 2215 2216 u32 *crash_dump_buf; 2217 dma_addr_t crash_dump_h; 2218 2219 struct MR_PD_LIST *pd_list_buf; 2220 dma_addr_t pd_list_buf_h; 2221 2222 struct megasas_ctrl_info *ctrl_info_buf; 2223 dma_addr_t ctrl_info_buf_h; 2224 2225 struct MR_LD_LIST *ld_list_buf; 2226 dma_addr_t ld_list_buf_h; 2227 2228 struct MR_LD_TARGETID_LIST *ld_targetid_list_buf; 2229 dma_addr_t ld_targetid_list_buf_h; 2230 2231 struct MR_HOST_DEVICE_LIST *host_device_list_buf; 2232 dma_addr_t host_device_list_buf_h; 2233 2234 struct MR_SNAPDUMP_PROPERTIES *snapdump_prop; 2235 dma_addr_t snapdump_prop_h; 2236 2237 void *crash_buf[MAX_CRASH_DUMP_SIZE]; 2238 unsigned int fw_crash_buffer_size; 2239 unsigned int fw_crash_state; 2240 unsigned int fw_crash_buffer_offset; 2241 u32 drv_buf_index; 2242 u32 drv_buf_alloc; 2243 u32 crash_dump_fw_support; 2244 u32 crash_dump_drv_support; 2245 u32 crash_dump_app_support; 2246 u32 secure_jbod_support; 2247 u32 support_morethan256jbod; /* FW support for more than 256 PD/JBOD */ 2248 bool use_seqnum_jbod_fp; /* Added for PD sequence */ 2249 spinlock_t crashdump_lock; 2250 2251 struct megasas_register_set __iomem *reg_set; 2252 u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY]; 2253 struct megasas_pd_list pd_list[MEGASAS_MAX_PD]; 2254 struct megasas_pd_list local_pd_list[MEGASAS_MAX_PD]; 2255 u8 ld_ids[MEGASAS_MAX_LD_IDS]; 2256 s8 init_id; 2257 2258 u16 max_num_sge; 2259 u16 max_fw_cmds; 2260 u16 max_mpt_cmds; 2261 u16 max_mfi_cmds; 2262 u16 max_scsi_cmds; 2263 u16 ldio_threshold; 2264 u16 cur_can_queue; 2265 u32 max_sectors_per_req; 2266 struct megasas_aen_event *ev; 2267 2268 struct megasas_cmd **cmd_list; 2269 struct list_head cmd_pool; 2270 /* used to sync fire the cmd to fw */ 2271 spinlock_t mfi_pool_lock; 2272 /* used to sync fire the cmd to fw */ 2273 spinlock_t hba_lock; 2274 /* used to synch producer, consumer ptrs in dpc */ 2275 spinlock_t stream_lock; 2276 spinlock_t completion_lock; 2277 struct dma_pool *frame_dma_pool; 2278 struct dma_pool *sense_dma_pool; 2279 2280 struct megasas_evt_detail *evt_detail; 2281 dma_addr_t evt_detail_h; 2282 struct megasas_cmd *aen_cmd; 2283 struct semaphore ioctl_sem; 2284 2285 struct Scsi_Host *host; 2286 2287 wait_queue_head_t int_cmd_wait_q; 2288 wait_queue_head_t abort_cmd_wait_q; 2289 2290 struct pci_dev *pdev; 2291 u32 unique_id; 2292 u32 fw_support_ieee; 2293 2294 atomic_t fw_outstanding; 2295 atomic_t ldio_outstanding; 2296 atomic_t fw_reset_no_pci_access; 2297 atomic_t ieee_sgl; 2298 atomic_t prp_sgl; 2299 atomic_t sge_holes_type1; 2300 atomic_t sge_holes_type2; 2301 atomic_t sge_holes_type3; 2302 2303 struct megasas_instance_template *instancet; 2304 struct tasklet_struct isr_tasklet; 2305 struct work_struct work_init; 2306 struct delayed_work fw_fault_work; 2307 struct workqueue_struct *fw_fault_work_q; 2308 char fault_handler_work_q_name[48]; 2309 2310 u8 flag; 2311 u8 unload; 2312 u8 flag_ieee; 2313 u8 issuepend_done; 2314 u8 disableOnlineCtrlReset; 2315 u8 UnevenSpanSupport; 2316 2317 u8 supportmax256vd; 2318 u8 pd_list_not_supported; 2319 u16 fw_supported_vd_count; 2320 u16 fw_supported_pd_count; 2321 2322 u16 drv_supported_vd_count; 2323 u16 drv_supported_pd_count; 2324 2325 atomic_t adprecovery; 2326 unsigned long last_time; 2327 u32 mfiStatus; 2328 u32 last_seq_num; 2329 2330 struct list_head internal_reset_pending_q; 2331 2332 /* Ptr to hba specific information */ 2333 void *ctrl_context; 2334 unsigned int msix_vectors; 2335 struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES]; 2336 u64 map_id; 2337 u64 pd_seq_map_id; 2338 struct megasas_cmd *map_update_cmd; 2339 struct megasas_cmd *jbod_seq_cmd; 2340 unsigned long bar; 2341 long reset_flags; 2342 struct mutex reset_mutex; 2343 struct timer_list sriov_heartbeat_timer; 2344 char skip_heartbeat_timer_del; 2345 u8 requestorId; 2346 char PlasmaFW111; 2347 char clusterId[MEGASAS_CLUSTER_ID_SIZE]; 2348 u8 peerIsPresent; 2349 u8 passive; 2350 u16 throttlequeuedepth; 2351 u8 mask_interrupts; 2352 u16 max_chain_frame_sz; 2353 u8 is_imr; 2354 u8 is_rdpq; 2355 bool dev_handle; 2356 bool fw_sync_cache_support; 2357 u32 mfi_frame_size; 2358 bool msix_combined; 2359 u16 max_raid_mapsize; 2360 /* preffered count to send as LDIO irrspective of FP capable.*/ 2361 u8 r1_ldio_hint_default; 2362 u32 nvme_page_size; 2363 u8 adapter_type; 2364 bool consistent_mask_64bit; 2365 bool support_nvme_passthru; 2366 u8 task_abort_tmo; 2367 u8 max_reset_tmo; 2368 u8 snapdump_wait_time; 2369 u8 enable_fw_dev_list; 2370 }; 2371 struct MR_LD_VF_MAP { 2372 u32 size; 2373 union MR_LD_REF ref; 2374 u8 ldVfCount; 2375 u8 reserved[6]; 2376 u8 policy[1]; 2377 }; 2378 2379 struct MR_LD_VF_AFFILIATION { 2380 u32 size; 2381 u8 ldCount; 2382 u8 vfCount; 2383 u8 thisVf; 2384 u8 reserved[9]; 2385 struct MR_LD_VF_MAP map[1]; 2386 }; 2387 2388 /* Plasma 1.11 FW backward compatibility structures */ 2389 #define IOV_111_OFFSET 0x7CE 2390 #define MAX_VIRTUAL_FUNCTIONS 8 2391 #define MR_LD_ACCESS_HIDDEN 15 2392 2393 struct IOV_111 { 2394 u8 maxVFsSupported; 2395 u8 numVFsEnabled; 2396 u8 requestorId; 2397 u8 reserved[5]; 2398 }; 2399 2400 struct MR_LD_VF_MAP_111 { 2401 u8 targetId; 2402 u8 reserved[3]; 2403 u8 policy[MAX_VIRTUAL_FUNCTIONS]; 2404 }; 2405 2406 struct MR_LD_VF_AFFILIATION_111 { 2407 u8 vdCount; 2408 u8 vfCount; 2409 u8 thisVf; 2410 u8 reserved[5]; 2411 struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES]; 2412 }; 2413 2414 struct MR_CTRL_HB_HOST_MEM { 2415 struct { 2416 u32 fwCounter; /* Firmware heart beat counter */ 2417 struct { 2418 u32 debugmode:1; /* 1=Firmware is in debug mode. 2419 Heart beat will not be updated. */ 2420 u32 reserved:31; 2421 } debug; 2422 u32 reserved_fw[6]; 2423 u32 driverCounter; /* Driver heart beat counter. 0x20 */ 2424 u32 reserved_driver[7]; 2425 } HB; 2426 u8 pad[0x400-0x40]; 2427 }; 2428 2429 enum { 2430 MEGASAS_HBA_OPERATIONAL = 0, 2431 MEGASAS_ADPRESET_SM_INFAULT = 1, 2432 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2, 2433 MEGASAS_ADPRESET_SM_OPERATIONAL = 3, 2434 MEGASAS_HW_CRITICAL_ERROR = 4, 2435 MEGASAS_ADPRESET_SM_POLLING = 5, 2436 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD, 2437 }; 2438 2439 struct megasas_instance_template { 2440 void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \ 2441 u32, struct megasas_register_set __iomem *); 2442 2443 void (*enable_intr)(struct megasas_instance *); 2444 void (*disable_intr)(struct megasas_instance *); 2445 2446 int (*clear_intr)(struct megasas_instance *); 2447 2448 u32 (*read_fw_status_reg)(struct megasas_instance *); 2449 int (*adp_reset)(struct megasas_instance *, \ 2450 struct megasas_register_set __iomem *); 2451 int (*check_reset)(struct megasas_instance *, \ 2452 struct megasas_register_set __iomem *); 2453 irqreturn_t (*service_isr)(int irq, void *devp); 2454 void (*tasklet)(unsigned long); 2455 u32 (*init_adapter)(struct megasas_instance *); 2456 u32 (*build_and_issue_cmd) (struct megasas_instance *, 2457 struct scsi_cmnd *); 2458 void (*issue_dcmd)(struct megasas_instance *instance, 2459 struct megasas_cmd *cmd); 2460 }; 2461 2462 #define MEGASAS_IS_LOGICAL(sdev) \ 2463 ((sdev->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1) 2464 2465 #define MEGASAS_DEV_INDEX(scp) \ 2466 (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \ 2467 scp->device->id) 2468 2469 #define MEGASAS_PD_INDEX(scp) \ 2470 ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) + \ 2471 scp->device->id) 2472 2473 struct megasas_cmd { 2474 2475 union megasas_frame *frame; 2476 dma_addr_t frame_phys_addr; 2477 u8 *sense; 2478 dma_addr_t sense_phys_addr; 2479 2480 u32 index; 2481 u8 sync_cmd; 2482 u8 cmd_status_drv; 2483 u8 abort_aen; 2484 u8 retry_for_fw_reset; 2485 2486 2487 struct list_head list; 2488 struct scsi_cmnd *scmd; 2489 u8 flags; 2490 2491 struct megasas_instance *instance; 2492 union { 2493 struct { 2494 u16 smid; 2495 u16 resvd; 2496 } context; 2497 u32 frame_count; 2498 }; 2499 }; 2500 2501 #define MAX_MGMT_ADAPTERS 1024 2502 #define MAX_IOCTL_SGE 16 2503 2504 struct megasas_iocpacket { 2505 2506 u16 host_no; 2507 u16 __pad1; 2508 u32 sgl_off; 2509 u32 sge_count; 2510 u32 sense_off; 2511 u32 sense_len; 2512 union { 2513 u8 raw[128]; 2514 struct megasas_header hdr; 2515 } frame; 2516 2517 struct iovec sgl[MAX_IOCTL_SGE]; 2518 2519 } __attribute__ ((packed)); 2520 2521 struct megasas_aen { 2522 u16 host_no; 2523 u16 __pad1; 2524 u32 seq_num; 2525 u32 class_locale_word; 2526 } __attribute__ ((packed)); 2527 2528 #ifdef CONFIG_COMPAT 2529 struct compat_megasas_iocpacket { 2530 u16 host_no; 2531 u16 __pad1; 2532 u32 sgl_off; 2533 u32 sge_count; 2534 u32 sense_off; 2535 u32 sense_len; 2536 union { 2537 u8 raw[128]; 2538 struct megasas_header hdr; 2539 } frame; 2540 struct compat_iovec sgl[MAX_IOCTL_SGE]; 2541 } __attribute__ ((packed)); 2542 2543 #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket) 2544 #endif 2545 2546 #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket) 2547 #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen) 2548 2549 struct megasas_mgmt_info { 2550 2551 u16 count; 2552 struct megasas_instance *instance[MAX_MGMT_ADAPTERS]; 2553 int max_index; 2554 }; 2555 2556 enum MEGASAS_OCR_CAUSE { 2557 FW_FAULT_OCR = 0, 2558 SCSIIO_TIMEOUT_OCR = 1, 2559 MFI_IO_TIMEOUT_OCR = 2, 2560 }; 2561 2562 enum DCMD_RETURN_STATUS { 2563 DCMD_SUCCESS = 0, 2564 DCMD_TIMEOUT = 1, 2565 DCMD_FAILED = 2, 2566 DCMD_NOT_FIRED = 3, 2567 }; 2568 2569 u8 2570 MR_BuildRaidContext(struct megasas_instance *instance, 2571 struct IO_REQUEST_INFO *io_info, 2572 struct RAID_CONTEXT *pRAID_Context, 2573 struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN); 2574 u16 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map); 2575 struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map); 2576 u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map); 2577 u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map); 2578 __le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map); 2579 u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map); 2580 2581 __le16 get_updated_dev_handle(struct megasas_instance *instance, 2582 struct LD_LOAD_BALANCE_INFO *lbInfo, 2583 struct IO_REQUEST_INFO *in_info, 2584 struct MR_DRV_RAID_MAP_ALL *drv_map); 2585 void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map, 2586 struct LD_LOAD_BALANCE_INFO *lbInfo); 2587 int megasas_get_ctrl_info(struct megasas_instance *instance); 2588 /* PD sequence */ 2589 int 2590 megasas_sync_pd_seq_num(struct megasas_instance *instance, bool pend); 2591 void megasas_set_dynamic_target_properties(struct scsi_device *sdev, 2592 bool is_target_prop); 2593 int megasas_get_target_prop(struct megasas_instance *instance, 2594 struct scsi_device *sdev); 2595 void megasas_get_snapdump_properties(struct megasas_instance *instance); 2596 2597 int megasas_set_crash_dump_params(struct megasas_instance *instance, 2598 u8 crash_buf_state); 2599 void megasas_free_host_crash_buffer(struct megasas_instance *instance); 2600 2601 void megasas_return_cmd_fusion(struct megasas_instance *instance, 2602 struct megasas_cmd_fusion *cmd); 2603 int megasas_issue_blocked_cmd(struct megasas_instance *instance, 2604 struct megasas_cmd *cmd, int timeout); 2605 void __megasas_return_cmd(struct megasas_instance *instance, 2606 struct megasas_cmd *cmd); 2607 2608 void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance, 2609 struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion); 2610 int megasas_cmd_type(struct scsi_cmnd *cmd); 2611 void megasas_setup_jbod_map(struct megasas_instance *instance); 2612 2613 void megasas_update_sdev_properties(struct scsi_device *sdev); 2614 int megasas_reset_fusion(struct Scsi_Host *shost, int reason); 2615 int megasas_task_abort_fusion(struct scsi_cmnd *scmd); 2616 int megasas_reset_target_fusion(struct scsi_cmnd *scmd); 2617 u32 mega_mod64(u64 dividend, u32 divisor); 2618 int megasas_alloc_fusion_context(struct megasas_instance *instance); 2619 void megasas_free_fusion_context(struct megasas_instance *instance); 2620 int megasas_fusion_start_watchdog(struct megasas_instance *instance); 2621 void megasas_fusion_stop_watchdog(struct megasas_instance *instance); 2622 2623 void megasas_set_dma_settings(struct megasas_instance *instance, 2624 struct megasas_dcmd_frame *dcmd, 2625 dma_addr_t dma_addr, u32 dma_len); 2626 #endif /*LSI_MEGARAID_SAS_H */ 2627