1*fae35c14SNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */ 2*fae35c14SNishad Kamdar /* 3081ff398SHannes Reinecke * Linux Driver for Mylex DAC960/AcceleRAID/eXtremeRAID PCI RAID Controllers 4081ff398SHannes Reinecke * 5081ff398SHannes Reinecke * Copyright 2017 Hannes Reinecke, SUSE Linux GmbH <hare@suse.com> 6081ff398SHannes Reinecke * 7081ff398SHannes Reinecke * Based on the original DAC960 driver, 8081ff398SHannes Reinecke * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com> 9081ff398SHannes Reinecke * Portions Copyright 2002 by Mylex (An IBM Business Unit) 10081ff398SHannes Reinecke * 11081ff398SHannes Reinecke */ 12081ff398SHannes Reinecke 13081ff398SHannes Reinecke #ifndef MYRB_H 14081ff398SHannes Reinecke #define MYRB_H 15081ff398SHannes Reinecke 16081ff398SHannes Reinecke #define MYRB_MAX_LDEVS 32 17081ff398SHannes Reinecke #define MYRB_MAX_CHANNELS 3 18081ff398SHannes Reinecke #define MYRB_MAX_TARGETS 16 19081ff398SHannes Reinecke #define MYRB_MAX_PHYSICAL_DEVICES 45 20081ff398SHannes Reinecke #define MYRB_SCATTER_GATHER_LIMIT 32 21081ff398SHannes Reinecke #define MYRB_CMD_MBOX_COUNT 256 22081ff398SHannes Reinecke #define MYRB_STAT_MBOX_COUNT 1024 23081ff398SHannes Reinecke 24081ff398SHannes Reinecke #define MYRB_BLKSIZE_BITS 9 25081ff398SHannes Reinecke #define MYRB_MAILBOX_TIMEOUT 1000000 26081ff398SHannes Reinecke 27081ff398SHannes Reinecke #define MYRB_DCMD_TAG 1 28081ff398SHannes Reinecke #define MYRB_MCMD_TAG 2 29081ff398SHannes Reinecke 30081ff398SHannes Reinecke #define MYRB_PRIMARY_MONITOR_INTERVAL (10 * HZ) 31081ff398SHannes Reinecke #define MYRB_SECONDARY_MONITOR_INTERVAL (60 * HZ) 32081ff398SHannes Reinecke 33081ff398SHannes Reinecke /* 34081ff398SHannes Reinecke * DAC960 V1 Firmware Command Opcodes. 35081ff398SHannes Reinecke */ 36081ff398SHannes Reinecke enum myrb_cmd_opcode { 37081ff398SHannes Reinecke /* I/O Commands */ 38081ff398SHannes Reinecke MYRB_CMD_READ_EXTENDED = 0x33, 39081ff398SHannes Reinecke MYRB_CMD_WRITE_EXTENDED = 0x34, 40081ff398SHannes Reinecke MYRB_CMD_READAHEAD_EXTENDED = 0x35, 41081ff398SHannes Reinecke MYRB_CMD_READ_EXTENDED_SG = 0xB3, 42081ff398SHannes Reinecke MYRB_CMD_WRITE_EXTENDED_SG = 0xB4, 43081ff398SHannes Reinecke MYRB_CMD_READ = 0x36, 44081ff398SHannes Reinecke MYRB_CMD_READ_SG = 0xB6, 45081ff398SHannes Reinecke MYRB_CMD_WRITE = 0x37, 46081ff398SHannes Reinecke MYRB_CMD_WRITE_SG = 0xB7, 47081ff398SHannes Reinecke MYRB_CMD_DCDB = 0x04, 48081ff398SHannes Reinecke MYRB_CMD_DCDB_SG = 0x84, 49081ff398SHannes Reinecke MYRB_CMD_FLUSH = 0x0A, 50081ff398SHannes Reinecke /* Controller Status Related Commands */ 51081ff398SHannes Reinecke MYRB_CMD_ENQUIRY = 0x53, 52081ff398SHannes Reinecke MYRB_CMD_ENQUIRY2 = 0x1C, 53081ff398SHannes Reinecke MYRB_CMD_GET_LDRV_ELEMENT = 0x55, 54081ff398SHannes Reinecke MYRB_CMD_GET_LDEV_INFO = 0x19, 55081ff398SHannes Reinecke MYRB_CMD_IOPORTREAD = 0x39, 56081ff398SHannes Reinecke MYRB_CMD_IOPORTWRITE = 0x3A, 57081ff398SHannes Reinecke MYRB_CMD_GET_SD_STATS = 0x3E, 58081ff398SHannes Reinecke MYRB_CMD_GET_PD_STATS = 0x3F, 59081ff398SHannes Reinecke MYRB_CMD_EVENT_LOG_OPERATION = 0x72, 60081ff398SHannes Reinecke /* Device Related Commands */ 61081ff398SHannes Reinecke MYRB_CMD_START_DEVICE = 0x10, 62081ff398SHannes Reinecke MYRB_CMD_GET_DEVICE_STATE = 0x50, 63081ff398SHannes Reinecke MYRB_CMD_STOP_CHANNEL = 0x13, 64081ff398SHannes Reinecke MYRB_CMD_START_CHANNEL = 0x12, 65081ff398SHannes Reinecke MYRB_CMD_RESET_CHANNEL = 0x1A, 66081ff398SHannes Reinecke /* Commands Associated with Data Consistency and Errors */ 67081ff398SHannes Reinecke MYRB_CMD_REBUILD = 0x09, 68081ff398SHannes Reinecke MYRB_CMD_REBUILD_ASYNC = 0x16, 69081ff398SHannes Reinecke MYRB_CMD_CHECK_CONSISTENCY = 0x0F, 70081ff398SHannes Reinecke MYRB_CMD_CHECK_CONSISTENCY_ASYNC = 0x1E, 71081ff398SHannes Reinecke MYRB_CMD_REBUILD_STAT = 0x0C, 72081ff398SHannes Reinecke MYRB_CMD_GET_REBUILD_PROGRESS = 0x27, 73081ff398SHannes Reinecke MYRB_CMD_REBUILD_CONTROL = 0x1F, 74081ff398SHannes Reinecke MYRB_CMD_READ_BADBLOCK_TABLE = 0x0B, 75081ff398SHannes Reinecke MYRB_CMD_READ_BADDATA_TABLE = 0x25, 76081ff398SHannes Reinecke MYRB_CMD_CLEAR_BADDATA_TABLE = 0x26, 77081ff398SHannes Reinecke MYRB_CMD_GET_ERROR_TABLE = 0x17, 78081ff398SHannes Reinecke MYRB_CMD_ADD_CAPACITY_ASYNC = 0x2A, 79081ff398SHannes Reinecke MYRB_CMD_BGI_CONTROL = 0x2B, 80081ff398SHannes Reinecke /* Configuration Related Commands */ 81081ff398SHannes Reinecke MYRB_CMD_READ_CONFIG2 = 0x3D, 82081ff398SHannes Reinecke MYRB_CMD_WRITE_CONFIG2 = 0x3C, 83081ff398SHannes Reinecke MYRB_CMD_READ_CONFIG_ONDISK = 0x4A, 84081ff398SHannes Reinecke MYRB_CMD_WRITE_CONFIG_ONDISK = 0x4B, 85081ff398SHannes Reinecke MYRB_CMD_READ_CONFIG = 0x4E, 86081ff398SHannes Reinecke MYRB_CMD_READ_BACKUP_CONFIG = 0x4D, 87081ff398SHannes Reinecke MYRB_CMD_WRITE_CONFIG = 0x4F, 88081ff398SHannes Reinecke MYRB_CMD_ADD_CONFIG = 0x4C, 89081ff398SHannes Reinecke MYRB_CMD_READ_CONFIG_LABEL = 0x48, 90081ff398SHannes Reinecke MYRB_CMD_WRITE_CONFIG_LABEL = 0x49, 91081ff398SHannes Reinecke /* Firmware Upgrade Related Commands */ 92081ff398SHannes Reinecke MYRB_CMD_LOAD_IMAGE = 0x20, 93081ff398SHannes Reinecke MYRB_CMD_STORE_IMAGE = 0x21, 94081ff398SHannes Reinecke MYRB_CMD_PROGRAM_IMAGE = 0x22, 95081ff398SHannes Reinecke /* Diagnostic Commands */ 96081ff398SHannes Reinecke MYRB_CMD_SET_DIAGNOSTIC_MODE = 0x31, 97081ff398SHannes Reinecke MYRB_CMD_RUN_DIAGNOSTIC = 0x32, 98081ff398SHannes Reinecke /* Subsystem Service Commands */ 99081ff398SHannes Reinecke MYRB_CMD_GET_SUBSYS_DATA = 0x70, 100081ff398SHannes Reinecke MYRB_CMD_SET_SUBSYS_PARAM = 0x71, 101081ff398SHannes Reinecke /* Version 2.xx Firmware Commands */ 102081ff398SHannes Reinecke MYRB_CMD_ENQUIRY_OLD = 0x05, 103081ff398SHannes Reinecke MYRB_CMD_GET_DEVICE_STATE_OLD = 0x14, 104081ff398SHannes Reinecke MYRB_CMD_READ_OLD = 0x02, 105081ff398SHannes Reinecke MYRB_CMD_WRITE_OLD = 0x03, 106081ff398SHannes Reinecke MYRB_CMD_READ_SG_OLD = 0x82, 107081ff398SHannes Reinecke MYRB_CMD_WRITE_SG_OLD = 0x83 108081ff398SHannes Reinecke } __packed; 109081ff398SHannes Reinecke 110081ff398SHannes Reinecke /* 111081ff398SHannes Reinecke * DAC960 V1 Firmware Command Status Codes. 112081ff398SHannes Reinecke */ 113081ff398SHannes Reinecke #define MYRB_STATUS_SUCCESS 0x0000 /* Common */ 114081ff398SHannes Reinecke #define MYRB_STATUS_CHECK_CONDITION 0x0002 /* Common */ 115081ff398SHannes Reinecke #define MYRB_STATUS_NO_DEVICE 0x0102 /* Common */ 116081ff398SHannes Reinecke #define MYRB_STATUS_INVALID_ADDRESS 0x0105 /* Common */ 117081ff398SHannes Reinecke #define MYRB_STATUS_INVALID_PARAM 0x0105 /* Common */ 118081ff398SHannes Reinecke #define MYRB_STATUS_IRRECOVERABLE_DATA_ERROR 0x0001 /* I/O */ 119081ff398SHannes Reinecke #define MYRB_STATUS_LDRV_NONEXISTENT_OR_OFFLINE 0x0002 /* I/O */ 120081ff398SHannes Reinecke #define MYRB_STATUS_ACCESS_BEYOND_END_OF_LDRV 0x0105 /* I/O */ 121081ff398SHannes Reinecke #define MYRB_STATUS_BAD_DATA 0x010C /* I/O */ 122081ff398SHannes Reinecke #define MYRB_STATUS_DEVICE_BUSY 0x0008 /* DCDB */ 123081ff398SHannes Reinecke #define MYRB_STATUS_DEVICE_NONRESPONSIVE 0x000E /* DCDB */ 124081ff398SHannes Reinecke #define MYRB_STATUS_COMMAND_TERMINATED 0x000F /* DCDB */ 125081ff398SHannes Reinecke #define MYRB_STATUS_START_DEVICE_FAILED 0x0002 /* Device */ 126081ff398SHannes Reinecke #define MYRB_STATUS_INVALID_CHANNEL_OR_TARGET 0x0105 /* Device */ 127081ff398SHannes Reinecke #define MYRB_STATUS_CHANNEL_BUSY 0x0106 /* Device */ 128081ff398SHannes Reinecke #define MYRB_STATUS_OUT_OF_MEMORY 0x0107 /* Device */ 129081ff398SHannes Reinecke #define MYRB_STATUS_CHANNEL_NOT_STOPPED 0x0002 /* Device */ 130081ff398SHannes Reinecke #define MYRB_STATUS_ATTEMPT_TO_RBLD_ONLINE_DRIVE 0x0002 /* Consistency */ 131081ff398SHannes Reinecke #define MYRB_STATUS_RBLD_BADBLOCKS 0x0003 /* Consistency */ 132081ff398SHannes Reinecke #define MYRB_STATUS_RBLD_NEW_DISK_FAILED 0x0004 /* Consistency */ 133081ff398SHannes Reinecke #define MYRB_STATUS_RBLD_OR_CHECK_INPROGRESS 0x0106 /* Consistency */ 134081ff398SHannes Reinecke #define MYRB_STATUS_DEPENDENT_DISK_DEAD 0x0002 /* Consistency */ 135081ff398SHannes Reinecke #define MYRB_STATUS_INCONSISTENT_BLOCKS 0x0003 /* Consistency */ 136081ff398SHannes Reinecke #define MYRB_STATUS_INVALID_OR_NONREDUNDANT_LDRV 0x0105 /* Consistency */ 137081ff398SHannes Reinecke #define MYRB_STATUS_NO_RBLD_OR_CHECK_INPROGRESS 0x0105 /* Consistency */ 138081ff398SHannes Reinecke #define MYRB_STATUS_RBLD_IN_PROGRESS_DATA_VALID 0x0000 /* Consistency */ 139081ff398SHannes Reinecke #define MYRB_STATUS_RBLD_FAILED_LDEV_FAILURE 0x0002 /* Consistency */ 140081ff398SHannes Reinecke #define MYRB_STATUS_RBLD_FAILED_BADBLOCKS 0x0003 /* Consistency */ 141081ff398SHannes Reinecke #define MYRB_STATUS_RBLD_FAILED_NEW_DRIVE_FAILED 0x0004 /* Consistency */ 142081ff398SHannes Reinecke #define MYRB_STATUS_RBLD_SUCCESS 0x0100 /* Consistency */ 143081ff398SHannes Reinecke #define MYRB_STATUS_RBLD_SUCCESS_TERMINATED 0x0107 /* Consistency */ 144081ff398SHannes Reinecke #define MYRB_STATUS_RBLD_NOT_CHECKED 0x0108 /* Consistency */ 145081ff398SHannes Reinecke #define MYRB_STATUS_BGI_SUCCESS 0x0100 /* Consistency */ 146081ff398SHannes Reinecke #define MYRB_STATUS_BGI_ABORTED 0x0005 /* Consistency */ 147081ff398SHannes Reinecke #define MYRB_STATUS_NO_BGI_INPROGRESS 0x0105 /* Consistency */ 148081ff398SHannes Reinecke #define MYRB_STATUS_ADD_CAPACITY_INPROGRESS 0x0004 /* Consistency */ 149081ff398SHannes Reinecke #define MYRB_STATUS_ADD_CAPACITY_FAILED_OR_SUSPENDED 0x00F4 /* Consistency */ 150081ff398SHannes Reinecke #define MYRB_STATUS_CONFIG2_CSUM_ERROR 0x0002 /* Configuration */ 151081ff398SHannes Reinecke #define MYRB_STATUS_CONFIGURATION_SUSPENDED 0x0106 /* Configuration */ 152081ff398SHannes Reinecke #define MYRB_STATUS_FAILED_TO_CONFIGURE_NVRAM 0x0105 /* Configuration */ 153081ff398SHannes Reinecke #define MYRB_STATUS_CONFIGURATION_NOT_SAVED 0x0106 /* Configuration */ 154081ff398SHannes Reinecke #define MYRB_STATUS_SUBSYS_NOTINSTALLED 0x0001 /* Subsystem */ 155081ff398SHannes Reinecke #define MYRB_STATUS_SUBSYS_FAILED 0x0002 /* Subsystem */ 156081ff398SHannes Reinecke #define MYRB_STATUS_SUBSYS_BUSY 0x0106 /* Subsystem */ 157081ff398SHannes Reinecke #define MYRB_STATUS_SUBSYS_TIMEOUT 0x0108 /* Subsystem */ 158081ff398SHannes Reinecke 159081ff398SHannes Reinecke /* 160081ff398SHannes Reinecke * DAC960 V1 Firmware Enquiry Command reply structure. 161081ff398SHannes Reinecke */ 162081ff398SHannes Reinecke struct myrb_enquiry { 163081ff398SHannes Reinecke unsigned char ldev_count; /* Byte 0 */ 164081ff398SHannes Reinecke unsigned int rsvd1:24; /* Bytes 1-3 */ 165081ff398SHannes Reinecke unsigned int ldev_sizes[32]; /* Bytes 4-131 */ 166081ff398SHannes Reinecke unsigned short flash_age; /* Bytes 132-133 */ 167081ff398SHannes Reinecke struct { 168081ff398SHannes Reinecke unsigned char deferred:1; /* Byte 134 Bit 0 */ 169081ff398SHannes Reinecke unsigned char low_bat:1; /* Byte 134 Bit 1 */ 170081ff398SHannes Reinecke unsigned char rsvd2:6; /* Byte 134 Bits 2-7 */ 171081ff398SHannes Reinecke } status; 172081ff398SHannes Reinecke unsigned char rsvd3:8; /* Byte 135 */ 173081ff398SHannes Reinecke unsigned char fw_minor_version; /* Byte 136 */ 174081ff398SHannes Reinecke unsigned char fw_major_version; /* Byte 137 */ 175081ff398SHannes Reinecke enum { 176081ff398SHannes Reinecke MYRB_NO_STDBY_RBLD_OR_CHECK_IN_PROGRESS = 0x00, 177081ff398SHannes Reinecke MYRB_STDBY_RBLD_IN_PROGRESS = 0x01, 178081ff398SHannes Reinecke MYRB_BG_RBLD_IN_PROGRESS = 0x02, 179081ff398SHannes Reinecke MYRB_BG_CHECK_IN_PROGRESS = 0x03, 180081ff398SHannes Reinecke MYRB_STDBY_RBLD_COMPLETED_WITH_ERROR = 0xFF, 181081ff398SHannes Reinecke MYRB_BG_RBLD_OR_CHECK_FAILED_DRIVE_FAILED = 0xF0, 182081ff398SHannes Reinecke MYRB_BG_RBLD_OR_CHECK_FAILED_LDEV_FAILED = 0xF1, 183081ff398SHannes Reinecke MYRB_BG_RBLD_OR_CHECK_FAILED_OTHER = 0xF2, 184081ff398SHannes Reinecke MYRB_BG_RBLD_OR_CHECK_SUCCESS_TERMINATED = 0xF3 185081ff398SHannes Reinecke } __packed rbld; /* Byte 138 */ 186081ff398SHannes Reinecke unsigned char max_tcq; /* Byte 139 */ 187081ff398SHannes Reinecke unsigned char ldev_offline; /* Byte 140 */ 188081ff398SHannes Reinecke unsigned char rsvd4:8; /* Byte 141 */ 189081ff398SHannes Reinecke unsigned short ev_seq; /* Bytes 142-143 */ 190081ff398SHannes Reinecke unsigned char ldev_critical; /* Byte 144 */ 191081ff398SHannes Reinecke unsigned int rsvd5:24; /* Bytes 145-147 */ 192081ff398SHannes Reinecke unsigned char pdev_dead; /* Byte 148 */ 193081ff398SHannes Reinecke unsigned char rsvd6:8; /* Byte 149 */ 194081ff398SHannes Reinecke unsigned char rbld_count; /* Byte 150 */ 195081ff398SHannes Reinecke struct { 196081ff398SHannes Reinecke unsigned char rsvd7:3; /* Byte 151 Bits 0-2 */ 197081ff398SHannes Reinecke unsigned char bbu_present:1; /* Byte 151 Bit 3 */ 198081ff398SHannes Reinecke unsigned char rsvd8:4; /* Byte 151 Bits 4-7 */ 199081ff398SHannes Reinecke } misc; 200081ff398SHannes Reinecke struct { 201081ff398SHannes Reinecke unsigned char target; 202081ff398SHannes Reinecke unsigned char channel; 203081ff398SHannes Reinecke } dead_drives[21]; /* Bytes 152-194 */ 204081ff398SHannes Reinecke unsigned char rsvd9[62]; /* Bytes 195-255 */ 205081ff398SHannes Reinecke } __packed; 206081ff398SHannes Reinecke 207081ff398SHannes Reinecke /* 208081ff398SHannes Reinecke * DAC960 V1 Firmware Enquiry2 Command reply structure. 209081ff398SHannes Reinecke */ 210081ff398SHannes Reinecke struct myrb_enquiry2 { 211081ff398SHannes Reinecke struct { 212081ff398SHannes Reinecke enum { 213081ff398SHannes Reinecke DAC960_V1_P_PD_PU = 0x01, 214081ff398SHannes Reinecke DAC960_V1_PL = 0x02, 215081ff398SHannes Reinecke DAC960_V1_PG = 0x10, 216081ff398SHannes Reinecke DAC960_V1_PJ = 0x11, 217081ff398SHannes Reinecke DAC960_V1_PR = 0x12, 218081ff398SHannes Reinecke DAC960_V1_PT = 0x13, 219081ff398SHannes Reinecke DAC960_V1_PTL0 = 0x14, 220081ff398SHannes Reinecke DAC960_V1_PRL = 0x15, 221081ff398SHannes Reinecke DAC960_V1_PTL1 = 0x16, 222081ff398SHannes Reinecke DAC960_V1_1164P = 0x20 223081ff398SHannes Reinecke } __packed sub_model; /* Byte 0 */ 224081ff398SHannes Reinecke unsigned char actual_channels; /* Byte 1 */ 225081ff398SHannes Reinecke enum { 226081ff398SHannes Reinecke MYRB_5_CHANNEL_BOARD = 0x01, 227081ff398SHannes Reinecke MYRB_3_CHANNEL_BOARD = 0x02, 228081ff398SHannes Reinecke MYRB_2_CHANNEL_BOARD = 0x03, 229081ff398SHannes Reinecke MYRB_3_CHANNEL_ASIC_DAC = 0x04 230081ff398SHannes Reinecke } __packed model; /* Byte 2 */ 231081ff398SHannes Reinecke enum { 232081ff398SHannes Reinecke MYRB_EISA_CONTROLLER = 0x01, 233081ff398SHannes Reinecke MYRB_MCA_CONTROLLER = 0x02, 234081ff398SHannes Reinecke MYRB_PCI_CONTROLLER = 0x03, 235081ff398SHannes Reinecke MYRB_SCSI_TO_SCSI = 0x08 236081ff398SHannes Reinecke } __packed controller; /* Byte 3 */ 237081ff398SHannes Reinecke } hw; /* Bytes 0-3 */ 238081ff398SHannes Reinecke /* MajorVersion.MinorVersion-FirmwareType-TurnID */ 239081ff398SHannes Reinecke struct { 240081ff398SHannes Reinecke unsigned char major_version; /* Byte 4 */ 241081ff398SHannes Reinecke unsigned char minor_version; /* Byte 5 */ 242081ff398SHannes Reinecke unsigned char turn_id; /* Byte 6 */ 243081ff398SHannes Reinecke char firmware_type; /* Byte 7 */ 244081ff398SHannes Reinecke } fw; /* Bytes 4-7 */ 245081ff398SHannes Reinecke unsigned int rsvd1; /* Byte 8-11 */ 246081ff398SHannes Reinecke unsigned char cfg_chan; /* Byte 12 */ 247081ff398SHannes Reinecke unsigned char cur_chan; /* Byte 13 */ 248081ff398SHannes Reinecke unsigned char max_targets; /* Byte 14 */ 249081ff398SHannes Reinecke unsigned char max_tcq; /* Byte 15 */ 250081ff398SHannes Reinecke unsigned char max_ldev; /* Byte 16 */ 251081ff398SHannes Reinecke unsigned char max_arms; /* Byte 17 */ 252081ff398SHannes Reinecke unsigned char max_spans; /* Byte 18 */ 253081ff398SHannes Reinecke unsigned char rsvd2; /* Byte 19 */ 254081ff398SHannes Reinecke unsigned int rsvd3; /* Bytes 20-23 */ 255081ff398SHannes Reinecke unsigned int mem_size; /* Bytes 24-27 */ 256081ff398SHannes Reinecke unsigned int cache_size; /* Bytes 28-31 */ 257081ff398SHannes Reinecke unsigned int flash_size; /* Bytes 32-35 */ 258081ff398SHannes Reinecke unsigned int nvram_size; /* Bytes 36-39 */ 259081ff398SHannes Reinecke struct { 260081ff398SHannes Reinecke enum { 261081ff398SHannes Reinecke MYRB_RAM_TYPE_DRAM = 0x0, 262081ff398SHannes Reinecke MYRB_RAM_TYPE_EDO = 0x1, 263081ff398SHannes Reinecke MYRB_RAM_TYPE_SDRAM = 0x2, 264081ff398SHannes Reinecke MYRB_RAM_TYPE_Last = 0x7 265081ff398SHannes Reinecke } __packed ram:3; /* Byte 40 Bits 0-2 */ 266081ff398SHannes Reinecke enum { 267081ff398SHannes Reinecke MYRB_ERR_CORR_None = 0x0, 268081ff398SHannes Reinecke MYRB_ERR_CORR_Parity = 0x1, 269081ff398SHannes Reinecke MYRB_ERR_CORR_ECC = 0x2, 270081ff398SHannes Reinecke MYRB_ERR_CORR_Last = 0x7 271081ff398SHannes Reinecke } __packed ec:3; /* Byte 40 Bits 3-5 */ 272081ff398SHannes Reinecke unsigned char fast_page:1; /* Byte 40 Bit 6 */ 273081ff398SHannes Reinecke unsigned char low_power:1; /* Byte 40 Bit 7 */ 274081ff398SHannes Reinecke unsigned char rsvd4; /* Bytes 41 */ 275081ff398SHannes Reinecke } mem_type; 276081ff398SHannes Reinecke unsigned short clock_speed; /* Bytes 42-43 */ 277081ff398SHannes Reinecke unsigned short mem_speed; /* Bytes 44-45 */ 278081ff398SHannes Reinecke unsigned short hw_speed; /* Bytes 46-47 */ 279081ff398SHannes Reinecke unsigned char rsvd5[12]; /* Bytes 48-59 */ 280081ff398SHannes Reinecke unsigned short max_cmds; /* Bytes 60-61 */ 281081ff398SHannes Reinecke unsigned short max_sge; /* Bytes 62-63 */ 282081ff398SHannes Reinecke unsigned short max_drv_cmds; /* Bytes 64-65 */ 283081ff398SHannes Reinecke unsigned short max_io_desc; /* Bytes 66-67 */ 284081ff398SHannes Reinecke unsigned short max_sectors; /* Bytes 68-69 */ 285081ff398SHannes Reinecke unsigned char latency; /* Byte 70 */ 286081ff398SHannes Reinecke unsigned char rsvd6; /* Byte 71 */ 287081ff398SHannes Reinecke unsigned char scsi_tmo; /* Byte 72 */ 288081ff398SHannes Reinecke unsigned char rsvd7; /* Byte 73 */ 289081ff398SHannes Reinecke unsigned short min_freelines; /* Bytes 74-75 */ 290081ff398SHannes Reinecke unsigned char rsvd8[8]; /* Bytes 76-83 */ 291081ff398SHannes Reinecke unsigned char rbld_rate_const; /* Byte 84 */ 292081ff398SHannes Reinecke unsigned char rsvd9[11]; /* Byte 85-95 */ 293081ff398SHannes Reinecke unsigned short pdrv_block_size; /* Bytes 96-97 */ 294081ff398SHannes Reinecke unsigned short ldev_block_size; /* Bytes 98-99 */ 295081ff398SHannes Reinecke unsigned short max_blocks_per_cmd; /* Bytes 100-101 */ 296081ff398SHannes Reinecke unsigned short block_factor; /* Bytes 102-103 */ 297081ff398SHannes Reinecke unsigned short cacheline_size; /* Bytes 104-105 */ 298081ff398SHannes Reinecke struct { 299081ff398SHannes Reinecke enum { 300081ff398SHannes Reinecke MYRB_WIDTH_NARROW_8BIT = 0x0, 301081ff398SHannes Reinecke MYRB_WIDTH_WIDE_16BIT = 0x1, 302081ff398SHannes Reinecke MYRB_WIDTH_WIDE_32BIT = 0x2 303081ff398SHannes Reinecke } __packed bus_width:2; /* Byte 106 Bits 0-1 */ 304081ff398SHannes Reinecke enum { 305081ff398SHannes Reinecke MYRB_SCSI_SPEED_FAST = 0x0, 306081ff398SHannes Reinecke MYRB_SCSI_SPEED_ULTRA = 0x1, 307081ff398SHannes Reinecke MYRB_SCSI_SPEED_ULTRA2 = 0x2 308081ff398SHannes Reinecke } __packed bus_speed:2; /* Byte 106 Bits 2-3 */ 309081ff398SHannes Reinecke unsigned char differential:1; /* Byte 106 Bit 4 */ 310081ff398SHannes Reinecke unsigned char rsvd10:3; /* Byte 106 Bits 5-7 */ 311081ff398SHannes Reinecke } scsi_cap; 312081ff398SHannes Reinecke unsigned char rsvd11[5]; /* Byte 107-111 */ 313081ff398SHannes Reinecke unsigned short fw_build; /* Bytes 112-113 */ 314081ff398SHannes Reinecke enum { 315081ff398SHannes Reinecke MYRB_FAULT_AEMI = 0x01, 316081ff398SHannes Reinecke MYRB_FAULT_OEM1 = 0x02, 317081ff398SHannes Reinecke MYRB_FAULT_OEM2 = 0x04, 318081ff398SHannes Reinecke MYRB_FAULT_OEM3 = 0x08, 319081ff398SHannes Reinecke MYRB_FAULT_CONNER = 0x10, 320081ff398SHannes Reinecke MYRB_FAULT_SAFTE = 0x20 321081ff398SHannes Reinecke } __packed fault_mgmt; /* Byte 114 */ 322081ff398SHannes Reinecke unsigned char rsvd12; /* Byte 115 */ 323081ff398SHannes Reinecke struct { 324081ff398SHannes Reinecke unsigned int clustering:1; /* Byte 116 Bit 0 */ 325081ff398SHannes Reinecke unsigned int online_RAID_expansion:1; /* Byte 116 Bit 1 */ 326081ff398SHannes Reinecke unsigned int readahead:1; /* Byte 116 Bit 2 */ 327081ff398SHannes Reinecke unsigned int bgi:1; /* Byte 116 Bit 3 */ 328081ff398SHannes Reinecke unsigned int rsvd13:28; /* Bytes 116-119 */ 329081ff398SHannes Reinecke } fw_features; 330081ff398SHannes Reinecke unsigned char rsvd14[8]; /* Bytes 120-127 */ 331081ff398SHannes Reinecke } __packed; 332081ff398SHannes Reinecke 333081ff398SHannes Reinecke /* 334081ff398SHannes Reinecke * DAC960 V1 Firmware Logical Drive State type. 335081ff398SHannes Reinecke */ 336081ff398SHannes Reinecke enum myrb_devstate { 337081ff398SHannes Reinecke MYRB_DEVICE_DEAD = 0x00, 338081ff398SHannes Reinecke MYRB_DEVICE_WO = 0x02, 339081ff398SHannes Reinecke MYRB_DEVICE_ONLINE = 0x03, 340081ff398SHannes Reinecke MYRB_DEVICE_CRITICAL = 0x04, 341081ff398SHannes Reinecke MYRB_DEVICE_STANDBY = 0x10, 342081ff398SHannes Reinecke MYRB_DEVICE_OFFLINE = 0xFF 343081ff398SHannes Reinecke } __packed; 344081ff398SHannes Reinecke 345081ff398SHannes Reinecke /* 346081ff398SHannes Reinecke * DAC960 V1 RAID Levels 347081ff398SHannes Reinecke */ 348081ff398SHannes Reinecke enum myrb_raidlevel { 349081ff398SHannes Reinecke MYRB_RAID_LEVEL0 = 0x0, /* RAID 0 */ 350081ff398SHannes Reinecke MYRB_RAID_LEVEL1 = 0x1, /* RAID 1 */ 351081ff398SHannes Reinecke MYRB_RAID_LEVEL3 = 0x3, /* RAID 3 */ 352081ff398SHannes Reinecke MYRB_RAID_LEVEL5 = 0x5, /* RAID 5 */ 353081ff398SHannes Reinecke MYRB_RAID_LEVEL6 = 0x6, /* RAID 6 */ 354081ff398SHannes Reinecke MYRB_RAID_JBOD = 0x7, /* RAID 7 (JBOD) */ 355081ff398SHannes Reinecke } __packed; 356081ff398SHannes Reinecke 357081ff398SHannes Reinecke /* 358081ff398SHannes Reinecke * DAC960 V1 Firmware Logical Drive Information structure. 359081ff398SHannes Reinecke */ 360081ff398SHannes Reinecke struct myrb_ldev_info { 361081ff398SHannes Reinecke unsigned int size; /* Bytes 0-3 */ 362081ff398SHannes Reinecke enum myrb_devstate state; /* Byte 4 */ 363081ff398SHannes Reinecke unsigned int raid_level:7; /* Byte 5 Bits 0-6 */ 364081ff398SHannes Reinecke unsigned int wb_enabled:1; /* Byte 5 Bit 7 */ 365081ff398SHannes Reinecke unsigned int rsvd:16; /* Bytes 6-7 */ 366081ff398SHannes Reinecke }; 367081ff398SHannes Reinecke 368081ff398SHannes Reinecke /* 369081ff398SHannes Reinecke * DAC960 V1 Firmware Perform Event Log Operation Types. 370081ff398SHannes Reinecke */ 371081ff398SHannes Reinecke #define DAC960_V1_GetEventLogEntry 0x00 372081ff398SHannes Reinecke 373081ff398SHannes Reinecke /* 374081ff398SHannes Reinecke * DAC960 V1 Firmware Get Event Log Entry Command reply structure. 375081ff398SHannes Reinecke */ 376081ff398SHannes Reinecke struct myrb_log_entry { 377081ff398SHannes Reinecke unsigned char msg_type; /* Byte 0 */ 378081ff398SHannes Reinecke unsigned char msg_len; /* Byte 1 */ 379081ff398SHannes Reinecke unsigned char target:5; /* Byte 2 Bits 0-4 */ 380081ff398SHannes Reinecke unsigned char channel:3; /* Byte 2 Bits 5-7 */ 381081ff398SHannes Reinecke unsigned char lun:6; /* Byte 3 Bits 0-5 */ 382081ff398SHannes Reinecke unsigned char rsvd1:2; /* Byte 3 Bits 6-7 */ 383081ff398SHannes Reinecke unsigned short seq_num; /* Bytes 4-5 */ 384081ff398SHannes Reinecke unsigned char sense[26]; /* Bytes 6-31 */ 385081ff398SHannes Reinecke }; 386081ff398SHannes Reinecke 387081ff398SHannes Reinecke /* 388081ff398SHannes Reinecke * DAC960 V1 Firmware Get Device State Command reply structure. 389081ff398SHannes Reinecke * The structure is padded by 2 bytes for compatibility with Version 2.xx 390081ff398SHannes Reinecke * Firmware. 391081ff398SHannes Reinecke */ 392081ff398SHannes Reinecke struct myrb_pdev_state { 393081ff398SHannes Reinecke unsigned int present:1; /* Byte 0 Bit 0 */ 394081ff398SHannes Reinecke unsigned int :7; /* Byte 0 Bits 1-7 */ 395081ff398SHannes Reinecke enum { 396081ff398SHannes Reinecke MYRB_TYPE_OTHER = 0x0, 397081ff398SHannes Reinecke MYRB_TYPE_DISK = 0x1, 398081ff398SHannes Reinecke MYRB_TYPE_TAPE = 0x2, 399081ff398SHannes Reinecke MYRB_TYPE_CDROM_OR_WORM = 0x3 400081ff398SHannes Reinecke } __packed devtype:2; /* Byte 1 Bits 0-1 */ 401081ff398SHannes Reinecke unsigned int rsvd1:1; /* Byte 1 Bit 2 */ 402081ff398SHannes Reinecke unsigned int fast20:1; /* Byte 1 Bit 3 */ 403081ff398SHannes Reinecke unsigned int sync:1; /* Byte 1 Bit 4 */ 404081ff398SHannes Reinecke unsigned int fast:1; /* Byte 1 Bit 5 */ 405081ff398SHannes Reinecke unsigned int wide:1; /* Byte 1 Bit 6 */ 406081ff398SHannes Reinecke unsigned int tcq_supported:1; /* Byte 1 Bit 7 */ 407081ff398SHannes Reinecke enum myrb_devstate state; /* Byte 2 */ 408081ff398SHannes Reinecke unsigned int rsvd2:8; /* Byte 3 */ 409081ff398SHannes Reinecke unsigned int sync_multiplier; /* Byte 4 */ 410081ff398SHannes Reinecke unsigned int sync_offset:5; /* Byte 5 Bits 0-4 */ 411081ff398SHannes Reinecke unsigned int rsvd3:3; /* Byte 5 Bits 5-7 */ 412081ff398SHannes Reinecke unsigned int size; /* Bytes 6-9 */ 413081ff398SHannes Reinecke unsigned int rsvd4:16; /* Bytes 10-11 */ 414081ff398SHannes Reinecke } __packed; 415081ff398SHannes Reinecke 416081ff398SHannes Reinecke /* 417081ff398SHannes Reinecke * DAC960 V1 Firmware Get Rebuild Progress Command reply structure. 418081ff398SHannes Reinecke */ 419081ff398SHannes Reinecke struct myrb_rbld_progress { 420081ff398SHannes Reinecke unsigned int ldev_num; /* Bytes 0-3 */ 421081ff398SHannes Reinecke unsigned int ldev_size; /* Bytes 4-7 */ 422081ff398SHannes Reinecke unsigned int blocks_left; /* Bytes 8-11 */ 423081ff398SHannes Reinecke }; 424081ff398SHannes Reinecke 425081ff398SHannes Reinecke /* 426081ff398SHannes Reinecke * DAC960 V1 Firmware Background Initialization Status Command reply structure. 427081ff398SHannes Reinecke */ 428081ff398SHannes Reinecke struct myrb_bgi_status { 429081ff398SHannes Reinecke unsigned int ldev_size; /* Bytes 0-3 */ 430081ff398SHannes Reinecke unsigned int blocks_done; /* Bytes 4-7 */ 431081ff398SHannes Reinecke unsigned char rsvd1[12]; /* Bytes 8-19 */ 432081ff398SHannes Reinecke unsigned int ldev_num; /* Bytes 20-23 */ 433081ff398SHannes Reinecke unsigned char raid_level; /* Byte 24 */ 434081ff398SHannes Reinecke enum { 435081ff398SHannes Reinecke MYRB_BGI_INVALID = 0x00, 436081ff398SHannes Reinecke MYRB_BGI_STARTED = 0x02, 437081ff398SHannes Reinecke MYRB_BGI_INPROGRESS = 0x04, 438081ff398SHannes Reinecke MYRB_BGI_SUSPENDED = 0x05, 439081ff398SHannes Reinecke MYRB_BGI_CANCELLED = 0x06 440081ff398SHannes Reinecke } __packed status; /* Byte 25 */ 441081ff398SHannes Reinecke unsigned char rsvd2[6]; /* Bytes 26-31 */ 442081ff398SHannes Reinecke }; 443081ff398SHannes Reinecke 444081ff398SHannes Reinecke /* 445081ff398SHannes Reinecke * DAC960 V1 Firmware Error Table Entry structure. 446081ff398SHannes Reinecke */ 447081ff398SHannes Reinecke struct myrb_error_entry { 448081ff398SHannes Reinecke unsigned char parity_err; /* Byte 0 */ 449081ff398SHannes Reinecke unsigned char soft_err; /* Byte 1 */ 450081ff398SHannes Reinecke unsigned char hard_err; /* Byte 2 */ 451081ff398SHannes Reinecke unsigned char misc_err; /* Byte 3 */ 452081ff398SHannes Reinecke }; 453081ff398SHannes Reinecke 454081ff398SHannes Reinecke /* 455081ff398SHannes Reinecke * DAC960 V1 Firmware Read Config2 Command reply structure. 456081ff398SHannes Reinecke */ 457081ff398SHannes Reinecke struct myrb_config2 { 458081ff398SHannes Reinecke unsigned rsvd1:1; /* Byte 0 Bit 0 */ 459081ff398SHannes Reinecke unsigned active_negation:1; /* Byte 0 Bit 1 */ 460081ff398SHannes Reinecke unsigned rsvd2:5; /* Byte 0 Bits 2-6 */ 461081ff398SHannes Reinecke unsigned no_rescan_on_reset_during_scan:1; /* Byte 0 Bit 7 */ 462081ff398SHannes Reinecke unsigned StorageWorks_support:1; /* Byte 1 Bit 0 */ 463081ff398SHannes Reinecke unsigned HewlettPackard_support:1; /* Byte 1 Bit 1 */ 464081ff398SHannes Reinecke unsigned no_disconnect_on_first_command:1; /* Byte 1 Bit 2 */ 465081ff398SHannes Reinecke unsigned rsvd3:2; /* Byte 1 Bits 3-4 */ 466081ff398SHannes Reinecke unsigned AEMI_ARM:1; /* Byte 1 Bit 5 */ 467081ff398SHannes Reinecke unsigned AEMI_OFM:1; /* Byte 1 Bit 6 */ 468081ff398SHannes Reinecke unsigned rsvd4:1; /* Byte 1 Bit 7 */ 469081ff398SHannes Reinecke enum { 470081ff398SHannes Reinecke MYRB_OEMID_MYLEX = 0x00, 471081ff398SHannes Reinecke MYRB_OEMID_IBM = 0x08, 472081ff398SHannes Reinecke MYRB_OEMID_HP = 0x0A, 473081ff398SHannes Reinecke MYRB_OEMID_DEC = 0x0C, 474081ff398SHannes Reinecke MYRB_OEMID_SIEMENS = 0x10, 475081ff398SHannes Reinecke MYRB_OEMID_INTEL = 0x12 476081ff398SHannes Reinecke } __packed OEMID; /* Byte 2 */ 477081ff398SHannes Reinecke unsigned char oem_model_number; /* Byte 3 */ 478081ff398SHannes Reinecke unsigned char physical_sector; /* Byte 4 */ 479081ff398SHannes Reinecke unsigned char logical_sector; /* Byte 5 */ 480081ff398SHannes Reinecke unsigned char block_factor; /* Byte 6 */ 481081ff398SHannes Reinecke unsigned readahead_enabled:1; /* Byte 7 Bit 0 */ 482081ff398SHannes Reinecke unsigned low_BIOS_delay:1; /* Byte 7 Bit 1 */ 483081ff398SHannes Reinecke unsigned rsvd5:2; /* Byte 7 Bits 2-3 */ 484081ff398SHannes Reinecke unsigned restrict_reassign_to_one_sector:1; /* Byte 7 Bit 4 */ 485081ff398SHannes Reinecke unsigned rsvd6:1; /* Byte 7 Bit 5 */ 486081ff398SHannes Reinecke unsigned FUA_during_write_recovery:1; /* Byte 7 Bit 6 */ 487081ff398SHannes Reinecke unsigned enable_LeftSymmetricRAID5Algorithm:1; /* Byte 7 Bit 7 */ 488081ff398SHannes Reinecke unsigned char default_rebuild_rate; /* Byte 8 */ 489081ff398SHannes Reinecke unsigned char rsvd7; /* Byte 9 */ 490081ff398SHannes Reinecke unsigned char blocks_per_cacheline; /* Byte 10 */ 491081ff398SHannes Reinecke unsigned char blocks_per_stripe; /* Byte 11 */ 492081ff398SHannes Reinecke struct { 493081ff398SHannes Reinecke enum { 494081ff398SHannes Reinecke MYRB_SPEED_ASYNC = 0x0, 495081ff398SHannes Reinecke MYRB_SPEED_SYNC_8MHz = 0x1, 496081ff398SHannes Reinecke MYRB_SPEED_SYNC_5MHz = 0x2, 497081ff398SHannes Reinecke MYRB_SPEED_SYNC_10_OR_20MHz = 0x3 498081ff398SHannes Reinecke } __packed speed:2; /* Byte 11 Bits 0-1 */ 499081ff398SHannes Reinecke unsigned force_8bit:1; /* Byte 11 Bit 2 */ 500081ff398SHannes Reinecke unsigned disable_fast20:1; /* Byte 11 Bit 3 */ 501081ff398SHannes Reinecke unsigned rsvd8:3; /* Byte 11 Bits 4-6 */ 502081ff398SHannes Reinecke unsigned enable_tcq:1; /* Byte 11 Bit 7 */ 503081ff398SHannes Reinecke } __packed channelparam[6]; /* Bytes 12-17 */ 504081ff398SHannes Reinecke unsigned char SCSIInitiatorID; /* Byte 18 */ 505081ff398SHannes Reinecke unsigned char rsvd9; /* Byte 19 */ 506081ff398SHannes Reinecke enum { 507081ff398SHannes Reinecke MYRB_STARTUP_CONTROLLER_SPINUP = 0x00, 508081ff398SHannes Reinecke MYRB_STARTUP_POWERON_SPINUP = 0x01 509081ff398SHannes Reinecke } __packed startup; /* Byte 20 */ 510081ff398SHannes Reinecke unsigned char simultaneous_device_spinup_count; /* Byte 21 */ 511081ff398SHannes Reinecke unsigned char seconds_delay_between_spinups; /* Byte 22 */ 512081ff398SHannes Reinecke unsigned char rsvd10[29]; /* Bytes 23-51 */ 513081ff398SHannes Reinecke unsigned BIOS_disabled:1; /* Byte 52 Bit 0 */ 514081ff398SHannes Reinecke unsigned CDROM_boot_enabled:1; /* Byte 52 Bit 1 */ 515081ff398SHannes Reinecke unsigned rsvd11:3; /* Byte 52 Bits 2-4 */ 516081ff398SHannes Reinecke enum { 517081ff398SHannes Reinecke MYRB_GEOM_128_32 = 0x0, 518081ff398SHannes Reinecke MYRB_GEOM_255_63 = 0x1, 519081ff398SHannes Reinecke MYRB_GEOM_RESERVED1 = 0x2, 520081ff398SHannes Reinecke MYRB_GEOM_RESERVED2 = 0x3 521081ff398SHannes Reinecke } __packed drive_geometry:2; /* Byte 52 Bits 5-6 */ 522081ff398SHannes Reinecke unsigned rsvd12:1; /* Byte 52 Bit 7 */ 523081ff398SHannes Reinecke unsigned char rsvd13[9]; /* Bytes 53-61 */ 524081ff398SHannes Reinecke unsigned short csum; /* Bytes 62-63 */ 525081ff398SHannes Reinecke }; 526081ff398SHannes Reinecke 527081ff398SHannes Reinecke /* 528081ff398SHannes Reinecke * DAC960 V1 Firmware DCDB request structure. 529081ff398SHannes Reinecke */ 530081ff398SHannes Reinecke struct myrb_dcdb { 531081ff398SHannes Reinecke unsigned target:4; /* Byte 0 Bits 0-3 */ 532081ff398SHannes Reinecke unsigned channel:4; /* Byte 0 Bits 4-7 */ 533081ff398SHannes Reinecke enum { 534081ff398SHannes Reinecke MYRB_DCDB_XFER_NONE = 0, 535081ff398SHannes Reinecke MYRB_DCDB_XFER_DEVICE_TO_SYSTEM = 1, 536081ff398SHannes Reinecke MYRB_DCDB_XFER_SYSTEM_TO_DEVICE = 2, 537081ff398SHannes Reinecke MYRB_DCDB_XFER_ILLEGAL = 3 538081ff398SHannes Reinecke } __packed data_xfer:2; /* Byte 1 Bits 0-1 */ 539081ff398SHannes Reinecke unsigned early_status:1; /* Byte 1 Bit 2 */ 540081ff398SHannes Reinecke unsigned rsvd1:1; /* Byte 1 Bit 3 */ 541081ff398SHannes Reinecke enum { 542081ff398SHannes Reinecke MYRB_DCDB_TMO_24_HRS = 0, 543081ff398SHannes Reinecke MYRB_DCDB_TMO_10_SECS = 1, 544081ff398SHannes Reinecke MYRB_DCDB_TMO_60_SECS = 2, 545081ff398SHannes Reinecke MYRB_DCDB_TMO_10_MINS = 3 546081ff398SHannes Reinecke } __packed timeout:2; /* Byte 1 Bits 4-5 */ 547081ff398SHannes Reinecke unsigned no_autosense:1; /* Byte 1 Bit 6 */ 548081ff398SHannes Reinecke unsigned allow_disconnect:1; /* Byte 1 Bit 7 */ 549081ff398SHannes Reinecke unsigned short xfer_len_lo; /* Bytes 2-3 */ 550081ff398SHannes Reinecke u32 dma_addr; /* Bytes 4-7 */ 551081ff398SHannes Reinecke unsigned char cdb_len:4; /* Byte 8 Bits 0-3 */ 552081ff398SHannes Reinecke unsigned char xfer_len_hi4:4; /* Byte 8 Bits 4-7 */ 553081ff398SHannes Reinecke unsigned char sense_len; /* Byte 9 */ 554081ff398SHannes Reinecke unsigned char cdb[12]; /* Bytes 10-21 */ 555081ff398SHannes Reinecke unsigned char sense[64]; /* Bytes 22-85 */ 556081ff398SHannes Reinecke unsigned char status; /* Byte 86 */ 557081ff398SHannes Reinecke unsigned char rsvd2; /* Byte 87 */ 558081ff398SHannes Reinecke }; 559081ff398SHannes Reinecke 560081ff398SHannes Reinecke /* 561081ff398SHannes Reinecke * DAC960 V1 Firmware Scatter/Gather List Type 1 32 Bit Address 562081ff398SHannes Reinecke *32 Bit Byte Count structure. 563081ff398SHannes Reinecke */ 564081ff398SHannes Reinecke struct myrb_sge { 565081ff398SHannes Reinecke u32 sge_addr; /* Bytes 0-3 */ 566081ff398SHannes Reinecke u32 sge_count; /* Bytes 4-7 */ 567081ff398SHannes Reinecke }; 568081ff398SHannes Reinecke 569081ff398SHannes Reinecke /* 570081ff398SHannes Reinecke * 13 Byte DAC960 V1 Firmware Command Mailbox structure. 571081ff398SHannes Reinecke * Bytes 13-15 are not used. The structure is padded to 16 bytes for 572081ff398SHannes Reinecke * efficient access. 573081ff398SHannes Reinecke */ 574081ff398SHannes Reinecke union myrb_cmd_mbox { 575081ff398SHannes Reinecke unsigned int words[4]; /* Words 0-3 */ 576081ff398SHannes Reinecke unsigned char bytes[16]; /* Bytes 0-15 */ 577081ff398SHannes Reinecke struct { 578081ff398SHannes Reinecke enum myrb_cmd_opcode opcode; /* Byte 0 */ 579081ff398SHannes Reinecke unsigned char id; /* Byte 1 */ 580081ff398SHannes Reinecke unsigned char rsvd[14]; /* Bytes 2-15 */ 581081ff398SHannes Reinecke } __packed common; 582081ff398SHannes Reinecke struct { 583081ff398SHannes Reinecke enum myrb_cmd_opcode opcode; /* Byte 0 */ 584081ff398SHannes Reinecke unsigned char id; /* Byte 1 */ 585081ff398SHannes Reinecke unsigned char rsvd1[6]; /* Bytes 2-7 */ 586081ff398SHannes Reinecke u32 addr; /* Bytes 8-11 */ 587081ff398SHannes Reinecke unsigned char rsvd2[4]; /* Bytes 12-15 */ 588081ff398SHannes Reinecke } __packed type3; 589081ff398SHannes Reinecke struct { 590081ff398SHannes Reinecke enum myrb_cmd_opcode opcode; /* Byte 0 */ 591081ff398SHannes Reinecke unsigned char id; /* Byte 1 */ 592081ff398SHannes Reinecke unsigned char optype; /* Byte 2 */ 593081ff398SHannes Reinecke unsigned char rsvd1[5]; /* Bytes 3-7 */ 594081ff398SHannes Reinecke u32 addr; /* Bytes 8-11 */ 595081ff398SHannes Reinecke unsigned char rsvd2[4]; /* Bytes 12-15 */ 596081ff398SHannes Reinecke } __packed type3B; 597081ff398SHannes Reinecke struct { 598081ff398SHannes Reinecke enum myrb_cmd_opcode opcode; /* Byte 0 */ 599081ff398SHannes Reinecke unsigned char id; /* Byte 1 */ 600081ff398SHannes Reinecke unsigned char rsvd1[5]; /* Bytes 2-6 */ 601081ff398SHannes Reinecke unsigned char ldev_num:6; /* Byte 7 Bits 0-6 */ 602081ff398SHannes Reinecke unsigned char auto_restore:1; /* Byte 7 Bit 7 */ 603081ff398SHannes Reinecke unsigned char rsvd2[8]; /* Bytes 8-15 */ 604081ff398SHannes Reinecke } __packed type3C; 605081ff398SHannes Reinecke struct { 606081ff398SHannes Reinecke enum myrb_cmd_opcode opcode; /* Byte 0 */ 607081ff398SHannes Reinecke unsigned char id; /* Byte 1 */ 608081ff398SHannes Reinecke unsigned char channel; /* Byte 2 */ 609081ff398SHannes Reinecke unsigned char target; /* Byte 3 */ 610081ff398SHannes Reinecke enum myrb_devstate state; /* Byte 4 */ 611081ff398SHannes Reinecke unsigned char rsvd1[3]; /* Bytes 5-7 */ 612081ff398SHannes Reinecke u32 addr; /* Bytes 8-11 */ 613081ff398SHannes Reinecke unsigned char rsvd2[4]; /* Bytes 12-15 */ 614081ff398SHannes Reinecke } __packed type3D; 615081ff398SHannes Reinecke struct { 616081ff398SHannes Reinecke enum myrb_cmd_opcode opcode; /* Byte 0 */ 617081ff398SHannes Reinecke unsigned char id; /* Byte 1 */ 618081ff398SHannes Reinecke unsigned char optype; /* Byte 2 */ 619081ff398SHannes Reinecke unsigned char opqual; /* Byte 3 */ 620081ff398SHannes Reinecke unsigned short ev_seq; /* Bytes 4-5 */ 621081ff398SHannes Reinecke unsigned char rsvd1[2]; /* Bytes 6-7 */ 622081ff398SHannes Reinecke u32 addr; /* Bytes 8-11 */ 623081ff398SHannes Reinecke unsigned char rsvd2[4]; /* Bytes 12-15 */ 624081ff398SHannes Reinecke } __packed type3E; 625081ff398SHannes Reinecke struct { 626081ff398SHannes Reinecke enum myrb_cmd_opcode opcode; /* Byte 0 */ 627081ff398SHannes Reinecke unsigned char id; /* Byte 1 */ 628081ff398SHannes Reinecke unsigned char rsvd1[2]; /* Bytes 2-3 */ 629081ff398SHannes Reinecke unsigned char rbld_rate; /* Byte 4 */ 630081ff398SHannes Reinecke unsigned char rsvd2[3]; /* Bytes 5-7 */ 631081ff398SHannes Reinecke u32 addr; /* Bytes 8-11 */ 632081ff398SHannes Reinecke unsigned char rsvd3[4]; /* Bytes 12-15 */ 633081ff398SHannes Reinecke } __packed type3R; 634081ff398SHannes Reinecke struct { 635081ff398SHannes Reinecke enum myrb_cmd_opcode opcode; /* Byte 0 */ 636081ff398SHannes Reinecke unsigned char id; /* Byte 1 */ 637081ff398SHannes Reinecke unsigned short xfer_len; /* Bytes 2-3 */ 638081ff398SHannes Reinecke unsigned int lba; /* Bytes 4-7 */ 639081ff398SHannes Reinecke u32 addr; /* Bytes 8-11 */ 640081ff398SHannes Reinecke unsigned char ldev_num; /* Byte 12 */ 641081ff398SHannes Reinecke unsigned char rsvd[3]; /* Bytes 13-15 */ 642081ff398SHannes Reinecke } __packed type4; 643081ff398SHannes Reinecke struct { 644081ff398SHannes Reinecke enum myrb_cmd_opcode opcode; /* Byte 0 */ 645081ff398SHannes Reinecke unsigned char id; /* Byte 1 */ 646081ff398SHannes Reinecke struct { 647081ff398SHannes Reinecke unsigned short xfer_len:11; /* Bytes 2-3 */ 648081ff398SHannes Reinecke unsigned char ldev_num:5; /* Byte 3 Bits 3-7 */ 649081ff398SHannes Reinecke } __packed ld; 650081ff398SHannes Reinecke unsigned int lba; /* Bytes 4-7 */ 651081ff398SHannes Reinecke u32 addr; /* Bytes 8-11 */ 652081ff398SHannes Reinecke unsigned char sg_count:6; /* Byte 12 Bits 0-5 */ 653081ff398SHannes Reinecke enum { 654081ff398SHannes Reinecke MYRB_SGL_ADDR32_COUNT32 = 0x0, 655081ff398SHannes Reinecke MYRB_SGL_ADDR32_COUNT16 = 0x1, 656081ff398SHannes Reinecke MYRB_SGL_COUNT32_ADDR32 = 0x2, 657081ff398SHannes Reinecke MYRB_SGL_COUNT16_ADDR32 = 0x3 658081ff398SHannes Reinecke } __packed sg_type:2; /* Byte 12 Bits 6-7 */ 659081ff398SHannes Reinecke unsigned char rsvd[3]; /* Bytes 13-15 */ 660081ff398SHannes Reinecke } __packed type5; 661081ff398SHannes Reinecke struct { 662081ff398SHannes Reinecke enum myrb_cmd_opcode opcode; /* Byte 0 */ 663081ff398SHannes Reinecke unsigned char id; /* Byte 1 */ 664081ff398SHannes Reinecke unsigned char opcode2; /* Byte 2 */ 665081ff398SHannes Reinecke unsigned char rsvd1:8; /* Byte 3 */ 666081ff398SHannes Reinecke u32 cmd_mbox_addr; /* Bytes 4-7 */ 667081ff398SHannes Reinecke u32 stat_mbox_addr; /* Bytes 8-11 */ 668081ff398SHannes Reinecke unsigned char rsvd2[4]; /* Bytes 12-15 */ 669081ff398SHannes Reinecke } __packed typeX; 670081ff398SHannes Reinecke }; 671081ff398SHannes Reinecke 672081ff398SHannes Reinecke /* 673081ff398SHannes Reinecke * DAC960 V1 Firmware Controller Status Mailbox structure. 674081ff398SHannes Reinecke */ 675081ff398SHannes Reinecke struct myrb_stat_mbox { 676081ff398SHannes Reinecke unsigned char id; /* Byte 0 */ 677081ff398SHannes Reinecke unsigned char rsvd:7; /* Byte 1 Bits 0-6 */ 678081ff398SHannes Reinecke unsigned char valid:1; /* Byte 1 Bit 7 */ 679081ff398SHannes Reinecke unsigned short status; /* Bytes 2-3 */ 680081ff398SHannes Reinecke }; 681081ff398SHannes Reinecke 682081ff398SHannes Reinecke struct myrb_cmdblk { 683081ff398SHannes Reinecke union myrb_cmd_mbox mbox; 684081ff398SHannes Reinecke unsigned short status; 685081ff398SHannes Reinecke struct completion *completion; 686081ff398SHannes Reinecke struct myrb_dcdb *dcdb; 687081ff398SHannes Reinecke dma_addr_t dcdb_addr; 688081ff398SHannes Reinecke struct myrb_sge *sgl; 689081ff398SHannes Reinecke dma_addr_t sgl_addr; 690081ff398SHannes Reinecke }; 691081ff398SHannes Reinecke 692081ff398SHannes Reinecke struct myrb_hba { 693081ff398SHannes Reinecke unsigned int ldev_block_size; 694081ff398SHannes Reinecke unsigned char ldev_geom_heads; 695081ff398SHannes Reinecke unsigned char ldev_geom_sectors; 696081ff398SHannes Reinecke unsigned char bus_width; 697081ff398SHannes Reinecke unsigned short stripe_size; 698081ff398SHannes Reinecke unsigned short segment_size; 699081ff398SHannes Reinecke unsigned short new_ev_seq; 700081ff398SHannes Reinecke unsigned short old_ev_seq; 701081ff398SHannes Reinecke bool dual_mode_interface; 702081ff398SHannes Reinecke bool bgi_status_supported; 703081ff398SHannes Reinecke bool safte_enabled; 704081ff398SHannes Reinecke bool need_ldev_info; 705081ff398SHannes Reinecke bool need_err_info; 706081ff398SHannes Reinecke bool need_rbld; 707081ff398SHannes Reinecke bool need_cc_status; 708081ff398SHannes Reinecke bool need_bgi_status; 709081ff398SHannes Reinecke bool rbld_first; 710081ff398SHannes Reinecke 711081ff398SHannes Reinecke struct pci_dev *pdev; 712081ff398SHannes Reinecke struct Scsi_Host *host; 713081ff398SHannes Reinecke 714081ff398SHannes Reinecke struct workqueue_struct *work_q; 715081ff398SHannes Reinecke char work_q_name[20]; 716081ff398SHannes Reinecke struct delayed_work monitor_work; 717081ff398SHannes Reinecke unsigned long primary_monitor_time; 718081ff398SHannes Reinecke unsigned long secondary_monitor_time; 719081ff398SHannes Reinecke 720081ff398SHannes Reinecke struct dma_pool *sg_pool; 721081ff398SHannes Reinecke struct dma_pool *dcdb_pool; 722081ff398SHannes Reinecke 723081ff398SHannes Reinecke spinlock_t queue_lock; 724081ff398SHannes Reinecke 725081ff398SHannes Reinecke void (*qcmd)(struct myrb_hba *cs, struct myrb_cmdblk *cmd_blk); 726081ff398SHannes Reinecke void (*write_cmd_mbox)(union myrb_cmd_mbox *next_mbox, 727081ff398SHannes Reinecke union myrb_cmd_mbox *cmd_mbox); 728081ff398SHannes Reinecke void (*get_cmd_mbox)(void __iomem *base); 729081ff398SHannes Reinecke void (*disable_intr)(void __iomem *base); 730081ff398SHannes Reinecke void (*reset)(void __iomem *base); 731081ff398SHannes Reinecke 732081ff398SHannes Reinecke unsigned int ctlr_num; 733081ff398SHannes Reinecke unsigned char model_name[20]; 734081ff398SHannes Reinecke unsigned char fw_version[12]; 735081ff398SHannes Reinecke 736081ff398SHannes Reinecke unsigned int irq; 737081ff398SHannes Reinecke phys_addr_t io_addr; 738081ff398SHannes Reinecke phys_addr_t pci_addr; 739081ff398SHannes Reinecke void __iomem *io_base; 740081ff398SHannes Reinecke void __iomem *mmio_base; 741081ff398SHannes Reinecke 742081ff398SHannes Reinecke size_t cmd_mbox_size; 743081ff398SHannes Reinecke dma_addr_t cmd_mbox_addr; 744081ff398SHannes Reinecke union myrb_cmd_mbox *first_cmd_mbox; 745081ff398SHannes Reinecke union myrb_cmd_mbox *last_cmd_mbox; 746081ff398SHannes Reinecke union myrb_cmd_mbox *next_cmd_mbox; 747081ff398SHannes Reinecke union myrb_cmd_mbox *prev_cmd_mbox1; 748081ff398SHannes Reinecke union myrb_cmd_mbox *prev_cmd_mbox2; 749081ff398SHannes Reinecke 750081ff398SHannes Reinecke size_t stat_mbox_size; 751081ff398SHannes Reinecke dma_addr_t stat_mbox_addr; 752081ff398SHannes Reinecke struct myrb_stat_mbox *first_stat_mbox; 753081ff398SHannes Reinecke struct myrb_stat_mbox *last_stat_mbox; 754081ff398SHannes Reinecke struct myrb_stat_mbox *next_stat_mbox; 755081ff398SHannes Reinecke 756081ff398SHannes Reinecke struct myrb_cmdblk dcmd_blk; 757081ff398SHannes Reinecke struct myrb_cmdblk mcmd_blk; 758081ff398SHannes Reinecke struct mutex dcmd_mutex; 759081ff398SHannes Reinecke 760081ff398SHannes Reinecke struct myrb_enquiry *enquiry; 761081ff398SHannes Reinecke dma_addr_t enquiry_addr; 762081ff398SHannes Reinecke 763081ff398SHannes Reinecke struct myrb_error_entry *err_table; 764081ff398SHannes Reinecke dma_addr_t err_table_addr; 765081ff398SHannes Reinecke 766081ff398SHannes Reinecke unsigned short last_rbld_status; 767081ff398SHannes Reinecke 768081ff398SHannes Reinecke struct myrb_ldev_info *ldev_info_buf; 769081ff398SHannes Reinecke dma_addr_t ldev_info_addr; 770081ff398SHannes Reinecke 771081ff398SHannes Reinecke struct myrb_bgi_status bgi_status; 772081ff398SHannes Reinecke 773081ff398SHannes Reinecke struct mutex dma_mutex; 774081ff398SHannes Reinecke }; 775081ff398SHannes Reinecke 776081ff398SHannes Reinecke /* 777081ff398SHannes Reinecke * DAC960 LA Series Controller Interface Register Offsets. 778081ff398SHannes Reinecke */ 779081ff398SHannes Reinecke #define DAC960_LA_mmio_size 0x80 780081ff398SHannes Reinecke 781081ff398SHannes Reinecke enum DAC960_LA_reg_offset { 782081ff398SHannes Reinecke DAC960_LA_IRQMASK_OFFSET = 0x34, 783081ff398SHannes Reinecke DAC960_LA_CMDOP_OFFSET = 0x50, 784081ff398SHannes Reinecke DAC960_LA_CMDID_OFFSET = 0x51, 785081ff398SHannes Reinecke DAC960_LA_MBOX2_OFFSET = 0x52, 786081ff398SHannes Reinecke DAC960_LA_MBOX3_OFFSET = 0x53, 787081ff398SHannes Reinecke DAC960_LA_MBOX4_OFFSET = 0x54, 788081ff398SHannes Reinecke DAC960_LA_MBOX5_OFFSET = 0x55, 789081ff398SHannes Reinecke DAC960_LA_MBOX6_OFFSET = 0x56, 790081ff398SHannes Reinecke DAC960_LA_MBOX7_OFFSET = 0x57, 791081ff398SHannes Reinecke DAC960_LA_MBOX8_OFFSET = 0x58, 792081ff398SHannes Reinecke DAC960_LA_MBOX9_OFFSET = 0x59, 793081ff398SHannes Reinecke DAC960_LA_MBOX10_OFFSET = 0x5A, 794081ff398SHannes Reinecke DAC960_LA_MBOX11_OFFSET = 0x5B, 795081ff398SHannes Reinecke DAC960_LA_MBOX12_OFFSET = 0x5C, 796081ff398SHannes Reinecke DAC960_LA_STSID_OFFSET = 0x5D, 797081ff398SHannes Reinecke DAC960_LA_STS_OFFSET = 0x5E, 798081ff398SHannes Reinecke DAC960_LA_IDB_OFFSET = 0x60, 799081ff398SHannes Reinecke DAC960_LA_ODB_OFFSET = 0x61, 800081ff398SHannes Reinecke DAC960_LA_ERRSTS_OFFSET = 0x63, 801081ff398SHannes Reinecke }; 802081ff398SHannes Reinecke 803081ff398SHannes Reinecke /* 804081ff398SHannes Reinecke * DAC960 LA Series Inbound Door Bell Register. 805081ff398SHannes Reinecke */ 806081ff398SHannes Reinecke #define DAC960_LA_IDB_HWMBOX_NEW_CMD 0x01 807081ff398SHannes Reinecke #define DAC960_LA_IDB_HWMBOX_ACK_STS 0x02 808081ff398SHannes Reinecke #define DAC960_LA_IDB_GEN_IRQ 0x04 809081ff398SHannes Reinecke #define DAC960_LA_IDB_CTRL_RESET 0x08 810081ff398SHannes Reinecke #define DAC960_LA_IDB_MMBOX_NEW_CMD 0x10 811081ff398SHannes Reinecke 812081ff398SHannes Reinecke #define DAC960_LA_IDB_HWMBOX_EMPTY 0x01 813081ff398SHannes Reinecke #define DAC960_LA_IDB_INIT_DONE 0x02 814081ff398SHannes Reinecke 815081ff398SHannes Reinecke /* 816081ff398SHannes Reinecke * DAC960 LA Series Outbound Door Bell Register. 817081ff398SHannes Reinecke */ 818081ff398SHannes Reinecke #define DAC960_LA_ODB_HWMBOX_ACK_IRQ 0x01 819081ff398SHannes Reinecke #define DAC960_LA_ODB_MMBOX_ACK_IRQ 0x02 820081ff398SHannes Reinecke #define DAC960_LA_ODB_HWMBOX_STS_AVAIL 0x01 821081ff398SHannes Reinecke #define DAC960_LA_ODB_MMBOX_STS_AVAIL 0x02 822081ff398SHannes Reinecke 823081ff398SHannes Reinecke /* 824081ff398SHannes Reinecke * DAC960 LA Series Interrupt Mask Register. 825081ff398SHannes Reinecke */ 826081ff398SHannes Reinecke #define DAC960_LA_IRQMASK_DISABLE_IRQ 0x04 827081ff398SHannes Reinecke 828081ff398SHannes Reinecke /* 829081ff398SHannes Reinecke * DAC960 LA Series Error Status Register. 830081ff398SHannes Reinecke */ 831081ff398SHannes Reinecke #define DAC960_LA_ERRSTS_PENDING 0x02 832081ff398SHannes Reinecke 833081ff398SHannes Reinecke /* 834081ff398SHannes Reinecke * DAC960 PG Series Controller Interface Register Offsets. 835081ff398SHannes Reinecke */ 836081ff398SHannes Reinecke #define DAC960_PG_mmio_size 0x2000 837081ff398SHannes Reinecke 838081ff398SHannes Reinecke enum DAC960_PG_reg_offset { 839081ff398SHannes Reinecke DAC960_PG_IDB_OFFSET = 0x0020, 840081ff398SHannes Reinecke DAC960_PG_ODB_OFFSET = 0x002C, 841081ff398SHannes Reinecke DAC960_PG_IRQMASK_OFFSET = 0x0034, 842081ff398SHannes Reinecke DAC960_PG_CMDOP_OFFSET = 0x1000, 843081ff398SHannes Reinecke DAC960_PG_CMDID_OFFSET = 0x1001, 844081ff398SHannes Reinecke DAC960_PG_MBOX2_OFFSET = 0x1002, 845081ff398SHannes Reinecke DAC960_PG_MBOX3_OFFSET = 0x1003, 846081ff398SHannes Reinecke DAC960_PG_MBOX4_OFFSET = 0x1004, 847081ff398SHannes Reinecke DAC960_PG_MBOX5_OFFSET = 0x1005, 848081ff398SHannes Reinecke DAC960_PG_MBOX6_OFFSET = 0x1006, 849081ff398SHannes Reinecke DAC960_PG_MBOX7_OFFSET = 0x1007, 850081ff398SHannes Reinecke DAC960_PG_MBOX8_OFFSET = 0x1008, 851081ff398SHannes Reinecke DAC960_PG_MBOX9_OFFSET = 0x1009, 852081ff398SHannes Reinecke DAC960_PG_MBOX10_OFFSET = 0x100A, 853081ff398SHannes Reinecke DAC960_PG_MBOX11_OFFSET = 0x100B, 854081ff398SHannes Reinecke DAC960_PG_MBOX12_OFFSET = 0x100C, 855081ff398SHannes Reinecke DAC960_PG_STSID_OFFSET = 0x1018, 856081ff398SHannes Reinecke DAC960_PG_STS_OFFSET = 0x101A, 857081ff398SHannes Reinecke DAC960_PG_ERRSTS_OFFSET = 0x103F, 858081ff398SHannes Reinecke }; 859081ff398SHannes Reinecke 860081ff398SHannes Reinecke /* 861081ff398SHannes Reinecke * DAC960 PG Series Inbound Door Bell Register. 862081ff398SHannes Reinecke */ 863081ff398SHannes Reinecke #define DAC960_PG_IDB_HWMBOX_NEW_CMD 0x01 864081ff398SHannes Reinecke #define DAC960_PG_IDB_HWMBOX_ACK_STS 0x02 865081ff398SHannes Reinecke #define DAC960_PG_IDB_GEN_IRQ 0x04 866081ff398SHannes Reinecke #define DAC960_PG_IDB_CTRL_RESET 0x08 867081ff398SHannes Reinecke #define DAC960_PG_IDB_MMBOX_NEW_CMD 0x10 868081ff398SHannes Reinecke 869081ff398SHannes Reinecke #define DAC960_PG_IDB_HWMBOX_FULL 0x01 870081ff398SHannes Reinecke #define DAC960_PG_IDB_INIT_IN_PROGRESS 0x02 871081ff398SHannes Reinecke 872081ff398SHannes Reinecke /* 873081ff398SHannes Reinecke * DAC960 PG Series Outbound Door Bell Register. 874081ff398SHannes Reinecke */ 875081ff398SHannes Reinecke #define DAC960_PG_ODB_HWMBOX_ACK_IRQ 0x01 876081ff398SHannes Reinecke #define DAC960_PG_ODB_MMBOX_ACK_IRQ 0x02 877081ff398SHannes Reinecke #define DAC960_PG_ODB_HWMBOX_STS_AVAIL 0x01 878081ff398SHannes Reinecke #define DAC960_PG_ODB_MMBOX_STS_AVAIL 0x02 879081ff398SHannes Reinecke 880081ff398SHannes Reinecke /* 881081ff398SHannes Reinecke * DAC960 PG Series Interrupt Mask Register. 882081ff398SHannes Reinecke */ 883081ff398SHannes Reinecke #define DAC960_PG_IRQMASK_MSI_MASK1 0x03 884081ff398SHannes Reinecke #define DAC960_PG_IRQMASK_DISABLE_IRQ 0x04 885081ff398SHannes Reinecke #define DAC960_PG_IRQMASK_MSI_MASK2 0xF8 886081ff398SHannes Reinecke 887081ff398SHannes Reinecke /* 888081ff398SHannes Reinecke * DAC960 PG Series Error Status Register. 889081ff398SHannes Reinecke */ 890081ff398SHannes Reinecke #define DAC960_PG_ERRSTS_PENDING 0x04 891081ff398SHannes Reinecke 892081ff398SHannes Reinecke /* 893081ff398SHannes Reinecke * DAC960 PD Series Controller Interface Register Offsets. 894081ff398SHannes Reinecke */ 895081ff398SHannes Reinecke #define DAC960_PD_mmio_size 0x80 896081ff398SHannes Reinecke 897081ff398SHannes Reinecke enum DAC960_PD_reg_offset { 898081ff398SHannes Reinecke DAC960_PD_CMDOP_OFFSET = 0x00, 899081ff398SHannes Reinecke DAC960_PD_CMDID_OFFSET = 0x01, 900081ff398SHannes Reinecke DAC960_PD_MBOX2_OFFSET = 0x02, 901081ff398SHannes Reinecke DAC960_PD_MBOX3_OFFSET = 0x03, 902081ff398SHannes Reinecke DAC960_PD_MBOX4_OFFSET = 0x04, 903081ff398SHannes Reinecke DAC960_PD_MBOX5_OFFSET = 0x05, 904081ff398SHannes Reinecke DAC960_PD_MBOX6_OFFSET = 0x06, 905081ff398SHannes Reinecke DAC960_PD_MBOX7_OFFSET = 0x07, 906081ff398SHannes Reinecke DAC960_PD_MBOX8_OFFSET = 0x08, 907081ff398SHannes Reinecke DAC960_PD_MBOX9_OFFSET = 0x09, 908081ff398SHannes Reinecke DAC960_PD_MBOX10_OFFSET = 0x0A, 909081ff398SHannes Reinecke DAC960_PD_MBOX11_OFFSET = 0x0B, 910081ff398SHannes Reinecke DAC960_PD_MBOX12_OFFSET = 0x0C, 911081ff398SHannes Reinecke DAC960_PD_STSID_OFFSET = 0x0D, 912081ff398SHannes Reinecke DAC960_PD_STS_OFFSET = 0x0E, 913081ff398SHannes Reinecke DAC960_PD_ERRSTS_OFFSET = 0x3F, 914081ff398SHannes Reinecke DAC960_PD_IDB_OFFSET = 0x40, 915081ff398SHannes Reinecke DAC960_PD_ODB_OFFSET = 0x41, 916081ff398SHannes Reinecke DAC960_PD_IRQEN_OFFSET = 0x43, 917081ff398SHannes Reinecke }; 918081ff398SHannes Reinecke 919081ff398SHannes Reinecke /* 920081ff398SHannes Reinecke * DAC960 PD Series Inbound Door Bell Register. 921081ff398SHannes Reinecke */ 922081ff398SHannes Reinecke #define DAC960_PD_IDB_HWMBOX_NEW_CMD 0x01 923081ff398SHannes Reinecke #define DAC960_PD_IDB_HWMBOX_ACK_STS 0x02 924081ff398SHannes Reinecke #define DAC960_PD_IDB_GEN_IRQ 0x04 925081ff398SHannes Reinecke #define DAC960_PD_IDB_CTRL_RESET 0x08 926081ff398SHannes Reinecke 927081ff398SHannes Reinecke #define DAC960_PD_IDB_HWMBOX_FULL 0x01 928081ff398SHannes Reinecke #define DAC960_PD_IDB_INIT_IN_PROGRESS 0x02 929081ff398SHannes Reinecke 930081ff398SHannes Reinecke /* 931081ff398SHannes Reinecke * DAC960 PD Series Outbound Door Bell Register. 932081ff398SHannes Reinecke */ 933081ff398SHannes Reinecke #define DAC960_PD_ODB_HWMBOX_ACK_IRQ 0x01 934081ff398SHannes Reinecke #define DAC960_PD_ODB_HWMBOX_STS_AVAIL 0x01 935081ff398SHannes Reinecke 936081ff398SHannes Reinecke /* 937081ff398SHannes Reinecke * DAC960 PD Series Interrupt Enable Register. 938081ff398SHannes Reinecke */ 939081ff398SHannes Reinecke #define DAC960_PD_IRQMASK_ENABLE_IRQ 0x01 940081ff398SHannes Reinecke 941081ff398SHannes Reinecke /* 942081ff398SHannes Reinecke * DAC960 PD Series Error Status Register. 943081ff398SHannes Reinecke */ 944081ff398SHannes Reinecke #define DAC960_PD_ERRSTS_PENDING 0x04 945081ff398SHannes Reinecke 946081ff398SHannes Reinecke typedef int (*myrb_hw_init_t)(struct pci_dev *pdev, 947081ff398SHannes Reinecke struct myrb_hba *cb, void __iomem *base); 948081ff398SHannes Reinecke typedef unsigned short (*mbox_mmio_init_t)(struct pci_dev *pdev, 949081ff398SHannes Reinecke void __iomem *base, 950081ff398SHannes Reinecke union myrb_cmd_mbox *mbox); 951081ff398SHannes Reinecke 952081ff398SHannes Reinecke struct myrb_privdata { 953081ff398SHannes Reinecke myrb_hw_init_t hw_init; 954081ff398SHannes Reinecke irq_handler_t irq_handler; 955081ff398SHannes Reinecke unsigned int mmio_size; 956081ff398SHannes Reinecke }; 957081ff398SHannes Reinecke 958081ff398SHannes Reinecke #endif /* MYRB_H */ 959