1 /* 2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 USI Co., Ltd. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 41 #include <linux/slab.h> 42 #include "pm8001_sas.h" 43 #include "pm8001_chips.h" 44 #include "pm80xx_hwi.h" 45 46 static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING; 47 module_param(logging_level, ulong, 0644); 48 MODULE_PARM_DESC(logging_level, " bits for enabling logging info."); 49 50 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120; 51 module_param(link_rate, ulong, 0644); 52 MODULE_PARM_DESC(link_rate, "Enable link rate.\n" 53 " 1: Link rate 1.5G\n" 54 " 2: Link rate 3.0G\n" 55 " 4: Link rate 6.0G\n" 56 " 8: Link rate 12.0G\n"); 57 58 static struct scsi_transport_template *pm8001_stt; 59 60 /** 61 * chip info structure to identify chip key functionality as 62 * encryption available/not, no of ports, hw specific function ref 63 */ 64 static const struct pm8001_chip_info pm8001_chips[] = { 65 [chip_8001] = {0, 8, &pm8001_8001_dispatch,}, 66 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,}, 67 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,}, 68 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,}, 69 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,}, 70 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,}, 71 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,}, 72 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,}, 73 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,}, 74 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,}, 75 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,}, 76 }; 77 static int pm8001_id; 78 79 LIST_HEAD(hba_list); 80 81 struct workqueue_struct *pm8001_wq; 82 83 /** 84 * The main structure which LLDD must register for scsi core. 85 */ 86 static struct scsi_host_template pm8001_sht = { 87 .module = THIS_MODULE, 88 .name = DRV_NAME, 89 .queuecommand = sas_queuecommand, 90 .target_alloc = sas_target_alloc, 91 .slave_configure = sas_slave_configure, 92 .scan_finished = pm8001_scan_finished, 93 .scan_start = pm8001_scan_start, 94 .change_queue_depth = sas_change_queue_depth, 95 .bios_param = sas_bios_param, 96 .can_queue = 1, 97 .this_id = -1, 98 .sg_tablesize = SG_ALL, 99 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 100 .eh_device_reset_handler = sas_eh_device_reset_handler, 101 .eh_target_reset_handler = sas_eh_target_reset_handler, 102 .target_destroy = sas_target_destroy, 103 .ioctl = sas_ioctl, 104 #ifdef CONFIG_COMPAT 105 .compat_ioctl = sas_ioctl, 106 #endif 107 .shost_attrs = pm8001_host_attrs, 108 .track_queue_depth = 1, 109 }; 110 111 /** 112 * Sas layer call this function to execute specific task. 113 */ 114 static struct sas_domain_function_template pm8001_transport_ops = { 115 .lldd_dev_found = pm8001_dev_found, 116 .lldd_dev_gone = pm8001_dev_gone, 117 118 .lldd_execute_task = pm8001_queue_command, 119 .lldd_control_phy = pm8001_phy_control, 120 121 .lldd_abort_task = pm8001_abort_task, 122 .lldd_abort_task_set = pm8001_abort_task_set, 123 .lldd_clear_aca = pm8001_clear_aca, 124 .lldd_clear_task_set = pm8001_clear_task_set, 125 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset, 126 .lldd_lu_reset = pm8001_lu_reset, 127 .lldd_query_task = pm8001_query_task, 128 }; 129 130 /** 131 *pm8001_phy_init - initiate our adapter phys 132 *@pm8001_ha: our hba structure. 133 *@phy_id: phy id. 134 */ 135 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id) 136 { 137 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; 138 struct asd_sas_phy *sas_phy = &phy->sas_phy; 139 phy->phy_state = PHY_LINK_DISABLE; 140 phy->pm8001_ha = pm8001_ha; 141 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0; 142 sas_phy->class = SAS; 143 sas_phy->iproto = SAS_PROTOCOL_ALL; 144 sas_phy->tproto = 0; 145 sas_phy->type = PHY_TYPE_PHYSICAL; 146 sas_phy->role = PHY_ROLE_INITIATOR; 147 sas_phy->oob_mode = OOB_NOT_CONNECTED; 148 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN; 149 sas_phy->id = phy_id; 150 sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr; 151 sas_phy->frame_rcvd = &phy->frame_rcvd[0]; 152 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata; 153 sas_phy->lldd_phy = phy; 154 } 155 156 /** 157 *pm8001_free - free hba 158 *@pm8001_ha: our hba structure. 159 * 160 */ 161 static void pm8001_free(struct pm8001_hba_info *pm8001_ha) 162 { 163 int i; 164 165 if (!pm8001_ha) 166 return; 167 168 for (i = 0; i < USI_MAX_MEMCNT; i++) { 169 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) { 170 dma_free_coherent(&pm8001_ha->pdev->dev, 171 (pm8001_ha->memoryMap.region[i].total_len + 172 pm8001_ha->memoryMap.region[i].alignment), 173 pm8001_ha->memoryMap.region[i].virt_ptr, 174 pm8001_ha->memoryMap.region[i].phys_addr); 175 } 176 } 177 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha); 178 flush_workqueue(pm8001_wq); 179 kfree(pm8001_ha->tags); 180 kfree(pm8001_ha); 181 } 182 183 #ifdef PM8001_USE_TASKLET 184 185 /** 186 * tasklet for 64 msi-x interrupt handler 187 * @opaque: the passed general host adapter struct 188 * Note: pm8001_tasklet is common for pm8001 & pm80xx 189 */ 190 static void pm8001_tasklet(unsigned long opaque) 191 { 192 struct pm8001_hba_info *pm8001_ha; 193 struct isr_param *irq_vector; 194 195 irq_vector = (struct isr_param *)opaque; 196 pm8001_ha = irq_vector->drv_inst; 197 if (unlikely(!pm8001_ha)) 198 BUG_ON(1); 199 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id); 200 } 201 #endif 202 203 /** 204 * pm8001_interrupt_handler_msix - main MSIX interrupt handler. 205 * It obtains the vector number and calls the equivalent bottom 206 * half or services directly. 207 * @opaque: the passed outbound queue/vector. Host structure is 208 * retrieved from the same. 209 */ 210 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque) 211 { 212 struct isr_param *irq_vector; 213 struct pm8001_hba_info *pm8001_ha; 214 irqreturn_t ret = IRQ_HANDLED; 215 irq_vector = (struct isr_param *)opaque; 216 pm8001_ha = irq_vector->drv_inst; 217 218 if (unlikely(!pm8001_ha)) 219 return IRQ_NONE; 220 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha)) 221 return IRQ_NONE; 222 #ifdef PM8001_USE_TASKLET 223 tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]); 224 #else 225 ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id); 226 #endif 227 return ret; 228 } 229 230 /** 231 * pm8001_interrupt_handler_intx - main INTx interrupt handler. 232 * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure. 233 */ 234 235 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id) 236 { 237 struct pm8001_hba_info *pm8001_ha; 238 irqreturn_t ret = IRQ_HANDLED; 239 struct sas_ha_struct *sha = dev_id; 240 pm8001_ha = sha->lldd_ha; 241 if (unlikely(!pm8001_ha)) 242 return IRQ_NONE; 243 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha)) 244 return IRQ_NONE; 245 246 #ifdef PM8001_USE_TASKLET 247 tasklet_schedule(&pm8001_ha->tasklet[0]); 248 #else 249 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0); 250 #endif 251 return ret; 252 } 253 254 /** 255 * pm8001_alloc - initiate our hba structure and 6 DMAs area. 256 * @pm8001_ha:our hba structure. 257 * 258 */ 259 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha, 260 const struct pci_device_id *ent) 261 { 262 int i; 263 spin_lock_init(&pm8001_ha->lock); 264 spin_lock_init(&pm8001_ha->bitmap_lock); 265 PM8001_INIT_DBG(pm8001_ha, 266 pm8001_printk("pm8001_alloc: PHY:%x\n", 267 pm8001_ha->chip->n_phy)); 268 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 269 pm8001_phy_init(pm8001_ha, i); 270 pm8001_ha->port[i].wide_port_phymap = 0; 271 pm8001_ha->port[i].port_attached = 0; 272 pm8001_ha->port[i].port_state = 0; 273 INIT_LIST_HEAD(&pm8001_ha->port[i].list); 274 } 275 276 pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL); 277 if (!pm8001_ha->tags) 278 goto err_out; 279 /* MPI Memory region 1 for AAP Event Log for fw */ 280 pm8001_ha->memoryMap.region[AAP1].num_elements = 1; 281 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE; 282 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE; 283 pm8001_ha->memoryMap.region[AAP1].alignment = 32; 284 285 /* MPI Memory region 2 for IOP Event Log for fw */ 286 pm8001_ha->memoryMap.region[IOP].num_elements = 1; 287 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE; 288 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE; 289 pm8001_ha->memoryMap.region[IOP].alignment = 32; 290 291 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) { 292 /* MPI Memory region 3 for consumer Index of inbound queues */ 293 pm8001_ha->memoryMap.region[CI+i].num_elements = 1; 294 pm8001_ha->memoryMap.region[CI+i].element_size = 4; 295 pm8001_ha->memoryMap.region[CI+i].total_len = 4; 296 pm8001_ha->memoryMap.region[CI+i].alignment = 4; 297 298 if ((ent->driver_data) != chip_8001) { 299 /* MPI Memory region 5 inbound queues */ 300 pm8001_ha->memoryMap.region[IB+i].num_elements = 301 PM8001_MPI_QUEUE; 302 pm8001_ha->memoryMap.region[IB+i].element_size = 128; 303 pm8001_ha->memoryMap.region[IB+i].total_len = 304 PM8001_MPI_QUEUE * 128; 305 pm8001_ha->memoryMap.region[IB+i].alignment = 128; 306 } else { 307 pm8001_ha->memoryMap.region[IB+i].num_elements = 308 PM8001_MPI_QUEUE; 309 pm8001_ha->memoryMap.region[IB+i].element_size = 64; 310 pm8001_ha->memoryMap.region[IB+i].total_len = 311 PM8001_MPI_QUEUE * 64; 312 pm8001_ha->memoryMap.region[IB+i].alignment = 64; 313 } 314 } 315 316 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) { 317 /* MPI Memory region 4 for producer Index of outbound queues */ 318 pm8001_ha->memoryMap.region[PI+i].num_elements = 1; 319 pm8001_ha->memoryMap.region[PI+i].element_size = 4; 320 pm8001_ha->memoryMap.region[PI+i].total_len = 4; 321 pm8001_ha->memoryMap.region[PI+i].alignment = 4; 322 323 if (ent->driver_data != chip_8001) { 324 /* MPI Memory region 6 Outbound queues */ 325 pm8001_ha->memoryMap.region[OB+i].num_elements = 326 PM8001_MPI_QUEUE; 327 pm8001_ha->memoryMap.region[OB+i].element_size = 128; 328 pm8001_ha->memoryMap.region[OB+i].total_len = 329 PM8001_MPI_QUEUE * 128; 330 pm8001_ha->memoryMap.region[OB+i].alignment = 128; 331 } else { 332 /* MPI Memory region 6 Outbound queues */ 333 pm8001_ha->memoryMap.region[OB+i].num_elements = 334 PM8001_MPI_QUEUE; 335 pm8001_ha->memoryMap.region[OB+i].element_size = 64; 336 pm8001_ha->memoryMap.region[OB+i].total_len = 337 PM8001_MPI_QUEUE * 64; 338 pm8001_ha->memoryMap.region[OB+i].alignment = 64; 339 } 340 341 } 342 /* Memory region write DMA*/ 343 pm8001_ha->memoryMap.region[NVMD].num_elements = 1; 344 pm8001_ha->memoryMap.region[NVMD].element_size = 4096; 345 pm8001_ha->memoryMap.region[NVMD].total_len = 4096; 346 /* Memory region for devices*/ 347 pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1; 348 pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES * 349 sizeof(struct pm8001_device); 350 pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES * 351 sizeof(struct pm8001_device); 352 353 /* Memory region for ccb_info*/ 354 pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1; 355 pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB * 356 sizeof(struct pm8001_ccb_info); 357 pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB * 358 sizeof(struct pm8001_ccb_info); 359 360 /* Memory region for fw flash */ 361 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096; 362 363 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1; 364 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000; 365 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000; 366 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000; 367 for (i = 0; i < USI_MAX_MEMCNT; i++) { 368 if (pm8001_mem_alloc(pm8001_ha->pdev, 369 &pm8001_ha->memoryMap.region[i].virt_ptr, 370 &pm8001_ha->memoryMap.region[i].phys_addr, 371 &pm8001_ha->memoryMap.region[i].phys_addr_hi, 372 &pm8001_ha->memoryMap.region[i].phys_addr_lo, 373 pm8001_ha->memoryMap.region[i].total_len, 374 pm8001_ha->memoryMap.region[i].alignment) != 0) { 375 PM8001_FAIL_DBG(pm8001_ha, 376 pm8001_printk("Mem%d alloc failed\n", 377 i)); 378 goto err_out; 379 } 380 } 381 382 pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr; 383 for (i = 0; i < PM8001_MAX_DEVICES; i++) { 384 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED; 385 pm8001_ha->devices[i].id = i; 386 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES; 387 pm8001_ha->devices[i].running_req = 0; 388 } 389 pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr; 390 for (i = 0; i < PM8001_MAX_CCB; i++) { 391 pm8001_ha->ccb_info[i].ccb_dma_handle = 392 pm8001_ha->memoryMap.region[CCB_MEM].phys_addr + 393 i * sizeof(struct pm8001_ccb_info); 394 pm8001_ha->ccb_info[i].task = NULL; 395 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff; 396 pm8001_ha->ccb_info[i].device = NULL; 397 ++pm8001_ha->tags_num; 398 } 399 pm8001_ha->flags = PM8001F_INIT_TIME; 400 /* Initialize tags */ 401 pm8001_tag_init(pm8001_ha); 402 return 0; 403 err_out: 404 return 1; 405 } 406 407 /** 408 * pm8001_ioremap - remap the pci high physical address to kernal virtual 409 * address so that we can access them. 410 * @pm8001_ha:our hba structure. 411 */ 412 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha) 413 { 414 u32 bar; 415 u32 logicalBar = 0; 416 struct pci_dev *pdev; 417 418 pdev = pm8001_ha->pdev; 419 /* map pci mem (PMC pci base 0-3)*/ 420 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { 421 /* 422 ** logical BARs for SPC: 423 ** bar 0 and 1 - logical BAR0 424 ** bar 2 and 3 - logical BAR1 425 ** bar4 - logical BAR2 426 ** bar5 - logical BAR3 427 ** Skip the appropriate assignments: 428 */ 429 if ((bar == 1) || (bar == 3)) 430 continue; 431 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 432 pm8001_ha->io_mem[logicalBar].membase = 433 pci_resource_start(pdev, bar); 434 pm8001_ha->io_mem[logicalBar].memsize = 435 pci_resource_len(pdev, bar); 436 pm8001_ha->io_mem[logicalBar].memvirtaddr = 437 ioremap(pm8001_ha->io_mem[logicalBar].membase, 438 pm8001_ha->io_mem[logicalBar].memsize); 439 PM8001_INIT_DBG(pm8001_ha, 440 pm8001_printk("PCI: bar %d, logicalBar %d ", 441 bar, logicalBar)); 442 PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 443 "base addr %llx virt_addr=%llx len=%d\n", 444 (u64)pm8001_ha->io_mem[logicalBar].membase, 445 (u64)(unsigned long) 446 pm8001_ha->io_mem[logicalBar].memvirtaddr, 447 pm8001_ha->io_mem[logicalBar].memsize)); 448 } else { 449 pm8001_ha->io_mem[logicalBar].membase = 0; 450 pm8001_ha->io_mem[logicalBar].memsize = 0; 451 pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL; 452 } 453 logicalBar++; 454 } 455 return 0; 456 } 457 458 /** 459 * pm8001_pci_alloc - initialize our ha card structure 460 * @pdev: pci device. 461 * @ent: ent 462 * @shost: scsi host struct which has been initialized before. 463 */ 464 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev, 465 const struct pci_device_id *ent, 466 struct Scsi_Host *shost) 467 468 { 469 struct pm8001_hba_info *pm8001_ha; 470 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 471 int j; 472 473 pm8001_ha = sha->lldd_ha; 474 if (!pm8001_ha) 475 return NULL; 476 477 pm8001_ha->pdev = pdev; 478 pm8001_ha->dev = &pdev->dev; 479 pm8001_ha->chip_id = ent->driver_data; 480 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id]; 481 pm8001_ha->irq = pdev->irq; 482 pm8001_ha->sas = sha; 483 pm8001_ha->shost = shost; 484 pm8001_ha->id = pm8001_id++; 485 pm8001_ha->logging_level = logging_level; 486 if (link_rate >= 1 && link_rate <= 15) 487 pm8001_ha->link_rate = (link_rate << 8); 488 else { 489 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 | 490 LINKRATE_60 | LINKRATE_120; 491 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 492 "Setting link rate to default value\n")); 493 } 494 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id); 495 /* IOMB size is 128 for 8088/89 controllers */ 496 if (pm8001_ha->chip_id != chip_8001) 497 pm8001_ha->iomb_size = IOMB_SIZE_SPCV; 498 else 499 pm8001_ha->iomb_size = IOMB_SIZE_SPC; 500 501 #ifdef PM8001_USE_TASKLET 502 /* Tasklet for non msi-x interrupt handler */ 503 if ((!pdev->msix_cap || !pci_msi_enabled()) 504 || (pm8001_ha->chip_id == chip_8001)) 505 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet, 506 (unsigned long)&(pm8001_ha->irq_vector[0])); 507 else 508 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 509 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet, 510 (unsigned long)&(pm8001_ha->irq_vector[j])); 511 #endif 512 pm8001_ioremap(pm8001_ha); 513 if (!pm8001_alloc(pm8001_ha, ent)) 514 return pm8001_ha; 515 pm8001_free(pm8001_ha); 516 return NULL; 517 } 518 519 /** 520 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit 521 * @pdev: pci device. 522 */ 523 static int pci_go_44(struct pci_dev *pdev) 524 { 525 int rc; 526 527 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44)); 528 if (rc) { 529 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 530 if (rc) 531 dev_printk(KERN_ERR, &pdev->dev, 532 "32-bit DMA enable failed\n"); 533 } 534 return rc; 535 } 536 537 /** 538 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them. 539 * @shost: scsi host which has been allocated outside. 540 * @chip_info: our ha struct. 541 */ 542 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost, 543 const struct pm8001_chip_info *chip_info) 544 { 545 int phy_nr, port_nr; 546 struct asd_sas_phy **arr_phy; 547 struct asd_sas_port **arr_port; 548 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 549 550 phy_nr = chip_info->n_phy; 551 port_nr = phy_nr; 552 memset(sha, 0x00, sizeof(*sha)); 553 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL); 554 if (!arr_phy) 555 goto exit; 556 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL); 557 if (!arr_port) 558 goto exit_free2; 559 560 sha->sas_phy = arr_phy; 561 sha->sas_port = arr_port; 562 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL); 563 if (!sha->lldd_ha) 564 goto exit_free1; 565 566 shost->transportt = pm8001_stt; 567 shost->max_id = PM8001_MAX_DEVICES; 568 shost->max_lun = 8; 569 shost->max_channel = 0; 570 shost->unique_id = pm8001_id; 571 shost->max_cmd_len = 16; 572 shost->can_queue = PM8001_CAN_QUEUE; 573 shost->cmd_per_lun = 32; 574 return 0; 575 exit_free1: 576 kfree(arr_port); 577 exit_free2: 578 kfree(arr_phy); 579 exit: 580 return -1; 581 } 582 583 /** 584 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas 585 * @shost: scsi host which has been allocated outside 586 * @chip_info: our ha struct. 587 */ 588 static void pm8001_post_sas_ha_init(struct Scsi_Host *shost, 589 const struct pm8001_chip_info *chip_info) 590 { 591 int i = 0; 592 struct pm8001_hba_info *pm8001_ha; 593 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 594 595 pm8001_ha = sha->lldd_ha; 596 for (i = 0; i < chip_info->n_phy; i++) { 597 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy; 598 sha->sas_port[i] = &pm8001_ha->port[i].sas_port; 599 sha->sas_phy[i]->sas_addr = 600 (u8 *)&pm8001_ha->phy[i].dev_sas_addr; 601 } 602 sha->sas_ha_name = DRV_NAME; 603 sha->dev = pm8001_ha->dev; 604 sha->strict_wide_ports = 1; 605 sha->lldd_module = THIS_MODULE; 606 sha->sas_addr = &pm8001_ha->sas_addr[0]; 607 sha->num_phys = chip_info->n_phy; 608 sha->core.shost = shost; 609 } 610 611 /** 612 * pm8001_init_sas_add - initialize sas address 613 * @chip_info: our ha struct. 614 * 615 * Currently we just set the fixed SAS address to our HBA,for manufacture, 616 * it should read from the EEPROM 617 */ 618 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha) 619 { 620 u8 i, j; 621 u8 sas_add[8]; 622 #ifdef PM8001_READ_VPD 623 /* For new SPC controllers WWN is stored in flash vpd 624 * For SPC/SPCve controllers WWN is stored in EEPROM 625 * For Older SPC WWN is stored in NVMD 626 */ 627 DECLARE_COMPLETION_ONSTACK(completion); 628 struct pm8001_ioctl_payload payload; 629 u16 deviceid; 630 int rc; 631 632 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); 633 pm8001_ha->nvmd_completion = &completion; 634 635 if (pm8001_ha->chip_id == chip_8001) { 636 if (deviceid == 0x8081 || deviceid == 0x0042) { 637 payload.minor_function = 4; 638 payload.length = 4096; 639 } else { 640 payload.minor_function = 0; 641 payload.length = 128; 642 } 643 } else if ((pm8001_ha->chip_id == chip_8070 || 644 pm8001_ha->chip_id == chip_8072) && 645 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) { 646 payload.minor_function = 4; 647 payload.length = 4096; 648 } else { 649 payload.minor_function = 1; 650 payload.length = 4096; 651 } 652 payload.offset = 0; 653 payload.func_specific = kzalloc(payload.length, GFP_KERNEL); 654 if (!payload.func_specific) { 655 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("mem alloc fail\n")); 656 return; 657 } 658 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); 659 if (rc) { 660 kfree(payload.func_specific); 661 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n")); 662 return; 663 } 664 wait_for_completion(&completion); 665 666 for (i = 0, j = 0; i <= 7; i++, j++) { 667 if (pm8001_ha->chip_id == chip_8001) { 668 if (deviceid == 0x8081) 669 pm8001_ha->sas_addr[j] = 670 payload.func_specific[0x704 + i]; 671 else if (deviceid == 0x0042) 672 pm8001_ha->sas_addr[j] = 673 payload.func_specific[0x010 + i]; 674 } else if ((pm8001_ha->chip_id == chip_8070 || 675 pm8001_ha->chip_id == chip_8072) && 676 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) { 677 pm8001_ha->sas_addr[j] = 678 payload.func_specific[0x010 + i]; 679 } else 680 pm8001_ha->sas_addr[j] = 681 payload.func_specific[0x804 + i]; 682 } 683 memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE); 684 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 685 if (i && ((i % 4) == 0)) 686 sas_add[7] = sas_add[7] + 4; 687 memcpy(&pm8001_ha->phy[i].dev_sas_addr, 688 sas_add, SAS_ADDR_SIZE); 689 PM8001_INIT_DBG(pm8001_ha, 690 pm8001_printk("phy %d sas_addr = %016llx\n", i, 691 pm8001_ha->phy[i].dev_sas_addr)); 692 } 693 kfree(payload.func_specific); 694 #else 695 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 696 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL; 697 pm8001_ha->phy[i].dev_sas_addr = 698 cpu_to_be64((u64) 699 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr)); 700 } 701 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr, 702 SAS_ADDR_SIZE); 703 #endif 704 } 705 706 /* 707 * pm8001_get_phy_settings_info : Read phy setting values. 708 * @pm8001_ha : our hba. 709 */ 710 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha) 711 { 712 713 #ifdef PM8001_READ_VPD 714 /*OPTION ROM FLASH read for the SPC cards */ 715 DECLARE_COMPLETION_ONSTACK(completion); 716 struct pm8001_ioctl_payload payload; 717 int rc; 718 719 pm8001_ha->nvmd_completion = &completion; 720 /* SAS ADDRESS read from flash / EEPROM */ 721 payload.minor_function = 6; 722 payload.offset = 0; 723 payload.length = 4096; 724 payload.func_specific = kzalloc(4096, GFP_KERNEL); 725 if (!payload.func_specific) 726 return -ENOMEM; 727 /* Read phy setting values from flash */ 728 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload); 729 if (rc) { 730 kfree(payload.func_specific); 731 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n")); 732 return -ENOMEM; 733 } 734 wait_for_completion(&completion); 735 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific); 736 kfree(payload.func_specific); 737 #endif 738 return 0; 739 } 740 741 struct pm8001_mpi3_phy_pg_trx_config { 742 u32 LaneLosCfg; 743 u32 LanePgaCfg1; 744 u32 LanePisoCfg1; 745 u32 LanePisoCfg2; 746 u32 LanePisoCfg3; 747 u32 LanePisoCfg4; 748 u32 LanePisoCfg5; 749 u32 LanePisoCfg6; 750 u32 LaneBctCtrl; 751 }; 752 753 /** 754 * pm8001_get_internal_phy_settings : Retrieves the internal PHY settings 755 * @pm8001_ha : our adapter 756 * @phycfg : PHY config page to populate 757 */ 758 static 759 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha, 760 struct pm8001_mpi3_phy_pg_trx_config *phycfg) 761 { 762 phycfg->LaneLosCfg = 0x00000132; 763 phycfg->LanePgaCfg1 = 0x00203949; 764 phycfg->LanePisoCfg1 = 0x000000FF; 765 phycfg->LanePisoCfg2 = 0xFF000001; 766 phycfg->LanePisoCfg3 = 0xE7011300; 767 phycfg->LanePisoCfg4 = 0x631C40C0; 768 phycfg->LanePisoCfg5 = 0xF8102036; 769 phycfg->LanePisoCfg6 = 0xF74A1000; 770 phycfg->LaneBctCtrl = 0x00FB33F8; 771 } 772 773 /** 774 * pm8001_get_external_phy_settings : Retrieves the external PHY settings 775 * @pm8001_ha : our adapter 776 * @phycfg : PHY config page to populate 777 */ 778 static 779 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha, 780 struct pm8001_mpi3_phy_pg_trx_config *phycfg) 781 { 782 phycfg->LaneLosCfg = 0x00000132; 783 phycfg->LanePgaCfg1 = 0x00203949; 784 phycfg->LanePisoCfg1 = 0x000000FF; 785 phycfg->LanePisoCfg2 = 0xFF000001; 786 phycfg->LanePisoCfg3 = 0xE7011300; 787 phycfg->LanePisoCfg4 = 0x63349140; 788 phycfg->LanePisoCfg5 = 0xF8102036; 789 phycfg->LanePisoCfg6 = 0xF80D9300; 790 phycfg->LaneBctCtrl = 0x00FB33F8; 791 } 792 793 /** 794 * pm8001_get_phy_mask : Retrieves the mask that denotes if a PHY is int/ext 795 * @pm8001_ha : our adapter 796 * @phymask : The PHY mask 797 */ 798 static 799 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask) 800 { 801 switch (pm8001_ha->pdev->subsystem_device) { 802 case 0x0070: /* H1280 - 8 external 0 internal */ 803 case 0x0072: /* H12F0 - 16 external 0 internal */ 804 *phymask = 0x0000; 805 break; 806 807 case 0x0071: /* H1208 - 0 external 8 internal */ 808 case 0x0073: /* H120F - 0 external 16 internal */ 809 *phymask = 0xFFFF; 810 break; 811 812 case 0x0080: /* H1244 - 4 external 4 internal */ 813 *phymask = 0x00F0; 814 break; 815 816 case 0x0081: /* H1248 - 4 external 8 internal */ 817 *phymask = 0x0FF0; 818 break; 819 820 case 0x0082: /* H1288 - 8 external 8 internal */ 821 *phymask = 0xFF00; 822 break; 823 824 default: 825 PM8001_INIT_DBG(pm8001_ha, 826 pm8001_printk("Unknown subsystem device=0x%.04x", 827 pm8001_ha->pdev->subsystem_device)); 828 } 829 } 830 831 /** 832 * pm8001_set_phy_settings_ven_117c_12Gb : Configure ATTO 12Gb PHY settings 833 * @pm8001_ha : our adapter 834 */ 835 static 836 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha) 837 { 838 struct pm8001_mpi3_phy_pg_trx_config phycfg_int; 839 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext; 840 int phymask = 0; 841 int i = 0; 842 843 memset(&phycfg_int, 0, sizeof(phycfg_int)); 844 memset(&phycfg_ext, 0, sizeof(phycfg_ext)); 845 846 pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int); 847 pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext); 848 pm8001_get_phy_mask(pm8001_ha, &phymask); 849 850 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 851 if (phymask & (1 << i)) {/* Internal PHY */ 852 pm8001_set_phy_profile_single(pm8001_ha, i, 853 sizeof(phycfg_int) / sizeof(u32), 854 (u32 *)&phycfg_int); 855 856 } else { /* External PHY */ 857 pm8001_set_phy_profile_single(pm8001_ha, i, 858 sizeof(phycfg_ext) / sizeof(u32), 859 (u32 *)&phycfg_ext); 860 } 861 } 862 863 return 0; 864 } 865 866 /** 867 * pm8001_configure_phy_settings : Configures PHY settings based on vendor ID. 868 * @pm8001_ha : our hba. 869 */ 870 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha) 871 { 872 switch (pm8001_ha->pdev->subsystem_vendor) { 873 case PCI_VENDOR_ID_ATTO: 874 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */ 875 return 0; 876 else 877 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha); 878 879 case PCI_VENDOR_ID_ADAPTEC2: 880 case 0: 881 return 0; 882 883 default: 884 return pm8001_get_phy_settings_info(pm8001_ha); 885 } 886 } 887 888 #ifdef PM8001_USE_MSIX 889 /** 890 * pm8001_setup_msix - enable MSI-X interrupt 891 * @chip_info: our ha struct. 892 * @irq_handler: irq_handler 893 */ 894 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha) 895 { 896 u32 i = 0, j = 0; 897 u32 number_of_intr; 898 int flag = 0; 899 int rc; 900 901 /* SPCv controllers supports 64 msi-x */ 902 if (pm8001_ha->chip_id == chip_8001) { 903 number_of_intr = 1; 904 } else { 905 number_of_intr = PM8001_MAX_MSIX_VEC; 906 flag &= ~IRQF_SHARED; 907 } 908 909 rc = pci_alloc_irq_vectors(pm8001_ha->pdev, number_of_intr, 910 number_of_intr, PCI_IRQ_MSIX); 911 if (rc < 0) 912 return rc; 913 pm8001_ha->number_of_intr = number_of_intr; 914 915 PM8001_INIT_DBG(pm8001_ha, pm8001_printk( 916 "pci_alloc_irq_vectors request ret:%d no of intr %d\n", 917 rc, pm8001_ha->number_of_intr)); 918 919 for (i = 0; i < number_of_intr; i++) { 920 snprintf(pm8001_ha->intr_drvname[i], 921 sizeof(pm8001_ha->intr_drvname[0]), 922 "%s-%d", pm8001_ha->name, i); 923 pm8001_ha->irq_vector[i].irq_id = i; 924 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha; 925 926 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i), 927 pm8001_interrupt_handler_msix, flag, 928 pm8001_ha->intr_drvname[i], 929 &(pm8001_ha->irq_vector[i])); 930 if (rc) { 931 for (j = 0; j < i; j++) { 932 free_irq(pci_irq_vector(pm8001_ha->pdev, i), 933 &(pm8001_ha->irq_vector[i])); 934 } 935 pci_free_irq_vectors(pm8001_ha->pdev); 936 break; 937 } 938 } 939 940 return rc; 941 } 942 #endif 943 944 /** 945 * pm8001_request_irq - register interrupt 946 * @chip_info: our ha struct. 947 */ 948 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha) 949 { 950 struct pci_dev *pdev; 951 int rc; 952 953 pdev = pm8001_ha->pdev; 954 955 #ifdef PM8001_USE_MSIX 956 if (pdev->msix_cap && pci_msi_enabled()) 957 return pm8001_setup_msix(pm8001_ha); 958 else { 959 PM8001_INIT_DBG(pm8001_ha, 960 pm8001_printk("MSIX not supported!!!\n")); 961 goto intx; 962 } 963 #endif 964 965 intx: 966 /* initialize the INT-X interrupt */ 967 pm8001_ha->irq_vector[0].irq_id = 0; 968 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha; 969 rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED, 970 pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost)); 971 return rc; 972 } 973 974 /** 975 * pm8001_pci_probe - probe supported device 976 * @pdev: pci device which kernel has been prepared for. 977 * @ent: pci device id 978 * 979 * This function is the main initialization function, when register a new 980 * pci driver it is invoked, all struct an hardware initilization should be done 981 * here, also, register interrupt 982 */ 983 static int pm8001_pci_probe(struct pci_dev *pdev, 984 const struct pci_device_id *ent) 985 { 986 unsigned int rc; 987 u32 pci_reg; 988 u8 i = 0; 989 struct pm8001_hba_info *pm8001_ha; 990 struct Scsi_Host *shost = NULL; 991 const struct pm8001_chip_info *chip; 992 993 dev_printk(KERN_INFO, &pdev->dev, 994 "pm80xx: driver version %s\n", DRV_VERSION); 995 rc = pci_enable_device(pdev); 996 if (rc) 997 goto err_out_enable; 998 pci_set_master(pdev); 999 /* 1000 * Enable pci slot busmaster by setting pci command register. 1001 * This is required by FW for Cyclone card. 1002 */ 1003 1004 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg); 1005 pci_reg |= 0x157; 1006 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg); 1007 rc = pci_request_regions(pdev, DRV_NAME); 1008 if (rc) 1009 goto err_out_disable; 1010 rc = pci_go_44(pdev); 1011 if (rc) 1012 goto err_out_regions; 1013 1014 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *)); 1015 if (!shost) { 1016 rc = -ENOMEM; 1017 goto err_out_regions; 1018 } 1019 chip = &pm8001_chips[ent->driver_data]; 1020 SHOST_TO_SAS_HA(shost) = 1021 kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL); 1022 if (!SHOST_TO_SAS_HA(shost)) { 1023 rc = -ENOMEM; 1024 goto err_out_free_host; 1025 } 1026 1027 rc = pm8001_prep_sas_ha_init(shost, chip); 1028 if (rc) { 1029 rc = -ENOMEM; 1030 goto err_out_free; 1031 } 1032 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost)); 1033 /* ent->driver variable is used to differentiate between controllers */ 1034 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost); 1035 if (!pm8001_ha) { 1036 rc = -ENOMEM; 1037 goto err_out_free; 1038 } 1039 list_add_tail(&pm8001_ha->list, &hba_list); 1040 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1041 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 1042 if (rc) { 1043 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 1044 "chip_init failed [ret: %d]\n", rc)); 1045 goto err_out_ha_free; 1046 } 1047 1048 rc = scsi_add_host(shost, &pdev->dev); 1049 if (rc) 1050 goto err_out_ha_free; 1051 rc = pm8001_request_irq(pm8001_ha); 1052 if (rc) { 1053 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( 1054 "pm8001_request_irq failed [ret: %d]\n", rc)); 1055 goto err_out_shost; 1056 } 1057 1058 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); 1059 if (pm8001_ha->chip_id != chip_8001) { 1060 for (i = 1; i < pm8001_ha->number_of_intr; i++) 1061 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i); 1062 /* setup thermal configuration. */ 1063 pm80xx_set_thermal_config(pm8001_ha); 1064 } 1065 1066 pm8001_init_sas_add(pm8001_ha); 1067 /* phy setting support for motherboard controller */ 1068 if (pm8001_configure_phy_settings(pm8001_ha)) 1069 goto err_out_shost; 1070 1071 pm8001_post_sas_ha_init(shost, chip); 1072 rc = sas_register_ha(SHOST_TO_SAS_HA(shost)); 1073 if (rc) 1074 goto err_out_shost; 1075 scsi_scan_host(pm8001_ha->shost); 1076 pm8001_ha->flags = PM8001F_RUN_TIME; 1077 return 0; 1078 1079 err_out_shost: 1080 scsi_remove_host(pm8001_ha->shost); 1081 err_out_ha_free: 1082 pm8001_free(pm8001_ha); 1083 err_out_free: 1084 kfree(SHOST_TO_SAS_HA(shost)); 1085 err_out_free_host: 1086 scsi_host_put(shost); 1087 err_out_regions: 1088 pci_release_regions(pdev); 1089 err_out_disable: 1090 pci_disable_device(pdev); 1091 err_out_enable: 1092 return rc; 1093 } 1094 1095 static void pm8001_pci_remove(struct pci_dev *pdev) 1096 { 1097 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1098 struct pm8001_hba_info *pm8001_ha; 1099 int i, j; 1100 pm8001_ha = sha->lldd_ha; 1101 sas_unregister_ha(sha); 1102 sas_remove_host(pm8001_ha->shost); 1103 list_del(&pm8001_ha->list); 1104 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1105 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1106 1107 #ifdef PM8001_USE_MSIX 1108 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1109 synchronize_irq(pci_irq_vector(pdev, i)); 1110 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1111 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]); 1112 pci_free_irq_vectors(pdev); 1113 #else 1114 free_irq(pm8001_ha->irq, sha); 1115 #endif 1116 #ifdef PM8001_USE_TASKLET 1117 /* For non-msix and msix interrupts */ 1118 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1119 (pm8001_ha->chip_id == chip_8001)) 1120 tasklet_kill(&pm8001_ha->tasklet[0]); 1121 else 1122 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1123 tasklet_kill(&pm8001_ha->tasklet[j]); 1124 #endif 1125 scsi_host_put(pm8001_ha->shost); 1126 pm8001_free(pm8001_ha); 1127 kfree(sha->sas_phy); 1128 kfree(sha->sas_port); 1129 kfree(sha); 1130 pci_release_regions(pdev); 1131 pci_disable_device(pdev); 1132 } 1133 1134 /** 1135 * pm8001_pci_suspend - power management suspend main entry point 1136 * @pdev: PCI device struct 1137 * @state: PM state change to (usually PCI_D3) 1138 * 1139 * Returns 0 success, anything else error. 1140 */ 1141 static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1142 { 1143 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1144 struct pm8001_hba_info *pm8001_ha; 1145 int i, j; 1146 u32 device_state; 1147 pm8001_ha = sha->lldd_ha; 1148 sas_suspend_ha(sha); 1149 flush_workqueue(pm8001_wq); 1150 scsi_block_requests(pm8001_ha->shost); 1151 if (!pdev->pm_cap) { 1152 dev_err(&pdev->dev, " PCI PM not supported\n"); 1153 return -ENODEV; 1154 } 1155 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1156 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1157 #ifdef PM8001_USE_MSIX 1158 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1159 synchronize_irq(pci_irq_vector(pdev, i)); 1160 for (i = 0; i < pm8001_ha->number_of_intr; i++) 1161 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]); 1162 pci_free_irq_vectors(pdev); 1163 #else 1164 free_irq(pm8001_ha->irq, sha); 1165 #endif 1166 #ifdef PM8001_USE_TASKLET 1167 /* For non-msix and msix interrupts */ 1168 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1169 (pm8001_ha->chip_id == chip_8001)) 1170 tasklet_kill(&pm8001_ha->tasklet[0]); 1171 else 1172 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1173 tasklet_kill(&pm8001_ha->tasklet[j]); 1174 #endif 1175 device_state = pci_choose_state(pdev, state); 1176 pm8001_printk("pdev=0x%p, slot=%s, entering " 1177 "operating state [D%d]\n", pdev, 1178 pm8001_ha->name, device_state); 1179 pci_save_state(pdev); 1180 pci_disable_device(pdev); 1181 pci_set_power_state(pdev, device_state); 1182 return 0; 1183 } 1184 1185 /** 1186 * pm8001_pci_resume - power management resume main entry point 1187 * @pdev: PCI device struct 1188 * 1189 * Returns 0 success, anything else error. 1190 */ 1191 static int pm8001_pci_resume(struct pci_dev *pdev) 1192 { 1193 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1194 struct pm8001_hba_info *pm8001_ha; 1195 int rc; 1196 u8 i = 0, j; 1197 u32 device_state; 1198 DECLARE_COMPLETION_ONSTACK(completion); 1199 pm8001_ha = sha->lldd_ha; 1200 device_state = pdev->current_state; 1201 1202 pm8001_printk("pdev=0x%p, slot=%s, resuming from previous " 1203 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state); 1204 1205 pci_set_power_state(pdev, PCI_D0); 1206 pci_enable_wake(pdev, PCI_D0, 0); 1207 pci_restore_state(pdev); 1208 rc = pci_enable_device(pdev); 1209 if (rc) { 1210 pm8001_printk("slot=%s Enable device failed during resume\n", 1211 pm8001_ha->name); 1212 goto err_out_enable; 1213 } 1214 1215 pci_set_master(pdev); 1216 rc = pci_go_44(pdev); 1217 if (rc) 1218 goto err_out_disable; 1219 sas_prep_resume_ha(sha); 1220 /* chip soft rst only for spc */ 1221 if (pm8001_ha->chip_id == chip_8001) { 1222 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha); 1223 PM8001_INIT_DBG(pm8001_ha, 1224 pm8001_printk("chip soft reset successful\n")); 1225 } 1226 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 1227 if (rc) 1228 goto err_out_disable; 1229 1230 /* disable all the interrupt bits */ 1231 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 1232 1233 rc = pm8001_request_irq(pm8001_ha); 1234 if (rc) 1235 goto err_out_disable; 1236 #ifdef PM8001_USE_TASKLET 1237 /* Tasklet for non msi-x interrupt handler */ 1238 if ((!pdev->msix_cap || !pci_msi_enabled()) || 1239 (pm8001_ha->chip_id == chip_8001)) 1240 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet, 1241 (unsigned long)&(pm8001_ha->irq_vector[0])); 1242 else 1243 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++) 1244 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet, 1245 (unsigned long)&(pm8001_ha->irq_vector[j])); 1246 #endif 1247 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); 1248 if (pm8001_ha->chip_id != chip_8001) { 1249 for (i = 1; i < pm8001_ha->number_of_intr; i++) 1250 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i); 1251 } 1252 1253 /* Chip documentation for the 8070 and 8072 SPCv */ 1254 /* states that a 500ms minimum delay is required */ 1255 /* before issuing commands. Otherwise, the firmware */ 1256 /* will enter an unrecoverable state. */ 1257 1258 if (pm8001_ha->chip_id == chip_8070 || 1259 pm8001_ha->chip_id == chip_8072) { 1260 mdelay(500); 1261 } 1262 1263 /* Spin up the PHYs */ 1264 1265 pm8001_ha->flags = PM8001F_RUN_TIME; 1266 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { 1267 pm8001_ha->phy[i].enable_completion = &completion; 1268 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i); 1269 wait_for_completion(&completion); 1270 } 1271 sas_resume_ha(sha); 1272 return 0; 1273 1274 err_out_disable: 1275 scsi_remove_host(pm8001_ha->shost); 1276 pci_disable_device(pdev); 1277 err_out_enable: 1278 return rc; 1279 } 1280 1281 /* update of pci device, vendor id and driver data with 1282 * unique value for each of the controller 1283 */ 1284 static struct pci_device_id pm8001_pci_table[] = { 1285 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 }, 1286 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 }, 1287 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 }, 1288 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 }, 1289 /* Support for SPC/SPCv/SPCve controllers */ 1290 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 }, 1291 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 }, 1292 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 }, 1293 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 }, 1294 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 }, 1295 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 }, 1296 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 }, 1297 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 }, 1298 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 }, 1299 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 }, 1300 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 }, 1301 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 }, 1302 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 }, 1303 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 }, 1304 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 }, 1305 { PCI_VENDOR_ID_ADAPTEC2, 0x8081, 1306 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 }, 1307 { PCI_VENDOR_ID_ADAPTEC2, 0x8081, 1308 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 }, 1309 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1310 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 }, 1311 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1312 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 }, 1313 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1314 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 }, 1315 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1316 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 }, 1317 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1318 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 }, 1319 { PCI_VENDOR_ID_ADAPTEC2, 0x8088, 1320 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 }, 1321 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1322 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 }, 1323 { PCI_VENDOR_ID_ADAPTEC2, 0x8089, 1324 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 }, 1325 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1326 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 }, 1327 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1328 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 }, 1329 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1330 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 }, 1331 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1332 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 }, 1333 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1334 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 }, 1335 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1336 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 }, 1337 { PCI_VENDOR_ID_ADAPTEC2, 0x8076, 1338 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 }, 1339 { PCI_VENDOR_ID_ADAPTEC2, 0x8077, 1340 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 }, 1341 { PCI_VENDOR_ID_ADAPTEC2, 0x8074, 1342 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 }, 1343 { PCI_VENDOR_ID_ATTO, 0x8070, 1344 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 }, 1345 { PCI_VENDOR_ID_ATTO, 0x8070, 1346 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 }, 1347 { PCI_VENDOR_ID_ATTO, 0x8072, 1348 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 }, 1349 { PCI_VENDOR_ID_ATTO, 0x8072, 1350 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 }, 1351 { PCI_VENDOR_ID_ATTO, 0x8070, 1352 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 }, 1353 { PCI_VENDOR_ID_ATTO, 0x8072, 1354 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 }, 1355 { PCI_VENDOR_ID_ATTO, 0x8072, 1356 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 }, 1357 {} /* terminate list */ 1358 }; 1359 1360 static struct pci_driver pm8001_pci_driver = { 1361 .name = DRV_NAME, 1362 .id_table = pm8001_pci_table, 1363 .probe = pm8001_pci_probe, 1364 .remove = pm8001_pci_remove, 1365 .suspend = pm8001_pci_suspend, 1366 .resume = pm8001_pci_resume, 1367 }; 1368 1369 /** 1370 * pm8001_init - initialize scsi transport template 1371 */ 1372 static int __init pm8001_init(void) 1373 { 1374 int rc = -ENOMEM; 1375 1376 pm8001_wq = alloc_workqueue("pm80xx", 0, 0); 1377 if (!pm8001_wq) 1378 goto err; 1379 1380 pm8001_id = 0; 1381 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops); 1382 if (!pm8001_stt) 1383 goto err_wq; 1384 rc = pci_register_driver(&pm8001_pci_driver); 1385 if (rc) 1386 goto err_tp; 1387 return 0; 1388 1389 err_tp: 1390 sas_release_transport(pm8001_stt); 1391 err_wq: 1392 destroy_workqueue(pm8001_wq); 1393 err: 1394 return rc; 1395 } 1396 1397 static void __exit pm8001_exit(void) 1398 { 1399 pci_unregister_driver(&pm8001_pci_driver); 1400 sas_release_transport(pm8001_stt); 1401 destroy_workqueue(pm8001_wq); 1402 } 1403 1404 module_init(pm8001_init); 1405 module_exit(pm8001_exit); 1406 1407 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>"); 1408 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>"); 1409 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>"); 1410 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>"); 1411 MODULE_DESCRIPTION( 1412 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 " 1413 "SAS/SATA controller driver"); 1414 MODULE_VERSION(DRV_VERSION); 1415 MODULE_LICENSE("GPL"); 1416 MODULE_DEVICE_TABLE(pci, pm8001_pci_table); 1417 1418