1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Cadence SPI controller driver (master mode only) 4 * 5 * Copyright (C) 2008 - 2014 Xilinx, Inc. 6 * 7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c) 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/of_irq.h> 17 #include <linux/of_address.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/spi/spi.h> 21 22 /* Name of this driver */ 23 #define CDNS_SPI_NAME "cdns-spi" 24 25 /* Register offset definitions */ 26 #define CDNS_SPI_CR 0x00 /* Configuration Register, RW */ 27 #define CDNS_SPI_ISR 0x04 /* Interrupt Status Register, RO */ 28 #define CDNS_SPI_IER 0x08 /* Interrupt Enable Register, WO */ 29 #define CDNS_SPI_IDR 0x0c /* Interrupt Disable Register, WO */ 30 #define CDNS_SPI_IMR 0x10 /* Interrupt Enabled Mask Register, RO */ 31 #define CDNS_SPI_ER 0x14 /* Enable/Disable Register, RW */ 32 #define CDNS_SPI_DR 0x18 /* Delay Register, RW */ 33 #define CDNS_SPI_TXD 0x1C /* Data Transmit Register, WO */ 34 #define CDNS_SPI_RXD 0x20 /* Data Receive Register, RO */ 35 #define CDNS_SPI_SICR 0x24 /* Slave Idle Count Register, RW */ 36 #define CDNS_SPI_THLD 0x28 /* Transmit FIFO Watermark Register,RW */ 37 38 #define SPI_AUTOSUSPEND_TIMEOUT 3000 39 /* 40 * SPI Configuration Register bit Masks 41 * 42 * This register contains various control bits that affect the operation 43 * of the SPI controller 44 */ 45 #define CDNS_SPI_CR_MANSTRT 0x00010000 /* Manual TX Start */ 46 #define CDNS_SPI_CR_CPHA 0x00000004 /* Clock Phase Control */ 47 #define CDNS_SPI_CR_CPOL 0x00000002 /* Clock Polarity Control */ 48 #define CDNS_SPI_CR_SSCTRL 0x00003C00 /* Slave Select Mask */ 49 #define CDNS_SPI_CR_PERI_SEL 0x00000200 /* Peripheral Select Decode */ 50 #define CDNS_SPI_CR_BAUD_DIV 0x00000038 /* Baud Rate Divisor Mask */ 51 #define CDNS_SPI_CR_MSTREN 0x00000001 /* Master Enable Mask */ 52 #define CDNS_SPI_CR_MANSTRTEN 0x00008000 /* Manual TX Enable Mask */ 53 #define CDNS_SPI_CR_SSFORCE 0x00004000 /* Manual SS Enable Mask */ 54 #define CDNS_SPI_CR_BAUD_DIV_4 0x00000008 /* Default Baud Div Mask */ 55 #define CDNS_SPI_CR_DEFAULT (CDNS_SPI_CR_MSTREN | \ 56 CDNS_SPI_CR_SSCTRL | \ 57 CDNS_SPI_CR_SSFORCE | \ 58 CDNS_SPI_CR_BAUD_DIV_4) 59 60 /* 61 * SPI Configuration Register - Baud rate and slave select 62 * 63 * These are the values used in the calculation of baud rate divisor and 64 * setting the slave select. 65 */ 66 67 #define CDNS_SPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */ 68 #define CDNS_SPI_BAUD_DIV_MIN 1 /* Baud rate divisor minimum */ 69 #define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */ 70 #define CDNS_SPI_SS_SHIFT 10 /* Slave Select field shift in CR */ 71 #define CDNS_SPI_SS0 0x1 /* Slave Select zero */ 72 73 /* 74 * SPI Interrupt Registers bit Masks 75 * 76 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same 77 * bit definitions. 78 */ 79 #define CDNS_SPI_IXR_TXOW 0x00000004 /* SPI TX FIFO Overwater */ 80 #define CDNS_SPI_IXR_MODF 0x00000002 /* SPI Mode Fault */ 81 #define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */ 82 #define CDNS_SPI_IXR_DEFAULT (CDNS_SPI_IXR_TXOW | \ 83 CDNS_SPI_IXR_MODF) 84 #define CDNS_SPI_IXR_TXFULL 0x00000008 /* SPI TX Full */ 85 #define CDNS_SPI_IXR_ALL 0x0000007F /* SPI all interrupts */ 86 87 /* 88 * SPI Enable Register bit Masks 89 * 90 * This register is used to enable or disable the SPI controller 91 */ 92 #define CDNS_SPI_ER_ENABLE 0x00000001 /* SPI Enable Bit Mask */ 93 #define CDNS_SPI_ER_DISABLE 0x0 /* SPI Disable Bit Mask */ 94 95 /* SPI FIFO depth in bytes */ 96 #define CDNS_SPI_FIFO_DEPTH 128 97 98 /* Default number of chip select lines */ 99 #define CDNS_SPI_DEFAULT_NUM_CS 4 100 101 /** 102 * struct cdns_spi - This definition defines spi driver instance 103 * @regs: Virtual address of the SPI controller registers 104 * @ref_clk: Pointer to the peripheral clock 105 * @pclk: Pointer to the APB clock 106 * @speed_hz: Current SPI bus clock speed in Hz 107 * @txbuf: Pointer to the TX buffer 108 * @rxbuf: Pointer to the RX buffer 109 * @tx_bytes: Number of bytes left to transfer 110 * @rx_bytes: Number of bytes requested 111 * @dev_busy: Device busy flag 112 * @is_decoded_cs: Flag for decoder property set or not 113 */ 114 struct cdns_spi { 115 void __iomem *regs; 116 struct clk *ref_clk; 117 struct clk *pclk; 118 u32 speed_hz; 119 const u8 *txbuf; 120 u8 *rxbuf; 121 int tx_bytes; 122 int rx_bytes; 123 u8 dev_busy; 124 u32 is_decoded_cs; 125 }; 126 127 /* Macros for the SPI controller read/write */ 128 static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset) 129 { 130 return readl_relaxed(xspi->regs + offset); 131 } 132 133 static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val) 134 { 135 writel_relaxed(val, xspi->regs + offset); 136 } 137 138 /** 139 * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller 140 * @xspi: Pointer to the cdns_spi structure 141 * 142 * On reset the SPI controller is configured to be in master mode, baud rate 143 * divisor is set to 4, threshold value for TX FIFO not full interrupt is set 144 * to 1 and size of the word to be transferred as 8 bit. 145 * This function initializes the SPI controller to disable and clear all the 146 * interrupts, enable manual slave select and manual start, deselect all the 147 * chip select lines, and enable the SPI controller. 148 */ 149 static void cdns_spi_init_hw(struct cdns_spi *xspi) 150 { 151 u32 ctrl_reg = CDNS_SPI_CR_DEFAULT; 152 153 if (xspi->is_decoded_cs) 154 ctrl_reg |= CDNS_SPI_CR_PERI_SEL; 155 156 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE); 157 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL); 158 159 /* Clear the RX FIFO */ 160 while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY) 161 cdns_spi_read(xspi, CDNS_SPI_RXD); 162 163 cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL); 164 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg); 165 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE); 166 } 167 168 /** 169 * cdns_spi_chipselect - Select or deselect the chip select line 170 * @spi: Pointer to the spi_device structure 171 * @is_high: Select(0) or deselect (1) the chip select line 172 */ 173 static void cdns_spi_chipselect(struct spi_device *spi, bool is_high) 174 { 175 struct cdns_spi *xspi = spi_master_get_devdata(spi->master); 176 u32 ctrl_reg; 177 178 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); 179 180 if (is_high) { 181 /* Deselect the slave */ 182 ctrl_reg |= CDNS_SPI_CR_SSCTRL; 183 } else { 184 /* Select the slave */ 185 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL; 186 if (!(xspi->is_decoded_cs)) 187 ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) << 188 CDNS_SPI_SS_SHIFT) & 189 CDNS_SPI_CR_SSCTRL; 190 else 191 ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) & 192 CDNS_SPI_CR_SSCTRL; 193 } 194 195 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg); 196 } 197 198 /** 199 * cdns_spi_config_clock_mode - Sets clock polarity and phase 200 * @spi: Pointer to the spi_device structure 201 * 202 * Sets the requested clock polarity and phase. 203 */ 204 static void cdns_spi_config_clock_mode(struct spi_device *spi) 205 { 206 struct cdns_spi *xspi = spi_master_get_devdata(spi->master); 207 u32 ctrl_reg, new_ctrl_reg; 208 209 new_ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); 210 ctrl_reg = new_ctrl_reg; 211 212 /* Set the SPI clock phase and clock polarity */ 213 new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL); 214 if (spi->mode & SPI_CPHA) 215 new_ctrl_reg |= CDNS_SPI_CR_CPHA; 216 if (spi->mode & SPI_CPOL) 217 new_ctrl_reg |= CDNS_SPI_CR_CPOL; 218 219 if (new_ctrl_reg != ctrl_reg) { 220 /* 221 * Just writing the CR register does not seem to apply the clock 222 * setting changes. This is problematic when changing the clock 223 * polarity as it will cause the SPI slave to see spurious clock 224 * transitions. To workaround the issue toggle the ER register. 225 */ 226 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE); 227 cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg); 228 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE); 229 } 230 } 231 232 /** 233 * cdns_spi_config_clock_freq - Sets clock frequency 234 * @spi: Pointer to the spi_device structure 235 * @transfer: Pointer to the spi_transfer structure which provides 236 * information about next transfer setup parameters 237 * 238 * Sets the requested clock frequency. 239 * Note: If the requested frequency is not an exact match with what can be 240 * obtained using the prescalar value the driver sets the clock frequency which 241 * is lower than the requested frequency (maximum lower) for the transfer. If 242 * the requested frequency is higher or lower than that is supported by the SPI 243 * controller the driver will set the highest or lowest frequency supported by 244 * controller. 245 */ 246 static void cdns_spi_config_clock_freq(struct spi_device *spi, 247 struct spi_transfer *transfer) 248 { 249 struct cdns_spi *xspi = spi_master_get_devdata(spi->master); 250 u32 ctrl_reg, baud_rate_val; 251 unsigned long frequency; 252 253 frequency = clk_get_rate(xspi->ref_clk); 254 255 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); 256 257 /* Set the clock frequency */ 258 if (xspi->speed_hz != transfer->speed_hz) { 259 /* first valid value is 1 */ 260 baud_rate_val = CDNS_SPI_BAUD_DIV_MIN; 261 while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) && 262 (frequency / (2 << baud_rate_val)) > transfer->speed_hz) 263 baud_rate_val++; 264 265 ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV; 266 ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT; 267 268 xspi->speed_hz = frequency / (2 << baud_rate_val); 269 } 270 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg); 271 } 272 273 /** 274 * cdns_spi_setup_transfer - Configure SPI controller for specified transfer 275 * @spi: Pointer to the spi_device structure 276 * @transfer: Pointer to the spi_transfer structure which provides 277 * information about next transfer setup parameters 278 * 279 * Sets the operational mode of SPI controller for the next SPI transfer and 280 * sets the requested clock frequency. 281 * 282 * Return: Always 0 283 */ 284 static int cdns_spi_setup_transfer(struct spi_device *spi, 285 struct spi_transfer *transfer) 286 { 287 struct cdns_spi *xspi = spi_master_get_devdata(spi->master); 288 289 cdns_spi_config_clock_freq(spi, transfer); 290 291 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n", 292 __func__, spi->mode, spi->bits_per_word, 293 xspi->speed_hz); 294 295 return 0; 296 } 297 298 /** 299 * cdns_spi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible 300 * @xspi: Pointer to the cdns_spi structure 301 */ 302 static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi) 303 { 304 unsigned long trans_cnt = 0; 305 306 while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) && 307 (xspi->tx_bytes > 0)) { 308 309 /* When xspi in busy condition, bytes may send failed, 310 * then spi control did't work thoroughly, add one byte delay 311 */ 312 if (cdns_spi_read(xspi, CDNS_SPI_ISR) & 313 CDNS_SPI_IXR_TXFULL) 314 udelay(10); 315 316 if (xspi->txbuf) 317 cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++); 318 else 319 cdns_spi_write(xspi, CDNS_SPI_TXD, 0); 320 321 xspi->tx_bytes--; 322 trans_cnt++; 323 } 324 } 325 326 /** 327 * cdns_spi_irq - Interrupt service routine of the SPI controller 328 * @irq: IRQ number 329 * @dev_id: Pointer to the xspi structure 330 * 331 * This function handles TX empty and Mode Fault interrupts only. 332 * On TX empty interrupt this function reads the received data from RX FIFO and 333 * fills the TX FIFO if there is any data remaining to be transferred. 334 * On Mode Fault interrupt this function indicates that transfer is completed, 335 * the SPI subsystem will identify the error as the remaining bytes to be 336 * transferred is non-zero. 337 * 338 * Return: IRQ_HANDLED when handled; IRQ_NONE otherwise. 339 */ 340 static irqreturn_t cdns_spi_irq(int irq, void *dev_id) 341 { 342 struct spi_master *master = dev_id; 343 struct cdns_spi *xspi = spi_master_get_devdata(master); 344 u32 intr_status, status; 345 346 status = IRQ_NONE; 347 intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR); 348 cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status); 349 350 if (intr_status & CDNS_SPI_IXR_MODF) { 351 /* Indicate that transfer is completed, the SPI subsystem will 352 * identify the error as the remaining bytes to be 353 * transferred is non-zero 354 */ 355 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT); 356 spi_finalize_current_transfer(master); 357 status = IRQ_HANDLED; 358 } else if (intr_status & CDNS_SPI_IXR_TXOW) { 359 unsigned long trans_cnt; 360 361 trans_cnt = xspi->rx_bytes - xspi->tx_bytes; 362 363 /* Read out the data from the RX FIFO */ 364 while (trans_cnt) { 365 u8 data; 366 367 data = cdns_spi_read(xspi, CDNS_SPI_RXD); 368 if (xspi->rxbuf) 369 *xspi->rxbuf++ = data; 370 371 xspi->rx_bytes--; 372 trans_cnt--; 373 } 374 375 if (xspi->tx_bytes) { 376 /* There is more data to send */ 377 cdns_spi_fill_tx_fifo(xspi); 378 } else { 379 /* Transfer is completed */ 380 cdns_spi_write(xspi, CDNS_SPI_IDR, 381 CDNS_SPI_IXR_DEFAULT); 382 spi_finalize_current_transfer(master); 383 } 384 status = IRQ_HANDLED; 385 } 386 387 return status; 388 } 389 390 static int cdns_prepare_message(struct spi_master *master, 391 struct spi_message *msg) 392 { 393 cdns_spi_config_clock_mode(msg->spi); 394 return 0; 395 } 396 397 /** 398 * cdns_transfer_one - Initiates the SPI transfer 399 * @master: Pointer to spi_master structure 400 * @spi: Pointer to the spi_device structure 401 * @transfer: Pointer to the spi_transfer structure which provides 402 * information about next transfer parameters 403 * 404 * This function fills the TX FIFO, starts the SPI transfer and 405 * returns a positive transfer count so that core will wait for completion. 406 * 407 * Return: Number of bytes transferred in the last transfer 408 */ 409 static int cdns_transfer_one(struct spi_master *master, 410 struct spi_device *spi, 411 struct spi_transfer *transfer) 412 { 413 struct cdns_spi *xspi = spi_master_get_devdata(master); 414 415 xspi->txbuf = transfer->tx_buf; 416 xspi->rxbuf = transfer->rx_buf; 417 xspi->tx_bytes = transfer->len; 418 xspi->rx_bytes = transfer->len; 419 420 cdns_spi_setup_transfer(spi, transfer); 421 422 cdns_spi_fill_tx_fifo(xspi); 423 424 cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT); 425 return transfer->len; 426 } 427 428 /** 429 * cdns_prepare_transfer_hardware - Prepares hardware for transfer. 430 * @master: Pointer to the spi_master structure which provides 431 * information about the controller. 432 * 433 * This function enables SPI master controller. 434 * 435 * Return: 0 always 436 */ 437 static int cdns_prepare_transfer_hardware(struct spi_master *master) 438 { 439 struct cdns_spi *xspi = spi_master_get_devdata(master); 440 441 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE); 442 443 return 0; 444 } 445 446 /** 447 * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer 448 * @master: Pointer to the spi_master structure which provides 449 * information about the controller. 450 * 451 * This function disables the SPI master controller. 452 * 453 * Return: 0 always 454 */ 455 static int cdns_unprepare_transfer_hardware(struct spi_master *master) 456 { 457 struct cdns_spi *xspi = spi_master_get_devdata(master); 458 459 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE); 460 461 return 0; 462 } 463 464 /** 465 * cdns_spi_probe - Probe method for the SPI driver 466 * @pdev: Pointer to the platform_device structure 467 * 468 * This function initializes the driver data structures and the hardware. 469 * 470 * Return: 0 on success and error value on error 471 */ 472 static int cdns_spi_probe(struct platform_device *pdev) 473 { 474 int ret = 0, irq; 475 struct spi_master *master; 476 struct cdns_spi *xspi; 477 u32 num_cs; 478 479 master = spi_alloc_master(&pdev->dev, sizeof(*xspi)); 480 if (!master) 481 return -ENOMEM; 482 483 xspi = spi_master_get_devdata(master); 484 master->dev.of_node = pdev->dev.of_node; 485 platform_set_drvdata(pdev, master); 486 487 xspi->regs = devm_platform_ioremap_resource(pdev, 0); 488 if (IS_ERR(xspi->regs)) { 489 ret = PTR_ERR(xspi->regs); 490 goto remove_master; 491 } 492 493 xspi->pclk = devm_clk_get(&pdev->dev, "pclk"); 494 if (IS_ERR(xspi->pclk)) { 495 dev_err(&pdev->dev, "pclk clock not found.\n"); 496 ret = PTR_ERR(xspi->pclk); 497 goto remove_master; 498 } 499 500 xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk"); 501 if (IS_ERR(xspi->ref_clk)) { 502 dev_err(&pdev->dev, "ref_clk clock not found.\n"); 503 ret = PTR_ERR(xspi->ref_clk); 504 goto remove_master; 505 } 506 507 ret = clk_prepare_enable(xspi->pclk); 508 if (ret) { 509 dev_err(&pdev->dev, "Unable to enable APB clock.\n"); 510 goto remove_master; 511 } 512 513 ret = clk_prepare_enable(xspi->ref_clk); 514 if (ret) { 515 dev_err(&pdev->dev, "Unable to enable device clock.\n"); 516 goto clk_dis_apb; 517 } 518 519 ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs); 520 if (ret < 0) 521 master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS; 522 else 523 master->num_chipselect = num_cs; 524 525 ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs", 526 &xspi->is_decoded_cs); 527 if (ret < 0) 528 xspi->is_decoded_cs = 0; 529 530 /* SPI controller initializations */ 531 cdns_spi_init_hw(xspi); 532 533 pm_runtime_set_active(&pdev->dev); 534 pm_runtime_enable(&pdev->dev); 535 pm_runtime_use_autosuspend(&pdev->dev); 536 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); 537 538 irq = platform_get_irq(pdev, 0); 539 if (irq <= 0) { 540 ret = -ENXIO; 541 goto clk_dis_all; 542 } 543 544 ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq, 545 0, pdev->name, master); 546 if (ret != 0) { 547 ret = -ENXIO; 548 dev_err(&pdev->dev, "request_irq failed\n"); 549 goto clk_dis_all; 550 } 551 552 master->use_gpio_descriptors = true; 553 master->prepare_transfer_hardware = cdns_prepare_transfer_hardware; 554 master->prepare_message = cdns_prepare_message; 555 master->transfer_one = cdns_transfer_one; 556 master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware; 557 master->set_cs = cdns_spi_chipselect; 558 master->auto_runtime_pm = true; 559 master->mode_bits = SPI_CPOL | SPI_CPHA; 560 561 /* Set to default valid value */ 562 master->max_speed_hz = clk_get_rate(xspi->ref_clk) / 4; 563 xspi->speed_hz = master->max_speed_hz; 564 565 master->bits_per_word_mask = SPI_BPW_MASK(8); 566 567 ret = spi_register_master(master); 568 if (ret) { 569 dev_err(&pdev->dev, "spi_register_master failed\n"); 570 goto clk_dis_all; 571 } 572 573 return ret; 574 575 clk_dis_all: 576 pm_runtime_set_suspended(&pdev->dev); 577 pm_runtime_disable(&pdev->dev); 578 clk_disable_unprepare(xspi->ref_clk); 579 clk_dis_apb: 580 clk_disable_unprepare(xspi->pclk); 581 remove_master: 582 spi_master_put(master); 583 return ret; 584 } 585 586 /** 587 * cdns_spi_remove - Remove method for the SPI driver 588 * @pdev: Pointer to the platform_device structure 589 * 590 * This function is called if a device is physically removed from the system or 591 * if the driver module is being unloaded. It frees all resources allocated to 592 * the device. 593 * 594 * Return: 0 on success and error value on error 595 */ 596 static int cdns_spi_remove(struct platform_device *pdev) 597 { 598 struct spi_master *master = platform_get_drvdata(pdev); 599 struct cdns_spi *xspi = spi_master_get_devdata(master); 600 601 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE); 602 603 clk_disable_unprepare(xspi->ref_clk); 604 clk_disable_unprepare(xspi->pclk); 605 pm_runtime_set_suspended(&pdev->dev); 606 pm_runtime_disable(&pdev->dev); 607 608 spi_unregister_master(master); 609 610 return 0; 611 } 612 613 /** 614 * cdns_spi_suspend - Suspend method for the SPI driver 615 * @dev: Address of the platform_device structure 616 * 617 * This function disables the SPI controller and 618 * changes the driver state to "suspend" 619 * 620 * Return: 0 on success and error value on error 621 */ 622 static int __maybe_unused cdns_spi_suspend(struct device *dev) 623 { 624 struct spi_master *master = dev_get_drvdata(dev); 625 626 return spi_master_suspend(master); 627 } 628 629 /** 630 * cdns_spi_resume - Resume method for the SPI driver 631 * @dev: Address of the platform_device structure 632 * 633 * This function changes the driver state to "ready" 634 * 635 * Return: 0 on success and error value on error 636 */ 637 static int __maybe_unused cdns_spi_resume(struct device *dev) 638 { 639 struct spi_master *master = dev_get_drvdata(dev); 640 struct cdns_spi *xspi = spi_master_get_devdata(master); 641 642 cdns_spi_init_hw(xspi); 643 return spi_master_resume(master); 644 } 645 646 /** 647 * cdns_spi_runtime_resume - Runtime resume method for the SPI driver 648 * @dev: Address of the platform_device structure 649 * 650 * This function enables the clocks 651 * 652 * Return: 0 on success and error value on error 653 */ 654 static int __maybe_unused cnds_runtime_resume(struct device *dev) 655 { 656 struct spi_master *master = dev_get_drvdata(dev); 657 struct cdns_spi *xspi = spi_master_get_devdata(master); 658 int ret; 659 660 ret = clk_prepare_enable(xspi->pclk); 661 if (ret) { 662 dev_err(dev, "Cannot enable APB clock.\n"); 663 return ret; 664 } 665 666 ret = clk_prepare_enable(xspi->ref_clk); 667 if (ret) { 668 dev_err(dev, "Cannot enable device clock.\n"); 669 clk_disable_unprepare(xspi->pclk); 670 return ret; 671 } 672 return 0; 673 } 674 675 /** 676 * cdns_spi_runtime_suspend - Runtime suspend method for the SPI driver 677 * @dev: Address of the platform_device structure 678 * 679 * This function disables the clocks 680 * 681 * Return: Always 0 682 */ 683 static int __maybe_unused cnds_runtime_suspend(struct device *dev) 684 { 685 struct spi_master *master = dev_get_drvdata(dev); 686 struct cdns_spi *xspi = spi_master_get_devdata(master); 687 688 clk_disable_unprepare(xspi->ref_clk); 689 clk_disable_unprepare(xspi->pclk); 690 691 return 0; 692 } 693 694 static const struct dev_pm_ops cdns_spi_dev_pm_ops = { 695 SET_RUNTIME_PM_OPS(cnds_runtime_suspend, 696 cnds_runtime_resume, NULL) 697 SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume) 698 }; 699 700 static const struct of_device_id cdns_spi_of_match[] = { 701 { .compatible = "xlnx,zynq-spi-r1p6" }, 702 { .compatible = "cdns,spi-r1p6" }, 703 { /* end of table */ } 704 }; 705 MODULE_DEVICE_TABLE(of, cdns_spi_of_match); 706 707 /* cdns_spi_driver - This structure defines the SPI subsystem platform driver */ 708 static struct platform_driver cdns_spi_driver = { 709 .probe = cdns_spi_probe, 710 .remove = cdns_spi_remove, 711 .driver = { 712 .name = CDNS_SPI_NAME, 713 .of_match_table = cdns_spi_of_match, 714 .pm = &cdns_spi_dev_pm_ops, 715 }, 716 }; 717 718 module_platform_driver(cdns_spi_driver); 719 720 MODULE_AUTHOR("Xilinx, Inc."); 721 MODULE_DESCRIPTION("Cadence SPI driver"); 722 MODULE_LICENSE("GPL"); 723