1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // CS42L43 SPI Controller Driver 4 // 5 // Copyright (C) 2022-2023 Cirrus Logic, Inc. and 6 // Cirrus Logic International Semiconductor Ltd. 7 8 #include <linux/bits.h> 9 #include <linux/bitfield.h> 10 #include <linux/device.h> 11 #include <linux/errno.h> 12 #include <linux/mfd/cs42l43.h> 13 #include <linux/mfd/cs42l43-regs.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 #include <linux/spi/spi.h> 19 #include <linux/units.h> 20 21 #define CS42L43_FIFO_SIZE 16 22 #define CS42L43_SPI_ROOT_HZ (40 * HZ_PER_MHZ) 23 #define CS42L43_SPI_MAX_LENGTH 65532 24 25 enum cs42l43_spi_cmd { 26 CS42L43_WRITE, 27 CS42L43_READ 28 }; 29 30 struct cs42l43_spi { 31 struct device *dev; 32 struct regmap *regmap; 33 struct spi_controller *ctlr; 34 }; 35 36 static const unsigned int cs42l43_clock_divs[] = { 37 2, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 38 }; 39 40 static int cs42l43_spi_tx(struct regmap *regmap, const u8 *buf, unsigned int len) 41 { 42 const u8 *end = buf + len; 43 u32 val = 0; 44 int ret; 45 46 while (buf < end) { 47 const u8 *block = min(buf + CS42L43_FIFO_SIZE, end); 48 49 while (buf < block) { 50 const u8 *word = min(buf + sizeof(u32), block); 51 int pad = (buf + sizeof(u32)) - word; 52 53 while (buf < word) { 54 val >>= BITS_PER_BYTE; 55 val |= FIELD_PREP(GENMASK(31, 24), *buf); 56 57 buf++; 58 } 59 60 val >>= pad * BITS_PER_BYTE; 61 62 regmap_write(regmap, CS42L43_TX_DATA, val); 63 } 64 65 regmap_write(regmap, CS42L43_TRAN_CONFIG8, CS42L43_SPI_TX_DONE_MASK); 66 67 ret = regmap_read_poll_timeout(regmap, CS42L43_TRAN_STATUS1, 68 val, (val & CS42L43_SPI_TX_REQUEST_MASK), 69 1000, 5000); 70 if (ret) 71 return ret; 72 } 73 74 return 0; 75 } 76 77 static int cs42l43_spi_rx(struct regmap *regmap, u8 *buf, unsigned int len) 78 { 79 u8 *end = buf + len; 80 u32 val; 81 int ret; 82 83 while (buf < end) { 84 u8 *block = min(buf + CS42L43_FIFO_SIZE, end); 85 86 ret = regmap_read_poll_timeout(regmap, CS42L43_TRAN_STATUS1, 87 val, (val & CS42L43_SPI_RX_REQUEST_MASK), 88 1000, 5000); 89 if (ret) 90 return ret; 91 92 while (buf < block) { 93 u8 *word = min(buf + sizeof(u32), block); 94 95 ret = regmap_read(regmap, CS42L43_RX_DATA, &val); 96 if (ret) 97 return ret; 98 99 while (buf < word) { 100 *buf = FIELD_GET(GENMASK(7, 0), val); 101 102 val >>= BITS_PER_BYTE; 103 buf++; 104 } 105 } 106 107 regmap_write(regmap, CS42L43_TRAN_CONFIG8, CS42L43_SPI_RX_DONE_MASK); 108 } 109 110 return 0; 111 } 112 113 static int cs42l43_transfer_one(struct spi_controller *ctlr, struct spi_device *spi, 114 struct spi_transfer *tfr) 115 { 116 struct cs42l43_spi *priv = spi_controller_get_devdata(spi->controller); 117 int i, ret = -EINVAL; 118 119 for (i = 0; i < ARRAY_SIZE(cs42l43_clock_divs); i++) { 120 if (CS42L43_SPI_ROOT_HZ / cs42l43_clock_divs[i] <= tfr->speed_hz) 121 break; 122 } 123 124 if (i == ARRAY_SIZE(cs42l43_clock_divs)) 125 return -EINVAL; 126 127 regmap_write(priv->regmap, CS42L43_SPI_CLK_CONFIG1, i); 128 129 if (tfr->tx_buf) { 130 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG3, CS42L43_WRITE); 131 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG4, tfr->len - 1); 132 } else if (tfr->rx_buf) { 133 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG3, CS42L43_READ); 134 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG5, tfr->len - 1); 135 } 136 137 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG1, CS42L43_SPI_START_MASK); 138 139 if (tfr->tx_buf) 140 ret = cs42l43_spi_tx(priv->regmap, (const u8 *)tfr->tx_buf, tfr->len); 141 else if (tfr->rx_buf) 142 ret = cs42l43_spi_rx(priv->regmap, (u8 *)tfr->rx_buf, tfr->len); 143 144 return ret; 145 } 146 147 static void cs42l43_set_cs(struct spi_device *spi, bool is_high) 148 { 149 struct cs42l43_spi *priv = spi_controller_get_devdata(spi->controller); 150 151 if (spi_get_chipselect(spi, 0) == 0) 152 regmap_write(priv->regmap, CS42L43_SPI_CONFIG2, !is_high); 153 } 154 155 static int cs42l43_prepare_message(struct spi_controller *ctlr, struct spi_message *msg) 156 { 157 struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr); 158 struct spi_device *spi = msg->spi; 159 unsigned int spi_config1 = 0; 160 161 /* select another internal CS, which doesn't exist, so CS 0 is not used */ 162 if (spi_get_csgpiod(spi, 0)) 163 spi_config1 |= 1 << CS42L43_SPI_SS_SEL_SHIFT; 164 if (spi->mode & SPI_CPOL) 165 spi_config1 |= CS42L43_SPI_CPOL_MASK; 166 if (spi->mode & SPI_CPHA) 167 spi_config1 |= CS42L43_SPI_CPHA_MASK; 168 if (spi->mode & SPI_3WIRE) 169 spi_config1 |= CS42L43_SPI_THREE_WIRE_MASK; 170 171 regmap_write(priv->regmap, CS42L43_SPI_CONFIG1, spi_config1); 172 173 return 0; 174 } 175 176 static int cs42l43_prepare_transfer_hardware(struct spi_controller *ctlr) 177 { 178 struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr); 179 int ret; 180 181 ret = regmap_write(priv->regmap, CS42L43_BLOCK_EN2, CS42L43_SPI_MSTR_EN_MASK); 182 if (ret) 183 dev_err(priv->dev, "Failed to enable SPI controller: %d\n", ret); 184 185 return ret; 186 } 187 188 static int cs42l43_unprepare_transfer_hardware(struct spi_controller *ctlr) 189 { 190 struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr); 191 int ret; 192 193 ret = regmap_write(priv->regmap, CS42L43_BLOCK_EN2, 0); 194 if (ret) 195 dev_err(priv->dev, "Failed to disable SPI controller: %d\n", ret); 196 197 return ret; 198 } 199 200 static size_t cs42l43_spi_max_length(struct spi_device *spi) 201 { 202 return CS42L43_SPI_MAX_LENGTH; 203 } 204 205 static int cs42l43_spi_probe(struct platform_device *pdev) 206 { 207 struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent); 208 struct cs42l43_spi *priv; 209 struct fwnode_handle *fwnode = dev_fwnode(cs42l43->dev); 210 int ret; 211 212 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 213 if (!priv) 214 return -ENOMEM; 215 216 priv->ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*priv->ctlr)); 217 if (!priv->ctlr) 218 return -ENOMEM; 219 220 spi_controller_set_devdata(priv->ctlr, priv); 221 222 priv->dev = &pdev->dev; 223 priv->regmap = cs42l43->regmap; 224 225 priv->ctlr->prepare_message = cs42l43_prepare_message; 226 priv->ctlr->prepare_transfer_hardware = cs42l43_prepare_transfer_hardware; 227 priv->ctlr->unprepare_transfer_hardware = cs42l43_unprepare_transfer_hardware; 228 priv->ctlr->transfer_one = cs42l43_transfer_one; 229 priv->ctlr->set_cs = cs42l43_set_cs; 230 priv->ctlr->max_transfer_size = cs42l43_spi_max_length; 231 232 if (is_of_node(fwnode)) 233 fwnode = fwnode_get_named_child_node(fwnode, "spi"); 234 235 device_set_node(&priv->ctlr->dev, fwnode); 236 237 priv->ctlr->mode_bits = SPI_3WIRE | SPI_MODE_X_MASK; 238 priv->ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX; 239 priv->ctlr->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) | 240 SPI_BPW_MASK(32); 241 priv->ctlr->min_speed_hz = CS42L43_SPI_ROOT_HZ / 242 cs42l43_clock_divs[ARRAY_SIZE(cs42l43_clock_divs) - 1]; 243 priv->ctlr->max_speed_hz = CS42L43_SPI_ROOT_HZ / cs42l43_clock_divs[0]; 244 priv->ctlr->use_gpio_descriptors = true; 245 priv->ctlr->auto_runtime_pm = true; 246 247 ret = devm_pm_runtime_enable(priv->dev); 248 if (ret) 249 return ret; 250 251 pm_runtime_idle(priv->dev); 252 253 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG6, CS42L43_FIFO_SIZE - 1); 254 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG7, CS42L43_FIFO_SIZE - 1); 255 256 // Disable Watchdog timer and enable stall 257 regmap_write(priv->regmap, CS42L43_SPI_CONFIG3, 0); 258 regmap_write(priv->regmap, CS42L43_SPI_CONFIG4, CS42L43_SPI_STALL_ENA_MASK); 259 260 ret = devm_spi_register_controller(priv->dev, priv->ctlr); 261 if (ret) { 262 dev_err(priv->dev, "Failed to register SPI controller: %d\n", ret); 263 } 264 265 return ret; 266 } 267 268 static const struct platform_device_id cs42l43_spi_id_table[] = { 269 { "cs42l43-spi", }, 270 {} 271 }; 272 MODULE_DEVICE_TABLE(platform, cs42l43_spi_id_table); 273 274 static struct platform_driver cs42l43_spi_driver = { 275 .driver = { 276 .name = "cs42l43-spi", 277 }, 278 .probe = cs42l43_spi_probe, 279 .id_table = cs42l43_spi_id_table, 280 }; 281 module_platform_driver(cs42l43_spi_driver); 282 283 MODULE_DESCRIPTION("CS42L43 SPI Driver"); 284 MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>"); 285 MODULE_AUTHOR("Maciej Strozek <mstrozek@opensource.cirrus.com>"); 286 MODULE_LICENSE("GPL"); 287