xref: /linux/drivers/spi/spi-dw-bt1.c (revision 84b9b44b) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
4 //
5 // Authors:
6 //   Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
7 //   Serge Semin <Sergey.Semin@baikalelectronics.ru>
8 //
9 // Baikal-T1 DW APB SPI and System Boot SPI driver
10 //
11 
12 #include <linux/clk.h>
13 #include <linux/cpumask.h>
14 #include <linux/err.h>
15 #include <linux/interrupt.h>
16 #include <linux/module.h>
17 #include <linux/mux/consumer.h>
18 #include <linux/of.h>
19 #include <linux/of_platform.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/property.h>
23 #include <linux/slab.h>
24 #include <linux/spi/spi-mem.h>
25 #include <linux/spi/spi.h>
26 
27 #include "spi-dw.h"
28 
29 #define BT1_BOOT_DIRMAP		0
30 #define BT1_BOOT_REGS		1
31 
32 struct dw_spi_bt1 {
33 	struct dw_spi		dws;
34 	struct clk		*clk;
35 	struct mux_control	*mux;
36 
37 #ifdef CONFIG_SPI_DW_BT1_DIRMAP
38 	void __iomem		*map;
39 	resource_size_t		map_len;
40 #endif
41 };
42 #define to_dw_spi_bt1(_ctlr) \
43 	container_of(spi_controller_get_devdata(_ctlr), struct dw_spi_bt1, dws)
44 
45 typedef int (*dw_spi_bt1_init_cb)(struct platform_device *pdev,
46 				    struct dw_spi_bt1 *dwsbt1);
47 
48 #ifdef CONFIG_SPI_DW_BT1_DIRMAP
49 
50 static int dw_spi_bt1_dirmap_create(struct spi_mem_dirmap_desc *desc)
51 {
52 	struct dw_spi_bt1 *dwsbt1 = to_dw_spi_bt1(desc->mem->spi->controller);
53 
54 	if (!dwsbt1->map ||
55 	    !dwsbt1->dws.mem_ops.supports_op(desc->mem, &desc->info.op_tmpl))
56 		return -EOPNOTSUPP;
57 
58 	/*
59 	 * Make sure the requested region doesn't go out of the physically
60 	 * mapped flash memory bounds and the operation is read-only.
61 	 */
62 	if (desc->info.offset + desc->info.length > dwsbt1->map_len ||
63 	    desc->info.op_tmpl.data.dir != SPI_MEM_DATA_IN)
64 		return -EOPNOTSUPP;
65 
66 	return 0;
67 }
68 
69 /*
70  * Directly mapped SPI memory region is only accessible in the dword chunks.
71  * That's why we have to create a dedicated read-method to copy data from there
72  * to the passed buffer.
73  */
74 static void dw_spi_bt1_dirmap_copy_from_map(void *to, void __iomem *from, size_t len)
75 {
76 	size_t shift, chunk;
77 	u32 data;
78 
79 	/*
80 	 * We split the copying up into the next three stages: unaligned head,
81 	 * aligned body, unaligned tail.
82 	 */
83 	shift = (size_t)from & 0x3;
84 	if (shift) {
85 		chunk = min_t(size_t, 4 - shift, len);
86 		data = readl_relaxed(from - shift);
87 		memcpy(to, (char *)&data + shift, chunk);
88 		from += chunk;
89 		to += chunk;
90 		len -= chunk;
91 	}
92 
93 	while (len >= 4) {
94 		data = readl_relaxed(from);
95 		memcpy(to, &data, 4);
96 		from += 4;
97 		to += 4;
98 		len -= 4;
99 	}
100 
101 	if (len) {
102 		data = readl_relaxed(from);
103 		memcpy(to, &data, len);
104 	}
105 }
106 
107 static ssize_t dw_spi_bt1_dirmap_read(struct spi_mem_dirmap_desc *desc,
108 				      u64 offs, size_t len, void *buf)
109 {
110 	struct dw_spi_bt1 *dwsbt1 = to_dw_spi_bt1(desc->mem->spi->controller);
111 	struct dw_spi *dws = &dwsbt1->dws;
112 	struct spi_mem *mem = desc->mem;
113 	struct dw_spi_cfg cfg;
114 	int ret;
115 
116 	/*
117 	 * Make sure the requested operation length is valid. Truncate the
118 	 * length if it's greater than the length of the MMIO region.
119 	 */
120 	if (offs >= dwsbt1->map_len || !len)
121 		return 0;
122 
123 	len = min_t(size_t, len, dwsbt1->map_len - offs);
124 
125 	/* Collect the controller configuration required by the operation */
126 	cfg.tmode = DW_SPI_CTRLR0_TMOD_EPROMREAD;
127 	cfg.dfs = 8;
128 	cfg.ndf = 4;
129 	cfg.freq = mem->spi->max_speed_hz;
130 
131 	/* Make sure the corresponding CS is de-asserted on transmission */
132 	dw_spi_set_cs(mem->spi, false);
133 
134 	dw_spi_enable_chip(dws, 0);
135 
136 	dw_spi_update_config(dws, mem->spi, &cfg);
137 
138 	dw_spi_umask_intr(dws, DW_SPI_INT_RXFI);
139 
140 	dw_spi_enable_chip(dws, 1);
141 
142 	/*
143 	 * Enable the transparent mode of the System Boot Controller.
144 	 * The SPI core IO should have been locked before calling this method
145 	 * so noone would be touching the controller' registers during the
146 	 * dirmap operation.
147 	 */
148 	ret = mux_control_select(dwsbt1->mux, BT1_BOOT_DIRMAP);
149 	if (ret)
150 		return ret;
151 
152 	dw_spi_bt1_dirmap_copy_from_map(buf, dwsbt1->map + offs, len);
153 
154 	mux_control_deselect(dwsbt1->mux);
155 
156 	dw_spi_set_cs(mem->spi, true);
157 
158 	ret = dw_spi_check_status(dws, true);
159 
160 	return ret ?: len;
161 }
162 
163 #endif /* CONFIG_SPI_DW_BT1_DIRMAP */
164 
165 static int dw_spi_bt1_std_init(struct platform_device *pdev,
166 			       struct dw_spi_bt1 *dwsbt1)
167 {
168 	struct dw_spi *dws = &dwsbt1->dws;
169 
170 	dws->irq = platform_get_irq(pdev, 0);
171 	if (dws->irq < 0)
172 		return dws->irq;
173 
174 	dws->num_cs = 4;
175 
176 	/*
177 	 * Baikal-T1 Normal SPI Controllers don't always keep up with full SPI
178 	 * bus speed especially when it comes to the concurrent access to the
179 	 * APB bus resources. Thus we have no choice but to set a constraint on
180 	 * the SPI bus frequency for the memory operations which require to
181 	 * read/write data as fast as possible.
182 	 */
183 	dws->max_mem_freq = 20000000U;
184 
185 	dw_spi_dma_setup_generic(dws);
186 
187 	return 0;
188 }
189 
190 static int dw_spi_bt1_sys_init(struct platform_device *pdev,
191 			       struct dw_spi_bt1 *dwsbt1)
192 {
193 	struct resource *mem __maybe_unused;
194 	struct dw_spi *dws = &dwsbt1->dws;
195 
196 	/*
197 	 * Baikal-T1 System Boot Controller is equipped with a mux, which
198 	 * switches between the directly mapped SPI flash access mode and
199 	 * IO access to the DW APB SSI registers. Note the mux controller
200 	 * must be setup to preserve the registers being accessible by default
201 	 * (on idle-state).
202 	 */
203 	dwsbt1->mux = devm_mux_control_get(&pdev->dev, NULL);
204 	if (IS_ERR(dwsbt1->mux))
205 		return PTR_ERR(dwsbt1->mux);
206 
207 	/*
208 	 * Directly mapped SPI flash memory is a 16MB MMIO region, which can be
209 	 * used to access a peripheral memory device just by reading/writing
210 	 * data from/to it. Note the system APB bus will stall during each IO
211 	 * from/to the dirmap region until the operation is finished. So don't
212 	 * use it concurrently with time-critical tasks (like the SPI memory
213 	 * operations implemented in the DW APB SSI driver).
214 	 */
215 #ifdef CONFIG_SPI_DW_BT1_DIRMAP
216 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
217 	if (mem) {
218 		dwsbt1->map = devm_ioremap_resource(&pdev->dev, mem);
219 		if (!IS_ERR(dwsbt1->map)) {
220 			dwsbt1->map_len = resource_size(mem);
221 			dws->mem_ops.dirmap_create = dw_spi_bt1_dirmap_create;
222 			dws->mem_ops.dirmap_read = dw_spi_bt1_dirmap_read;
223 		} else {
224 			dwsbt1->map = NULL;
225 		}
226 	}
227 #endif /* CONFIG_SPI_DW_BT1_DIRMAP */
228 
229 	/*
230 	 * There is no IRQ, no DMA and just one CS available on the System Boot
231 	 * SPI controller.
232 	 */
233 	dws->irq = IRQ_NOTCONNECTED;
234 	dws->num_cs = 1;
235 
236 	/*
237 	 * Baikal-T1 System Boot SPI Controller doesn't keep up with the full
238 	 * SPI bus speed due to relatively slow APB bus and races for it'
239 	 * resources from different CPUs. The situation is worsen by a small
240 	 * FIFOs depth (just 8 words). It works better in a single CPU mode
241 	 * though, but still tends to be not fast enough at low CPU
242 	 * frequencies.
243 	 */
244 	if (num_possible_cpus() > 1)
245 		dws->max_mem_freq = 10000000U;
246 	else
247 		dws->max_mem_freq = 20000000U;
248 
249 	return 0;
250 }
251 
252 static int dw_spi_bt1_probe(struct platform_device *pdev)
253 {
254 	dw_spi_bt1_init_cb init_func;
255 	struct dw_spi_bt1 *dwsbt1;
256 	struct resource *mem;
257 	struct dw_spi *dws;
258 	int ret;
259 
260 	dwsbt1 = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_bt1), GFP_KERNEL);
261 	if (!dwsbt1)
262 		return -ENOMEM;
263 
264 	dws = &dwsbt1->dws;
265 
266 	dws->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
267 	if (IS_ERR(dws->regs))
268 		return PTR_ERR(dws->regs);
269 
270 	dws->paddr = mem->start;
271 
272 	dwsbt1->clk = devm_clk_get(&pdev->dev, NULL);
273 	if (IS_ERR(dwsbt1->clk))
274 		return PTR_ERR(dwsbt1->clk);
275 
276 	ret = clk_prepare_enable(dwsbt1->clk);
277 	if (ret)
278 		return ret;
279 
280 	dws->bus_num = pdev->id;
281 	dws->reg_io_width = 4;
282 	dws->max_freq = clk_get_rate(dwsbt1->clk);
283 	if (!dws->max_freq) {
284 		ret = -EINVAL;
285 		goto err_disable_clk;
286 	}
287 
288 	init_func = device_get_match_data(&pdev->dev);
289 	ret = init_func(pdev, dwsbt1);
290 	if (ret)
291 		goto err_disable_clk;
292 
293 	pm_runtime_enable(&pdev->dev);
294 
295 	ret = dw_spi_add_host(&pdev->dev, dws);
296 	if (ret) {
297 		pm_runtime_disable(&pdev->dev);
298 		goto err_disable_clk;
299 	}
300 
301 	platform_set_drvdata(pdev, dwsbt1);
302 
303 	return 0;
304 
305 err_disable_clk:
306 	clk_disable_unprepare(dwsbt1->clk);
307 
308 	return ret;
309 }
310 
311 static void dw_spi_bt1_remove(struct platform_device *pdev)
312 {
313 	struct dw_spi_bt1 *dwsbt1 = platform_get_drvdata(pdev);
314 
315 	dw_spi_remove_host(&dwsbt1->dws);
316 
317 	pm_runtime_disable(&pdev->dev);
318 
319 	clk_disable_unprepare(dwsbt1->clk);
320 }
321 
322 static const struct of_device_id dw_spi_bt1_of_match[] = {
323 	{ .compatible = "baikal,bt1-ssi", .data = dw_spi_bt1_std_init},
324 	{ .compatible = "baikal,bt1-sys-ssi", .data = dw_spi_bt1_sys_init},
325 	{ }
326 };
327 MODULE_DEVICE_TABLE(of, dw_spi_bt1_of_match);
328 
329 static struct platform_driver dw_spi_bt1_driver = {
330 	.probe	= dw_spi_bt1_probe,
331 	.remove_new = dw_spi_bt1_remove,
332 	.driver	= {
333 		.name		= "bt1-sys-ssi",
334 		.of_match_table	= dw_spi_bt1_of_match,
335 	},
336 };
337 module_platform_driver(dw_spi_bt1_driver);
338 
339 MODULE_AUTHOR("Serge Semin <Sergey.Semin@baikalelectronics.ru>");
340 MODULE_DESCRIPTION("Baikal-T1 System Boot SPI Controller driver");
341 MODULE_LICENSE("GPL v2");
342 MODULE_IMPORT_NS(SPI_DW_CORE);
343