1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 3 // Copyright (C) 2008 Juergen Beisert 4 5 #include <linux/clk.h> 6 #include <linux/completion.h> 7 #include <linux/delay.h> 8 #include <linux/dmaengine.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/err.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/irq.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/pinctrl/consumer.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/slab.h> 20 #include <linux/spi/spi.h> 21 #include <linux/types.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/property.h> 25 26 #include <linux/dma/imx-dma.h> 27 28 #define DRIVER_NAME "spi_imx" 29 30 static bool use_dma = true; 31 module_param(use_dma, bool, 0644); 32 MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)"); 33 34 /* define polling limits */ 35 static unsigned int polling_limit_us = 30; 36 module_param(polling_limit_us, uint, 0664); 37 MODULE_PARM_DESC(polling_limit_us, 38 "time in us to run a transfer in polling mode\n"); 39 40 #define MXC_RPM_TIMEOUT 2000 /* 2000ms */ 41 42 #define MXC_CSPIRXDATA 0x00 43 #define MXC_CSPITXDATA 0x04 44 #define MXC_CSPICTRL 0x08 45 #define MXC_CSPIINT 0x0c 46 #define MXC_RESET 0x1c 47 48 /* generic defines to abstract from the different register layouts */ 49 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ 50 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ 51 #define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */ 52 53 /* The maximum bytes that a sdma BD can transfer. */ 54 #define MAX_SDMA_BD_BYTES (1 << 15) 55 #define MX51_ECSPI_CTRL_MAX_BURST 512 56 /* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/ 57 #define MX53_MAX_TRANSFER_BYTES 512 58 59 enum spi_imx_devtype { 60 IMX1_CSPI, 61 IMX21_CSPI, 62 IMX27_CSPI, 63 IMX31_CSPI, 64 IMX35_CSPI, /* CSPI on all i.mx except above */ 65 IMX51_ECSPI, /* ECSPI on i.mx51 */ 66 IMX53_ECSPI, /* ECSPI on i.mx53 and later */ 67 }; 68 69 struct spi_imx_data; 70 71 struct spi_imx_devtype_data { 72 void (*intctrl)(struct spi_imx_data *spi_imx, int enable); 73 int (*prepare_message)(struct spi_imx_data *spi_imx, struct spi_message *msg); 74 int (*prepare_transfer)(struct spi_imx_data *spi_imx, struct spi_device *spi); 75 void (*trigger)(struct spi_imx_data *spi_imx); 76 int (*rx_available)(struct spi_imx_data *spi_imx); 77 void (*reset)(struct spi_imx_data *spi_imx); 78 void (*setup_wml)(struct spi_imx_data *spi_imx); 79 void (*disable)(struct spi_imx_data *spi_imx); 80 bool has_dmamode; 81 bool has_slavemode; 82 unsigned int fifo_size; 83 bool dynamic_burst; 84 /* 85 * ERR009165 fixed or not: 86 * https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf 87 */ 88 bool tx_glitch_fixed; 89 enum spi_imx_devtype devtype; 90 }; 91 92 struct spi_imx_data { 93 struct spi_controller *controller; 94 struct device *dev; 95 96 struct completion xfer_done; 97 void __iomem *base; 98 unsigned long base_phys; 99 100 struct clk *clk_per; 101 struct clk *clk_ipg; 102 unsigned long spi_clk; 103 unsigned int spi_bus_clk; 104 105 unsigned int bits_per_word; 106 unsigned int spi_drctl; 107 108 unsigned int count, remainder; 109 void (*tx)(struct spi_imx_data *spi_imx); 110 void (*rx)(struct spi_imx_data *spi_imx); 111 void *rx_buf; 112 const void *tx_buf; 113 unsigned int txfifo; /* number of words pushed in tx FIFO */ 114 unsigned int dynamic_burst; 115 bool rx_only; 116 117 /* Slave mode */ 118 bool slave_mode; 119 bool slave_aborted; 120 unsigned int slave_burst; 121 122 /* DMA */ 123 bool usedma; 124 u32 wml; 125 struct completion dma_rx_completion; 126 struct completion dma_tx_completion; 127 128 const struct spi_imx_devtype_data *devtype_data; 129 }; 130 131 static inline int is_imx27_cspi(struct spi_imx_data *d) 132 { 133 return d->devtype_data->devtype == IMX27_CSPI; 134 } 135 136 static inline int is_imx35_cspi(struct spi_imx_data *d) 137 { 138 return d->devtype_data->devtype == IMX35_CSPI; 139 } 140 141 static inline int is_imx51_ecspi(struct spi_imx_data *d) 142 { 143 return d->devtype_data->devtype == IMX51_ECSPI; 144 } 145 146 static inline int is_imx53_ecspi(struct spi_imx_data *d) 147 { 148 return d->devtype_data->devtype == IMX53_ECSPI; 149 } 150 151 #define MXC_SPI_BUF_RX(type) \ 152 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \ 153 { \ 154 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ 155 \ 156 if (spi_imx->rx_buf) { \ 157 *(type *)spi_imx->rx_buf = val; \ 158 spi_imx->rx_buf += sizeof(type); \ 159 } \ 160 \ 161 spi_imx->remainder -= sizeof(type); \ 162 } 163 164 #define MXC_SPI_BUF_TX(type) \ 165 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \ 166 { \ 167 type val = 0; \ 168 \ 169 if (spi_imx->tx_buf) { \ 170 val = *(type *)spi_imx->tx_buf; \ 171 spi_imx->tx_buf += sizeof(type); \ 172 } \ 173 \ 174 spi_imx->count -= sizeof(type); \ 175 \ 176 writel(val, spi_imx->base + MXC_CSPITXDATA); \ 177 } 178 179 MXC_SPI_BUF_RX(u8) 180 MXC_SPI_BUF_TX(u8) 181 MXC_SPI_BUF_RX(u16) 182 MXC_SPI_BUF_TX(u16) 183 MXC_SPI_BUF_RX(u32) 184 MXC_SPI_BUF_TX(u32) 185 186 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set 187 * (which is currently not the case in this driver) 188 */ 189 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, 190 256, 384, 512, 768, 1024}; 191 192 /* MX21, MX27 */ 193 static unsigned int spi_imx_clkdiv_1(unsigned int fin, 194 unsigned int fspi, unsigned int max, unsigned int *fres) 195 { 196 int i; 197 198 for (i = 2; i < max; i++) 199 if (fspi * mxc_clkdivs[i] >= fin) 200 break; 201 202 *fres = fin / mxc_clkdivs[i]; 203 return i; 204 } 205 206 /* MX1, MX31, MX35, MX51 CSPI */ 207 static unsigned int spi_imx_clkdiv_2(unsigned int fin, 208 unsigned int fspi, unsigned int *fres) 209 { 210 int i, div = 4; 211 212 for (i = 0; i < 7; i++) { 213 if (fspi * div >= fin) 214 goto out; 215 div <<= 1; 216 } 217 218 out: 219 *fres = fin / div; 220 return i; 221 } 222 223 static int spi_imx_bytes_per_word(const int bits_per_word) 224 { 225 if (bits_per_word <= 8) 226 return 1; 227 else if (bits_per_word <= 16) 228 return 2; 229 else 230 return 4; 231 } 232 233 static bool spi_imx_can_dma(struct spi_controller *controller, struct spi_device *spi, 234 struct spi_transfer *transfer) 235 { 236 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller); 237 238 if (!use_dma || controller->fallback) 239 return false; 240 241 if (!controller->dma_rx) 242 return false; 243 244 if (spi_imx->slave_mode) 245 return false; 246 247 if (transfer->len < spi_imx->devtype_data->fifo_size) 248 return false; 249 250 spi_imx->dynamic_burst = 0; 251 252 return true; 253 } 254 255 #define MX51_ECSPI_CTRL 0x08 256 #define MX51_ECSPI_CTRL_ENABLE (1 << 0) 257 #define MX51_ECSPI_CTRL_XCH (1 << 2) 258 #define MX51_ECSPI_CTRL_SMC (1 << 3) 259 #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4) 260 #define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16) 261 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8 262 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 263 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) 264 #define MX51_ECSPI_CTRL_BL_OFFSET 20 265 #define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20) 266 267 #define MX51_ECSPI_CONFIG 0x0c 268 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) 269 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) 270 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) 271 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) 272 #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20)) 273 274 #define MX51_ECSPI_INT 0x10 275 #define MX51_ECSPI_INT_TEEN (1 << 0) 276 #define MX51_ECSPI_INT_RREN (1 << 3) 277 #define MX51_ECSPI_INT_RDREN (1 << 4) 278 279 #define MX51_ECSPI_DMA 0x14 280 #define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f) 281 #define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16) 282 #define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24) 283 284 #define MX51_ECSPI_DMA_TEDEN (1 << 7) 285 #define MX51_ECSPI_DMA_RXDEN (1 << 23) 286 #define MX51_ECSPI_DMA_RXTDEN (1 << 31) 287 288 #define MX51_ECSPI_STAT 0x18 289 #define MX51_ECSPI_STAT_RR (1 << 3) 290 291 #define MX51_ECSPI_TESTREG 0x20 292 #define MX51_ECSPI_TESTREG_LBC BIT(31) 293 294 static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx) 295 { 296 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); 297 298 if (spi_imx->rx_buf) { 299 #ifdef __LITTLE_ENDIAN 300 unsigned int bytes_per_word; 301 302 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); 303 if (bytes_per_word == 1) 304 swab32s(&val); 305 else if (bytes_per_word == 2) 306 swahw32s(&val); 307 #endif 308 *(u32 *)spi_imx->rx_buf = val; 309 spi_imx->rx_buf += sizeof(u32); 310 } 311 312 spi_imx->remainder -= sizeof(u32); 313 } 314 315 static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx) 316 { 317 int unaligned; 318 u32 val; 319 320 unaligned = spi_imx->remainder % 4; 321 322 if (!unaligned) { 323 spi_imx_buf_rx_swap_u32(spi_imx); 324 return; 325 } 326 327 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { 328 spi_imx_buf_rx_u16(spi_imx); 329 return; 330 } 331 332 val = readl(spi_imx->base + MXC_CSPIRXDATA); 333 334 while (unaligned--) { 335 if (spi_imx->rx_buf) { 336 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff; 337 spi_imx->rx_buf++; 338 } 339 spi_imx->remainder--; 340 } 341 } 342 343 static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx) 344 { 345 u32 val = 0; 346 #ifdef __LITTLE_ENDIAN 347 unsigned int bytes_per_word; 348 #endif 349 350 if (spi_imx->tx_buf) { 351 val = *(u32 *)spi_imx->tx_buf; 352 spi_imx->tx_buf += sizeof(u32); 353 } 354 355 spi_imx->count -= sizeof(u32); 356 #ifdef __LITTLE_ENDIAN 357 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); 358 359 if (bytes_per_word == 1) 360 swab32s(&val); 361 else if (bytes_per_word == 2) 362 swahw32s(&val); 363 #endif 364 writel(val, spi_imx->base + MXC_CSPITXDATA); 365 } 366 367 static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx) 368 { 369 int unaligned; 370 u32 val = 0; 371 372 unaligned = spi_imx->count % 4; 373 374 if (!unaligned) { 375 spi_imx_buf_tx_swap_u32(spi_imx); 376 return; 377 } 378 379 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { 380 spi_imx_buf_tx_u16(spi_imx); 381 return; 382 } 383 384 while (unaligned--) { 385 if (spi_imx->tx_buf) { 386 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned); 387 spi_imx->tx_buf++; 388 } 389 spi_imx->count--; 390 } 391 392 writel(val, spi_imx->base + MXC_CSPITXDATA); 393 } 394 395 static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx) 396 { 397 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA)); 398 399 if (spi_imx->rx_buf) { 400 int n_bytes = spi_imx->slave_burst % sizeof(val); 401 402 if (!n_bytes) 403 n_bytes = sizeof(val); 404 405 memcpy(spi_imx->rx_buf, 406 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes); 407 408 spi_imx->rx_buf += n_bytes; 409 spi_imx->slave_burst -= n_bytes; 410 } 411 412 spi_imx->remainder -= sizeof(u32); 413 } 414 415 static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx) 416 { 417 u32 val = 0; 418 int n_bytes = spi_imx->count % sizeof(val); 419 420 if (!n_bytes) 421 n_bytes = sizeof(val); 422 423 if (spi_imx->tx_buf) { 424 memcpy(((u8 *)&val) + sizeof(val) - n_bytes, 425 spi_imx->tx_buf, n_bytes); 426 val = cpu_to_be32(val); 427 spi_imx->tx_buf += n_bytes; 428 } 429 430 spi_imx->count -= n_bytes; 431 432 writel(val, spi_imx->base + MXC_CSPITXDATA); 433 } 434 435 /* MX51 eCSPI */ 436 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx, 437 unsigned int fspi, unsigned int *fres) 438 { 439 /* 440 * there are two 4-bit dividers, the pre-divider divides by 441 * $pre, the post-divider by 2^$post 442 */ 443 unsigned int pre, post; 444 unsigned int fin = spi_imx->spi_clk; 445 446 fspi = min(fspi, fin); 447 448 post = fls(fin) - fls(fspi); 449 if (fin > fspi << post) 450 post++; 451 452 /* now we have: (fin <= fspi << post) with post being minimal */ 453 454 post = max(4U, post) - 4; 455 if (unlikely(post > 0xf)) { 456 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n", 457 fspi, fin); 458 return 0xff; 459 } 460 461 pre = DIV_ROUND_UP(fin, fspi << post) - 1; 462 463 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n", 464 __func__, fin, fspi, post, pre); 465 466 /* Resulting frequency for the SCLK line. */ 467 *fres = (fin / (pre + 1)) >> post; 468 469 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) | 470 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET); 471 } 472 473 static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable) 474 { 475 unsigned int val = 0; 476 477 if (enable & MXC_INT_TE) 478 val |= MX51_ECSPI_INT_TEEN; 479 480 if (enable & MXC_INT_RR) 481 val |= MX51_ECSPI_INT_RREN; 482 483 if (enable & MXC_INT_RDR) 484 val |= MX51_ECSPI_INT_RDREN; 485 486 writel(val, spi_imx->base + MX51_ECSPI_INT); 487 } 488 489 static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx) 490 { 491 u32 reg; 492 493 reg = readl(spi_imx->base + MX51_ECSPI_CTRL); 494 reg |= MX51_ECSPI_CTRL_XCH; 495 writel(reg, spi_imx->base + MX51_ECSPI_CTRL); 496 } 497 498 static void mx51_ecspi_disable(struct spi_imx_data *spi_imx) 499 { 500 u32 ctrl; 501 502 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); 503 ctrl &= ~MX51_ECSPI_CTRL_ENABLE; 504 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 505 } 506 507 static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx, 508 struct spi_message *msg) 509 { 510 struct spi_device *spi = msg->spi; 511 struct spi_transfer *xfer; 512 u32 ctrl = MX51_ECSPI_CTRL_ENABLE; 513 u32 min_speed_hz = ~0U; 514 u32 testreg, delay; 515 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); 516 u32 current_cfg = cfg; 517 518 /* set Master or Slave mode */ 519 if (spi_imx->slave_mode) 520 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK; 521 else 522 ctrl |= MX51_ECSPI_CTRL_MODE_MASK; 523 524 /* 525 * Enable SPI_RDY handling (falling edge/level triggered). 526 */ 527 if (spi->mode & SPI_READY) 528 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl); 529 530 /* set chip select to use */ 531 ctrl |= MX51_ECSPI_CTRL_CS(spi_get_chipselect(spi, 0)); 532 533 /* 534 * The ctrl register must be written first, with the EN bit set other 535 * registers must not be written to. 536 */ 537 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 538 539 testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG); 540 if (spi->mode & SPI_LOOP) 541 testreg |= MX51_ECSPI_TESTREG_LBC; 542 else 543 testreg &= ~MX51_ECSPI_TESTREG_LBC; 544 writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG); 545 546 /* 547 * eCSPI burst completion by Chip Select signal in Slave mode 548 * is not functional for imx53 Soc, config SPI burst completed when 549 * BURST_LENGTH + 1 bits are received 550 */ 551 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) 552 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi_get_chipselect(spi, 0)); 553 else 554 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi_get_chipselect(spi, 0)); 555 556 if (spi->mode & SPI_CPOL) { 557 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi_get_chipselect(spi, 0)); 558 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi_get_chipselect(spi, 0)); 559 } else { 560 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi_get_chipselect(spi, 0)); 561 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi_get_chipselect(spi, 0)); 562 } 563 564 if (spi->mode & SPI_CS_HIGH) 565 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi_get_chipselect(spi, 0)); 566 else 567 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi_get_chipselect(spi, 0)); 568 569 if (cfg == current_cfg) 570 return 0; 571 572 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); 573 574 /* 575 * Wait until the changes in the configuration register CONFIGREG 576 * propagate into the hardware. It takes exactly one tick of the 577 * SCLK clock, but we will wait two SCLK clock just to be sure. The 578 * effect of the delay it takes for the hardware to apply changes 579 * is noticable if the SCLK clock run very slow. In such a case, if 580 * the polarity of SCLK should be inverted, the GPIO ChipSelect might 581 * be asserted before the SCLK polarity changes, which would disrupt 582 * the SPI communication as the device on the other end would consider 583 * the change of SCLK polarity as a clock tick already. 584 * 585 * Because spi_imx->spi_bus_clk is only set in prepare_message 586 * callback, iterate over all the transfers in spi_message, find the 587 * one with lowest bus frequency, and use that bus frequency for the 588 * delay calculation. In case all transfers have speed_hz == 0, then 589 * min_speed_hz is ~0 and the resulting delay is zero. 590 */ 591 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 592 if (!xfer->speed_hz) 593 continue; 594 min_speed_hz = min(xfer->speed_hz, min_speed_hz); 595 } 596 597 delay = (2 * 1000000) / min_speed_hz; 598 if (likely(delay < 10)) /* SCLK is faster than 200 kHz */ 599 udelay(delay); 600 else /* SCLK is _very_ slow */ 601 usleep_range(delay, delay + 10); 602 603 return 0; 604 } 605 606 static void mx51_configure_cpha(struct spi_imx_data *spi_imx, 607 struct spi_device *spi) 608 { 609 bool cpha = (spi->mode & SPI_CPHA); 610 bool flip_cpha = (spi->mode & SPI_RX_CPHA_FLIP) && spi_imx->rx_only; 611 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); 612 613 /* Flip cpha logical value iff flip_cpha */ 614 cpha ^= flip_cpha; 615 616 if (cpha) 617 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi_get_chipselect(spi, 0)); 618 else 619 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi_get_chipselect(spi, 0)); 620 621 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); 622 } 623 624 static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx, 625 struct spi_device *spi) 626 { 627 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); 628 u32 clk; 629 630 /* Clear BL field and set the right value */ 631 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK; 632 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) 633 ctrl |= (spi_imx->slave_burst * 8 - 1) 634 << MX51_ECSPI_CTRL_BL_OFFSET; 635 else 636 ctrl |= (spi_imx->bits_per_word - 1) 637 << MX51_ECSPI_CTRL_BL_OFFSET; 638 639 /* set clock speed */ 640 ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET | 641 0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET); 642 ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk); 643 spi_imx->spi_bus_clk = clk; 644 645 mx51_configure_cpha(spi_imx, spi); 646 647 /* 648 * ERR009165: work in XHC mode instead of SMC as PIO on the chips 649 * before i.mx6ul. 650 */ 651 if (spi_imx->usedma && spi_imx->devtype_data->tx_glitch_fixed) 652 ctrl |= MX51_ECSPI_CTRL_SMC; 653 else 654 ctrl &= ~MX51_ECSPI_CTRL_SMC; 655 656 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 657 658 return 0; 659 } 660 661 static void mx51_setup_wml(struct spi_imx_data *spi_imx) 662 { 663 u32 tx_wml = 0; 664 665 if (spi_imx->devtype_data->tx_glitch_fixed) 666 tx_wml = spi_imx->wml; 667 /* 668 * Configure the DMA register: setup the watermark 669 * and enable DMA request. 670 */ 671 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) | 672 MX51_ECSPI_DMA_TX_WML(tx_wml) | 673 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) | 674 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN | 675 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA); 676 } 677 678 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx) 679 { 680 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; 681 } 682 683 static void mx51_ecspi_reset(struct spi_imx_data *spi_imx) 684 { 685 /* drain receive buffer */ 686 while (mx51_ecspi_rx_available(spi_imx)) 687 readl(spi_imx->base + MXC_CSPIRXDATA); 688 } 689 690 #define MX31_INTREG_TEEN (1 << 0) 691 #define MX31_INTREG_RREN (1 << 3) 692 693 #define MX31_CSPICTRL_ENABLE (1 << 0) 694 #define MX31_CSPICTRL_MASTER (1 << 1) 695 #define MX31_CSPICTRL_XCH (1 << 2) 696 #define MX31_CSPICTRL_SMC (1 << 3) 697 #define MX31_CSPICTRL_POL (1 << 4) 698 #define MX31_CSPICTRL_PHA (1 << 5) 699 #define MX31_CSPICTRL_SSCTL (1 << 6) 700 #define MX31_CSPICTRL_SSPOL (1 << 7) 701 #define MX31_CSPICTRL_BC_SHIFT 8 702 #define MX35_CSPICTRL_BL_SHIFT 20 703 #define MX31_CSPICTRL_CS_SHIFT 24 704 #define MX35_CSPICTRL_CS_SHIFT 12 705 #define MX31_CSPICTRL_DR_SHIFT 16 706 707 #define MX31_CSPI_DMAREG 0x10 708 #define MX31_DMAREG_RH_DEN (1<<4) 709 #define MX31_DMAREG_TH_DEN (1<<1) 710 711 #define MX31_CSPISTATUS 0x14 712 #define MX31_STATUS_RR (1 << 3) 713 714 #define MX31_CSPI_TESTREG 0x1C 715 #define MX31_TEST_LBC (1 << 14) 716 717 /* These functions also work for the i.MX35, but be aware that 718 * the i.MX35 has a slightly different register layout for bits 719 * we do not use here. 720 */ 721 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable) 722 { 723 unsigned int val = 0; 724 725 if (enable & MXC_INT_TE) 726 val |= MX31_INTREG_TEEN; 727 if (enable & MXC_INT_RR) 728 val |= MX31_INTREG_RREN; 729 730 writel(val, spi_imx->base + MXC_CSPIINT); 731 } 732 733 static void mx31_trigger(struct spi_imx_data *spi_imx) 734 { 735 unsigned int reg; 736 737 reg = readl(spi_imx->base + MXC_CSPICTRL); 738 reg |= MX31_CSPICTRL_XCH; 739 writel(reg, spi_imx->base + MXC_CSPICTRL); 740 } 741 742 static int mx31_prepare_message(struct spi_imx_data *spi_imx, 743 struct spi_message *msg) 744 { 745 return 0; 746 } 747 748 static int mx31_prepare_transfer(struct spi_imx_data *spi_imx, 749 struct spi_device *spi) 750 { 751 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; 752 unsigned int clk; 753 754 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) << 755 MX31_CSPICTRL_DR_SHIFT; 756 spi_imx->spi_bus_clk = clk; 757 758 if (is_imx35_cspi(spi_imx)) { 759 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT; 760 reg |= MX31_CSPICTRL_SSCTL; 761 } else { 762 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT; 763 } 764 765 if (spi->mode & SPI_CPHA) 766 reg |= MX31_CSPICTRL_PHA; 767 if (spi->mode & SPI_CPOL) 768 reg |= MX31_CSPICTRL_POL; 769 if (spi->mode & SPI_CS_HIGH) 770 reg |= MX31_CSPICTRL_SSPOL; 771 if (!spi_get_csgpiod(spi, 0)) 772 reg |= (spi_get_chipselect(spi, 0)) << 773 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT : 774 MX31_CSPICTRL_CS_SHIFT); 775 776 if (spi_imx->usedma) 777 reg |= MX31_CSPICTRL_SMC; 778 779 writel(reg, spi_imx->base + MXC_CSPICTRL); 780 781 reg = readl(spi_imx->base + MX31_CSPI_TESTREG); 782 if (spi->mode & SPI_LOOP) 783 reg |= MX31_TEST_LBC; 784 else 785 reg &= ~MX31_TEST_LBC; 786 writel(reg, spi_imx->base + MX31_CSPI_TESTREG); 787 788 if (spi_imx->usedma) { 789 /* 790 * configure DMA requests when RXFIFO is half full and 791 * when TXFIFO is half empty 792 */ 793 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN, 794 spi_imx->base + MX31_CSPI_DMAREG); 795 } 796 797 return 0; 798 } 799 800 static int mx31_rx_available(struct spi_imx_data *spi_imx) 801 { 802 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; 803 } 804 805 static void mx31_reset(struct spi_imx_data *spi_imx) 806 { 807 /* drain receive buffer */ 808 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) 809 readl(spi_imx->base + MXC_CSPIRXDATA); 810 } 811 812 #define MX21_INTREG_RR (1 << 4) 813 #define MX21_INTREG_TEEN (1 << 9) 814 #define MX21_INTREG_RREN (1 << 13) 815 816 #define MX21_CSPICTRL_POL (1 << 5) 817 #define MX21_CSPICTRL_PHA (1 << 6) 818 #define MX21_CSPICTRL_SSPOL (1 << 8) 819 #define MX21_CSPICTRL_XCH (1 << 9) 820 #define MX21_CSPICTRL_ENABLE (1 << 10) 821 #define MX21_CSPICTRL_MASTER (1 << 11) 822 #define MX21_CSPICTRL_DR_SHIFT 14 823 #define MX21_CSPICTRL_CS_SHIFT 19 824 825 static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable) 826 { 827 unsigned int val = 0; 828 829 if (enable & MXC_INT_TE) 830 val |= MX21_INTREG_TEEN; 831 if (enable & MXC_INT_RR) 832 val |= MX21_INTREG_RREN; 833 834 writel(val, spi_imx->base + MXC_CSPIINT); 835 } 836 837 static void mx21_trigger(struct spi_imx_data *spi_imx) 838 { 839 unsigned int reg; 840 841 reg = readl(spi_imx->base + MXC_CSPICTRL); 842 reg |= MX21_CSPICTRL_XCH; 843 writel(reg, spi_imx->base + MXC_CSPICTRL); 844 } 845 846 static int mx21_prepare_message(struct spi_imx_data *spi_imx, 847 struct spi_message *msg) 848 { 849 return 0; 850 } 851 852 static int mx21_prepare_transfer(struct spi_imx_data *spi_imx, 853 struct spi_device *spi) 854 { 855 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER; 856 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18; 857 unsigned int clk; 858 859 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk) 860 << MX21_CSPICTRL_DR_SHIFT; 861 spi_imx->spi_bus_clk = clk; 862 863 reg |= spi_imx->bits_per_word - 1; 864 865 if (spi->mode & SPI_CPHA) 866 reg |= MX21_CSPICTRL_PHA; 867 if (spi->mode & SPI_CPOL) 868 reg |= MX21_CSPICTRL_POL; 869 if (spi->mode & SPI_CS_HIGH) 870 reg |= MX21_CSPICTRL_SSPOL; 871 if (!spi_get_csgpiod(spi, 0)) 872 reg |= spi_get_chipselect(spi, 0) << MX21_CSPICTRL_CS_SHIFT; 873 874 writel(reg, spi_imx->base + MXC_CSPICTRL); 875 876 return 0; 877 } 878 879 static int mx21_rx_available(struct spi_imx_data *spi_imx) 880 { 881 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; 882 } 883 884 static void mx21_reset(struct spi_imx_data *spi_imx) 885 { 886 writel(1, spi_imx->base + MXC_RESET); 887 } 888 889 #define MX1_INTREG_RR (1 << 3) 890 #define MX1_INTREG_TEEN (1 << 8) 891 #define MX1_INTREG_RREN (1 << 11) 892 893 #define MX1_CSPICTRL_POL (1 << 4) 894 #define MX1_CSPICTRL_PHA (1 << 5) 895 #define MX1_CSPICTRL_XCH (1 << 8) 896 #define MX1_CSPICTRL_ENABLE (1 << 9) 897 #define MX1_CSPICTRL_MASTER (1 << 10) 898 #define MX1_CSPICTRL_DR_SHIFT 13 899 900 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable) 901 { 902 unsigned int val = 0; 903 904 if (enable & MXC_INT_TE) 905 val |= MX1_INTREG_TEEN; 906 if (enable & MXC_INT_RR) 907 val |= MX1_INTREG_RREN; 908 909 writel(val, spi_imx->base + MXC_CSPIINT); 910 } 911 912 static void mx1_trigger(struct spi_imx_data *spi_imx) 913 { 914 unsigned int reg; 915 916 reg = readl(spi_imx->base + MXC_CSPICTRL); 917 reg |= MX1_CSPICTRL_XCH; 918 writel(reg, spi_imx->base + MXC_CSPICTRL); 919 } 920 921 static int mx1_prepare_message(struct spi_imx_data *spi_imx, 922 struct spi_message *msg) 923 { 924 return 0; 925 } 926 927 static int mx1_prepare_transfer(struct spi_imx_data *spi_imx, 928 struct spi_device *spi) 929 { 930 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; 931 unsigned int clk; 932 933 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) << 934 MX1_CSPICTRL_DR_SHIFT; 935 spi_imx->spi_bus_clk = clk; 936 937 reg |= spi_imx->bits_per_word - 1; 938 939 if (spi->mode & SPI_CPHA) 940 reg |= MX1_CSPICTRL_PHA; 941 if (spi->mode & SPI_CPOL) 942 reg |= MX1_CSPICTRL_POL; 943 944 writel(reg, spi_imx->base + MXC_CSPICTRL); 945 946 return 0; 947 } 948 949 static int mx1_rx_available(struct spi_imx_data *spi_imx) 950 { 951 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; 952 } 953 954 static void mx1_reset(struct spi_imx_data *spi_imx) 955 { 956 writel(1, spi_imx->base + MXC_RESET); 957 } 958 959 static struct spi_imx_devtype_data imx1_cspi_devtype_data = { 960 .intctrl = mx1_intctrl, 961 .prepare_message = mx1_prepare_message, 962 .prepare_transfer = mx1_prepare_transfer, 963 .trigger = mx1_trigger, 964 .rx_available = mx1_rx_available, 965 .reset = mx1_reset, 966 .fifo_size = 8, 967 .has_dmamode = false, 968 .dynamic_burst = false, 969 .has_slavemode = false, 970 .devtype = IMX1_CSPI, 971 }; 972 973 static struct spi_imx_devtype_data imx21_cspi_devtype_data = { 974 .intctrl = mx21_intctrl, 975 .prepare_message = mx21_prepare_message, 976 .prepare_transfer = mx21_prepare_transfer, 977 .trigger = mx21_trigger, 978 .rx_available = mx21_rx_available, 979 .reset = mx21_reset, 980 .fifo_size = 8, 981 .has_dmamode = false, 982 .dynamic_burst = false, 983 .has_slavemode = false, 984 .devtype = IMX21_CSPI, 985 }; 986 987 static struct spi_imx_devtype_data imx27_cspi_devtype_data = { 988 /* i.mx27 cspi shares the functions with i.mx21 one */ 989 .intctrl = mx21_intctrl, 990 .prepare_message = mx21_prepare_message, 991 .prepare_transfer = mx21_prepare_transfer, 992 .trigger = mx21_trigger, 993 .rx_available = mx21_rx_available, 994 .reset = mx21_reset, 995 .fifo_size = 8, 996 .has_dmamode = false, 997 .dynamic_burst = false, 998 .has_slavemode = false, 999 .devtype = IMX27_CSPI, 1000 }; 1001 1002 static struct spi_imx_devtype_data imx31_cspi_devtype_data = { 1003 .intctrl = mx31_intctrl, 1004 .prepare_message = mx31_prepare_message, 1005 .prepare_transfer = mx31_prepare_transfer, 1006 .trigger = mx31_trigger, 1007 .rx_available = mx31_rx_available, 1008 .reset = mx31_reset, 1009 .fifo_size = 8, 1010 .has_dmamode = false, 1011 .dynamic_burst = false, 1012 .has_slavemode = false, 1013 .devtype = IMX31_CSPI, 1014 }; 1015 1016 static struct spi_imx_devtype_data imx35_cspi_devtype_data = { 1017 /* i.mx35 and later cspi shares the functions with i.mx31 one */ 1018 .intctrl = mx31_intctrl, 1019 .prepare_message = mx31_prepare_message, 1020 .prepare_transfer = mx31_prepare_transfer, 1021 .trigger = mx31_trigger, 1022 .rx_available = mx31_rx_available, 1023 .reset = mx31_reset, 1024 .fifo_size = 8, 1025 .has_dmamode = true, 1026 .dynamic_burst = false, 1027 .has_slavemode = false, 1028 .devtype = IMX35_CSPI, 1029 }; 1030 1031 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = { 1032 .intctrl = mx51_ecspi_intctrl, 1033 .prepare_message = mx51_ecspi_prepare_message, 1034 .prepare_transfer = mx51_ecspi_prepare_transfer, 1035 .trigger = mx51_ecspi_trigger, 1036 .rx_available = mx51_ecspi_rx_available, 1037 .reset = mx51_ecspi_reset, 1038 .setup_wml = mx51_setup_wml, 1039 .fifo_size = 64, 1040 .has_dmamode = true, 1041 .dynamic_burst = true, 1042 .has_slavemode = true, 1043 .disable = mx51_ecspi_disable, 1044 .devtype = IMX51_ECSPI, 1045 }; 1046 1047 static struct spi_imx_devtype_data imx53_ecspi_devtype_data = { 1048 .intctrl = mx51_ecspi_intctrl, 1049 .prepare_message = mx51_ecspi_prepare_message, 1050 .prepare_transfer = mx51_ecspi_prepare_transfer, 1051 .trigger = mx51_ecspi_trigger, 1052 .rx_available = mx51_ecspi_rx_available, 1053 .reset = mx51_ecspi_reset, 1054 .fifo_size = 64, 1055 .has_dmamode = true, 1056 .has_slavemode = true, 1057 .disable = mx51_ecspi_disable, 1058 .devtype = IMX53_ECSPI, 1059 }; 1060 1061 static struct spi_imx_devtype_data imx6ul_ecspi_devtype_data = { 1062 .intctrl = mx51_ecspi_intctrl, 1063 .prepare_message = mx51_ecspi_prepare_message, 1064 .prepare_transfer = mx51_ecspi_prepare_transfer, 1065 .trigger = mx51_ecspi_trigger, 1066 .rx_available = mx51_ecspi_rx_available, 1067 .reset = mx51_ecspi_reset, 1068 .setup_wml = mx51_setup_wml, 1069 .fifo_size = 64, 1070 .has_dmamode = true, 1071 .dynamic_burst = true, 1072 .has_slavemode = true, 1073 .tx_glitch_fixed = true, 1074 .disable = mx51_ecspi_disable, 1075 .devtype = IMX51_ECSPI, 1076 }; 1077 1078 static const struct of_device_id spi_imx_dt_ids[] = { 1079 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, }, 1080 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, }, 1081 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, }, 1082 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, }, 1083 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, }, 1084 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, }, 1085 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, }, 1086 { .compatible = "fsl,imx6ul-ecspi", .data = &imx6ul_ecspi_devtype_data, }, 1087 { /* sentinel */ } 1088 }; 1089 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids); 1090 1091 static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits) 1092 { 1093 u32 ctrl; 1094 1095 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); 1096 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK; 1097 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET); 1098 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 1099 } 1100 1101 static void spi_imx_push(struct spi_imx_data *spi_imx) 1102 { 1103 unsigned int burst_len; 1104 1105 /* 1106 * Reload the FIFO when the remaining bytes to be transferred in the 1107 * current burst is 0. This only applies when bits_per_word is a 1108 * multiple of 8. 1109 */ 1110 if (!spi_imx->remainder) { 1111 if (spi_imx->dynamic_burst) { 1112 1113 /* We need to deal unaligned data first */ 1114 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST; 1115 1116 if (!burst_len) 1117 burst_len = MX51_ECSPI_CTRL_MAX_BURST; 1118 1119 spi_imx_set_burst_len(spi_imx, burst_len * 8); 1120 1121 spi_imx->remainder = burst_len; 1122 } else { 1123 spi_imx->remainder = spi_imx_bytes_per_word(spi_imx->bits_per_word); 1124 } 1125 } 1126 1127 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) { 1128 if (!spi_imx->count) 1129 break; 1130 if (spi_imx->dynamic_burst && 1131 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder, 4)) 1132 break; 1133 spi_imx->tx(spi_imx); 1134 spi_imx->txfifo++; 1135 } 1136 1137 if (!spi_imx->slave_mode) 1138 spi_imx->devtype_data->trigger(spi_imx); 1139 } 1140 1141 static irqreturn_t spi_imx_isr(int irq, void *dev_id) 1142 { 1143 struct spi_imx_data *spi_imx = dev_id; 1144 1145 while (spi_imx->txfifo && 1146 spi_imx->devtype_data->rx_available(spi_imx)) { 1147 spi_imx->rx(spi_imx); 1148 spi_imx->txfifo--; 1149 } 1150 1151 if (spi_imx->count) { 1152 spi_imx_push(spi_imx); 1153 return IRQ_HANDLED; 1154 } 1155 1156 if (spi_imx->txfifo) { 1157 /* No data left to push, but still waiting for rx data, 1158 * enable receive data available interrupt. 1159 */ 1160 spi_imx->devtype_data->intctrl( 1161 spi_imx, MXC_INT_RR); 1162 return IRQ_HANDLED; 1163 } 1164 1165 spi_imx->devtype_data->intctrl(spi_imx, 0); 1166 complete(&spi_imx->xfer_done); 1167 1168 return IRQ_HANDLED; 1169 } 1170 1171 static int spi_imx_dma_configure(struct spi_controller *controller) 1172 { 1173 int ret; 1174 enum dma_slave_buswidth buswidth; 1175 struct dma_slave_config rx = {}, tx = {}; 1176 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller); 1177 1178 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) { 1179 case 4: 1180 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES; 1181 break; 1182 case 2: 1183 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; 1184 break; 1185 case 1: 1186 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; 1187 break; 1188 default: 1189 return -EINVAL; 1190 } 1191 1192 tx.direction = DMA_MEM_TO_DEV; 1193 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA; 1194 tx.dst_addr_width = buswidth; 1195 tx.dst_maxburst = spi_imx->wml; 1196 ret = dmaengine_slave_config(controller->dma_tx, &tx); 1197 if (ret) { 1198 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret); 1199 return ret; 1200 } 1201 1202 rx.direction = DMA_DEV_TO_MEM; 1203 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA; 1204 rx.src_addr_width = buswidth; 1205 rx.src_maxburst = spi_imx->wml; 1206 ret = dmaengine_slave_config(controller->dma_rx, &rx); 1207 if (ret) { 1208 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret); 1209 return ret; 1210 } 1211 1212 return 0; 1213 } 1214 1215 static int spi_imx_setupxfer(struct spi_device *spi, 1216 struct spi_transfer *t) 1217 { 1218 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); 1219 1220 if (!t) 1221 return 0; 1222 1223 if (!t->speed_hz) { 1224 if (!spi->max_speed_hz) { 1225 dev_err(&spi->dev, "no speed_hz provided!\n"); 1226 return -EINVAL; 1227 } 1228 dev_dbg(&spi->dev, "using spi->max_speed_hz!\n"); 1229 spi_imx->spi_bus_clk = spi->max_speed_hz; 1230 } else 1231 spi_imx->spi_bus_clk = t->speed_hz; 1232 1233 spi_imx->bits_per_word = t->bits_per_word; 1234 1235 /* 1236 * Initialize the functions for transfer. To transfer non byte-aligned 1237 * words, we have to use multiple word-size bursts, we can't use 1238 * dynamic_burst in that case. 1239 */ 1240 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode && 1241 !(spi->mode & SPI_CS_WORD) && 1242 (spi_imx->bits_per_word == 8 || 1243 spi_imx->bits_per_word == 16 || 1244 spi_imx->bits_per_word == 32)) { 1245 1246 spi_imx->rx = spi_imx_buf_rx_swap; 1247 spi_imx->tx = spi_imx_buf_tx_swap; 1248 spi_imx->dynamic_burst = 1; 1249 1250 } else { 1251 if (spi_imx->bits_per_word <= 8) { 1252 spi_imx->rx = spi_imx_buf_rx_u8; 1253 spi_imx->tx = spi_imx_buf_tx_u8; 1254 } else if (spi_imx->bits_per_word <= 16) { 1255 spi_imx->rx = spi_imx_buf_rx_u16; 1256 spi_imx->tx = spi_imx_buf_tx_u16; 1257 } else { 1258 spi_imx->rx = spi_imx_buf_rx_u32; 1259 spi_imx->tx = spi_imx_buf_tx_u32; 1260 } 1261 spi_imx->dynamic_burst = 0; 1262 } 1263 1264 if (spi_imx_can_dma(spi_imx->controller, spi, t)) 1265 spi_imx->usedma = true; 1266 else 1267 spi_imx->usedma = false; 1268 1269 spi_imx->rx_only = ((t->tx_buf == NULL) 1270 || (t->tx_buf == spi->controller->dummy_tx)); 1271 1272 if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) { 1273 spi_imx->rx = mx53_ecspi_rx_slave; 1274 spi_imx->tx = mx53_ecspi_tx_slave; 1275 spi_imx->slave_burst = t->len; 1276 } 1277 1278 spi_imx->devtype_data->prepare_transfer(spi_imx, spi); 1279 1280 return 0; 1281 } 1282 1283 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx) 1284 { 1285 struct spi_controller *controller = spi_imx->controller; 1286 1287 if (controller->dma_rx) { 1288 dma_release_channel(controller->dma_rx); 1289 controller->dma_rx = NULL; 1290 } 1291 1292 if (controller->dma_tx) { 1293 dma_release_channel(controller->dma_tx); 1294 controller->dma_tx = NULL; 1295 } 1296 } 1297 1298 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx, 1299 struct spi_controller *controller) 1300 { 1301 int ret; 1302 1303 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2; 1304 1305 /* Prepare for TX DMA: */ 1306 controller->dma_tx = dma_request_chan(dev, "tx"); 1307 if (IS_ERR(controller->dma_tx)) { 1308 ret = PTR_ERR(controller->dma_tx); 1309 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret); 1310 controller->dma_tx = NULL; 1311 goto err; 1312 } 1313 1314 /* Prepare for RX : */ 1315 controller->dma_rx = dma_request_chan(dev, "rx"); 1316 if (IS_ERR(controller->dma_rx)) { 1317 ret = PTR_ERR(controller->dma_rx); 1318 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret); 1319 controller->dma_rx = NULL; 1320 goto err; 1321 } 1322 1323 init_completion(&spi_imx->dma_rx_completion); 1324 init_completion(&spi_imx->dma_tx_completion); 1325 controller->can_dma = spi_imx_can_dma; 1326 controller->max_dma_len = MAX_SDMA_BD_BYTES; 1327 spi_imx->controller->flags = SPI_CONTROLLER_MUST_RX | 1328 SPI_CONTROLLER_MUST_TX; 1329 1330 return 0; 1331 err: 1332 spi_imx_sdma_exit(spi_imx); 1333 return ret; 1334 } 1335 1336 static void spi_imx_dma_rx_callback(void *cookie) 1337 { 1338 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; 1339 1340 complete(&spi_imx->dma_rx_completion); 1341 } 1342 1343 static void spi_imx_dma_tx_callback(void *cookie) 1344 { 1345 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; 1346 1347 complete(&spi_imx->dma_tx_completion); 1348 } 1349 1350 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size) 1351 { 1352 unsigned long timeout = 0; 1353 1354 /* Time with actual data transfer and CS change delay related to HW */ 1355 timeout = (8 + 4) * size / spi_imx->spi_bus_clk; 1356 1357 /* Add extra second for scheduler related activities */ 1358 timeout += 1; 1359 1360 /* Double calculated timeout */ 1361 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC); 1362 } 1363 1364 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, 1365 struct spi_transfer *transfer) 1366 { 1367 struct dma_async_tx_descriptor *desc_tx, *desc_rx; 1368 unsigned long transfer_timeout; 1369 unsigned long timeout; 1370 struct spi_controller *controller = spi_imx->controller; 1371 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; 1372 struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents); 1373 unsigned int bytes_per_word, i; 1374 int ret; 1375 1376 /* Get the right burst length from the last sg to ensure no tail data */ 1377 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word); 1378 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) { 1379 if (!(sg_dma_len(last_sg) % (i * bytes_per_word))) 1380 break; 1381 } 1382 /* Use 1 as wml in case no available burst length got */ 1383 if (i == 0) 1384 i = 1; 1385 1386 spi_imx->wml = i; 1387 1388 ret = spi_imx_dma_configure(controller); 1389 if (ret) 1390 goto dma_failure_no_start; 1391 1392 if (!spi_imx->devtype_data->setup_wml) { 1393 dev_err(spi_imx->dev, "No setup_wml()?\n"); 1394 ret = -EINVAL; 1395 goto dma_failure_no_start; 1396 } 1397 spi_imx->devtype_data->setup_wml(spi_imx); 1398 1399 /* 1400 * The TX DMA setup starts the transfer, so make sure RX is configured 1401 * before TX. 1402 */ 1403 desc_rx = dmaengine_prep_slave_sg(controller->dma_rx, 1404 rx->sgl, rx->nents, DMA_DEV_TO_MEM, 1405 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1406 if (!desc_rx) { 1407 ret = -EINVAL; 1408 goto dma_failure_no_start; 1409 } 1410 1411 desc_rx->callback = spi_imx_dma_rx_callback; 1412 desc_rx->callback_param = (void *)spi_imx; 1413 dmaengine_submit(desc_rx); 1414 reinit_completion(&spi_imx->dma_rx_completion); 1415 dma_async_issue_pending(controller->dma_rx); 1416 1417 desc_tx = dmaengine_prep_slave_sg(controller->dma_tx, 1418 tx->sgl, tx->nents, DMA_MEM_TO_DEV, 1419 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1420 if (!desc_tx) { 1421 dmaengine_terminate_all(controller->dma_tx); 1422 dmaengine_terminate_all(controller->dma_rx); 1423 return -EINVAL; 1424 } 1425 1426 desc_tx->callback = spi_imx_dma_tx_callback; 1427 desc_tx->callback_param = (void *)spi_imx; 1428 dmaengine_submit(desc_tx); 1429 reinit_completion(&spi_imx->dma_tx_completion); 1430 dma_async_issue_pending(controller->dma_tx); 1431 1432 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); 1433 1434 /* Wait SDMA to finish the data transfer.*/ 1435 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion, 1436 transfer_timeout); 1437 if (!timeout) { 1438 dev_err(spi_imx->dev, "I/O Error in DMA TX\n"); 1439 dmaengine_terminate_all(controller->dma_tx); 1440 dmaengine_terminate_all(controller->dma_rx); 1441 return -ETIMEDOUT; 1442 } 1443 1444 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion, 1445 transfer_timeout); 1446 if (!timeout) { 1447 dev_err(&controller->dev, "I/O Error in DMA RX\n"); 1448 spi_imx->devtype_data->reset(spi_imx); 1449 dmaengine_terminate_all(controller->dma_rx); 1450 return -ETIMEDOUT; 1451 } 1452 1453 return 0; 1454 /* fallback to pio */ 1455 dma_failure_no_start: 1456 transfer->error |= SPI_TRANS_FAIL_NO_START; 1457 return ret; 1458 } 1459 1460 static int spi_imx_pio_transfer(struct spi_device *spi, 1461 struct spi_transfer *transfer) 1462 { 1463 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); 1464 unsigned long transfer_timeout; 1465 unsigned long timeout; 1466 1467 spi_imx->tx_buf = transfer->tx_buf; 1468 spi_imx->rx_buf = transfer->rx_buf; 1469 spi_imx->count = transfer->len; 1470 spi_imx->txfifo = 0; 1471 spi_imx->remainder = 0; 1472 1473 reinit_completion(&spi_imx->xfer_done); 1474 1475 spi_imx_push(spi_imx); 1476 1477 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); 1478 1479 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); 1480 1481 timeout = wait_for_completion_timeout(&spi_imx->xfer_done, 1482 transfer_timeout); 1483 if (!timeout) { 1484 dev_err(&spi->dev, "I/O Error in PIO\n"); 1485 spi_imx->devtype_data->reset(spi_imx); 1486 return -ETIMEDOUT; 1487 } 1488 1489 return 0; 1490 } 1491 1492 static int spi_imx_poll_transfer(struct spi_device *spi, 1493 struct spi_transfer *transfer) 1494 { 1495 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); 1496 unsigned long timeout; 1497 1498 spi_imx->tx_buf = transfer->tx_buf; 1499 spi_imx->rx_buf = transfer->rx_buf; 1500 spi_imx->count = transfer->len; 1501 spi_imx->txfifo = 0; 1502 spi_imx->remainder = 0; 1503 1504 /* fill in the fifo before timeout calculations if we are 1505 * interrupted here, then the data is getting transferred by 1506 * the HW while we are interrupted 1507 */ 1508 spi_imx_push(spi_imx); 1509 1510 timeout = spi_imx_calculate_timeout(spi_imx, transfer->len) + jiffies; 1511 while (spi_imx->txfifo) { 1512 /* RX */ 1513 while (spi_imx->txfifo && 1514 spi_imx->devtype_data->rx_available(spi_imx)) { 1515 spi_imx->rx(spi_imx); 1516 spi_imx->txfifo--; 1517 } 1518 1519 /* TX */ 1520 if (spi_imx->count) { 1521 spi_imx_push(spi_imx); 1522 continue; 1523 } 1524 1525 if (spi_imx->txfifo && 1526 time_after(jiffies, timeout)) { 1527 1528 dev_err_ratelimited(&spi->dev, 1529 "timeout period reached: jiffies: %lu- falling back to interrupt mode\n", 1530 jiffies - timeout); 1531 1532 /* fall back to interrupt mode */ 1533 return spi_imx_pio_transfer(spi, transfer); 1534 } 1535 } 1536 1537 return 0; 1538 } 1539 1540 static int spi_imx_pio_transfer_slave(struct spi_device *spi, 1541 struct spi_transfer *transfer) 1542 { 1543 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); 1544 int ret = 0; 1545 1546 if (is_imx53_ecspi(spi_imx) && 1547 transfer->len > MX53_MAX_TRANSFER_BYTES) { 1548 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n", 1549 MX53_MAX_TRANSFER_BYTES); 1550 return -EMSGSIZE; 1551 } 1552 1553 spi_imx->tx_buf = transfer->tx_buf; 1554 spi_imx->rx_buf = transfer->rx_buf; 1555 spi_imx->count = transfer->len; 1556 spi_imx->txfifo = 0; 1557 spi_imx->remainder = 0; 1558 1559 reinit_completion(&spi_imx->xfer_done); 1560 spi_imx->slave_aborted = false; 1561 1562 spi_imx_push(spi_imx); 1563 1564 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR); 1565 1566 if (wait_for_completion_interruptible(&spi_imx->xfer_done) || 1567 spi_imx->slave_aborted) { 1568 dev_dbg(&spi->dev, "interrupted\n"); 1569 ret = -EINTR; 1570 } 1571 1572 /* ecspi has a HW issue when works in Slave mode, 1573 * after 64 words writtern to TXFIFO, even TXFIFO becomes empty, 1574 * ECSPI_TXDATA keeps shift out the last word data, 1575 * so we have to disable ECSPI when in slave mode after the 1576 * transfer completes 1577 */ 1578 if (spi_imx->devtype_data->disable) 1579 spi_imx->devtype_data->disable(spi_imx); 1580 1581 return ret; 1582 } 1583 1584 static int spi_imx_transfer_one(struct spi_controller *controller, 1585 struct spi_device *spi, 1586 struct spi_transfer *transfer) 1587 { 1588 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); 1589 unsigned long hz_per_byte, byte_limit; 1590 1591 spi_imx_setupxfer(spi, transfer); 1592 transfer->effective_speed_hz = spi_imx->spi_bus_clk; 1593 1594 /* flush rxfifo before transfer */ 1595 while (spi_imx->devtype_data->rx_available(spi_imx)) 1596 readl(spi_imx->base + MXC_CSPIRXDATA); 1597 1598 if (spi_imx->slave_mode) 1599 return spi_imx_pio_transfer_slave(spi, transfer); 1600 1601 /* 1602 * If we decided in spi_imx_can_dma() that we want to do a DMA 1603 * transfer, the SPI transfer has already been mapped, so we 1604 * have to do the DMA transfer here. 1605 */ 1606 if (spi_imx->usedma) 1607 return spi_imx_dma_transfer(spi_imx, transfer); 1608 /* 1609 * Calculate the estimated time in us the transfer runs. Find 1610 * the number of Hz per byte per polling limit. 1611 */ 1612 hz_per_byte = polling_limit_us ? ((8 + 4) * USEC_PER_SEC) / polling_limit_us : 0; 1613 byte_limit = hz_per_byte ? transfer->effective_speed_hz / hz_per_byte : 1; 1614 1615 /* run in polling mode for short transfers */ 1616 if (transfer->len < byte_limit) 1617 return spi_imx_poll_transfer(spi, transfer); 1618 1619 return spi_imx_pio_transfer(spi, transfer); 1620 } 1621 1622 static int spi_imx_setup(struct spi_device *spi) 1623 { 1624 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, 1625 spi->mode, spi->bits_per_word, spi->max_speed_hz); 1626 1627 return 0; 1628 } 1629 1630 static void spi_imx_cleanup(struct spi_device *spi) 1631 { 1632 } 1633 1634 static int 1635 spi_imx_prepare_message(struct spi_controller *controller, struct spi_message *msg) 1636 { 1637 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller); 1638 int ret; 1639 1640 ret = pm_runtime_resume_and_get(spi_imx->dev); 1641 if (ret < 0) { 1642 dev_err(spi_imx->dev, "failed to enable clock\n"); 1643 return ret; 1644 } 1645 1646 ret = spi_imx->devtype_data->prepare_message(spi_imx, msg); 1647 if (ret) { 1648 pm_runtime_mark_last_busy(spi_imx->dev); 1649 pm_runtime_put_autosuspend(spi_imx->dev); 1650 } 1651 1652 return ret; 1653 } 1654 1655 static int 1656 spi_imx_unprepare_message(struct spi_controller *controller, struct spi_message *msg) 1657 { 1658 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller); 1659 1660 pm_runtime_mark_last_busy(spi_imx->dev); 1661 pm_runtime_put_autosuspend(spi_imx->dev); 1662 return 0; 1663 } 1664 1665 static int spi_imx_slave_abort(struct spi_controller *controller) 1666 { 1667 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller); 1668 1669 spi_imx->slave_aborted = true; 1670 complete(&spi_imx->xfer_done); 1671 1672 return 0; 1673 } 1674 1675 static int spi_imx_probe(struct platform_device *pdev) 1676 { 1677 struct device_node *np = pdev->dev.of_node; 1678 struct spi_controller *controller; 1679 struct spi_imx_data *spi_imx; 1680 struct resource *res; 1681 int ret, irq, spi_drctl; 1682 const struct spi_imx_devtype_data *devtype_data = 1683 of_device_get_match_data(&pdev->dev); 1684 bool slave_mode; 1685 u32 val; 1686 1687 slave_mode = devtype_data->has_slavemode && 1688 of_property_read_bool(np, "spi-slave"); 1689 if (slave_mode) 1690 controller = spi_alloc_slave(&pdev->dev, 1691 sizeof(struct spi_imx_data)); 1692 else 1693 controller = spi_alloc_master(&pdev->dev, 1694 sizeof(struct spi_imx_data)); 1695 if (!controller) 1696 return -ENOMEM; 1697 1698 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl); 1699 if ((ret < 0) || (spi_drctl >= 0x3)) { 1700 /* '11' is reserved */ 1701 spi_drctl = 0; 1702 } 1703 1704 platform_set_drvdata(pdev, controller); 1705 1706 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); 1707 controller->bus_num = np ? -1 : pdev->id; 1708 controller->use_gpio_descriptors = true; 1709 1710 spi_imx = spi_controller_get_devdata(controller); 1711 spi_imx->controller = controller; 1712 spi_imx->dev = &pdev->dev; 1713 spi_imx->slave_mode = slave_mode; 1714 1715 spi_imx->devtype_data = devtype_data; 1716 1717 /* 1718 * Get number of chip selects from device properties. This can be 1719 * coming from device tree or boardfiles, if it is not defined, 1720 * a default value of 3 chip selects will be used, as all the legacy 1721 * board files have <= 3 chip selects. 1722 */ 1723 if (!device_property_read_u32(&pdev->dev, "num-cs", &val)) 1724 controller->num_chipselect = val; 1725 else 1726 controller->num_chipselect = 3; 1727 1728 spi_imx->controller->transfer_one = spi_imx_transfer_one; 1729 spi_imx->controller->setup = spi_imx_setup; 1730 spi_imx->controller->cleanup = spi_imx_cleanup; 1731 spi_imx->controller->prepare_message = spi_imx_prepare_message; 1732 spi_imx->controller->unprepare_message = spi_imx_unprepare_message; 1733 spi_imx->controller->slave_abort = spi_imx_slave_abort; 1734 spi_imx->controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS; 1735 1736 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) || 1737 is_imx53_ecspi(spi_imx)) 1738 spi_imx->controller->mode_bits |= SPI_LOOP | SPI_READY; 1739 1740 if (is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx)) 1741 spi_imx->controller->mode_bits |= SPI_RX_CPHA_FLIP; 1742 1743 if (is_imx51_ecspi(spi_imx) && 1744 device_property_read_u32(&pdev->dev, "cs-gpios", NULL)) 1745 /* 1746 * When using HW-CS implementing SPI_CS_WORD can be done by just 1747 * setting the burst length to the word size. This is 1748 * considerably faster than manually controlling the CS. 1749 */ 1750 spi_imx->controller->mode_bits |= SPI_CS_WORD; 1751 1752 spi_imx->spi_drctl = spi_drctl; 1753 1754 init_completion(&spi_imx->xfer_done); 1755 1756 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1757 spi_imx->base = devm_ioremap_resource(&pdev->dev, res); 1758 if (IS_ERR(spi_imx->base)) { 1759 ret = PTR_ERR(spi_imx->base); 1760 goto out_controller_put; 1761 } 1762 spi_imx->base_phys = res->start; 1763 1764 irq = platform_get_irq(pdev, 0); 1765 if (irq < 0) { 1766 ret = irq; 1767 goto out_controller_put; 1768 } 1769 1770 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0, 1771 dev_name(&pdev->dev), spi_imx); 1772 if (ret) { 1773 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); 1774 goto out_controller_put; 1775 } 1776 1777 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1778 if (IS_ERR(spi_imx->clk_ipg)) { 1779 ret = PTR_ERR(spi_imx->clk_ipg); 1780 goto out_controller_put; 1781 } 1782 1783 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); 1784 if (IS_ERR(spi_imx->clk_per)) { 1785 ret = PTR_ERR(spi_imx->clk_per); 1786 goto out_controller_put; 1787 } 1788 1789 ret = clk_prepare_enable(spi_imx->clk_per); 1790 if (ret) 1791 goto out_controller_put; 1792 1793 ret = clk_prepare_enable(spi_imx->clk_ipg); 1794 if (ret) 1795 goto out_put_per; 1796 1797 pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT); 1798 pm_runtime_use_autosuspend(spi_imx->dev); 1799 pm_runtime_get_noresume(spi_imx->dev); 1800 pm_runtime_set_active(spi_imx->dev); 1801 pm_runtime_enable(spi_imx->dev); 1802 1803 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); 1804 /* 1805 * Only validated on i.mx35 and i.mx6 now, can remove the constraint 1806 * if validated on other chips. 1807 */ 1808 if (spi_imx->devtype_data->has_dmamode) { 1809 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, controller); 1810 if (ret == -EPROBE_DEFER) 1811 goto out_runtime_pm_put; 1812 1813 if (ret < 0) 1814 dev_dbg(&pdev->dev, "dma setup error %d, use pio\n", 1815 ret); 1816 } 1817 1818 spi_imx->devtype_data->reset(spi_imx); 1819 1820 spi_imx->devtype_data->intctrl(spi_imx, 0); 1821 1822 controller->dev.of_node = pdev->dev.of_node; 1823 ret = spi_register_controller(controller); 1824 if (ret) { 1825 dev_err_probe(&pdev->dev, ret, "register controller failed\n"); 1826 goto out_register_controller; 1827 } 1828 1829 pm_runtime_mark_last_busy(spi_imx->dev); 1830 pm_runtime_put_autosuspend(spi_imx->dev); 1831 1832 return ret; 1833 1834 out_register_controller: 1835 if (spi_imx->devtype_data->has_dmamode) 1836 spi_imx_sdma_exit(spi_imx); 1837 out_runtime_pm_put: 1838 pm_runtime_dont_use_autosuspend(spi_imx->dev); 1839 pm_runtime_set_suspended(&pdev->dev); 1840 pm_runtime_disable(spi_imx->dev); 1841 1842 clk_disable_unprepare(spi_imx->clk_ipg); 1843 out_put_per: 1844 clk_disable_unprepare(spi_imx->clk_per); 1845 out_controller_put: 1846 spi_controller_put(controller); 1847 1848 return ret; 1849 } 1850 1851 static int spi_imx_remove(struct platform_device *pdev) 1852 { 1853 struct spi_controller *controller = platform_get_drvdata(pdev); 1854 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller); 1855 int ret; 1856 1857 spi_unregister_controller(controller); 1858 1859 ret = pm_runtime_get_sync(spi_imx->dev); 1860 if (ret >= 0) 1861 writel(0, spi_imx->base + MXC_CSPICTRL); 1862 else 1863 dev_warn(spi_imx->dev, "failed to enable clock, skip hw disable\n"); 1864 1865 pm_runtime_dont_use_autosuspend(spi_imx->dev); 1866 pm_runtime_put_sync(spi_imx->dev); 1867 pm_runtime_disable(spi_imx->dev); 1868 1869 spi_imx_sdma_exit(spi_imx); 1870 1871 return 0; 1872 } 1873 1874 static int __maybe_unused spi_imx_runtime_resume(struct device *dev) 1875 { 1876 struct spi_controller *controller = dev_get_drvdata(dev); 1877 struct spi_imx_data *spi_imx; 1878 int ret; 1879 1880 spi_imx = spi_controller_get_devdata(controller); 1881 1882 ret = clk_prepare_enable(spi_imx->clk_per); 1883 if (ret) 1884 return ret; 1885 1886 ret = clk_prepare_enable(spi_imx->clk_ipg); 1887 if (ret) { 1888 clk_disable_unprepare(spi_imx->clk_per); 1889 return ret; 1890 } 1891 1892 return 0; 1893 } 1894 1895 static int __maybe_unused spi_imx_runtime_suspend(struct device *dev) 1896 { 1897 struct spi_controller *controller = dev_get_drvdata(dev); 1898 struct spi_imx_data *spi_imx; 1899 1900 spi_imx = spi_controller_get_devdata(controller); 1901 1902 clk_disable_unprepare(spi_imx->clk_per); 1903 clk_disable_unprepare(spi_imx->clk_ipg); 1904 1905 return 0; 1906 } 1907 1908 static int __maybe_unused spi_imx_suspend(struct device *dev) 1909 { 1910 pinctrl_pm_select_sleep_state(dev); 1911 return 0; 1912 } 1913 1914 static int __maybe_unused spi_imx_resume(struct device *dev) 1915 { 1916 pinctrl_pm_select_default_state(dev); 1917 return 0; 1918 } 1919 1920 static const struct dev_pm_ops imx_spi_pm = { 1921 SET_RUNTIME_PM_OPS(spi_imx_runtime_suspend, 1922 spi_imx_runtime_resume, NULL) 1923 SET_SYSTEM_SLEEP_PM_OPS(spi_imx_suspend, spi_imx_resume) 1924 }; 1925 1926 static struct platform_driver spi_imx_driver = { 1927 .driver = { 1928 .name = DRIVER_NAME, 1929 .of_match_table = spi_imx_dt_ids, 1930 .pm = &imx_spi_pm, 1931 }, 1932 .probe = spi_imx_probe, 1933 .remove = spi_imx_remove, 1934 }; 1935 module_platform_driver(spi_imx_driver); 1936 1937 MODULE_DESCRIPTION("i.MX SPI Controller driver"); 1938 MODULE_AUTHOR("Sascha Hauer, Pengutronix"); 1939 MODULE_LICENSE("GPL"); 1940 MODULE_ALIAS("platform:" DRIVER_NAME); 1941