1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 3 // Copyright (C) 2008 Juergen Beisert 4 5 #include <linux/clk.h> 6 #include <linux/completion.h> 7 #include <linux/delay.h> 8 #include <linux/dmaengine.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/err.h> 11 #include <linux/gpio.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/irq.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/platform_device.h> 18 #include <linux/slab.h> 19 #include <linux/spi/spi.h> 20 #include <linux/spi/spi_bitbang.h> 21 #include <linux/types.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/of_gpio.h> 25 26 #include <linux/platform_data/dma-imx.h> 27 #include <linux/platform_data/spi-imx.h> 28 29 #define DRIVER_NAME "spi_imx" 30 31 static bool use_dma = true; 32 module_param(use_dma, bool, 0644); 33 MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)"); 34 35 #define MXC_CSPIRXDATA 0x00 36 #define MXC_CSPITXDATA 0x04 37 #define MXC_CSPICTRL 0x08 38 #define MXC_CSPIINT 0x0c 39 #define MXC_RESET 0x1c 40 41 /* generic defines to abstract from the different register layouts */ 42 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ 43 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ 44 #define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */ 45 46 /* The maximum bytes that a sdma BD can transfer. */ 47 #define MAX_SDMA_BD_BYTES (1 << 15) 48 #define MX51_ECSPI_CTRL_MAX_BURST 512 49 /* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/ 50 #define MX53_MAX_TRANSFER_BYTES 512 51 52 enum spi_imx_devtype { 53 IMX1_CSPI, 54 IMX21_CSPI, 55 IMX27_CSPI, 56 IMX31_CSPI, 57 IMX35_CSPI, /* CSPI on all i.mx except above */ 58 IMX51_ECSPI, /* ECSPI on i.mx51 */ 59 IMX53_ECSPI, /* ECSPI on i.mx53 and later */ 60 }; 61 62 struct spi_imx_data; 63 64 struct spi_imx_devtype_data { 65 void (*intctrl)(struct spi_imx_data *, int); 66 int (*prepare_message)(struct spi_imx_data *, struct spi_message *); 67 int (*prepare_transfer)(struct spi_imx_data *, struct spi_device *, 68 struct spi_transfer *); 69 void (*trigger)(struct spi_imx_data *); 70 int (*rx_available)(struct spi_imx_data *); 71 void (*reset)(struct spi_imx_data *); 72 void (*setup_wml)(struct spi_imx_data *); 73 void (*disable)(struct spi_imx_data *); 74 bool has_dmamode; 75 bool has_slavemode; 76 unsigned int fifo_size; 77 bool dynamic_burst; 78 enum spi_imx_devtype devtype; 79 }; 80 81 struct spi_imx_data { 82 struct spi_bitbang bitbang; 83 struct device *dev; 84 85 struct completion xfer_done; 86 void __iomem *base; 87 unsigned long base_phys; 88 89 struct clk *clk_per; 90 struct clk *clk_ipg; 91 unsigned long spi_clk; 92 unsigned int spi_bus_clk; 93 94 unsigned int bits_per_word; 95 unsigned int spi_drctl; 96 97 unsigned int count, remainder; 98 void (*tx)(struct spi_imx_data *); 99 void (*rx)(struct spi_imx_data *); 100 void *rx_buf; 101 const void *tx_buf; 102 unsigned int txfifo; /* number of words pushed in tx FIFO */ 103 unsigned int dynamic_burst; 104 105 /* Slave mode */ 106 bool slave_mode; 107 bool slave_aborted; 108 unsigned int slave_burst; 109 110 /* DMA */ 111 bool usedma; 112 u32 wml; 113 struct completion dma_rx_completion; 114 struct completion dma_tx_completion; 115 116 const struct spi_imx_devtype_data *devtype_data; 117 }; 118 119 static inline int is_imx27_cspi(struct spi_imx_data *d) 120 { 121 return d->devtype_data->devtype == IMX27_CSPI; 122 } 123 124 static inline int is_imx35_cspi(struct spi_imx_data *d) 125 { 126 return d->devtype_data->devtype == IMX35_CSPI; 127 } 128 129 static inline int is_imx51_ecspi(struct spi_imx_data *d) 130 { 131 return d->devtype_data->devtype == IMX51_ECSPI; 132 } 133 134 static inline int is_imx53_ecspi(struct spi_imx_data *d) 135 { 136 return d->devtype_data->devtype == IMX53_ECSPI; 137 } 138 139 #define MXC_SPI_BUF_RX(type) \ 140 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \ 141 { \ 142 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ 143 \ 144 if (spi_imx->rx_buf) { \ 145 *(type *)spi_imx->rx_buf = val; \ 146 spi_imx->rx_buf += sizeof(type); \ 147 } \ 148 \ 149 spi_imx->remainder -= sizeof(type); \ 150 } 151 152 #define MXC_SPI_BUF_TX(type) \ 153 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \ 154 { \ 155 type val = 0; \ 156 \ 157 if (spi_imx->tx_buf) { \ 158 val = *(type *)spi_imx->tx_buf; \ 159 spi_imx->tx_buf += sizeof(type); \ 160 } \ 161 \ 162 spi_imx->count -= sizeof(type); \ 163 \ 164 writel(val, spi_imx->base + MXC_CSPITXDATA); \ 165 } 166 167 MXC_SPI_BUF_RX(u8) 168 MXC_SPI_BUF_TX(u8) 169 MXC_SPI_BUF_RX(u16) 170 MXC_SPI_BUF_TX(u16) 171 MXC_SPI_BUF_RX(u32) 172 MXC_SPI_BUF_TX(u32) 173 174 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set 175 * (which is currently not the case in this driver) 176 */ 177 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, 178 256, 384, 512, 768, 1024}; 179 180 /* MX21, MX27 */ 181 static unsigned int spi_imx_clkdiv_1(unsigned int fin, 182 unsigned int fspi, unsigned int max, unsigned int *fres) 183 { 184 int i; 185 186 for (i = 2; i < max; i++) 187 if (fspi * mxc_clkdivs[i] >= fin) 188 break; 189 190 *fres = fin / mxc_clkdivs[i]; 191 return i; 192 } 193 194 /* MX1, MX31, MX35, MX51 CSPI */ 195 static unsigned int spi_imx_clkdiv_2(unsigned int fin, 196 unsigned int fspi, unsigned int *fres) 197 { 198 int i, div = 4; 199 200 for (i = 0; i < 7; i++) { 201 if (fspi * div >= fin) 202 goto out; 203 div <<= 1; 204 } 205 206 out: 207 *fres = fin / div; 208 return i; 209 } 210 211 static int spi_imx_bytes_per_word(const int bits_per_word) 212 { 213 if (bits_per_word <= 8) 214 return 1; 215 else if (bits_per_word <= 16) 216 return 2; 217 else 218 return 4; 219 } 220 221 static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, 222 struct spi_transfer *transfer) 223 { 224 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 225 226 if (!use_dma) 227 return false; 228 229 if (!master->dma_rx) 230 return false; 231 232 if (spi_imx->slave_mode) 233 return false; 234 235 if (transfer->len < spi_imx->devtype_data->fifo_size) 236 return false; 237 238 spi_imx->dynamic_burst = 0; 239 240 return true; 241 } 242 243 #define MX51_ECSPI_CTRL 0x08 244 #define MX51_ECSPI_CTRL_ENABLE (1 << 0) 245 #define MX51_ECSPI_CTRL_XCH (1 << 2) 246 #define MX51_ECSPI_CTRL_SMC (1 << 3) 247 #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4) 248 #define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16) 249 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8 250 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 251 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) 252 #define MX51_ECSPI_CTRL_BL_OFFSET 20 253 #define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20) 254 255 #define MX51_ECSPI_CONFIG 0x0c 256 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) 257 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) 258 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) 259 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) 260 #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20)) 261 262 #define MX51_ECSPI_INT 0x10 263 #define MX51_ECSPI_INT_TEEN (1 << 0) 264 #define MX51_ECSPI_INT_RREN (1 << 3) 265 #define MX51_ECSPI_INT_RDREN (1 << 4) 266 267 #define MX51_ECSPI_DMA 0x14 268 #define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f) 269 #define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16) 270 #define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24) 271 272 #define MX51_ECSPI_DMA_TEDEN (1 << 7) 273 #define MX51_ECSPI_DMA_RXDEN (1 << 23) 274 #define MX51_ECSPI_DMA_RXTDEN (1 << 31) 275 276 #define MX51_ECSPI_STAT 0x18 277 #define MX51_ECSPI_STAT_RR (1 << 3) 278 279 #define MX51_ECSPI_TESTREG 0x20 280 #define MX51_ECSPI_TESTREG_LBC BIT(31) 281 282 static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx) 283 { 284 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); 285 #ifdef __LITTLE_ENDIAN 286 unsigned int bytes_per_word; 287 #endif 288 289 if (spi_imx->rx_buf) { 290 #ifdef __LITTLE_ENDIAN 291 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); 292 if (bytes_per_word == 1) 293 val = cpu_to_be32(val); 294 else if (bytes_per_word == 2) 295 val = (val << 16) | (val >> 16); 296 #endif 297 *(u32 *)spi_imx->rx_buf = val; 298 spi_imx->rx_buf += sizeof(u32); 299 } 300 301 spi_imx->remainder -= sizeof(u32); 302 } 303 304 static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx) 305 { 306 int unaligned; 307 u32 val; 308 309 unaligned = spi_imx->remainder % 4; 310 311 if (!unaligned) { 312 spi_imx_buf_rx_swap_u32(spi_imx); 313 return; 314 } 315 316 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { 317 spi_imx_buf_rx_u16(spi_imx); 318 return; 319 } 320 321 val = readl(spi_imx->base + MXC_CSPIRXDATA); 322 323 while (unaligned--) { 324 if (spi_imx->rx_buf) { 325 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff; 326 spi_imx->rx_buf++; 327 } 328 spi_imx->remainder--; 329 } 330 } 331 332 static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx) 333 { 334 u32 val = 0; 335 #ifdef __LITTLE_ENDIAN 336 unsigned int bytes_per_word; 337 #endif 338 339 if (spi_imx->tx_buf) { 340 val = *(u32 *)spi_imx->tx_buf; 341 spi_imx->tx_buf += sizeof(u32); 342 } 343 344 spi_imx->count -= sizeof(u32); 345 #ifdef __LITTLE_ENDIAN 346 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); 347 348 if (bytes_per_word == 1) 349 val = cpu_to_be32(val); 350 else if (bytes_per_word == 2) 351 val = (val << 16) | (val >> 16); 352 #endif 353 writel(val, spi_imx->base + MXC_CSPITXDATA); 354 } 355 356 static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx) 357 { 358 int unaligned; 359 u32 val = 0; 360 361 unaligned = spi_imx->count % 4; 362 363 if (!unaligned) { 364 spi_imx_buf_tx_swap_u32(spi_imx); 365 return; 366 } 367 368 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { 369 spi_imx_buf_tx_u16(spi_imx); 370 return; 371 } 372 373 while (unaligned--) { 374 if (spi_imx->tx_buf) { 375 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned); 376 spi_imx->tx_buf++; 377 } 378 spi_imx->count--; 379 } 380 381 writel(val, spi_imx->base + MXC_CSPITXDATA); 382 } 383 384 static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx) 385 { 386 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA)); 387 388 if (spi_imx->rx_buf) { 389 int n_bytes = spi_imx->slave_burst % sizeof(val); 390 391 if (!n_bytes) 392 n_bytes = sizeof(val); 393 394 memcpy(spi_imx->rx_buf, 395 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes); 396 397 spi_imx->rx_buf += n_bytes; 398 spi_imx->slave_burst -= n_bytes; 399 } 400 401 spi_imx->remainder -= sizeof(u32); 402 } 403 404 static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx) 405 { 406 u32 val = 0; 407 int n_bytes = spi_imx->count % sizeof(val); 408 409 if (!n_bytes) 410 n_bytes = sizeof(val); 411 412 if (spi_imx->tx_buf) { 413 memcpy(((u8 *)&val) + sizeof(val) - n_bytes, 414 spi_imx->tx_buf, n_bytes); 415 val = cpu_to_be32(val); 416 spi_imx->tx_buf += n_bytes; 417 } 418 419 spi_imx->count -= n_bytes; 420 421 writel(val, spi_imx->base + MXC_CSPITXDATA); 422 } 423 424 /* MX51 eCSPI */ 425 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx, 426 unsigned int fspi, unsigned int *fres) 427 { 428 /* 429 * there are two 4-bit dividers, the pre-divider divides by 430 * $pre, the post-divider by 2^$post 431 */ 432 unsigned int pre, post; 433 unsigned int fin = spi_imx->spi_clk; 434 435 if (unlikely(fspi > fin)) 436 return 0; 437 438 post = fls(fin) - fls(fspi); 439 if (fin > fspi << post) 440 post++; 441 442 /* now we have: (fin <= fspi << post) with post being minimal */ 443 444 post = max(4U, post) - 4; 445 if (unlikely(post > 0xf)) { 446 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n", 447 fspi, fin); 448 return 0xff; 449 } 450 451 pre = DIV_ROUND_UP(fin, fspi << post) - 1; 452 453 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n", 454 __func__, fin, fspi, post, pre); 455 456 /* Resulting frequency for the SCLK line. */ 457 *fres = (fin / (pre + 1)) >> post; 458 459 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) | 460 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET); 461 } 462 463 static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable) 464 { 465 unsigned val = 0; 466 467 if (enable & MXC_INT_TE) 468 val |= MX51_ECSPI_INT_TEEN; 469 470 if (enable & MXC_INT_RR) 471 val |= MX51_ECSPI_INT_RREN; 472 473 if (enable & MXC_INT_RDR) 474 val |= MX51_ECSPI_INT_RDREN; 475 476 writel(val, spi_imx->base + MX51_ECSPI_INT); 477 } 478 479 static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx) 480 { 481 u32 reg; 482 483 reg = readl(spi_imx->base + MX51_ECSPI_CTRL); 484 reg |= MX51_ECSPI_CTRL_XCH; 485 writel(reg, spi_imx->base + MX51_ECSPI_CTRL); 486 } 487 488 static void mx51_ecspi_disable(struct spi_imx_data *spi_imx) 489 { 490 u32 ctrl; 491 492 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); 493 ctrl &= ~MX51_ECSPI_CTRL_ENABLE; 494 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 495 } 496 497 static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx, 498 struct spi_message *msg) 499 { 500 struct spi_device *spi = msg->spi; 501 u32 ctrl = MX51_ECSPI_CTRL_ENABLE; 502 u32 testreg; 503 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); 504 505 /* set Master or Slave mode */ 506 if (spi_imx->slave_mode) 507 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK; 508 else 509 ctrl |= MX51_ECSPI_CTRL_MODE_MASK; 510 511 /* 512 * Enable SPI_RDY handling (falling edge/level triggered). 513 */ 514 if (spi->mode & SPI_READY) 515 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl); 516 517 /* set chip select to use */ 518 ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select); 519 520 /* 521 * The ctrl register must be written first, with the EN bit set other 522 * registers must not be written to. 523 */ 524 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 525 526 testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG); 527 if (spi->mode & SPI_LOOP) 528 testreg |= MX51_ECSPI_TESTREG_LBC; 529 else 530 testreg &= ~MX51_ECSPI_TESTREG_LBC; 531 writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG); 532 533 /* 534 * eCSPI burst completion by Chip Select signal in Slave mode 535 * is not functional for imx53 Soc, config SPI burst completed when 536 * BURST_LENGTH + 1 bits are received 537 */ 538 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) 539 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); 540 else 541 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); 542 543 if (spi->mode & SPI_CPHA) 544 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); 545 else 546 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); 547 548 if (spi->mode & SPI_CPOL) { 549 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); 550 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); 551 } else { 552 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); 553 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); 554 } 555 556 if (spi->mode & SPI_CS_HIGH) 557 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); 558 else 559 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); 560 561 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); 562 563 return 0; 564 } 565 566 static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx, 567 struct spi_device *spi, 568 struct spi_transfer *t) 569 { 570 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); 571 u32 clk = t->speed_hz, delay; 572 573 /* Clear BL field and set the right value */ 574 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK; 575 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) 576 ctrl |= (spi_imx->slave_burst * 8 - 1) 577 << MX51_ECSPI_CTRL_BL_OFFSET; 578 else 579 ctrl |= (spi_imx->bits_per_word - 1) 580 << MX51_ECSPI_CTRL_BL_OFFSET; 581 582 /* set clock speed */ 583 ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET | 584 0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET); 585 ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk); 586 spi_imx->spi_bus_clk = clk; 587 588 if (spi_imx->usedma) 589 ctrl |= MX51_ECSPI_CTRL_SMC; 590 591 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 592 593 /* 594 * Wait until the changes in the configuration register CONFIGREG 595 * propagate into the hardware. It takes exactly one tick of the 596 * SCLK clock, but we will wait two SCLK clock just to be sure. The 597 * effect of the delay it takes for the hardware to apply changes 598 * is noticable if the SCLK clock run very slow. In such a case, if 599 * the polarity of SCLK should be inverted, the GPIO ChipSelect might 600 * be asserted before the SCLK polarity changes, which would disrupt 601 * the SPI communication as the device on the other end would consider 602 * the change of SCLK polarity as a clock tick already. 603 */ 604 delay = (2 * 1000000) / clk; 605 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */ 606 udelay(delay); 607 else /* SCLK is _very_ slow */ 608 usleep_range(delay, delay + 10); 609 610 return 0; 611 } 612 613 static void mx51_setup_wml(struct spi_imx_data *spi_imx) 614 { 615 /* 616 * Configure the DMA register: setup the watermark 617 * and enable DMA request. 618 */ 619 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) | 620 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) | 621 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) | 622 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN | 623 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA); 624 } 625 626 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx) 627 { 628 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; 629 } 630 631 static void mx51_ecspi_reset(struct spi_imx_data *spi_imx) 632 { 633 /* drain receive buffer */ 634 while (mx51_ecspi_rx_available(spi_imx)) 635 readl(spi_imx->base + MXC_CSPIRXDATA); 636 } 637 638 #define MX31_INTREG_TEEN (1 << 0) 639 #define MX31_INTREG_RREN (1 << 3) 640 641 #define MX31_CSPICTRL_ENABLE (1 << 0) 642 #define MX31_CSPICTRL_MASTER (1 << 1) 643 #define MX31_CSPICTRL_XCH (1 << 2) 644 #define MX31_CSPICTRL_SMC (1 << 3) 645 #define MX31_CSPICTRL_POL (1 << 4) 646 #define MX31_CSPICTRL_PHA (1 << 5) 647 #define MX31_CSPICTRL_SSCTL (1 << 6) 648 #define MX31_CSPICTRL_SSPOL (1 << 7) 649 #define MX31_CSPICTRL_BC_SHIFT 8 650 #define MX35_CSPICTRL_BL_SHIFT 20 651 #define MX31_CSPICTRL_CS_SHIFT 24 652 #define MX35_CSPICTRL_CS_SHIFT 12 653 #define MX31_CSPICTRL_DR_SHIFT 16 654 655 #define MX31_CSPI_DMAREG 0x10 656 #define MX31_DMAREG_RH_DEN (1<<4) 657 #define MX31_DMAREG_TH_DEN (1<<1) 658 659 #define MX31_CSPISTATUS 0x14 660 #define MX31_STATUS_RR (1 << 3) 661 662 #define MX31_CSPI_TESTREG 0x1C 663 #define MX31_TEST_LBC (1 << 14) 664 665 /* These functions also work for the i.MX35, but be aware that 666 * the i.MX35 has a slightly different register layout for bits 667 * we do not use here. 668 */ 669 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable) 670 { 671 unsigned int val = 0; 672 673 if (enable & MXC_INT_TE) 674 val |= MX31_INTREG_TEEN; 675 if (enable & MXC_INT_RR) 676 val |= MX31_INTREG_RREN; 677 678 writel(val, spi_imx->base + MXC_CSPIINT); 679 } 680 681 static void mx31_trigger(struct spi_imx_data *spi_imx) 682 { 683 unsigned int reg; 684 685 reg = readl(spi_imx->base + MXC_CSPICTRL); 686 reg |= MX31_CSPICTRL_XCH; 687 writel(reg, spi_imx->base + MXC_CSPICTRL); 688 } 689 690 static int mx31_prepare_message(struct spi_imx_data *spi_imx, 691 struct spi_message *msg) 692 { 693 return 0; 694 } 695 696 static int mx31_prepare_transfer(struct spi_imx_data *spi_imx, 697 struct spi_device *spi, 698 struct spi_transfer *t) 699 { 700 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; 701 unsigned int clk; 702 703 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, t->speed_hz, &clk) << 704 MX31_CSPICTRL_DR_SHIFT; 705 spi_imx->spi_bus_clk = clk; 706 707 if (is_imx35_cspi(spi_imx)) { 708 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT; 709 reg |= MX31_CSPICTRL_SSCTL; 710 } else { 711 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT; 712 } 713 714 if (spi->mode & SPI_CPHA) 715 reg |= MX31_CSPICTRL_PHA; 716 if (spi->mode & SPI_CPOL) 717 reg |= MX31_CSPICTRL_POL; 718 if (spi->mode & SPI_CS_HIGH) 719 reg |= MX31_CSPICTRL_SSPOL; 720 if (!gpio_is_valid(spi->cs_gpio)) 721 reg |= (spi->chip_select) << 722 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT : 723 MX31_CSPICTRL_CS_SHIFT); 724 725 if (spi_imx->usedma) 726 reg |= MX31_CSPICTRL_SMC; 727 728 writel(reg, spi_imx->base + MXC_CSPICTRL); 729 730 reg = readl(spi_imx->base + MX31_CSPI_TESTREG); 731 if (spi->mode & SPI_LOOP) 732 reg |= MX31_TEST_LBC; 733 else 734 reg &= ~MX31_TEST_LBC; 735 writel(reg, spi_imx->base + MX31_CSPI_TESTREG); 736 737 if (spi_imx->usedma) { 738 /* 739 * configure DMA requests when RXFIFO is half full and 740 * when TXFIFO is half empty 741 */ 742 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN, 743 spi_imx->base + MX31_CSPI_DMAREG); 744 } 745 746 return 0; 747 } 748 749 static int mx31_rx_available(struct spi_imx_data *spi_imx) 750 { 751 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; 752 } 753 754 static void mx31_reset(struct spi_imx_data *spi_imx) 755 { 756 /* drain receive buffer */ 757 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) 758 readl(spi_imx->base + MXC_CSPIRXDATA); 759 } 760 761 #define MX21_INTREG_RR (1 << 4) 762 #define MX21_INTREG_TEEN (1 << 9) 763 #define MX21_INTREG_RREN (1 << 13) 764 765 #define MX21_CSPICTRL_POL (1 << 5) 766 #define MX21_CSPICTRL_PHA (1 << 6) 767 #define MX21_CSPICTRL_SSPOL (1 << 8) 768 #define MX21_CSPICTRL_XCH (1 << 9) 769 #define MX21_CSPICTRL_ENABLE (1 << 10) 770 #define MX21_CSPICTRL_MASTER (1 << 11) 771 #define MX21_CSPICTRL_DR_SHIFT 14 772 #define MX21_CSPICTRL_CS_SHIFT 19 773 774 static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable) 775 { 776 unsigned int val = 0; 777 778 if (enable & MXC_INT_TE) 779 val |= MX21_INTREG_TEEN; 780 if (enable & MXC_INT_RR) 781 val |= MX21_INTREG_RREN; 782 783 writel(val, spi_imx->base + MXC_CSPIINT); 784 } 785 786 static void mx21_trigger(struct spi_imx_data *spi_imx) 787 { 788 unsigned int reg; 789 790 reg = readl(spi_imx->base + MXC_CSPICTRL); 791 reg |= MX21_CSPICTRL_XCH; 792 writel(reg, spi_imx->base + MXC_CSPICTRL); 793 } 794 795 static int mx21_prepare_message(struct spi_imx_data *spi_imx, 796 struct spi_message *msg) 797 { 798 return 0; 799 } 800 801 static int mx21_prepare_transfer(struct spi_imx_data *spi_imx, 802 struct spi_device *spi, 803 struct spi_transfer *t) 804 { 805 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER; 806 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18; 807 unsigned int clk; 808 809 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, t->speed_hz, max, &clk) 810 << MX21_CSPICTRL_DR_SHIFT; 811 spi_imx->spi_bus_clk = clk; 812 813 reg |= spi_imx->bits_per_word - 1; 814 815 if (spi->mode & SPI_CPHA) 816 reg |= MX21_CSPICTRL_PHA; 817 if (spi->mode & SPI_CPOL) 818 reg |= MX21_CSPICTRL_POL; 819 if (spi->mode & SPI_CS_HIGH) 820 reg |= MX21_CSPICTRL_SSPOL; 821 if (!gpio_is_valid(spi->cs_gpio)) 822 reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT; 823 824 writel(reg, spi_imx->base + MXC_CSPICTRL); 825 826 return 0; 827 } 828 829 static int mx21_rx_available(struct spi_imx_data *spi_imx) 830 { 831 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; 832 } 833 834 static void mx21_reset(struct spi_imx_data *spi_imx) 835 { 836 writel(1, spi_imx->base + MXC_RESET); 837 } 838 839 #define MX1_INTREG_RR (1 << 3) 840 #define MX1_INTREG_TEEN (1 << 8) 841 #define MX1_INTREG_RREN (1 << 11) 842 843 #define MX1_CSPICTRL_POL (1 << 4) 844 #define MX1_CSPICTRL_PHA (1 << 5) 845 #define MX1_CSPICTRL_XCH (1 << 8) 846 #define MX1_CSPICTRL_ENABLE (1 << 9) 847 #define MX1_CSPICTRL_MASTER (1 << 10) 848 #define MX1_CSPICTRL_DR_SHIFT 13 849 850 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable) 851 { 852 unsigned int val = 0; 853 854 if (enable & MXC_INT_TE) 855 val |= MX1_INTREG_TEEN; 856 if (enable & MXC_INT_RR) 857 val |= MX1_INTREG_RREN; 858 859 writel(val, spi_imx->base + MXC_CSPIINT); 860 } 861 862 static void mx1_trigger(struct spi_imx_data *spi_imx) 863 { 864 unsigned int reg; 865 866 reg = readl(spi_imx->base + MXC_CSPICTRL); 867 reg |= MX1_CSPICTRL_XCH; 868 writel(reg, spi_imx->base + MXC_CSPICTRL); 869 } 870 871 static int mx1_prepare_message(struct spi_imx_data *spi_imx, 872 struct spi_message *msg) 873 { 874 return 0; 875 } 876 877 static int mx1_prepare_transfer(struct spi_imx_data *spi_imx, 878 struct spi_device *spi, 879 struct spi_transfer *t) 880 { 881 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; 882 unsigned int clk; 883 884 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, t->speed_hz, &clk) << 885 MX1_CSPICTRL_DR_SHIFT; 886 spi_imx->spi_bus_clk = clk; 887 888 reg |= spi_imx->bits_per_word - 1; 889 890 if (spi->mode & SPI_CPHA) 891 reg |= MX1_CSPICTRL_PHA; 892 if (spi->mode & SPI_CPOL) 893 reg |= MX1_CSPICTRL_POL; 894 895 writel(reg, spi_imx->base + MXC_CSPICTRL); 896 897 return 0; 898 } 899 900 static int mx1_rx_available(struct spi_imx_data *spi_imx) 901 { 902 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; 903 } 904 905 static void mx1_reset(struct spi_imx_data *spi_imx) 906 { 907 writel(1, spi_imx->base + MXC_RESET); 908 } 909 910 static struct spi_imx_devtype_data imx1_cspi_devtype_data = { 911 .intctrl = mx1_intctrl, 912 .prepare_message = mx1_prepare_message, 913 .prepare_transfer = mx1_prepare_transfer, 914 .trigger = mx1_trigger, 915 .rx_available = mx1_rx_available, 916 .reset = mx1_reset, 917 .fifo_size = 8, 918 .has_dmamode = false, 919 .dynamic_burst = false, 920 .has_slavemode = false, 921 .devtype = IMX1_CSPI, 922 }; 923 924 static struct spi_imx_devtype_data imx21_cspi_devtype_data = { 925 .intctrl = mx21_intctrl, 926 .prepare_message = mx21_prepare_message, 927 .prepare_transfer = mx21_prepare_transfer, 928 .trigger = mx21_trigger, 929 .rx_available = mx21_rx_available, 930 .reset = mx21_reset, 931 .fifo_size = 8, 932 .has_dmamode = false, 933 .dynamic_burst = false, 934 .has_slavemode = false, 935 .devtype = IMX21_CSPI, 936 }; 937 938 static struct spi_imx_devtype_data imx27_cspi_devtype_data = { 939 /* i.mx27 cspi shares the functions with i.mx21 one */ 940 .intctrl = mx21_intctrl, 941 .prepare_message = mx21_prepare_message, 942 .prepare_transfer = mx21_prepare_transfer, 943 .trigger = mx21_trigger, 944 .rx_available = mx21_rx_available, 945 .reset = mx21_reset, 946 .fifo_size = 8, 947 .has_dmamode = false, 948 .dynamic_burst = false, 949 .has_slavemode = false, 950 .devtype = IMX27_CSPI, 951 }; 952 953 static struct spi_imx_devtype_data imx31_cspi_devtype_data = { 954 .intctrl = mx31_intctrl, 955 .prepare_message = mx31_prepare_message, 956 .prepare_transfer = mx31_prepare_transfer, 957 .trigger = mx31_trigger, 958 .rx_available = mx31_rx_available, 959 .reset = mx31_reset, 960 .fifo_size = 8, 961 .has_dmamode = false, 962 .dynamic_burst = false, 963 .has_slavemode = false, 964 .devtype = IMX31_CSPI, 965 }; 966 967 static struct spi_imx_devtype_data imx35_cspi_devtype_data = { 968 /* i.mx35 and later cspi shares the functions with i.mx31 one */ 969 .intctrl = mx31_intctrl, 970 .prepare_message = mx31_prepare_message, 971 .prepare_transfer = mx31_prepare_transfer, 972 .trigger = mx31_trigger, 973 .rx_available = mx31_rx_available, 974 .reset = mx31_reset, 975 .fifo_size = 8, 976 .has_dmamode = true, 977 .dynamic_burst = false, 978 .has_slavemode = false, 979 .devtype = IMX35_CSPI, 980 }; 981 982 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = { 983 .intctrl = mx51_ecspi_intctrl, 984 .prepare_message = mx51_ecspi_prepare_message, 985 .prepare_transfer = mx51_ecspi_prepare_transfer, 986 .trigger = mx51_ecspi_trigger, 987 .rx_available = mx51_ecspi_rx_available, 988 .reset = mx51_ecspi_reset, 989 .setup_wml = mx51_setup_wml, 990 .fifo_size = 64, 991 .has_dmamode = true, 992 .dynamic_burst = true, 993 .has_slavemode = true, 994 .disable = mx51_ecspi_disable, 995 .devtype = IMX51_ECSPI, 996 }; 997 998 static struct spi_imx_devtype_data imx53_ecspi_devtype_data = { 999 .intctrl = mx51_ecspi_intctrl, 1000 .prepare_message = mx51_ecspi_prepare_message, 1001 .prepare_transfer = mx51_ecspi_prepare_transfer, 1002 .trigger = mx51_ecspi_trigger, 1003 .rx_available = mx51_ecspi_rx_available, 1004 .reset = mx51_ecspi_reset, 1005 .fifo_size = 64, 1006 .has_dmamode = true, 1007 .has_slavemode = true, 1008 .disable = mx51_ecspi_disable, 1009 .devtype = IMX53_ECSPI, 1010 }; 1011 1012 static const struct platform_device_id spi_imx_devtype[] = { 1013 { 1014 .name = "imx1-cspi", 1015 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data, 1016 }, { 1017 .name = "imx21-cspi", 1018 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data, 1019 }, { 1020 .name = "imx27-cspi", 1021 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data, 1022 }, { 1023 .name = "imx31-cspi", 1024 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data, 1025 }, { 1026 .name = "imx35-cspi", 1027 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data, 1028 }, { 1029 .name = "imx51-ecspi", 1030 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data, 1031 }, { 1032 .name = "imx53-ecspi", 1033 .driver_data = (kernel_ulong_t) &imx53_ecspi_devtype_data, 1034 }, { 1035 /* sentinel */ 1036 } 1037 }; 1038 1039 static const struct of_device_id spi_imx_dt_ids[] = { 1040 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, }, 1041 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, }, 1042 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, }, 1043 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, }, 1044 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, }, 1045 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, }, 1046 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, }, 1047 { /* sentinel */ } 1048 }; 1049 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids); 1050 1051 static void spi_imx_chipselect(struct spi_device *spi, int is_active) 1052 { 1053 int active = is_active != BITBANG_CS_INACTIVE; 1054 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); 1055 1056 if (spi->mode & SPI_NO_CS) 1057 return; 1058 1059 if (!gpio_is_valid(spi->cs_gpio)) 1060 return; 1061 1062 gpio_set_value(spi->cs_gpio, dev_is_lowactive ^ active); 1063 } 1064 1065 static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits) 1066 { 1067 u32 ctrl; 1068 1069 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); 1070 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK; 1071 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET); 1072 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 1073 } 1074 1075 static void spi_imx_push(struct spi_imx_data *spi_imx) 1076 { 1077 unsigned int burst_len, fifo_words; 1078 1079 if (spi_imx->dynamic_burst) 1080 fifo_words = 4; 1081 else 1082 fifo_words = spi_imx_bytes_per_word(spi_imx->bits_per_word); 1083 /* 1084 * Reload the FIFO when the remaining bytes to be transferred in the 1085 * current burst is 0. This only applies when bits_per_word is a 1086 * multiple of 8. 1087 */ 1088 if (!spi_imx->remainder) { 1089 if (spi_imx->dynamic_burst) { 1090 1091 /* We need to deal unaligned data first */ 1092 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST; 1093 1094 if (!burst_len) 1095 burst_len = MX51_ECSPI_CTRL_MAX_BURST; 1096 1097 spi_imx_set_burst_len(spi_imx, burst_len * 8); 1098 1099 spi_imx->remainder = burst_len; 1100 } else { 1101 spi_imx->remainder = fifo_words; 1102 } 1103 } 1104 1105 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) { 1106 if (!spi_imx->count) 1107 break; 1108 if (spi_imx->dynamic_burst && 1109 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder, 1110 fifo_words)) 1111 break; 1112 spi_imx->tx(spi_imx); 1113 spi_imx->txfifo++; 1114 } 1115 1116 if (!spi_imx->slave_mode) 1117 spi_imx->devtype_data->trigger(spi_imx); 1118 } 1119 1120 static irqreturn_t spi_imx_isr(int irq, void *dev_id) 1121 { 1122 struct spi_imx_data *spi_imx = dev_id; 1123 1124 while (spi_imx->txfifo && 1125 spi_imx->devtype_data->rx_available(spi_imx)) { 1126 spi_imx->rx(spi_imx); 1127 spi_imx->txfifo--; 1128 } 1129 1130 if (spi_imx->count) { 1131 spi_imx_push(spi_imx); 1132 return IRQ_HANDLED; 1133 } 1134 1135 if (spi_imx->txfifo) { 1136 /* No data left to push, but still waiting for rx data, 1137 * enable receive data available interrupt. 1138 */ 1139 spi_imx->devtype_data->intctrl( 1140 spi_imx, MXC_INT_RR); 1141 return IRQ_HANDLED; 1142 } 1143 1144 spi_imx->devtype_data->intctrl(spi_imx, 0); 1145 complete(&spi_imx->xfer_done); 1146 1147 return IRQ_HANDLED; 1148 } 1149 1150 static int spi_imx_dma_configure(struct spi_master *master) 1151 { 1152 int ret; 1153 enum dma_slave_buswidth buswidth; 1154 struct dma_slave_config rx = {}, tx = {}; 1155 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1156 1157 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) { 1158 case 4: 1159 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES; 1160 break; 1161 case 2: 1162 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; 1163 break; 1164 case 1: 1165 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; 1166 break; 1167 default: 1168 return -EINVAL; 1169 } 1170 1171 tx.direction = DMA_MEM_TO_DEV; 1172 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA; 1173 tx.dst_addr_width = buswidth; 1174 tx.dst_maxburst = spi_imx->wml; 1175 ret = dmaengine_slave_config(master->dma_tx, &tx); 1176 if (ret) { 1177 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret); 1178 return ret; 1179 } 1180 1181 rx.direction = DMA_DEV_TO_MEM; 1182 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA; 1183 rx.src_addr_width = buswidth; 1184 rx.src_maxburst = spi_imx->wml; 1185 ret = dmaengine_slave_config(master->dma_rx, &rx); 1186 if (ret) { 1187 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret); 1188 return ret; 1189 } 1190 1191 return 0; 1192 } 1193 1194 static int spi_imx_setupxfer(struct spi_device *spi, 1195 struct spi_transfer *t) 1196 { 1197 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1198 1199 if (!t) 1200 return 0; 1201 1202 spi_imx->bits_per_word = t->bits_per_word; 1203 1204 /* 1205 * Initialize the functions for transfer. To transfer non byte-aligned 1206 * words, we have to use multiple word-size bursts, we can't use 1207 * dynamic_burst in that case. 1208 */ 1209 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode && 1210 (spi_imx->bits_per_word == 8 || 1211 spi_imx->bits_per_word == 16 || 1212 spi_imx->bits_per_word == 32)) { 1213 1214 spi_imx->rx = spi_imx_buf_rx_swap; 1215 spi_imx->tx = spi_imx_buf_tx_swap; 1216 spi_imx->dynamic_burst = 1; 1217 1218 } else { 1219 if (spi_imx->bits_per_word <= 8) { 1220 spi_imx->rx = spi_imx_buf_rx_u8; 1221 spi_imx->tx = spi_imx_buf_tx_u8; 1222 } else if (spi_imx->bits_per_word <= 16) { 1223 spi_imx->rx = spi_imx_buf_rx_u16; 1224 spi_imx->tx = spi_imx_buf_tx_u16; 1225 } else { 1226 spi_imx->rx = spi_imx_buf_rx_u32; 1227 spi_imx->tx = spi_imx_buf_tx_u32; 1228 } 1229 spi_imx->dynamic_burst = 0; 1230 } 1231 1232 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t)) 1233 spi_imx->usedma = 1; 1234 else 1235 spi_imx->usedma = 0; 1236 1237 if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) { 1238 spi_imx->rx = mx53_ecspi_rx_slave; 1239 spi_imx->tx = mx53_ecspi_tx_slave; 1240 spi_imx->slave_burst = t->len; 1241 } 1242 1243 spi_imx->devtype_data->prepare_transfer(spi_imx, spi, t); 1244 1245 return 0; 1246 } 1247 1248 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx) 1249 { 1250 struct spi_master *master = spi_imx->bitbang.master; 1251 1252 if (master->dma_rx) { 1253 dma_release_channel(master->dma_rx); 1254 master->dma_rx = NULL; 1255 } 1256 1257 if (master->dma_tx) { 1258 dma_release_channel(master->dma_tx); 1259 master->dma_tx = NULL; 1260 } 1261 } 1262 1263 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx, 1264 struct spi_master *master) 1265 { 1266 int ret; 1267 1268 /* use pio mode for i.mx6dl chip TKT238285 */ 1269 if (of_machine_is_compatible("fsl,imx6dl")) 1270 return 0; 1271 1272 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2; 1273 1274 /* Prepare for TX DMA: */ 1275 master->dma_tx = dma_request_chan(dev, "tx"); 1276 if (IS_ERR(master->dma_tx)) { 1277 ret = PTR_ERR(master->dma_tx); 1278 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret); 1279 master->dma_tx = NULL; 1280 goto err; 1281 } 1282 1283 /* Prepare for RX : */ 1284 master->dma_rx = dma_request_chan(dev, "rx"); 1285 if (IS_ERR(master->dma_rx)) { 1286 ret = PTR_ERR(master->dma_rx); 1287 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret); 1288 master->dma_rx = NULL; 1289 goto err; 1290 } 1291 1292 init_completion(&spi_imx->dma_rx_completion); 1293 init_completion(&spi_imx->dma_tx_completion); 1294 master->can_dma = spi_imx_can_dma; 1295 master->max_dma_len = MAX_SDMA_BD_BYTES; 1296 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX | 1297 SPI_MASTER_MUST_TX; 1298 1299 return 0; 1300 err: 1301 spi_imx_sdma_exit(spi_imx); 1302 return ret; 1303 } 1304 1305 static void spi_imx_dma_rx_callback(void *cookie) 1306 { 1307 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; 1308 1309 complete(&spi_imx->dma_rx_completion); 1310 } 1311 1312 static void spi_imx_dma_tx_callback(void *cookie) 1313 { 1314 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; 1315 1316 complete(&spi_imx->dma_tx_completion); 1317 } 1318 1319 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size) 1320 { 1321 unsigned long timeout = 0; 1322 1323 /* Time with actual data transfer and CS change delay related to HW */ 1324 timeout = (8 + 4) * size / spi_imx->spi_bus_clk; 1325 1326 /* Add extra second for scheduler related activities */ 1327 timeout += 1; 1328 1329 /* Double calculated timeout */ 1330 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC); 1331 } 1332 1333 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, 1334 struct spi_transfer *transfer) 1335 { 1336 struct dma_async_tx_descriptor *desc_tx, *desc_rx; 1337 unsigned long transfer_timeout; 1338 unsigned long timeout; 1339 struct spi_master *master = spi_imx->bitbang.master; 1340 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; 1341 struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents); 1342 unsigned int bytes_per_word, i; 1343 int ret; 1344 1345 /* Get the right burst length from the last sg to ensure no tail data */ 1346 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word); 1347 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) { 1348 if (!(sg_dma_len(last_sg) % (i * bytes_per_word))) 1349 break; 1350 } 1351 /* Use 1 as wml in case no available burst length got */ 1352 if (i == 0) 1353 i = 1; 1354 1355 spi_imx->wml = i; 1356 1357 ret = spi_imx_dma_configure(master); 1358 if (ret) 1359 return ret; 1360 1361 if (!spi_imx->devtype_data->setup_wml) { 1362 dev_err(spi_imx->dev, "No setup_wml()?\n"); 1363 return -EINVAL; 1364 } 1365 spi_imx->devtype_data->setup_wml(spi_imx); 1366 1367 /* 1368 * The TX DMA setup starts the transfer, so make sure RX is configured 1369 * before TX. 1370 */ 1371 desc_rx = dmaengine_prep_slave_sg(master->dma_rx, 1372 rx->sgl, rx->nents, DMA_DEV_TO_MEM, 1373 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1374 if (!desc_rx) 1375 return -EINVAL; 1376 1377 desc_rx->callback = spi_imx_dma_rx_callback; 1378 desc_rx->callback_param = (void *)spi_imx; 1379 dmaengine_submit(desc_rx); 1380 reinit_completion(&spi_imx->dma_rx_completion); 1381 dma_async_issue_pending(master->dma_rx); 1382 1383 desc_tx = dmaengine_prep_slave_sg(master->dma_tx, 1384 tx->sgl, tx->nents, DMA_MEM_TO_DEV, 1385 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1386 if (!desc_tx) { 1387 dmaengine_terminate_all(master->dma_tx); 1388 return -EINVAL; 1389 } 1390 1391 desc_tx->callback = spi_imx_dma_tx_callback; 1392 desc_tx->callback_param = (void *)spi_imx; 1393 dmaengine_submit(desc_tx); 1394 reinit_completion(&spi_imx->dma_tx_completion); 1395 dma_async_issue_pending(master->dma_tx); 1396 1397 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); 1398 1399 /* Wait SDMA to finish the data transfer.*/ 1400 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion, 1401 transfer_timeout); 1402 if (!timeout) { 1403 dev_err(spi_imx->dev, "I/O Error in DMA TX\n"); 1404 dmaengine_terminate_all(master->dma_tx); 1405 dmaengine_terminate_all(master->dma_rx); 1406 return -ETIMEDOUT; 1407 } 1408 1409 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion, 1410 transfer_timeout); 1411 if (!timeout) { 1412 dev_err(&master->dev, "I/O Error in DMA RX\n"); 1413 spi_imx->devtype_data->reset(spi_imx); 1414 dmaengine_terminate_all(master->dma_rx); 1415 return -ETIMEDOUT; 1416 } 1417 1418 return transfer->len; 1419 } 1420 1421 static int spi_imx_pio_transfer(struct spi_device *spi, 1422 struct spi_transfer *transfer) 1423 { 1424 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1425 unsigned long transfer_timeout; 1426 unsigned long timeout; 1427 1428 spi_imx->tx_buf = transfer->tx_buf; 1429 spi_imx->rx_buf = transfer->rx_buf; 1430 spi_imx->count = transfer->len; 1431 spi_imx->txfifo = 0; 1432 spi_imx->remainder = 0; 1433 1434 reinit_completion(&spi_imx->xfer_done); 1435 1436 spi_imx_push(spi_imx); 1437 1438 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); 1439 1440 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); 1441 1442 timeout = wait_for_completion_timeout(&spi_imx->xfer_done, 1443 transfer_timeout); 1444 if (!timeout) { 1445 dev_err(&spi->dev, "I/O Error in PIO\n"); 1446 spi_imx->devtype_data->reset(spi_imx); 1447 return -ETIMEDOUT; 1448 } 1449 1450 return transfer->len; 1451 } 1452 1453 static int spi_imx_pio_transfer_slave(struct spi_device *spi, 1454 struct spi_transfer *transfer) 1455 { 1456 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1457 int ret = transfer->len; 1458 1459 if (is_imx53_ecspi(spi_imx) && 1460 transfer->len > MX53_MAX_TRANSFER_BYTES) { 1461 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n", 1462 MX53_MAX_TRANSFER_BYTES); 1463 return -EMSGSIZE; 1464 } 1465 1466 spi_imx->tx_buf = transfer->tx_buf; 1467 spi_imx->rx_buf = transfer->rx_buf; 1468 spi_imx->count = transfer->len; 1469 spi_imx->txfifo = 0; 1470 spi_imx->remainder = 0; 1471 1472 reinit_completion(&spi_imx->xfer_done); 1473 spi_imx->slave_aborted = false; 1474 1475 spi_imx_push(spi_imx); 1476 1477 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR); 1478 1479 if (wait_for_completion_interruptible(&spi_imx->xfer_done) || 1480 spi_imx->slave_aborted) { 1481 dev_dbg(&spi->dev, "interrupted\n"); 1482 ret = -EINTR; 1483 } 1484 1485 /* ecspi has a HW issue when works in Slave mode, 1486 * after 64 words writtern to TXFIFO, even TXFIFO becomes empty, 1487 * ECSPI_TXDATA keeps shift out the last word data, 1488 * so we have to disable ECSPI when in slave mode after the 1489 * transfer completes 1490 */ 1491 if (spi_imx->devtype_data->disable) 1492 spi_imx->devtype_data->disable(spi_imx); 1493 1494 return ret; 1495 } 1496 1497 static int spi_imx_transfer(struct spi_device *spi, 1498 struct spi_transfer *transfer) 1499 { 1500 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1501 1502 /* flush rxfifo before transfer */ 1503 while (spi_imx->devtype_data->rx_available(spi_imx)) 1504 readl(spi_imx->base + MXC_CSPIRXDATA); 1505 1506 if (spi_imx->slave_mode) 1507 return spi_imx_pio_transfer_slave(spi, transfer); 1508 1509 if (spi_imx->usedma) 1510 return spi_imx_dma_transfer(spi_imx, transfer); 1511 else 1512 return spi_imx_pio_transfer(spi, transfer); 1513 } 1514 1515 static int spi_imx_setup(struct spi_device *spi) 1516 { 1517 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, 1518 spi->mode, spi->bits_per_word, spi->max_speed_hz); 1519 1520 if (spi->mode & SPI_NO_CS) 1521 return 0; 1522 1523 if (gpio_is_valid(spi->cs_gpio)) 1524 gpio_direction_output(spi->cs_gpio, 1525 spi->mode & SPI_CS_HIGH ? 0 : 1); 1526 1527 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE); 1528 1529 return 0; 1530 } 1531 1532 static void spi_imx_cleanup(struct spi_device *spi) 1533 { 1534 } 1535 1536 static int 1537 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg) 1538 { 1539 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1540 int ret; 1541 1542 ret = clk_enable(spi_imx->clk_per); 1543 if (ret) 1544 return ret; 1545 1546 ret = clk_enable(spi_imx->clk_ipg); 1547 if (ret) { 1548 clk_disable(spi_imx->clk_per); 1549 return ret; 1550 } 1551 1552 ret = spi_imx->devtype_data->prepare_message(spi_imx, msg); 1553 if (ret) { 1554 clk_disable(spi_imx->clk_ipg); 1555 clk_disable(spi_imx->clk_per); 1556 } 1557 1558 return ret; 1559 } 1560 1561 static int 1562 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg) 1563 { 1564 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1565 1566 clk_disable(spi_imx->clk_ipg); 1567 clk_disable(spi_imx->clk_per); 1568 return 0; 1569 } 1570 1571 static int spi_imx_slave_abort(struct spi_master *master) 1572 { 1573 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1574 1575 spi_imx->slave_aborted = true; 1576 complete(&spi_imx->xfer_done); 1577 1578 return 0; 1579 } 1580 1581 static int spi_imx_probe(struct platform_device *pdev) 1582 { 1583 struct device_node *np = pdev->dev.of_node; 1584 const struct of_device_id *of_id = 1585 of_match_device(spi_imx_dt_ids, &pdev->dev); 1586 struct spi_imx_master *mxc_platform_info = 1587 dev_get_platdata(&pdev->dev); 1588 struct spi_master *master; 1589 struct spi_imx_data *spi_imx; 1590 struct resource *res; 1591 int i, ret, irq, spi_drctl; 1592 const struct spi_imx_devtype_data *devtype_data = of_id ? of_id->data : 1593 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data; 1594 bool slave_mode; 1595 1596 if (!np && !mxc_platform_info) { 1597 dev_err(&pdev->dev, "can't get the platform data\n"); 1598 return -EINVAL; 1599 } 1600 1601 slave_mode = devtype_data->has_slavemode && 1602 of_property_read_bool(np, "spi-slave"); 1603 if (slave_mode) 1604 master = spi_alloc_slave(&pdev->dev, 1605 sizeof(struct spi_imx_data)); 1606 else 1607 master = spi_alloc_master(&pdev->dev, 1608 sizeof(struct spi_imx_data)); 1609 if (!master) 1610 return -ENOMEM; 1611 1612 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl); 1613 if ((ret < 0) || (spi_drctl >= 0x3)) { 1614 /* '11' is reserved */ 1615 spi_drctl = 0; 1616 } 1617 1618 platform_set_drvdata(pdev, master); 1619 1620 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); 1621 master->bus_num = np ? -1 : pdev->id; 1622 1623 spi_imx = spi_master_get_devdata(master); 1624 spi_imx->bitbang.master = master; 1625 spi_imx->dev = &pdev->dev; 1626 spi_imx->slave_mode = slave_mode; 1627 1628 spi_imx->devtype_data = devtype_data; 1629 1630 /* Get number of chip selects, either platform data or OF */ 1631 if (mxc_platform_info) { 1632 master->num_chipselect = mxc_platform_info->num_chipselect; 1633 if (mxc_platform_info->chipselect) { 1634 master->cs_gpios = devm_kcalloc(&master->dev, 1635 master->num_chipselect, sizeof(int), 1636 GFP_KERNEL); 1637 if (!master->cs_gpios) 1638 return -ENOMEM; 1639 1640 for (i = 0; i < master->num_chipselect; i++) 1641 master->cs_gpios[i] = mxc_platform_info->chipselect[i]; 1642 } 1643 } else { 1644 u32 num_cs; 1645 1646 if (!of_property_read_u32(np, "num-cs", &num_cs)) 1647 master->num_chipselect = num_cs; 1648 /* If not preset, default value of 1 is used */ 1649 } 1650 1651 spi_imx->bitbang.chipselect = spi_imx_chipselect; 1652 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer; 1653 spi_imx->bitbang.txrx_bufs = spi_imx_transfer; 1654 spi_imx->bitbang.master->setup = spi_imx_setup; 1655 spi_imx->bitbang.master->cleanup = spi_imx_cleanup; 1656 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message; 1657 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message; 1658 spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort; 1659 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ 1660 | SPI_NO_CS; 1661 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) || 1662 is_imx53_ecspi(spi_imx)) 1663 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY; 1664 1665 spi_imx->spi_drctl = spi_drctl; 1666 1667 init_completion(&spi_imx->xfer_done); 1668 1669 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1670 spi_imx->base = devm_ioremap_resource(&pdev->dev, res); 1671 if (IS_ERR(spi_imx->base)) { 1672 ret = PTR_ERR(spi_imx->base); 1673 goto out_master_put; 1674 } 1675 spi_imx->base_phys = res->start; 1676 1677 irq = platform_get_irq(pdev, 0); 1678 if (irq < 0) { 1679 ret = irq; 1680 goto out_master_put; 1681 } 1682 1683 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0, 1684 dev_name(&pdev->dev), spi_imx); 1685 if (ret) { 1686 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); 1687 goto out_master_put; 1688 } 1689 1690 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1691 if (IS_ERR(spi_imx->clk_ipg)) { 1692 ret = PTR_ERR(spi_imx->clk_ipg); 1693 goto out_master_put; 1694 } 1695 1696 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); 1697 if (IS_ERR(spi_imx->clk_per)) { 1698 ret = PTR_ERR(spi_imx->clk_per); 1699 goto out_master_put; 1700 } 1701 1702 ret = clk_prepare_enable(spi_imx->clk_per); 1703 if (ret) 1704 goto out_master_put; 1705 1706 ret = clk_prepare_enable(spi_imx->clk_ipg); 1707 if (ret) 1708 goto out_put_per; 1709 1710 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); 1711 /* 1712 * Only validated on i.mx35 and i.mx6 now, can remove the constraint 1713 * if validated on other chips. 1714 */ 1715 if (spi_imx->devtype_data->has_dmamode) { 1716 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master); 1717 if (ret == -EPROBE_DEFER) 1718 goto out_clk_put; 1719 1720 if (ret < 0) 1721 dev_err(&pdev->dev, "dma setup error %d, use pio\n", 1722 ret); 1723 } 1724 1725 spi_imx->devtype_data->reset(spi_imx); 1726 1727 spi_imx->devtype_data->intctrl(spi_imx, 0); 1728 1729 master->dev.of_node = pdev->dev.of_node; 1730 ret = spi_bitbang_start(&spi_imx->bitbang); 1731 if (ret) { 1732 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret); 1733 goto out_clk_put; 1734 } 1735 1736 /* Request GPIO CS lines, if any */ 1737 if (!spi_imx->slave_mode && master->cs_gpios) { 1738 for (i = 0; i < master->num_chipselect; i++) { 1739 if (!gpio_is_valid(master->cs_gpios[i])) 1740 continue; 1741 1742 ret = devm_gpio_request(&pdev->dev, 1743 master->cs_gpios[i], 1744 DRIVER_NAME); 1745 if (ret) { 1746 dev_err(&pdev->dev, "Can't get CS GPIO %i\n", 1747 master->cs_gpios[i]); 1748 goto out_spi_bitbang; 1749 } 1750 } 1751 } 1752 1753 dev_info(&pdev->dev, "probed\n"); 1754 1755 clk_disable(spi_imx->clk_ipg); 1756 clk_disable(spi_imx->clk_per); 1757 return ret; 1758 1759 out_spi_bitbang: 1760 spi_bitbang_stop(&spi_imx->bitbang); 1761 out_clk_put: 1762 clk_disable_unprepare(spi_imx->clk_ipg); 1763 out_put_per: 1764 clk_disable_unprepare(spi_imx->clk_per); 1765 out_master_put: 1766 spi_master_put(master); 1767 1768 return ret; 1769 } 1770 1771 static int spi_imx_remove(struct platform_device *pdev) 1772 { 1773 struct spi_master *master = platform_get_drvdata(pdev); 1774 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1775 int ret; 1776 1777 spi_bitbang_stop(&spi_imx->bitbang); 1778 1779 ret = clk_enable(spi_imx->clk_per); 1780 if (ret) 1781 return ret; 1782 1783 ret = clk_enable(spi_imx->clk_ipg); 1784 if (ret) { 1785 clk_disable(spi_imx->clk_per); 1786 return ret; 1787 } 1788 1789 writel(0, spi_imx->base + MXC_CSPICTRL); 1790 clk_disable_unprepare(spi_imx->clk_ipg); 1791 clk_disable_unprepare(spi_imx->clk_per); 1792 spi_imx_sdma_exit(spi_imx); 1793 spi_master_put(master); 1794 1795 return 0; 1796 } 1797 1798 static struct platform_driver spi_imx_driver = { 1799 .driver = { 1800 .name = DRIVER_NAME, 1801 .of_match_table = spi_imx_dt_ids, 1802 }, 1803 .id_table = spi_imx_devtype, 1804 .probe = spi_imx_probe, 1805 .remove = spi_imx_remove, 1806 }; 1807 module_platform_driver(spi_imx_driver); 1808 1809 MODULE_DESCRIPTION("SPI Controller driver"); 1810 MODULE_AUTHOR("Sascha Hauer, Pengutronix"); 1811 MODULE_LICENSE("GPL"); 1812 MODULE_ALIAS("platform:" DRIVER_NAME); 1813