1 // SPDX-License-Identifier: GPL-2.0+ 2 3 /* 4 * NXP FlexSPI(FSPI) controller driver. 5 * 6 * Copyright 2019-2020 NXP 7 * Copyright 2020 Puresoftware Ltd. 8 * 9 * FlexSPI is a flexsible SPI host controller which supports two SPI 10 * channels and up to 4 external devices. Each channel supports 11 * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional 12 * data lines). 13 * 14 * FlexSPI controller is driven by the LUT(Look-up Table) registers 15 * LUT registers are a look-up-table for sequences of instructions. 16 * A valid sequence consists of four LUT registers. 17 * Maximum 32 LUT sequences can be programmed simultaneously. 18 * 19 * LUTs are being created at run-time based on the commands passed 20 * from the spi-mem framework, thus using single LUT index. 21 * 22 * Software triggered Flash read/write access by IP Bus. 23 * 24 * Memory mapped read access by AHB Bus. 25 * 26 * Based on SPI MEM interface and spi-fsl-qspi.c driver. 27 * 28 * Author: 29 * Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> 30 * Boris Brezillon <bbrezillon@kernel.org> 31 * Frieder Schrempf <frieder.schrempf@kontron.de> 32 */ 33 34 #include <linux/acpi.h> 35 #include <linux/bitops.h> 36 #include <linux/bitfield.h> 37 #include <linux/clk.h> 38 #include <linux/completion.h> 39 #include <linux/delay.h> 40 #include <linux/err.h> 41 #include <linux/errno.h> 42 #include <linux/interrupt.h> 43 #include <linux/io.h> 44 #include <linux/iopoll.h> 45 #include <linux/jiffies.h> 46 #include <linux/kernel.h> 47 #include <linux/module.h> 48 #include <linux/mutex.h> 49 #include <linux/of.h> 50 #include <linux/of_device.h> 51 #include <linux/platform_device.h> 52 #include <linux/pm_qos.h> 53 #include <linux/regmap.h> 54 #include <linux/sizes.h> 55 #include <linux/sys_soc.h> 56 57 #include <linux/mfd/syscon.h> 58 #include <linux/spi/spi.h> 59 #include <linux/spi/spi-mem.h> 60 61 /* 62 * The driver only uses one single LUT entry, that is updated on 63 * each call of exec_op(). Index 0 is preset at boot with a basic 64 * read operation, so let's use the last entry (31). 65 */ 66 #define SEQID_LUT 31 67 68 /* Registers used by the driver */ 69 #define FSPI_MCR0 0x00 70 #define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24) 71 #define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16) 72 #define FSPI_MCR0_LEARN_EN BIT(15) 73 #define FSPI_MCR0_SCRFRUN_EN BIT(14) 74 #define FSPI_MCR0_OCTCOMB_EN BIT(13) 75 #define FSPI_MCR0_DOZE_EN BIT(12) 76 #define FSPI_MCR0_HSEN BIT(11) 77 #define FSPI_MCR0_SERCLKDIV BIT(8) 78 #define FSPI_MCR0_ATDF_EN BIT(7) 79 #define FSPI_MCR0_ARDF_EN BIT(6) 80 #define FSPI_MCR0_RXCLKSRC(x) ((x) << 4) 81 #define FSPI_MCR0_END_CFG(x) ((x) << 2) 82 #define FSPI_MCR0_MDIS BIT(1) 83 #define FSPI_MCR0_SWRST BIT(0) 84 85 #define FSPI_MCR1 0x04 86 #define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16) 87 #define FSPI_MCR1_AHB_TIMEOUT(x) (x) 88 89 #define FSPI_MCR2 0x08 90 #define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24) 91 #define FSPI_MCR2_SAMEDEVICEEN BIT(15) 92 #define FSPI_MCR2_CLRLRPHS BIT(14) 93 #define FSPI_MCR2_ABRDATSZ BIT(8) 94 #define FSPI_MCR2_ABRLEARN BIT(7) 95 #define FSPI_MCR2_ABR_READ BIT(6) 96 #define FSPI_MCR2_ABRWRITE BIT(5) 97 #define FSPI_MCR2_ABRDUMMY BIT(4) 98 #define FSPI_MCR2_ABR_MODE BIT(3) 99 #define FSPI_MCR2_ABRCADDR BIT(2) 100 #define FSPI_MCR2_ABRRADDR BIT(1) 101 #define FSPI_MCR2_ABR_CMD BIT(0) 102 103 #define FSPI_AHBCR 0x0c 104 #define FSPI_AHBCR_RDADDROPT BIT(6) 105 #define FSPI_AHBCR_PREF_EN BIT(5) 106 #define FSPI_AHBCR_BUFF_EN BIT(4) 107 #define FSPI_AHBCR_CACH_EN BIT(3) 108 #define FSPI_AHBCR_CLRTXBUF BIT(2) 109 #define FSPI_AHBCR_CLRRXBUF BIT(1) 110 #define FSPI_AHBCR_PAR_EN BIT(0) 111 112 #define FSPI_INTEN 0x10 113 #define FSPI_INTEN_SCLKSBWR BIT(9) 114 #define FSPI_INTEN_SCLKSBRD BIT(8) 115 #define FSPI_INTEN_DATALRNFL BIT(7) 116 #define FSPI_INTEN_IPTXWE BIT(6) 117 #define FSPI_INTEN_IPRXWA BIT(5) 118 #define FSPI_INTEN_AHBCMDERR BIT(4) 119 #define FSPI_INTEN_IPCMDERR BIT(3) 120 #define FSPI_INTEN_AHBCMDGE BIT(2) 121 #define FSPI_INTEN_IPCMDGE BIT(1) 122 #define FSPI_INTEN_IPCMDDONE BIT(0) 123 124 #define FSPI_INTR 0x14 125 #define FSPI_INTR_SCLKSBWR BIT(9) 126 #define FSPI_INTR_SCLKSBRD BIT(8) 127 #define FSPI_INTR_DATALRNFL BIT(7) 128 #define FSPI_INTR_IPTXWE BIT(6) 129 #define FSPI_INTR_IPRXWA BIT(5) 130 #define FSPI_INTR_AHBCMDERR BIT(4) 131 #define FSPI_INTR_IPCMDERR BIT(3) 132 #define FSPI_INTR_AHBCMDGE BIT(2) 133 #define FSPI_INTR_IPCMDGE BIT(1) 134 #define FSPI_INTR_IPCMDDONE BIT(0) 135 136 #define FSPI_LUTKEY 0x18 137 #define FSPI_LUTKEY_VALUE 0x5AF05AF0 138 139 #define FSPI_LCKCR 0x1C 140 141 #define FSPI_LCKER_LOCK 0x1 142 #define FSPI_LCKER_UNLOCK 0x2 143 144 #define FSPI_BUFXCR_INVALID_MSTRID 0xE 145 #define FSPI_AHBRX_BUF0CR0 0x20 146 #define FSPI_AHBRX_BUF1CR0 0x24 147 #define FSPI_AHBRX_BUF2CR0 0x28 148 #define FSPI_AHBRX_BUF3CR0 0x2C 149 #define FSPI_AHBRX_BUF4CR0 0x30 150 #define FSPI_AHBRX_BUF5CR0 0x34 151 #define FSPI_AHBRX_BUF6CR0 0x38 152 #define FSPI_AHBRX_BUF7CR0 0x3C 153 #define FSPI_AHBRXBUF0CR7_PREF BIT(31) 154 155 #define FSPI_AHBRX_BUF0CR1 0x40 156 #define FSPI_AHBRX_BUF1CR1 0x44 157 #define FSPI_AHBRX_BUF2CR1 0x48 158 #define FSPI_AHBRX_BUF3CR1 0x4C 159 #define FSPI_AHBRX_BUF4CR1 0x50 160 #define FSPI_AHBRX_BUF5CR1 0x54 161 #define FSPI_AHBRX_BUF6CR1 0x58 162 #define FSPI_AHBRX_BUF7CR1 0x5C 163 164 #define FSPI_FLSHA1CR0 0x60 165 #define FSPI_FLSHA2CR0 0x64 166 #define FSPI_FLSHB1CR0 0x68 167 #define FSPI_FLSHB2CR0 0x6C 168 #define FSPI_FLSHXCR0_SZ_KB 10 169 #define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB) 170 171 #define FSPI_FLSHA1CR1 0x70 172 #define FSPI_FLSHA2CR1 0x74 173 #define FSPI_FLSHB1CR1 0x78 174 #define FSPI_FLSHB2CR1 0x7C 175 #define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16) 176 #define FSPI_FLSHXCR1_CAS(x) ((x) << 11) 177 #define FSPI_FLSHXCR1_WA BIT(10) 178 #define FSPI_FLSHXCR1_TCSH(x) ((x) << 5) 179 #define FSPI_FLSHXCR1_TCSS(x) (x) 180 181 #define FSPI_FLSHA1CR2 0x80 182 #define FSPI_FLSHA2CR2 0x84 183 #define FSPI_FLSHB1CR2 0x88 184 #define FSPI_FLSHB2CR2 0x8C 185 #define FSPI_FLSHXCR2_CLRINSP BIT(24) 186 #define FSPI_FLSHXCR2_AWRWAIT BIT(16) 187 #define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13 188 #define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8 189 #define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5 190 #define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0 191 192 #define FSPI_IPCR0 0xA0 193 194 #define FSPI_IPCR1 0xA4 195 #define FSPI_IPCR1_IPAREN BIT(31) 196 #define FSPI_IPCR1_SEQNUM_SHIFT 24 197 #define FSPI_IPCR1_SEQID_SHIFT 16 198 #define FSPI_IPCR1_IDATSZ(x) (x) 199 200 #define FSPI_IPCMD 0xB0 201 #define FSPI_IPCMD_TRG BIT(0) 202 203 #define FSPI_DLPR 0xB4 204 205 #define FSPI_IPRXFCR 0xB8 206 #define FSPI_IPRXFCR_CLR BIT(0) 207 #define FSPI_IPRXFCR_DMA_EN BIT(1) 208 #define FSPI_IPRXFCR_WMRK(x) ((x) << 2) 209 210 #define FSPI_IPTXFCR 0xBC 211 #define FSPI_IPTXFCR_CLR BIT(0) 212 #define FSPI_IPTXFCR_DMA_EN BIT(1) 213 #define FSPI_IPTXFCR_WMRK(x) ((x) << 2) 214 215 #define FSPI_DLLACR 0xC0 216 #define FSPI_DLLACR_OVRDEN BIT(8) 217 218 #define FSPI_DLLBCR 0xC4 219 #define FSPI_DLLBCR_OVRDEN BIT(8) 220 221 #define FSPI_STS0 0xE0 222 #define FSPI_STS0_DLPHB(x) ((x) << 8) 223 #define FSPI_STS0_DLPHA(x) ((x) << 4) 224 #define FSPI_STS0_CMD_SRC(x) ((x) << 2) 225 #define FSPI_STS0_ARB_IDLE BIT(1) 226 #define FSPI_STS0_SEQ_IDLE BIT(0) 227 228 #define FSPI_STS1 0xE4 229 #define FSPI_STS1_IP_ERRCD(x) ((x) << 24) 230 #define FSPI_STS1_IP_ERRID(x) ((x) << 16) 231 #define FSPI_STS1_AHB_ERRCD(x) ((x) << 8) 232 #define FSPI_STS1_AHB_ERRID(x) (x) 233 234 #define FSPI_AHBSPNST 0xEC 235 #define FSPI_AHBSPNST_DATLFT(x) ((x) << 16) 236 #define FSPI_AHBSPNST_BUFID(x) ((x) << 1) 237 #define FSPI_AHBSPNST_ACTIVE BIT(0) 238 239 #define FSPI_IPRXFSTS 0xF0 240 #define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16) 241 #define FSPI_IPRXFSTS_FILL(x) (x) 242 243 #define FSPI_IPTXFSTS 0xF4 244 #define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16) 245 #define FSPI_IPTXFSTS_FILL(x) (x) 246 247 #define FSPI_RFDR 0x100 248 #define FSPI_TFDR 0x180 249 250 #define FSPI_LUT_BASE 0x200 251 #define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4) 252 #define FSPI_LUT_REG(idx) \ 253 (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4) 254 255 /* register map end */ 256 257 /* Instruction set for the LUT register. */ 258 #define LUT_STOP 0x00 259 #define LUT_CMD 0x01 260 #define LUT_ADDR 0x02 261 #define LUT_CADDR_SDR 0x03 262 #define LUT_MODE 0x04 263 #define LUT_MODE2 0x05 264 #define LUT_MODE4 0x06 265 #define LUT_MODE8 0x07 266 #define LUT_NXP_WRITE 0x08 267 #define LUT_NXP_READ 0x09 268 #define LUT_LEARN_SDR 0x0A 269 #define LUT_DATSZ_SDR 0x0B 270 #define LUT_DUMMY 0x0C 271 #define LUT_DUMMY_RWDS_SDR 0x0D 272 #define LUT_JMP_ON_CS 0x1F 273 #define LUT_CMD_DDR 0x21 274 #define LUT_ADDR_DDR 0x22 275 #define LUT_CADDR_DDR 0x23 276 #define LUT_MODE_DDR 0x24 277 #define LUT_MODE2_DDR 0x25 278 #define LUT_MODE4_DDR 0x26 279 #define LUT_MODE8_DDR 0x27 280 #define LUT_WRITE_DDR 0x28 281 #define LUT_READ_DDR 0x29 282 #define LUT_LEARN_DDR 0x2A 283 #define LUT_DATSZ_DDR 0x2B 284 #define LUT_DUMMY_DDR 0x2C 285 #define LUT_DUMMY_RWDS_DDR 0x2D 286 287 /* 288 * Calculate number of required PAD bits for LUT register. 289 * 290 * The pad stands for the number of IO lines [0:7]. 291 * For example, the octal read needs eight IO lines, 292 * so you should use LUT_PAD(8). This macro 293 * returns 3 i.e. use eight (2^3) IP lines for read. 294 */ 295 #define LUT_PAD(x) (fls(x) - 1) 296 297 /* 298 * Macro for constructing the LUT entries with the following 299 * register layout: 300 * 301 * --------------------------------------------------- 302 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | 303 * --------------------------------------------------- 304 */ 305 #define PAD_SHIFT 8 306 #define INSTR_SHIFT 10 307 #define OPRND_SHIFT 16 308 309 /* Macros for constructing the LUT register. */ 310 #define LUT_DEF(idx, ins, pad, opr) \ 311 ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \ 312 (opr)) << (((idx) % 2) * OPRND_SHIFT)) 313 314 #define POLL_TOUT 5000 315 #define NXP_FSPI_MAX_CHIPSELECT 4 316 #define NXP_FSPI_MIN_IOMAP SZ_4M 317 318 #define DCFG_RCWSR1 0x100 319 #define SYS_PLL_RAT GENMASK(6, 2) 320 321 /* Access flash memory using IP bus only */ 322 #define FSPI_QUIRK_USE_IP_ONLY BIT(0) 323 324 struct nxp_fspi_devtype_data { 325 unsigned int rxfifo; 326 unsigned int txfifo; 327 unsigned int ahb_buf_size; 328 unsigned int quirks; 329 bool little_endian; 330 }; 331 332 static struct nxp_fspi_devtype_data lx2160a_data = { 333 .rxfifo = SZ_512, /* (64 * 64 bits) */ 334 .txfifo = SZ_1K, /* (128 * 64 bits) */ 335 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 336 .quirks = 0, 337 .little_endian = true, /* little-endian */ 338 }; 339 340 static struct nxp_fspi_devtype_data imx8mm_data = { 341 .rxfifo = SZ_512, /* (64 * 64 bits) */ 342 .txfifo = SZ_1K, /* (128 * 64 bits) */ 343 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 344 .quirks = 0, 345 .little_endian = true, /* little-endian */ 346 }; 347 348 static struct nxp_fspi_devtype_data imx8qxp_data = { 349 .rxfifo = SZ_512, /* (64 * 64 bits) */ 350 .txfifo = SZ_1K, /* (128 * 64 bits) */ 351 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 352 .quirks = 0, 353 .little_endian = true, /* little-endian */ 354 }; 355 356 static struct nxp_fspi_devtype_data imx8dxl_data = { 357 .rxfifo = SZ_512, /* (64 * 64 bits) */ 358 .txfifo = SZ_1K, /* (128 * 64 bits) */ 359 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 360 .quirks = FSPI_QUIRK_USE_IP_ONLY, 361 .little_endian = true, /* little-endian */ 362 }; 363 364 struct nxp_fspi { 365 void __iomem *iobase; 366 void __iomem *ahb_addr; 367 u32 memmap_phy; 368 u32 memmap_phy_size; 369 u32 memmap_start; 370 u32 memmap_len; 371 struct clk *clk, *clk_en; 372 struct device *dev; 373 struct completion c; 374 struct nxp_fspi_devtype_data *devtype_data; 375 struct mutex lock; 376 struct pm_qos_request pm_qos_req; 377 int selected; 378 }; 379 380 static inline int needs_ip_only(struct nxp_fspi *f) 381 { 382 return f->devtype_data->quirks & FSPI_QUIRK_USE_IP_ONLY; 383 } 384 385 /* 386 * R/W functions for big- or little-endian registers: 387 * The FSPI controller's endianness is independent of 388 * the CPU core's endianness. So far, although the CPU 389 * core is little-endian the FSPI controller can use 390 * big-endian or little-endian. 391 */ 392 static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr) 393 { 394 if (f->devtype_data->little_endian) 395 iowrite32(val, addr); 396 else 397 iowrite32be(val, addr); 398 } 399 400 static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr) 401 { 402 if (f->devtype_data->little_endian) 403 return ioread32(addr); 404 else 405 return ioread32be(addr); 406 } 407 408 static irqreturn_t nxp_fspi_irq_handler(int irq, void *dev_id) 409 { 410 struct nxp_fspi *f = dev_id; 411 u32 reg; 412 413 /* clear interrupt */ 414 reg = fspi_readl(f, f->iobase + FSPI_INTR); 415 fspi_writel(f, FSPI_INTR_IPCMDDONE, f->iobase + FSPI_INTR); 416 417 if (reg & FSPI_INTR_IPCMDDONE) 418 complete(&f->c); 419 420 return IRQ_HANDLED; 421 } 422 423 static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width) 424 { 425 switch (width) { 426 case 1: 427 case 2: 428 case 4: 429 case 8: 430 return 0; 431 } 432 433 return -ENOTSUPP; 434 } 435 436 static bool nxp_fspi_supports_op(struct spi_mem *mem, 437 const struct spi_mem_op *op) 438 { 439 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); 440 int ret; 441 442 ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth); 443 444 if (op->addr.nbytes) 445 ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth); 446 447 if (op->dummy.nbytes) 448 ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth); 449 450 if (op->data.nbytes) 451 ret |= nxp_fspi_check_buswidth(f, op->data.buswidth); 452 453 if (ret) 454 return false; 455 456 /* 457 * The number of address bytes should be equal to or less than 4 bytes. 458 */ 459 if (op->addr.nbytes > 4) 460 return false; 461 462 /* 463 * If requested address value is greater than controller assigned 464 * memory mapped space, return error as it didn't fit in the range 465 * of assigned address space. 466 */ 467 if (op->addr.val >= f->memmap_phy_size) 468 return false; 469 470 /* Max 64 dummy clock cycles supported */ 471 if (op->dummy.buswidth && 472 (op->dummy.nbytes * 8 / op->dummy.buswidth > 64)) 473 return false; 474 475 /* Max data length, check controller limits and alignment */ 476 if (op->data.dir == SPI_MEM_DATA_IN && 477 (op->data.nbytes > f->devtype_data->ahb_buf_size || 478 (op->data.nbytes > f->devtype_data->rxfifo - 4 && 479 !IS_ALIGNED(op->data.nbytes, 8)))) 480 return false; 481 482 if (op->data.dir == SPI_MEM_DATA_OUT && 483 op->data.nbytes > f->devtype_data->txfifo) 484 return false; 485 486 return spi_mem_default_supports_op(mem, op); 487 } 488 489 /* Instead of busy looping invoke readl_poll_timeout functionality. */ 490 static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base, 491 u32 mask, u32 delay_us, 492 u32 timeout_us, bool c) 493 { 494 u32 reg; 495 496 if (!f->devtype_data->little_endian) 497 mask = (u32)cpu_to_be32(mask); 498 499 if (c) 500 return readl_poll_timeout(base, reg, (reg & mask), 501 delay_us, timeout_us); 502 else 503 return readl_poll_timeout(base, reg, !(reg & mask), 504 delay_us, timeout_us); 505 } 506 507 /* 508 * If the slave device content being changed by Write/Erase, need to 509 * invalidate the AHB buffer. This can be achieved by doing the reset 510 * of controller after setting MCR0[SWRESET] bit. 511 */ 512 static inline void nxp_fspi_invalid(struct nxp_fspi *f) 513 { 514 u32 reg; 515 int ret; 516 517 reg = fspi_readl(f, f->iobase + FSPI_MCR0); 518 fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0); 519 520 /* w1c register, wait unit clear */ 521 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0, 522 FSPI_MCR0_SWRST, 0, POLL_TOUT, false); 523 WARN_ON(ret); 524 } 525 526 static void nxp_fspi_prepare_lut(struct nxp_fspi *f, 527 const struct spi_mem_op *op) 528 { 529 void __iomem *base = f->iobase; 530 u32 lutval[4] = {}; 531 int lutidx = 1, i; 532 533 /* cmd */ 534 lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth), 535 op->cmd.opcode); 536 537 /* addr bytes */ 538 if (op->addr.nbytes) { 539 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR, 540 LUT_PAD(op->addr.buswidth), 541 op->addr.nbytes * 8); 542 lutidx++; 543 } 544 545 /* dummy bytes, if needed */ 546 if (op->dummy.nbytes) { 547 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY, 548 /* 549 * Due to FlexSPI controller limitation number of PAD for dummy 550 * buswidth needs to be programmed as equal to data buswidth. 551 */ 552 LUT_PAD(op->data.buswidth), 553 op->dummy.nbytes * 8 / 554 op->dummy.buswidth); 555 lutidx++; 556 } 557 558 /* read/write data bytes */ 559 if (op->data.nbytes) { 560 lutval[lutidx / 2] |= LUT_DEF(lutidx, 561 op->data.dir == SPI_MEM_DATA_IN ? 562 LUT_NXP_READ : LUT_NXP_WRITE, 563 LUT_PAD(op->data.buswidth), 564 0); 565 lutidx++; 566 } 567 568 /* stop condition. */ 569 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0); 570 571 /* unlock LUT */ 572 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY); 573 fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR); 574 575 /* fill LUT */ 576 for (i = 0; i < ARRAY_SIZE(lutval); i++) 577 fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i)); 578 579 dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x], size: 0x%08x\n", 580 op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3], op->data.nbytes); 581 582 /* lock LUT */ 583 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY); 584 fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR); 585 } 586 587 static int nxp_fspi_clk_prep_enable(struct nxp_fspi *f) 588 { 589 int ret; 590 591 if (is_acpi_node(dev_fwnode(f->dev))) 592 return 0; 593 594 ret = clk_prepare_enable(f->clk_en); 595 if (ret) 596 return ret; 597 598 ret = clk_prepare_enable(f->clk); 599 if (ret) { 600 clk_disable_unprepare(f->clk_en); 601 return ret; 602 } 603 604 return 0; 605 } 606 607 static int nxp_fspi_clk_disable_unprep(struct nxp_fspi *f) 608 { 609 if (is_acpi_node(dev_fwnode(f->dev))) 610 return 0; 611 612 clk_disable_unprepare(f->clk); 613 clk_disable_unprepare(f->clk_en); 614 615 return 0; 616 } 617 618 /* 619 * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0 620 * register and start base address of the slave device. 621 * 622 * (Higher address) 623 * -------- <-- FLSHB2CR0 624 * | B2 | 625 * | | 626 * B2 start address --> -------- <-- FLSHB1CR0 627 * | B1 | 628 * | | 629 * B1 start address --> -------- <-- FLSHA2CR0 630 * | A2 | 631 * | | 632 * A2 start address --> -------- <-- FLSHA1CR0 633 * | A1 | 634 * | | 635 * A1 start address --> -------- (Lower address) 636 * 637 * 638 * Start base address defines the starting address range for given CS and 639 * FSPI_FLSHXXCR0 defines the size of the slave device connected at given CS. 640 * 641 * But, different targets are having different combinations of number of CS, 642 * some targets only have single CS or two CS covering controller's full 643 * memory mapped space area. 644 * Thus, implementation is being done as independent of the size and number 645 * of the connected slave device. 646 * Assign controller memory mapped space size as the size to the connected 647 * slave device. 648 * Mark FLSHxxCR0 as zero initially and then assign value only to the selected 649 * chip-select Flash configuration register. 650 * 651 * For e.g. to access CS2 (B1), FLSHB1CR0 register would be equal to the 652 * memory mapped size of the controller. 653 * Value for rest of the CS FLSHxxCR0 register would be zero. 654 * 655 */ 656 static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi) 657 { 658 unsigned long rate = spi->max_speed_hz; 659 int ret; 660 uint64_t size_kb; 661 662 /* 663 * Return, if previously selected slave device is same as current 664 * requested slave device. 665 */ 666 if (f->selected == spi->chip_select) 667 return; 668 669 /* Reset FLSHxxCR0 registers */ 670 fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0); 671 fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0); 672 fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0); 673 fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0); 674 675 /* Assign controller memory mapped space as size, KBytes, of flash. */ 676 size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size); 677 678 fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 + 679 4 * spi->chip_select); 680 681 dev_dbg(f->dev, "Slave device [CS:%x] selected\n", spi->chip_select); 682 683 nxp_fspi_clk_disable_unprep(f); 684 685 ret = clk_set_rate(f->clk, rate); 686 if (ret) 687 return; 688 689 ret = nxp_fspi_clk_prep_enable(f); 690 if (ret) 691 return; 692 693 f->selected = spi->chip_select; 694 } 695 696 static int nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op) 697 { 698 u32 start = op->addr.val; 699 u32 len = op->data.nbytes; 700 701 /* if necessary, ioremap before AHB read */ 702 if ((!f->ahb_addr) || start < f->memmap_start || 703 start + len > f->memmap_start + f->memmap_len) { 704 if (f->ahb_addr) 705 iounmap(f->ahb_addr); 706 707 f->memmap_start = start; 708 f->memmap_len = len > NXP_FSPI_MIN_IOMAP ? 709 len : NXP_FSPI_MIN_IOMAP; 710 711 f->ahb_addr = ioremap_wc(f->memmap_phy + f->memmap_start, 712 f->memmap_len); 713 714 if (!f->ahb_addr) { 715 dev_err(f->dev, "failed to alloc memory\n"); 716 return -ENOMEM; 717 } 718 } 719 720 /* Read out the data directly from the AHB buffer. */ 721 memcpy_fromio(op->data.buf.in, 722 f->ahb_addr + start - f->memmap_start, len); 723 724 return 0; 725 } 726 727 static void nxp_fspi_fill_txfifo(struct nxp_fspi *f, 728 const struct spi_mem_op *op) 729 { 730 void __iomem *base = f->iobase; 731 int i, ret; 732 u8 *buf = (u8 *) op->data.buf.out; 733 734 /* clear the TX FIFO. */ 735 fspi_writel(f, FSPI_IPTXFCR_CLR, base + FSPI_IPTXFCR); 736 737 /* 738 * Default value of water mark level is 8 bytes, hence in single 739 * write request controller can write max 8 bytes of data. 740 */ 741 742 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) { 743 /* Wait for TXFIFO empty */ 744 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 745 FSPI_INTR_IPTXWE, 0, 746 POLL_TOUT, true); 747 WARN_ON(ret); 748 749 fspi_writel(f, *(u32 *) (buf + i), base + FSPI_TFDR); 750 fspi_writel(f, *(u32 *) (buf + i + 4), base + FSPI_TFDR + 4); 751 fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR); 752 } 753 754 if (i < op->data.nbytes) { 755 u32 data = 0; 756 int j; 757 /* Wait for TXFIFO empty */ 758 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 759 FSPI_INTR_IPTXWE, 0, 760 POLL_TOUT, true); 761 WARN_ON(ret); 762 763 for (j = 0; j < ALIGN(op->data.nbytes - i, 4); j += 4) { 764 memcpy(&data, buf + i + j, 4); 765 fspi_writel(f, data, base + FSPI_TFDR + j); 766 } 767 fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR); 768 } 769 } 770 771 static void nxp_fspi_read_rxfifo(struct nxp_fspi *f, 772 const struct spi_mem_op *op) 773 { 774 void __iomem *base = f->iobase; 775 int i, ret; 776 int len = op->data.nbytes; 777 u8 *buf = (u8 *) op->data.buf.in; 778 779 /* 780 * Default value of water mark level is 8 bytes, hence in single 781 * read request controller can read max 8 bytes of data. 782 */ 783 for (i = 0; i < ALIGN_DOWN(len, 8); i += 8) { 784 /* Wait for RXFIFO available */ 785 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 786 FSPI_INTR_IPRXWA, 0, 787 POLL_TOUT, true); 788 WARN_ON(ret); 789 790 *(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR); 791 *(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4); 792 /* move the FIFO pointer */ 793 fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR); 794 } 795 796 if (i < len) { 797 u32 tmp; 798 int size, j; 799 800 buf = op->data.buf.in + i; 801 /* Wait for RXFIFO available */ 802 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 803 FSPI_INTR_IPRXWA, 0, 804 POLL_TOUT, true); 805 WARN_ON(ret); 806 807 len = op->data.nbytes - i; 808 for (j = 0; j < op->data.nbytes - i; j += 4) { 809 tmp = fspi_readl(f, base + FSPI_RFDR + j); 810 size = min(len, 4); 811 memcpy(buf + j, &tmp, size); 812 len -= size; 813 } 814 } 815 816 /* invalid the RXFIFO */ 817 fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR); 818 /* move the FIFO pointer */ 819 fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR); 820 } 821 822 static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op) 823 { 824 void __iomem *base = f->iobase; 825 int seqnum = 0; 826 int err = 0; 827 u32 reg; 828 829 reg = fspi_readl(f, base + FSPI_IPRXFCR); 830 /* invalid RXFIFO first */ 831 reg &= ~FSPI_IPRXFCR_DMA_EN; 832 reg = reg | FSPI_IPRXFCR_CLR; 833 fspi_writel(f, reg, base + FSPI_IPRXFCR); 834 835 init_completion(&f->c); 836 837 fspi_writel(f, op->addr.val, base + FSPI_IPCR0); 838 /* 839 * Always start the sequence at the same index since we update 840 * the LUT at each exec_op() call. And also specify the DATA 841 * length, since it's has not been specified in the LUT. 842 */ 843 fspi_writel(f, op->data.nbytes | 844 (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) | 845 (seqnum << FSPI_IPCR1_SEQNUM_SHIFT), 846 base + FSPI_IPCR1); 847 848 /* Trigger the LUT now. */ 849 fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD); 850 851 /* Wait for the interrupt. */ 852 if (!wait_for_completion_timeout(&f->c, msecs_to_jiffies(1000))) 853 err = -ETIMEDOUT; 854 855 /* Invoke IP data read, if request is of data read. */ 856 if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN) 857 nxp_fspi_read_rxfifo(f, op); 858 859 return err; 860 } 861 862 static int nxp_fspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) 863 { 864 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); 865 int err = 0; 866 867 mutex_lock(&f->lock); 868 869 /* Wait for controller being ready. */ 870 err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0, 871 FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true); 872 WARN_ON(err); 873 874 nxp_fspi_select_mem(f, mem->spi); 875 876 nxp_fspi_prepare_lut(f, op); 877 /* 878 * If we have large chunks of data, we read them through the AHB bus by 879 * accessing the mapped memory. In all other cases we use IP commands 880 * to access the flash. Read via AHB bus may be corrupted due to 881 * existence of an errata and therefore discard AHB read in such cases. 882 */ 883 if (op->data.nbytes > (f->devtype_data->rxfifo - 4) && 884 op->data.dir == SPI_MEM_DATA_IN && 885 !needs_ip_only(f)) { 886 err = nxp_fspi_read_ahb(f, op); 887 } else { 888 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) 889 nxp_fspi_fill_txfifo(f, op); 890 891 err = nxp_fspi_do_op(f, op); 892 } 893 894 /* Invalidate the data in the AHB buffer. */ 895 nxp_fspi_invalid(f); 896 897 mutex_unlock(&f->lock); 898 899 return err; 900 } 901 902 static int nxp_fspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) 903 { 904 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); 905 906 if (op->data.dir == SPI_MEM_DATA_OUT) { 907 if (op->data.nbytes > f->devtype_data->txfifo) 908 op->data.nbytes = f->devtype_data->txfifo; 909 } else { 910 if (op->data.nbytes > f->devtype_data->ahb_buf_size) 911 op->data.nbytes = f->devtype_data->ahb_buf_size; 912 else if (op->data.nbytes > (f->devtype_data->rxfifo - 4)) 913 op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8); 914 } 915 916 /* Limit data bytes to RX FIFO in case of IP read only */ 917 if (op->data.dir == SPI_MEM_DATA_IN && 918 needs_ip_only(f) && 919 op->data.nbytes > f->devtype_data->rxfifo) 920 op->data.nbytes = f->devtype_data->rxfifo; 921 922 return 0; 923 } 924 925 static void erratum_err050568(struct nxp_fspi *f) 926 { 927 const struct soc_device_attribute ls1028a_soc_attr[] = { 928 { .family = "QorIQ LS1028A" }, 929 { /* sentinel */ } 930 }; 931 struct regmap *map; 932 u32 val, sys_pll_ratio; 933 int ret; 934 935 /* Check for LS1028A family */ 936 if (!soc_device_match(ls1028a_soc_attr)) { 937 dev_dbg(f->dev, "Errata applicable only for LS1028A\n"); 938 return; 939 } 940 941 map = syscon_regmap_lookup_by_compatible("fsl,ls1028a-dcfg"); 942 if (IS_ERR(map)) { 943 dev_err(f->dev, "No syscon regmap\n"); 944 goto err; 945 } 946 947 ret = regmap_read(map, DCFG_RCWSR1, &val); 948 if (ret < 0) 949 goto err; 950 951 sys_pll_ratio = FIELD_GET(SYS_PLL_RAT, val); 952 dev_dbg(f->dev, "val: 0x%08x, sys_pll_ratio: %d\n", val, sys_pll_ratio); 953 954 /* Use IP bus only if platform clock is 300MHz */ 955 if (sys_pll_ratio == 3) 956 f->devtype_data->quirks |= FSPI_QUIRK_USE_IP_ONLY; 957 958 return; 959 960 err: 961 dev_err(f->dev, "Errata cannot be executed. Read via IP bus may not work\n"); 962 } 963 964 static int nxp_fspi_default_setup(struct nxp_fspi *f) 965 { 966 void __iomem *base = f->iobase; 967 int ret, i; 968 u32 reg; 969 970 /* disable and unprepare clock to avoid glitch pass to controller */ 971 nxp_fspi_clk_disable_unprep(f); 972 973 /* the default frequency, we will change it later if necessary. */ 974 ret = clk_set_rate(f->clk, 20000000); 975 if (ret) 976 return ret; 977 978 ret = nxp_fspi_clk_prep_enable(f); 979 if (ret) 980 return ret; 981 982 /* 983 * ERR050568: Flash access by FlexSPI AHB command may not work with 984 * platform frequency equal to 300 MHz on LS1028A. 985 * LS1028A reuses LX2160A compatible entry. Make errata applicable for 986 * Layerscape LS1028A platform. 987 */ 988 if (of_device_is_compatible(f->dev->of_node, "nxp,lx2160a-fspi")) 989 erratum_err050568(f); 990 991 /* Reset the module */ 992 /* w1c register, wait unit clear */ 993 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0, 994 FSPI_MCR0_SWRST, 0, POLL_TOUT, false); 995 WARN_ON(ret); 996 997 /* Disable the module */ 998 fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0); 999 1000 /* Reset the DLL register to default value */ 1001 fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR); 1002 fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR); 1003 1004 /* enable module */ 1005 fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) | 1006 FSPI_MCR0_IP_TIMEOUT(0xFF) | (u32) FSPI_MCR0_OCTCOMB_EN, 1007 base + FSPI_MCR0); 1008 1009 /* 1010 * Disable same device enable bit and configure all slave devices 1011 * independently. 1012 */ 1013 reg = fspi_readl(f, f->iobase + FSPI_MCR2); 1014 reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN); 1015 fspi_writel(f, reg, base + FSPI_MCR2); 1016 1017 /* AHB configuration for access buffer 0~7. */ 1018 for (i = 0; i < 7; i++) 1019 fspi_writel(f, 0, base + FSPI_AHBRX_BUF0CR0 + 4 * i); 1020 1021 /* 1022 * Set ADATSZ with the maximum AHB buffer size to improve the read 1023 * performance. 1024 */ 1025 fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 | 1026 FSPI_AHBRXBUF0CR7_PREF), base + FSPI_AHBRX_BUF7CR0); 1027 1028 /* prefetch and no start address alignment limitation */ 1029 fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT, 1030 base + FSPI_AHBCR); 1031 1032 /* AHB Read - Set lut sequence ID for all CS. */ 1033 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2); 1034 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2); 1035 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2); 1036 fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2); 1037 1038 f->selected = -1; 1039 1040 /* enable the interrupt */ 1041 fspi_writel(f, FSPI_INTEN_IPCMDDONE, base + FSPI_INTEN); 1042 1043 return 0; 1044 } 1045 1046 static const char *nxp_fspi_get_name(struct spi_mem *mem) 1047 { 1048 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->master); 1049 struct device *dev = &mem->spi->dev; 1050 const char *name; 1051 1052 // Set custom name derived from the platform_device of the controller. 1053 if (of_get_available_child_count(f->dev->of_node) == 1) 1054 return dev_name(f->dev); 1055 1056 name = devm_kasprintf(dev, GFP_KERNEL, 1057 "%s-%d", dev_name(f->dev), 1058 mem->spi->chip_select); 1059 1060 if (!name) { 1061 dev_err(dev, "failed to get memory for custom flash name\n"); 1062 return ERR_PTR(-ENOMEM); 1063 } 1064 1065 return name; 1066 } 1067 1068 static const struct spi_controller_mem_ops nxp_fspi_mem_ops = { 1069 .adjust_op_size = nxp_fspi_adjust_op_size, 1070 .supports_op = nxp_fspi_supports_op, 1071 .exec_op = nxp_fspi_exec_op, 1072 .get_name = nxp_fspi_get_name, 1073 }; 1074 1075 static int nxp_fspi_probe(struct platform_device *pdev) 1076 { 1077 struct spi_controller *ctlr; 1078 struct device *dev = &pdev->dev; 1079 struct device_node *np = dev->of_node; 1080 struct resource *res; 1081 struct nxp_fspi *f; 1082 int ret; 1083 u32 reg; 1084 1085 ctlr = spi_alloc_master(&pdev->dev, sizeof(*f)); 1086 if (!ctlr) 1087 return -ENOMEM; 1088 1089 ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL | 1090 SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL; 1091 1092 f = spi_controller_get_devdata(ctlr); 1093 f->dev = dev; 1094 f->devtype_data = (struct nxp_fspi_devtype_data *)device_get_match_data(dev); 1095 if (!f->devtype_data) { 1096 ret = -ENODEV; 1097 goto err_put_ctrl; 1098 } 1099 1100 platform_set_drvdata(pdev, f); 1101 1102 /* find the resources - configuration register address space */ 1103 if (is_acpi_node(dev_fwnode(f->dev))) 1104 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1105 else 1106 res = platform_get_resource_byname(pdev, 1107 IORESOURCE_MEM, "fspi_base"); 1108 1109 f->iobase = devm_ioremap_resource(dev, res); 1110 if (IS_ERR(f->iobase)) { 1111 ret = PTR_ERR(f->iobase); 1112 goto err_put_ctrl; 1113 } 1114 1115 /* find the resources - controller memory mapped space */ 1116 if (is_acpi_node(dev_fwnode(f->dev))) 1117 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1118 else 1119 res = platform_get_resource_byname(pdev, 1120 IORESOURCE_MEM, "fspi_mmap"); 1121 1122 if (!res) { 1123 ret = -ENODEV; 1124 goto err_put_ctrl; 1125 } 1126 1127 /* assign memory mapped starting address and mapped size. */ 1128 f->memmap_phy = res->start; 1129 f->memmap_phy_size = resource_size(res); 1130 1131 /* find the clocks */ 1132 if (dev_of_node(&pdev->dev)) { 1133 f->clk_en = devm_clk_get(dev, "fspi_en"); 1134 if (IS_ERR(f->clk_en)) { 1135 ret = PTR_ERR(f->clk_en); 1136 goto err_put_ctrl; 1137 } 1138 1139 f->clk = devm_clk_get(dev, "fspi"); 1140 if (IS_ERR(f->clk)) { 1141 ret = PTR_ERR(f->clk); 1142 goto err_put_ctrl; 1143 } 1144 1145 ret = nxp_fspi_clk_prep_enable(f); 1146 if (ret) { 1147 dev_err(dev, "can not enable the clock\n"); 1148 goto err_put_ctrl; 1149 } 1150 } 1151 1152 /* Clear potential interrupts */ 1153 reg = fspi_readl(f, f->iobase + FSPI_INTR); 1154 if (reg) 1155 fspi_writel(f, reg, f->iobase + FSPI_INTR); 1156 1157 /* find the irq */ 1158 ret = platform_get_irq(pdev, 0); 1159 if (ret < 0) 1160 goto err_disable_clk; 1161 1162 ret = devm_request_irq(dev, ret, 1163 nxp_fspi_irq_handler, 0, pdev->name, f); 1164 if (ret) { 1165 dev_err(dev, "failed to request irq: %d\n", ret); 1166 goto err_disable_clk; 1167 } 1168 1169 mutex_init(&f->lock); 1170 1171 ctlr->bus_num = -1; 1172 ctlr->num_chipselect = NXP_FSPI_MAX_CHIPSELECT; 1173 ctlr->mem_ops = &nxp_fspi_mem_ops; 1174 1175 nxp_fspi_default_setup(f); 1176 1177 ctlr->dev.of_node = np; 1178 1179 ret = devm_spi_register_controller(&pdev->dev, ctlr); 1180 if (ret) 1181 goto err_destroy_mutex; 1182 1183 return 0; 1184 1185 err_destroy_mutex: 1186 mutex_destroy(&f->lock); 1187 1188 err_disable_clk: 1189 nxp_fspi_clk_disable_unprep(f); 1190 1191 err_put_ctrl: 1192 spi_controller_put(ctlr); 1193 1194 dev_err(dev, "NXP FSPI probe failed\n"); 1195 return ret; 1196 } 1197 1198 static int nxp_fspi_remove(struct platform_device *pdev) 1199 { 1200 struct nxp_fspi *f = platform_get_drvdata(pdev); 1201 1202 /* disable the hardware */ 1203 fspi_writel(f, FSPI_MCR0_MDIS, f->iobase + FSPI_MCR0); 1204 1205 nxp_fspi_clk_disable_unprep(f); 1206 1207 mutex_destroy(&f->lock); 1208 1209 if (f->ahb_addr) 1210 iounmap(f->ahb_addr); 1211 1212 return 0; 1213 } 1214 1215 static int nxp_fspi_suspend(struct device *dev) 1216 { 1217 return 0; 1218 } 1219 1220 static int nxp_fspi_resume(struct device *dev) 1221 { 1222 struct nxp_fspi *f = dev_get_drvdata(dev); 1223 1224 nxp_fspi_default_setup(f); 1225 1226 return 0; 1227 } 1228 1229 static const struct of_device_id nxp_fspi_dt_ids[] = { 1230 { .compatible = "nxp,lx2160a-fspi", .data = (void *)&lx2160a_data, }, 1231 { .compatible = "nxp,imx8mm-fspi", .data = (void *)&imx8mm_data, }, 1232 { .compatible = "nxp,imx8mp-fspi", .data = (void *)&imx8mm_data, }, 1233 { .compatible = "nxp,imx8qxp-fspi", .data = (void *)&imx8qxp_data, }, 1234 { .compatible = "nxp,imx8dxl-fspi", .data = (void *)&imx8dxl_data, }, 1235 { /* sentinel */ } 1236 }; 1237 MODULE_DEVICE_TABLE(of, nxp_fspi_dt_ids); 1238 1239 #ifdef CONFIG_ACPI 1240 static const struct acpi_device_id nxp_fspi_acpi_ids[] = { 1241 { "NXP0009", .driver_data = (kernel_ulong_t)&lx2160a_data, }, 1242 {} 1243 }; 1244 MODULE_DEVICE_TABLE(acpi, nxp_fspi_acpi_ids); 1245 #endif 1246 1247 static const struct dev_pm_ops nxp_fspi_pm_ops = { 1248 .suspend = nxp_fspi_suspend, 1249 .resume = nxp_fspi_resume, 1250 }; 1251 1252 static struct platform_driver nxp_fspi_driver = { 1253 .driver = { 1254 .name = "nxp-fspi", 1255 .of_match_table = nxp_fspi_dt_ids, 1256 .acpi_match_table = ACPI_PTR(nxp_fspi_acpi_ids), 1257 .pm = &nxp_fspi_pm_ops, 1258 }, 1259 .probe = nxp_fspi_probe, 1260 .remove = nxp_fspi_remove, 1261 }; 1262 module_platform_driver(nxp_fspi_driver); 1263 1264 MODULE_DESCRIPTION("NXP FSPI Controller Driver"); 1265 MODULE_AUTHOR("NXP Semiconductor"); 1266 MODULE_AUTHOR("Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>"); 1267 MODULE_AUTHOR("Boris Brezillon <bbrezillon@kernel.org>"); 1268 MODULE_AUTHOR("Frieder Schrempf <frieder.schrempf@kontron.de>"); 1269 MODULE_LICENSE("GPL v2"); 1270