1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AD5933 AD5934 Impedance Converter, Network Analyzer 4 * 5 * Copyright 2011 Analog Devices Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/err.h> 12 #include <linux/i2c.h> 13 #include <linux/interrupt.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/sysfs.h> 18 #include <linux/types.h> 19 20 #include <linux/iio/buffer.h> 21 #include <linux/iio/iio.h> 22 #include <linux/iio/kfifo_buf.h> 23 #include <linux/iio/sysfs.h> 24 25 /* AD5933/AD5934 Registers */ 26 #define AD5933_REG_CONTROL_HB 0x80 /* R/W, 1 byte */ 27 #define AD5933_REG_CONTROL_LB 0x81 /* R/W, 1 byte */ 28 #define AD5933_REG_FREQ_START 0x82 /* R/W, 3 bytes */ 29 #define AD5933_REG_FREQ_INC 0x85 /* R/W, 3 bytes */ 30 #define AD5933_REG_INC_NUM 0x88 /* R/W, 2 bytes, 9 bit */ 31 #define AD5933_REG_SETTLING_CYCLES 0x8A /* R/W, 2 bytes */ 32 #define AD5933_REG_STATUS 0x8F /* R, 1 byte */ 33 #define AD5933_REG_TEMP_DATA 0x92 /* R, 2 bytes*/ 34 #define AD5933_REG_REAL_DATA 0x94 /* R, 2 bytes*/ 35 #define AD5933_REG_IMAG_DATA 0x96 /* R, 2 bytes*/ 36 37 /* AD5933_REG_CONTROL_HB Bits */ 38 #define AD5933_CTRL_INIT_START_FREQ (0x1 << 4) 39 #define AD5933_CTRL_START_SWEEP (0x2 << 4) 40 #define AD5933_CTRL_INC_FREQ (0x3 << 4) 41 #define AD5933_CTRL_REPEAT_FREQ (0x4 << 4) 42 #define AD5933_CTRL_MEASURE_TEMP (0x9 << 4) 43 #define AD5933_CTRL_POWER_DOWN (0xA << 4) 44 #define AD5933_CTRL_STANDBY (0xB << 4) 45 46 #define AD5933_CTRL_RANGE_2000mVpp (0x0 << 1) 47 #define AD5933_CTRL_RANGE_200mVpp (0x1 << 1) 48 #define AD5933_CTRL_RANGE_400mVpp (0x2 << 1) 49 #define AD5933_CTRL_RANGE_1000mVpp (0x3 << 1) 50 #define AD5933_CTRL_RANGE(x) ((x) << 1) 51 52 #define AD5933_CTRL_PGA_GAIN_1 (0x1 << 0) 53 #define AD5933_CTRL_PGA_GAIN_5 (0x0 << 0) 54 55 /* AD5933_REG_CONTROL_LB Bits */ 56 #define AD5933_CTRL_RESET (0x1 << 4) 57 #define AD5933_CTRL_INT_SYSCLK (0x0 << 3) 58 #define AD5933_CTRL_EXT_SYSCLK (0x1 << 3) 59 60 /* AD5933_REG_STATUS Bits */ 61 #define AD5933_STAT_TEMP_VALID (0x1 << 0) 62 #define AD5933_STAT_DATA_VALID (0x1 << 1) 63 #define AD5933_STAT_SWEEP_DONE (0x1 << 2) 64 65 /* I2C Block Commands */ 66 #define AD5933_I2C_BLOCK_WRITE 0xA0 67 #define AD5933_I2C_BLOCK_READ 0xA1 68 #define AD5933_I2C_ADDR_POINTER 0xB0 69 70 /* Device Specs */ 71 #define AD5933_INT_OSC_FREQ_Hz 16776000 72 #define AD5933_MAX_OUTPUT_FREQ_Hz 100000 73 #define AD5933_MAX_RETRIES 100 74 75 #define AD5933_OUT_RANGE 1 76 #define AD5933_OUT_RANGE_AVAIL 2 77 #define AD5933_OUT_SETTLING_CYCLES 3 78 #define AD5933_IN_PGA_GAIN 4 79 #define AD5933_IN_PGA_GAIN_AVAIL 5 80 #define AD5933_FREQ_POINTS 6 81 82 #define AD5933_POLL_TIME_ms 10 83 #define AD5933_INIT_EXCITATION_TIME_ms 100 84 85 struct ad5933_state { 86 struct i2c_client *client; 87 struct regulator *reg; 88 struct clk *mclk; 89 struct delayed_work work; 90 struct mutex lock; /* Protect sensor state */ 91 unsigned long mclk_hz; 92 unsigned char ctrl_hb; 93 unsigned char ctrl_lb; 94 unsigned int range_avail[4]; 95 unsigned short vref_mv; 96 unsigned short settling_cycles; 97 unsigned short freq_points; 98 unsigned int freq_start; 99 unsigned int freq_inc; 100 unsigned int state; 101 unsigned int poll_time_jiffies; 102 }; 103 104 #define AD5933_CHANNEL(_type, _extend_name, _info_mask_separate, _address, \ 105 _scan_index, _realbits) { \ 106 .type = (_type), \ 107 .extend_name = (_extend_name), \ 108 .info_mask_separate = (_info_mask_separate), \ 109 .address = (_address), \ 110 .scan_index = (_scan_index), \ 111 .scan_type = { \ 112 .sign = 's', \ 113 .realbits = (_realbits), \ 114 .storagebits = 16, \ 115 }, \ 116 } 117 118 static const struct iio_chan_spec ad5933_channels[] = { 119 AD5933_CHANNEL(IIO_TEMP, NULL, BIT(IIO_CHAN_INFO_RAW) | 120 BIT(IIO_CHAN_INFO_SCALE), AD5933_REG_TEMP_DATA, -1, 14), 121 /* Ring Channels */ 122 AD5933_CHANNEL(IIO_VOLTAGE, "real", 0, AD5933_REG_REAL_DATA, 0, 16), 123 AD5933_CHANNEL(IIO_VOLTAGE, "imag", 0, AD5933_REG_IMAG_DATA, 1, 16), 124 }; 125 126 static int ad5933_i2c_write(struct i2c_client *client, u8 reg, u8 len, u8 *data) 127 { 128 int ret; 129 130 while (len--) { 131 ret = i2c_smbus_write_byte_data(client, reg++, *data++); 132 if (ret < 0) { 133 dev_err(&client->dev, "I2C write error\n"); 134 return ret; 135 } 136 } 137 return 0; 138 } 139 140 static int ad5933_i2c_read(struct i2c_client *client, u8 reg, u8 len, u8 *data) 141 { 142 int ret; 143 144 while (len--) { 145 ret = i2c_smbus_read_byte_data(client, reg++); 146 if (ret < 0) { 147 dev_err(&client->dev, "I2C read error\n"); 148 return ret; 149 } 150 *data++ = ret; 151 } 152 return 0; 153 } 154 155 static int ad5933_cmd(struct ad5933_state *st, unsigned char cmd) 156 { 157 unsigned char dat = st->ctrl_hb | cmd; 158 159 return ad5933_i2c_write(st->client, 160 AD5933_REG_CONTROL_HB, 1, &dat); 161 } 162 163 static int ad5933_reset(struct ad5933_state *st) 164 { 165 unsigned char dat = st->ctrl_lb | AD5933_CTRL_RESET; 166 167 return ad5933_i2c_write(st->client, 168 AD5933_REG_CONTROL_LB, 1, &dat); 169 } 170 171 static int ad5933_wait_busy(struct ad5933_state *st, unsigned char event) 172 { 173 unsigned char val, timeout = AD5933_MAX_RETRIES; 174 int ret; 175 176 while (timeout--) { 177 ret = ad5933_i2c_read(st->client, AD5933_REG_STATUS, 1, &val); 178 if (ret < 0) 179 return ret; 180 if (val & event) 181 return val; 182 cpu_relax(); 183 mdelay(1); 184 } 185 186 return -EAGAIN; 187 } 188 189 static int ad5933_set_freq(struct ad5933_state *st, 190 unsigned int reg, unsigned long freq) 191 { 192 unsigned long long freqreg; 193 union { 194 __be32 d32; 195 u8 d8[4]; 196 } dat; 197 198 freqreg = (u64)freq * (u64)(1 << 27); 199 do_div(freqreg, st->mclk_hz / 4); 200 201 switch (reg) { 202 case AD5933_REG_FREQ_START: 203 st->freq_start = freq; 204 break; 205 case AD5933_REG_FREQ_INC: 206 st->freq_inc = freq; 207 break; 208 default: 209 return -EINVAL; 210 } 211 212 dat.d32 = cpu_to_be32(freqreg); 213 return ad5933_i2c_write(st->client, reg, 3, &dat.d8[1]); 214 } 215 216 static int ad5933_setup(struct ad5933_state *st) 217 { 218 __be16 dat; 219 int ret; 220 221 ret = ad5933_reset(st); 222 if (ret < 0) 223 return ret; 224 225 ret = ad5933_set_freq(st, AD5933_REG_FREQ_START, 10000); 226 if (ret < 0) 227 return ret; 228 229 ret = ad5933_set_freq(st, AD5933_REG_FREQ_INC, 200); 230 if (ret < 0) 231 return ret; 232 233 st->settling_cycles = 10; 234 dat = cpu_to_be16(st->settling_cycles); 235 236 ret = ad5933_i2c_write(st->client, 237 AD5933_REG_SETTLING_CYCLES, 238 2, (u8 *)&dat); 239 if (ret < 0) 240 return ret; 241 242 st->freq_points = 100; 243 dat = cpu_to_be16(st->freq_points); 244 245 return ad5933_i2c_write(st->client, AD5933_REG_INC_NUM, 2, (u8 *)&dat); 246 } 247 248 static void ad5933_calc_out_ranges(struct ad5933_state *st) 249 { 250 int i; 251 unsigned int normalized_3v3[4] = {1980, 198, 383, 970}; 252 253 for (i = 0; i < 4; i++) 254 st->range_avail[i] = normalized_3v3[i] * st->vref_mv / 3300; 255 } 256 257 /* 258 * handles: AD5933_REG_FREQ_START and AD5933_REG_FREQ_INC 259 */ 260 261 static ssize_t ad5933_show_frequency(struct device *dev, 262 struct device_attribute *attr, 263 char *buf) 264 { 265 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 266 struct ad5933_state *st = iio_priv(indio_dev); 267 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 268 int ret; 269 unsigned long long freqreg; 270 union { 271 __be32 d32; 272 u8 d8[4]; 273 } dat; 274 275 ret = iio_device_claim_direct_mode(indio_dev); 276 if (ret) 277 return ret; 278 ret = ad5933_i2c_read(st->client, this_attr->address, 3, &dat.d8[1]); 279 iio_device_release_direct_mode(indio_dev); 280 if (ret < 0) 281 return ret; 282 283 freqreg = be32_to_cpu(dat.d32) & 0xFFFFFF; 284 285 freqreg = (u64)freqreg * (u64)(st->mclk_hz / 4); 286 do_div(freqreg, BIT(27)); 287 288 return sprintf(buf, "%d\n", (int)freqreg); 289 } 290 291 static ssize_t ad5933_store_frequency(struct device *dev, 292 struct device_attribute *attr, 293 const char *buf, 294 size_t len) 295 { 296 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 297 struct ad5933_state *st = iio_priv(indio_dev); 298 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 299 unsigned long val; 300 int ret; 301 302 ret = kstrtoul(buf, 10, &val); 303 if (ret) 304 return ret; 305 306 if (val > AD5933_MAX_OUTPUT_FREQ_Hz) 307 return -EINVAL; 308 309 ret = iio_device_claim_direct_mode(indio_dev); 310 if (ret) 311 return ret; 312 ret = ad5933_set_freq(st, this_attr->address, val); 313 iio_device_release_direct_mode(indio_dev); 314 315 return ret ? ret : len; 316 } 317 318 static IIO_DEVICE_ATTR(out_altvoltage0_frequency_start, 0644, 319 ad5933_show_frequency, 320 ad5933_store_frequency, 321 AD5933_REG_FREQ_START); 322 323 static IIO_DEVICE_ATTR(out_altvoltage0_frequency_increment, 0644, 324 ad5933_show_frequency, 325 ad5933_store_frequency, 326 AD5933_REG_FREQ_INC); 327 328 static ssize_t ad5933_show(struct device *dev, 329 struct device_attribute *attr, 330 char *buf) 331 { 332 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 333 struct ad5933_state *st = iio_priv(indio_dev); 334 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 335 int ret = 0, len = 0; 336 337 mutex_lock(&st->lock); 338 switch ((u32)this_attr->address) { 339 case AD5933_OUT_RANGE: 340 len = sprintf(buf, "%u\n", 341 st->range_avail[(st->ctrl_hb >> 1) & 0x3]); 342 break; 343 case AD5933_OUT_RANGE_AVAIL: 344 len = sprintf(buf, "%u %u %u %u\n", st->range_avail[0], 345 st->range_avail[3], st->range_avail[2], 346 st->range_avail[1]); 347 break; 348 case AD5933_OUT_SETTLING_CYCLES: 349 len = sprintf(buf, "%d\n", st->settling_cycles); 350 break; 351 case AD5933_IN_PGA_GAIN: 352 len = sprintf(buf, "%s\n", 353 (st->ctrl_hb & AD5933_CTRL_PGA_GAIN_1) ? 354 "1" : "0.2"); 355 break; 356 case AD5933_IN_PGA_GAIN_AVAIL: 357 len = sprintf(buf, "1 0.2\n"); 358 break; 359 case AD5933_FREQ_POINTS: 360 len = sprintf(buf, "%d\n", st->freq_points); 361 break; 362 default: 363 ret = -EINVAL; 364 } 365 366 mutex_unlock(&st->lock); 367 return ret ? ret : len; 368 } 369 370 static ssize_t ad5933_store(struct device *dev, 371 struct device_attribute *attr, 372 const char *buf, 373 size_t len) 374 { 375 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 376 struct ad5933_state *st = iio_priv(indio_dev); 377 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 378 u16 val; 379 int i, ret = 0; 380 __be16 dat; 381 382 if (this_attr->address != AD5933_IN_PGA_GAIN) { 383 ret = kstrtou16(buf, 10, &val); 384 if (ret) 385 return ret; 386 } 387 388 ret = iio_device_claim_direct_mode(indio_dev); 389 if (ret) 390 return ret; 391 mutex_lock(&st->lock); 392 switch ((u32)this_attr->address) { 393 case AD5933_OUT_RANGE: 394 ret = -EINVAL; 395 for (i = 0; i < 4; i++) 396 if (val == st->range_avail[i]) { 397 st->ctrl_hb &= ~AD5933_CTRL_RANGE(0x3); 398 st->ctrl_hb |= AD5933_CTRL_RANGE(i); 399 ret = ad5933_cmd(st, 0); 400 break; 401 } 402 break; 403 case AD5933_IN_PGA_GAIN: 404 if (sysfs_streq(buf, "1")) { 405 st->ctrl_hb |= AD5933_CTRL_PGA_GAIN_1; 406 } else if (sysfs_streq(buf, "0.2")) { 407 st->ctrl_hb &= ~AD5933_CTRL_PGA_GAIN_1; 408 } else { 409 ret = -EINVAL; 410 break; 411 } 412 ret = ad5933_cmd(st, 0); 413 break; 414 case AD5933_OUT_SETTLING_CYCLES: 415 val = clamp(val, (u16)0, (u16)0x7FF); 416 st->settling_cycles = val; 417 418 /* 2x, 4x handling, see datasheet */ 419 if (val > 1022) 420 val = (val >> 2) | (3 << 9); 421 else if (val > 511) 422 val = (val >> 1) | BIT(9); 423 424 dat = cpu_to_be16(val); 425 ret = ad5933_i2c_write(st->client, 426 AD5933_REG_SETTLING_CYCLES, 427 2, (u8 *)&dat); 428 break; 429 case AD5933_FREQ_POINTS: 430 val = clamp(val, (u16)0, (u16)511); 431 st->freq_points = val; 432 433 dat = cpu_to_be16(val); 434 ret = ad5933_i2c_write(st->client, AD5933_REG_INC_NUM, 2, 435 (u8 *)&dat); 436 break; 437 default: 438 ret = -EINVAL; 439 } 440 441 mutex_unlock(&st->lock); 442 iio_device_release_direct_mode(indio_dev); 443 return ret ? ret : len; 444 } 445 446 static IIO_DEVICE_ATTR(out_altvoltage0_raw, 0644, 447 ad5933_show, 448 ad5933_store, 449 AD5933_OUT_RANGE); 450 451 static IIO_DEVICE_ATTR(out_altvoltage0_scale_available, 0444, 452 ad5933_show, 453 NULL, 454 AD5933_OUT_RANGE_AVAIL); 455 456 static IIO_DEVICE_ATTR(in_voltage0_scale, 0644, 457 ad5933_show, 458 ad5933_store, 459 AD5933_IN_PGA_GAIN); 460 461 static IIO_DEVICE_ATTR(in_voltage0_scale_available, 0444, 462 ad5933_show, 463 NULL, 464 AD5933_IN_PGA_GAIN_AVAIL); 465 466 static IIO_DEVICE_ATTR(out_altvoltage0_frequency_points, 0644, 467 ad5933_show, 468 ad5933_store, 469 AD5933_FREQ_POINTS); 470 471 static IIO_DEVICE_ATTR(out_altvoltage0_settling_cycles, 0644, 472 ad5933_show, 473 ad5933_store, 474 AD5933_OUT_SETTLING_CYCLES); 475 476 /* 477 * note: 478 * ideally we would handle the scale attributes via the iio_info 479 * (read|write)_raw methods, however this part is a untypical since we 480 * don't create dedicated sysfs channel attributes for out0 and in0. 481 */ 482 static struct attribute *ad5933_attributes[] = { 483 &iio_dev_attr_out_altvoltage0_raw.dev_attr.attr, 484 &iio_dev_attr_out_altvoltage0_scale_available.dev_attr.attr, 485 &iio_dev_attr_out_altvoltage0_frequency_start.dev_attr.attr, 486 &iio_dev_attr_out_altvoltage0_frequency_increment.dev_attr.attr, 487 &iio_dev_attr_out_altvoltage0_frequency_points.dev_attr.attr, 488 &iio_dev_attr_out_altvoltage0_settling_cycles.dev_attr.attr, 489 &iio_dev_attr_in_voltage0_scale.dev_attr.attr, 490 &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr, 491 NULL 492 }; 493 494 static const struct attribute_group ad5933_attribute_group = { 495 .attrs = ad5933_attributes, 496 }; 497 498 static int ad5933_read_raw(struct iio_dev *indio_dev, 499 struct iio_chan_spec const *chan, 500 int *val, 501 int *val2, 502 long m) 503 { 504 struct ad5933_state *st = iio_priv(indio_dev); 505 __be16 dat; 506 int ret; 507 508 switch (m) { 509 case IIO_CHAN_INFO_RAW: 510 ret = iio_device_claim_direct_mode(indio_dev); 511 if (ret) 512 return ret; 513 ret = ad5933_cmd(st, AD5933_CTRL_MEASURE_TEMP); 514 if (ret < 0) 515 goto out; 516 ret = ad5933_wait_busy(st, AD5933_STAT_TEMP_VALID); 517 if (ret < 0) 518 goto out; 519 520 ret = ad5933_i2c_read(st->client, 521 AD5933_REG_TEMP_DATA, 522 2, (u8 *)&dat); 523 if (ret < 0) 524 goto out; 525 iio_device_release_direct_mode(indio_dev); 526 *val = sign_extend32(be16_to_cpu(dat), 13); 527 528 return IIO_VAL_INT; 529 case IIO_CHAN_INFO_SCALE: 530 *val = 1000; 531 *val2 = 5; 532 return IIO_VAL_FRACTIONAL_LOG2; 533 } 534 535 return -EINVAL; 536 out: 537 iio_device_release_direct_mode(indio_dev); 538 return ret; 539 } 540 541 static const struct iio_info ad5933_info = { 542 .read_raw = ad5933_read_raw, 543 .attrs = &ad5933_attribute_group, 544 }; 545 546 static int ad5933_ring_preenable(struct iio_dev *indio_dev) 547 { 548 struct ad5933_state *st = iio_priv(indio_dev); 549 int ret; 550 551 if (bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength)) 552 return -EINVAL; 553 554 ret = ad5933_reset(st); 555 if (ret < 0) 556 return ret; 557 558 ret = ad5933_cmd(st, AD5933_CTRL_STANDBY); 559 if (ret < 0) 560 return ret; 561 562 ret = ad5933_cmd(st, AD5933_CTRL_INIT_START_FREQ); 563 if (ret < 0) 564 return ret; 565 566 st->state = AD5933_CTRL_INIT_START_FREQ; 567 568 return 0; 569 } 570 571 static int ad5933_ring_postenable(struct iio_dev *indio_dev) 572 { 573 struct ad5933_state *st = iio_priv(indio_dev); 574 575 /* 576 * AD5933_CTRL_INIT_START_FREQ: 577 * High Q complex circuits require a long time to reach steady state. 578 * To facilitate the measurement of such impedances, this mode allows 579 * the user full control of the settling time requirement before 580 * entering start frequency sweep mode where the impedance measurement 581 * takes place. In this mode the impedance is excited with the 582 * programmed start frequency (ad5933_ring_preenable), 583 * but no measurement takes place. 584 */ 585 586 schedule_delayed_work(&st->work, 587 msecs_to_jiffies(AD5933_INIT_EXCITATION_TIME_ms)); 588 return 0; 589 } 590 591 static int ad5933_ring_postdisable(struct iio_dev *indio_dev) 592 { 593 struct ad5933_state *st = iio_priv(indio_dev); 594 595 cancel_delayed_work_sync(&st->work); 596 return ad5933_cmd(st, AD5933_CTRL_POWER_DOWN); 597 } 598 599 static const struct iio_buffer_setup_ops ad5933_ring_setup_ops = { 600 .preenable = ad5933_ring_preenable, 601 .postenable = ad5933_ring_postenable, 602 .postdisable = ad5933_ring_postdisable, 603 }; 604 605 static int ad5933_register_ring_funcs_and_init(struct iio_dev *indio_dev) 606 { 607 struct iio_buffer *buffer; 608 609 buffer = iio_kfifo_allocate(); 610 if (!buffer) 611 return -ENOMEM; 612 613 iio_device_attach_buffer(indio_dev, buffer); 614 615 /* Ring buffer functions - here trigger setup related */ 616 indio_dev->setup_ops = &ad5933_ring_setup_ops; 617 618 return 0; 619 } 620 621 static void ad5933_work(struct work_struct *work) 622 { 623 struct ad5933_state *st = container_of(work, 624 struct ad5933_state, work.work); 625 struct iio_dev *indio_dev = i2c_get_clientdata(st->client); 626 __be16 buf[2]; 627 int val[2]; 628 unsigned char status; 629 int ret; 630 631 if (st->state == AD5933_CTRL_INIT_START_FREQ) { 632 /* start sweep */ 633 ad5933_cmd(st, AD5933_CTRL_START_SWEEP); 634 st->state = AD5933_CTRL_START_SWEEP; 635 schedule_delayed_work(&st->work, st->poll_time_jiffies); 636 return; 637 } 638 639 ret = ad5933_i2c_read(st->client, AD5933_REG_STATUS, 1, &status); 640 if (ret) 641 return; 642 643 if (status & AD5933_STAT_DATA_VALID) { 644 int scan_count = bitmap_weight(indio_dev->active_scan_mask, 645 indio_dev->masklength); 646 ret = ad5933_i2c_read(st->client, 647 test_bit(1, indio_dev->active_scan_mask) ? 648 AD5933_REG_REAL_DATA : AD5933_REG_IMAG_DATA, 649 scan_count * 2, (u8 *)buf); 650 if (ret) 651 return; 652 653 if (scan_count == 2) { 654 val[0] = be16_to_cpu(buf[0]); 655 val[1] = be16_to_cpu(buf[1]); 656 } else { 657 val[0] = be16_to_cpu(buf[0]); 658 } 659 iio_push_to_buffers(indio_dev, val); 660 } else { 661 /* no data available - try again later */ 662 schedule_delayed_work(&st->work, st->poll_time_jiffies); 663 return; 664 } 665 666 if (status & AD5933_STAT_SWEEP_DONE) { 667 /* 668 * last sample received - power down do 669 * nothing until the ring enable is toggled 670 */ 671 ad5933_cmd(st, AD5933_CTRL_POWER_DOWN); 672 } else { 673 /* we just received a valid datum, move on to the next */ 674 ad5933_cmd(st, AD5933_CTRL_INC_FREQ); 675 schedule_delayed_work(&st->work, st->poll_time_jiffies); 676 } 677 } 678 679 static int ad5933_probe(struct i2c_client *client, 680 const struct i2c_device_id *id) 681 { 682 int ret; 683 struct ad5933_state *st; 684 struct iio_dev *indio_dev; 685 unsigned long ext_clk_hz = 0; 686 687 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*st)); 688 if (!indio_dev) 689 return -ENOMEM; 690 691 st = iio_priv(indio_dev); 692 i2c_set_clientdata(client, indio_dev); 693 st->client = client; 694 695 mutex_init(&st->lock); 696 697 st->reg = devm_regulator_get(&client->dev, "vdd"); 698 if (IS_ERR(st->reg)) 699 return PTR_ERR(st->reg); 700 701 ret = regulator_enable(st->reg); 702 if (ret) { 703 dev_err(&client->dev, "Failed to enable specified VDD supply\n"); 704 return ret; 705 } 706 ret = regulator_get_voltage(st->reg); 707 708 if (ret < 0) 709 goto error_disable_reg; 710 711 st->vref_mv = ret / 1000; 712 713 st->mclk = devm_clk_get(&client->dev, "mclk"); 714 if (IS_ERR(st->mclk) && PTR_ERR(st->mclk) != -ENOENT) { 715 ret = PTR_ERR(st->mclk); 716 goto error_disable_reg; 717 } 718 719 if (!IS_ERR(st->mclk)) { 720 ret = clk_prepare_enable(st->mclk); 721 if (ret < 0) 722 goto error_disable_reg; 723 ext_clk_hz = clk_get_rate(st->mclk); 724 } 725 726 if (ext_clk_hz) { 727 st->mclk_hz = ext_clk_hz; 728 st->ctrl_lb = AD5933_CTRL_EXT_SYSCLK; 729 } else { 730 st->mclk_hz = AD5933_INT_OSC_FREQ_Hz; 731 st->ctrl_lb = AD5933_CTRL_INT_SYSCLK; 732 } 733 734 ad5933_calc_out_ranges(st); 735 INIT_DELAYED_WORK(&st->work, ad5933_work); 736 st->poll_time_jiffies = msecs_to_jiffies(AD5933_POLL_TIME_ms); 737 738 indio_dev->dev.parent = &client->dev; 739 indio_dev->info = &ad5933_info; 740 indio_dev->name = id->name; 741 indio_dev->modes = (INDIO_BUFFER_SOFTWARE | INDIO_DIRECT_MODE); 742 indio_dev->channels = ad5933_channels; 743 indio_dev->num_channels = ARRAY_SIZE(ad5933_channels); 744 745 ret = ad5933_register_ring_funcs_and_init(indio_dev); 746 if (ret) 747 goto error_disable_mclk; 748 749 ret = ad5933_setup(st); 750 if (ret) 751 goto error_unreg_ring; 752 753 ret = iio_device_register(indio_dev); 754 if (ret) 755 goto error_unreg_ring; 756 757 return 0; 758 759 error_unreg_ring: 760 iio_kfifo_free(indio_dev->buffer); 761 error_disable_mclk: 762 clk_disable_unprepare(st->mclk); 763 error_disable_reg: 764 regulator_disable(st->reg); 765 766 return ret; 767 } 768 769 static int ad5933_remove(struct i2c_client *client) 770 { 771 struct iio_dev *indio_dev = i2c_get_clientdata(client); 772 struct ad5933_state *st = iio_priv(indio_dev); 773 774 iio_device_unregister(indio_dev); 775 iio_kfifo_free(indio_dev->buffer); 776 regulator_disable(st->reg); 777 clk_disable_unprepare(st->mclk); 778 779 return 0; 780 } 781 782 static const struct i2c_device_id ad5933_id[] = { 783 { "ad5933", 0 }, 784 { "ad5934", 0 }, 785 {} 786 }; 787 788 MODULE_DEVICE_TABLE(i2c, ad5933_id); 789 790 static const struct of_device_id ad5933_of_match[] = { 791 { .compatible = "adi,ad5933" }, 792 { .compatible = "adi,ad5934" }, 793 { }, 794 }; 795 796 MODULE_DEVICE_TABLE(of, ad5933_of_match); 797 798 static struct i2c_driver ad5933_driver = { 799 .driver = { 800 .name = "ad5933", 801 .of_match_table = ad5933_of_match, 802 }, 803 .probe = ad5933_probe, 804 .remove = ad5933_remove, 805 .id_table = ad5933_id, 806 }; 807 module_i2c_driver(ad5933_driver); 808 809 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 810 MODULE_DESCRIPTION("Analog Devices AD5933 Impedance Conv. Network Analyzer"); 811 MODULE_LICENSE("GPL v2"); 812