1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Support for GalaxyCore GC0310 VGA camera sensor. 4 * 5 * Copyright (c) 2013 Intel Corporation. All Rights Reserved. 6 * Copyright (c) 2023 Hans de Goede <hdegoede@redhat.com> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License version 10 * 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 */ 18 19 #include <linux/delay.h> 20 #include <linux/errno.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/i2c.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/string.h> 27 #include <linux/types.h> 28 29 #include <media/v4l2-ctrls.h> 30 #include <media/v4l2-device.h> 31 32 #define GC0310_NATIVE_WIDTH 656 33 #define GC0310_NATIVE_HEIGHT 496 34 35 #define GC0310_FPS 30 36 #define GC0310_SKIP_FRAMES 3 37 38 #define GC0310_FOCAL_LENGTH_NUM 278 /* 2.78mm */ 39 40 #define GC0310_ID 0xa310 41 42 #define GC0310_RESET_RELATED 0xFE 43 #define GC0310_REGISTER_PAGE_0 0x0 44 #define GC0310_REGISTER_PAGE_3 0x3 45 46 /* 47 * GC0310 System control registers 48 */ 49 #define GC0310_SW_STREAM 0x10 50 51 #define GC0310_SC_CMMN_CHIP_ID_H 0xf0 52 #define GC0310_SC_CMMN_CHIP_ID_L 0xf1 53 54 #define GC0310_AEC_PK_EXPO_H 0x03 55 #define GC0310_AEC_PK_EXPO_L 0x04 56 #define GC0310_AGC_ADJ 0x48 57 #define GC0310_DGC_ADJ 0x71 58 #define GC0310_GROUP_ACCESS 0x3208 59 60 #define GC0310_H_CROP_START_H 0x09 61 #define GC0310_H_CROP_START_L 0x0A 62 #define GC0310_V_CROP_START_H 0x0B 63 #define GC0310_V_CROP_START_L 0x0C 64 #define GC0310_H_OUTSIZE_H 0x0F 65 #define GC0310_H_OUTSIZE_L 0x10 66 #define GC0310_V_OUTSIZE_H 0x0D 67 #define GC0310_V_OUTSIZE_L 0x0E 68 #define GC0310_H_BLANKING_H 0x05 69 #define GC0310_H_BLANKING_L 0x06 70 #define GC0310_V_BLANKING_H 0x07 71 #define GC0310_V_BLANKING_L 0x08 72 #define GC0310_SH_DELAY 0x11 73 74 #define GC0310_START_STREAMING 0x94 /* 8-bit enable */ 75 #define GC0310_STOP_STREAMING 0x0 /* 8-bit disable */ 76 77 #define to_gc0310_sensor(x) container_of(x, struct gc0310_device, sd) 78 79 struct gc0310_device { 80 struct v4l2_subdev sd; 81 struct media_pad pad; 82 /* Protect against concurrent changes to controls */ 83 struct mutex input_lock; 84 bool is_streaming; 85 86 struct gpio_desc *reset; 87 struct gpio_desc *powerdown; 88 89 struct gc0310_mode { 90 struct v4l2_mbus_framefmt fmt; 91 } mode; 92 93 struct gc0310_ctrls { 94 struct v4l2_ctrl_handler handler; 95 struct v4l2_ctrl *exposure; 96 struct v4l2_ctrl *gain; 97 } ctrls; 98 }; 99 100 struct gc0310_reg { 101 u8 reg; 102 u8 val; 103 }; 104 105 static const struct gc0310_reg gc0310_reset_register[] = { 106 /* System registers */ 107 { 0xfe, 0xf0 }, 108 { 0xfe, 0xf0 }, 109 { 0xfe, 0x00 }, 110 111 { 0xfc, 0x0e }, /* 4e */ 112 { 0xfc, 0x0e }, /* 16//4e // [0]apwd [6]regf_clk_gate */ 113 { 0xf2, 0x80 }, /* sync output */ 114 { 0xf3, 0x00 }, /* 1f//01 data output */ 115 { 0xf7, 0x33 }, /* f9 */ 116 { 0xf8, 0x05 }, /* 00 */ 117 { 0xf9, 0x0e }, /* 0x8e //0f */ 118 { 0xfa, 0x11 }, 119 120 /* MIPI */ 121 { 0xfe, 0x03 }, 122 { 0x01, 0x03 }, /* mipi 1lane */ 123 { 0x02, 0x22 }, /* 0x33 */ 124 { 0x03, 0x94 }, 125 { 0x04, 0x01 }, /* fifo_prog */ 126 { 0x05, 0x00 }, /* fifo_prog */ 127 { 0x06, 0x80 }, /* b0 //YUV ISP data */ 128 { 0x11, 0x2a }, /* 1e //LDI set YUV422 */ 129 { 0x12, 0x90 }, /* 00 //04 //00 //04//00 //LWC[7:0] */ 130 { 0x13, 0x02 }, /* 05 //05 //LWC[15:8] */ 131 { 0x15, 0x12 }, /* 0x10 //DPHYY_MODE read_ready */ 132 { 0x17, 0x01 }, 133 { 0x40, 0x08 }, 134 { 0x41, 0x00 }, 135 { 0x42, 0x00 }, 136 { 0x43, 0x00 }, 137 { 0x21, 0x02 }, /* 0x01 */ 138 { 0x22, 0x02 }, /* 0x01 */ 139 { 0x23, 0x01 }, /* 0x05 //Nor:0x05 DOU:0x06 */ 140 { 0x29, 0x00 }, 141 { 0x2A, 0x25 }, /* 0x05 //data zero 0x7a de */ 142 { 0x2B, 0x02 }, 143 144 { 0xfe, 0x00 }, 145 146 /* CISCTL */ 147 { 0x00, 0x2f }, /* 2f//0f//02//01 */ 148 { 0x01, 0x0f }, /* 06 */ 149 { 0x02, 0x04 }, 150 { 0x4f, 0x00 }, /* AEC 0FF */ 151 { 0x03, 0x01 }, /* 0x03 //04 */ 152 { 0x04, 0xc0 }, /* 0xe8 //58 */ 153 { 0x05, 0x00 }, 154 { 0x06, 0xb2 }, /* 0x0a //HB */ 155 { 0x07, 0x00 }, 156 { 0x08, 0x0c }, /* 0x89 //VB */ 157 { 0x09, 0x00 }, /* row start */ 158 { 0x0a, 0x00 }, 159 { 0x0b, 0x00 }, /* col start */ 160 { 0x0c, 0x00 }, 161 { 0x0d, 0x01 }, /* height */ 162 { 0x0e, 0xf2 }, /* 0xf7 //height */ 163 { 0x0f, 0x02 }, /* width */ 164 { 0x10, 0x94 }, /* 0xa0 //height */ 165 { 0x17, 0x14 }, 166 { 0x18, 0x1a }, /* 0a//[4]double reset */ 167 { 0x19, 0x14 }, /* AD pipeline */ 168 { 0x1b, 0x48 }, 169 { 0x1e, 0x6b }, /* 3b//col bias */ 170 { 0x1f, 0x28 }, /* 20//00//08//txlow */ 171 { 0x20, 0x89 }, /* 88//0c//[3:2]DA15 */ 172 { 0x21, 0x49 }, /* 48//[3] txhigh */ 173 { 0x22, 0xb0 }, 174 { 0x23, 0x04 }, /* [1:0]vcm_r */ 175 { 0x24, 0x16 }, /* 15 */ 176 { 0x34, 0x20 }, /* [6:4] rsg high//range */ 177 178 /* BLK */ 179 { 0x26, 0x23 }, /* [1]dark_current_en [0]offset_en */ 180 { 0x28, 0xff }, /* BLK_limie_value */ 181 { 0x29, 0x00 }, /* global offset */ 182 { 0x33, 0x18 }, /* offset_ratio */ 183 { 0x37, 0x20 }, /* dark_current_ratio */ 184 { 0x2a, 0x00 }, 185 { 0x2b, 0x00 }, 186 { 0x2c, 0x00 }, 187 { 0x2d, 0x00 }, 188 { 0x2e, 0x00 }, 189 { 0x2f, 0x00 }, 190 { 0x30, 0x00 }, 191 { 0x31, 0x00 }, 192 { 0x47, 0x80 }, /* a7 */ 193 { 0x4e, 0x66 }, /* select_row */ 194 { 0xa8, 0x02 }, /* win_width_dark, same with crop_win_width */ 195 { 0xa9, 0x80 }, 196 197 /* ISP */ 198 { 0x40, 0x06 }, /* 0xff //ff //48 */ 199 { 0x41, 0x00 }, /* 0x21 //00//[0]curve_en */ 200 { 0x42, 0x04 }, /* 0xcf //0a//[1]awn_en */ 201 { 0x44, 0x18 }, /* 0x18 //02 */ 202 { 0x46, 0x02 }, /* 0x03 //sync */ 203 { 0x49, 0x03 }, 204 { 0x4c, 0x20 }, /* 00[5]pretect exp */ 205 { 0x50, 0x01 }, /* crop enable */ 206 { 0x51, 0x00 }, 207 { 0x52, 0x00 }, 208 { 0x53, 0x00 }, 209 { 0x54, 0x01 }, 210 { 0x55, 0x01 }, /* crop window height */ 211 { 0x56, 0xf0 }, 212 { 0x57, 0x02 }, /* crop window width */ 213 { 0x58, 0x90 }, 214 215 /* Gain */ 216 { 0x70, 0x70 }, /* 70 //80//global gain */ 217 { 0x71, 0x20 }, /* pregain gain */ 218 { 0x72, 0x40 }, /* post gain */ 219 { 0x5a, 0x84 }, /* 84//analog gain 0 */ 220 { 0x5b, 0xc9 }, /* c9 */ 221 { 0x5c, 0xed }, /* ed//not use pga gain highest level */ 222 { 0x77, 0x40 }, /* R gain 0x74 //awb gain */ 223 { 0x78, 0x40 }, /* G gain */ 224 { 0x79, 0x40 }, /* B gain 0x5f */ 225 226 { 0x48, 0x00 }, 227 { 0xfe, 0x01 }, 228 { 0x0a, 0x45 }, /* [7]col gain mode */ 229 230 { 0x3e, 0x40 }, 231 { 0x3f, 0x5c }, 232 { 0x40, 0x7b }, 233 { 0x41, 0xbd }, 234 { 0x42, 0xf6 }, 235 { 0x43, 0x63 }, 236 { 0x03, 0x60 }, 237 { 0x44, 0x03 }, 238 239 /* Dark / Sun mode related */ 240 { 0xfe, 0x01 }, 241 { 0x45, 0xa4 }, /* 0xf7 */ 242 { 0x46, 0xf0 }, /* 0xff //f0//sun value th */ 243 { 0x48, 0x03 }, /* sun mode */ 244 { 0x4f, 0x60 }, /* sun_clamp */ 245 { 0xfe, 0x00 }, 246 }; 247 248 static const struct gc0310_reg gc0310_VGA_30fps[] = { 249 { 0xfe, 0x00 }, 250 { 0x0d, 0x01 }, /* height */ 251 { 0x0e, 0xf2 }, /* 0xf7 //height */ 252 { 0x0f, 0x02 }, /* width */ 253 { 0x10, 0x94 }, /* 0xa0 //height */ 254 255 { 0x50, 0x01 }, /* crop enable */ 256 { 0x51, 0x00 }, 257 { 0x52, 0x00 }, 258 { 0x53, 0x00 }, 259 { 0x54, 0x01 }, 260 { 0x55, 0x01 }, /* crop window height */ 261 { 0x56, 0xf0 }, 262 { 0x57, 0x02 }, /* crop window width */ 263 { 0x58, 0x90 }, 264 265 { 0xfe, 0x03 }, 266 { 0x12, 0x90 }, /* 00 //04 //00 //04//00 //LWC[7:0] */ 267 { 0x13, 0x02 }, /* 05 //05 //LWC[15:8] */ 268 269 { 0xfe, 0x00 }, 270 }; 271 272 /* 273 * gc0310_write_reg_array - Initializes a list of GC0310 registers 274 * @client: i2c driver client structure 275 * @reglist: list of registers to be written 276 * @count: number of register, value pairs in the list 277 */ 278 static int gc0310_write_reg_array(struct i2c_client *client, 279 const struct gc0310_reg *reglist, int count) 280 { 281 int i, err; 282 283 for (i = 0; i < count; i++) { 284 err = i2c_smbus_write_byte_data(client, reglist[i].reg, reglist[i].val); 285 if (err) { 286 dev_err(&client->dev, "write error: wrote 0x%x to offset 0x%x error %d", 287 reglist[i].val, reglist[i].reg, err); 288 return err; 289 } 290 } 291 292 return 0; 293 } 294 295 static int gc0310_exposure_set(struct gc0310_device *dev, u32 exp) 296 { 297 struct i2c_client *client = v4l2_get_subdevdata(&dev->sd); 298 299 return i2c_smbus_write_word_swapped(client, GC0310_AEC_PK_EXPO_H, exp); 300 } 301 302 static int gc0310_gain_set(struct gc0310_device *dev, u32 gain) 303 { 304 struct i2c_client *client = v4l2_get_subdevdata(&dev->sd); 305 u8 again, dgain; 306 int ret; 307 308 /* Taken from original driver, this never sets dgain lower then 32? */ 309 310 /* Change 0 - 95 to 32 - 127 */ 311 gain += 32; 312 313 if (gain < 64) { 314 again = 0x0; /* sqrt(2) */ 315 dgain = gain; 316 } else { 317 again = 0x2; /* 2 * sqrt(2) */ 318 dgain = gain / 2; 319 } 320 321 ret = i2c_smbus_write_byte_data(client, GC0310_AGC_ADJ, again); 322 if (ret) 323 return ret; 324 325 return i2c_smbus_write_byte_data(client, GC0310_DGC_ADJ, dgain); 326 } 327 328 static int gc0310_s_ctrl(struct v4l2_ctrl *ctrl) 329 { 330 struct gc0310_device *dev = 331 container_of(ctrl->handler, struct gc0310_device, ctrls.handler); 332 int ret; 333 334 /* Only apply changes to the controls if the device is powered up */ 335 if (!pm_runtime_get_if_in_use(dev->sd.dev)) 336 return 0; 337 338 switch (ctrl->id) { 339 case V4L2_CID_EXPOSURE: 340 ret = gc0310_exposure_set(dev, ctrl->val); 341 break; 342 case V4L2_CID_GAIN: 343 ret = gc0310_gain_set(dev, ctrl->val); 344 break; 345 default: 346 ret = -EINVAL; 347 break; 348 } 349 350 pm_runtime_put(dev->sd.dev); 351 return ret; 352 } 353 354 static const struct v4l2_ctrl_ops ctrl_ops = { 355 .s_ctrl = gc0310_s_ctrl, 356 }; 357 358 static struct v4l2_mbus_framefmt * 359 gc0310_get_pad_format(struct gc0310_device *dev, 360 struct v4l2_subdev_state *state, 361 unsigned int pad, enum v4l2_subdev_format_whence which) 362 { 363 if (which == V4L2_SUBDEV_FORMAT_TRY) 364 return v4l2_subdev_state_get_format(state, pad); 365 366 return &dev->mode.fmt; 367 } 368 369 /* The GC0310 currently only supports 1 fixed fmt */ 370 static void gc0310_fill_format(struct v4l2_mbus_framefmt *fmt) 371 { 372 memset(fmt, 0, sizeof(*fmt)); 373 fmt->width = GC0310_NATIVE_WIDTH; 374 fmt->height = GC0310_NATIVE_HEIGHT; 375 fmt->field = V4L2_FIELD_NONE; 376 fmt->code = MEDIA_BUS_FMT_SGRBG8_1X8; 377 } 378 379 static int gc0310_set_fmt(struct v4l2_subdev *sd, 380 struct v4l2_subdev_state *sd_state, 381 struct v4l2_subdev_format *format) 382 { 383 struct gc0310_device *dev = to_gc0310_sensor(sd); 384 struct v4l2_mbus_framefmt *fmt; 385 386 fmt = gc0310_get_pad_format(dev, sd_state, format->pad, format->which); 387 gc0310_fill_format(fmt); 388 389 format->format = *fmt; 390 return 0; 391 } 392 393 static int gc0310_get_fmt(struct v4l2_subdev *sd, 394 struct v4l2_subdev_state *sd_state, 395 struct v4l2_subdev_format *format) 396 { 397 struct gc0310_device *dev = to_gc0310_sensor(sd); 398 struct v4l2_mbus_framefmt *fmt; 399 400 fmt = gc0310_get_pad_format(dev, sd_state, format->pad, format->which); 401 format->format = *fmt; 402 return 0; 403 } 404 405 static int gc0310_detect(struct i2c_client *client) 406 { 407 struct i2c_adapter *adapter = client->adapter; 408 int ret; 409 410 if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) 411 return -ENODEV; 412 413 ret = pm_runtime_get_sync(&client->dev); 414 if (ret >= 0) 415 ret = i2c_smbus_read_word_swapped(client, GC0310_SC_CMMN_CHIP_ID_H); 416 pm_runtime_put(&client->dev); 417 if (ret < 0) { 418 dev_err(&client->dev, "read sensor_id failed: %d\n", ret); 419 return -ENODEV; 420 } 421 422 dev_dbg(&client->dev, "sensor ID = 0x%x\n", ret); 423 424 if (ret != GC0310_ID) { 425 dev_err(&client->dev, "sensor ID error, read id = 0x%x, target id = 0x%x\n", 426 ret, GC0310_ID); 427 return -ENODEV; 428 } 429 430 dev_dbg(&client->dev, "detect gc0310 success\n"); 431 432 return 0; 433 } 434 435 static int gc0310_s_stream(struct v4l2_subdev *sd, int enable) 436 { 437 struct gc0310_device *dev = to_gc0310_sensor(sd); 438 struct i2c_client *client = v4l2_get_subdevdata(sd); 439 int ret = 0; 440 441 dev_dbg(&client->dev, "%s S enable=%d\n", __func__, enable); 442 mutex_lock(&dev->input_lock); 443 444 if (enable) { 445 ret = pm_runtime_get_sync(&client->dev); 446 if (ret < 0) 447 goto error_power_down; 448 449 msleep(100); 450 451 ret = gc0310_write_reg_array(client, gc0310_reset_register, 452 ARRAY_SIZE(gc0310_reset_register)); 453 if (ret) 454 goto error_power_down; 455 456 ret = gc0310_write_reg_array(client, gc0310_VGA_30fps, 457 ARRAY_SIZE(gc0310_VGA_30fps)); 458 if (ret) 459 goto error_power_down; 460 461 /* restore value of all ctrls */ 462 ret = __v4l2_ctrl_handler_setup(&dev->ctrls.handler); 463 if (ret) 464 goto error_power_down; 465 466 /* enable per frame MIPI and sensor ctrl reset */ 467 ret = i2c_smbus_write_byte_data(client, 0xFE, 0x30); 468 if (ret) 469 goto error_power_down; 470 } 471 472 ret = i2c_smbus_write_byte_data(client, GC0310_RESET_RELATED, GC0310_REGISTER_PAGE_3); 473 if (ret) 474 goto error_power_down; 475 476 ret = i2c_smbus_write_byte_data(client, GC0310_SW_STREAM, 477 enable ? GC0310_START_STREAMING : GC0310_STOP_STREAMING); 478 if (ret) 479 goto error_power_down; 480 481 ret = i2c_smbus_write_byte_data(client, GC0310_RESET_RELATED, GC0310_REGISTER_PAGE_0); 482 if (ret) 483 goto error_power_down; 484 485 if (!enable) 486 pm_runtime_put(&client->dev); 487 488 dev->is_streaming = enable; 489 mutex_unlock(&dev->input_lock); 490 return 0; 491 492 error_power_down: 493 pm_runtime_put(&client->dev); 494 dev->is_streaming = false; 495 mutex_unlock(&dev->input_lock); 496 return ret; 497 } 498 499 static int gc0310_get_frame_interval(struct v4l2_subdev *sd, 500 struct v4l2_subdev_state *sd_state, 501 struct v4l2_subdev_frame_interval *interval) 502 { 503 /* 504 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2 505 * subdev active state API. 506 */ 507 if (interval->which != V4L2_SUBDEV_FORMAT_ACTIVE) 508 return -EINVAL; 509 510 interval->interval.numerator = 1; 511 interval->interval.denominator = GC0310_FPS; 512 513 return 0; 514 } 515 516 static int gc0310_enum_mbus_code(struct v4l2_subdev *sd, 517 struct v4l2_subdev_state *sd_state, 518 struct v4l2_subdev_mbus_code_enum *code) 519 { 520 /* We support only a single format */ 521 if (code->index) 522 return -EINVAL; 523 524 code->code = MEDIA_BUS_FMT_SGRBG8_1X8; 525 return 0; 526 } 527 528 static int gc0310_enum_frame_size(struct v4l2_subdev *sd, 529 struct v4l2_subdev_state *sd_state, 530 struct v4l2_subdev_frame_size_enum *fse) 531 { 532 /* We support only a single resolution */ 533 if (fse->index) 534 return -EINVAL; 535 536 fse->min_width = GC0310_NATIVE_WIDTH; 537 fse->max_width = GC0310_NATIVE_WIDTH; 538 fse->min_height = GC0310_NATIVE_HEIGHT; 539 fse->max_height = GC0310_NATIVE_HEIGHT; 540 541 return 0; 542 } 543 544 static int gc0310_g_skip_frames(struct v4l2_subdev *sd, u32 *frames) 545 { 546 *frames = GC0310_SKIP_FRAMES; 547 return 0; 548 } 549 550 static const struct v4l2_subdev_sensor_ops gc0310_sensor_ops = { 551 .g_skip_frames = gc0310_g_skip_frames, 552 }; 553 554 static const struct v4l2_subdev_video_ops gc0310_video_ops = { 555 .s_stream = gc0310_s_stream, 556 }; 557 558 static const struct v4l2_subdev_pad_ops gc0310_pad_ops = { 559 .enum_mbus_code = gc0310_enum_mbus_code, 560 .enum_frame_size = gc0310_enum_frame_size, 561 .get_fmt = gc0310_get_fmt, 562 .set_fmt = gc0310_set_fmt, 563 .get_frame_interval = gc0310_get_frame_interval, 564 }; 565 566 static const struct v4l2_subdev_ops gc0310_ops = { 567 .video = &gc0310_video_ops, 568 .pad = &gc0310_pad_ops, 569 .sensor = &gc0310_sensor_ops, 570 }; 571 572 static int gc0310_init_controls(struct gc0310_device *dev) 573 { 574 struct v4l2_ctrl_handler *hdl = &dev->ctrls.handler; 575 576 v4l2_ctrl_handler_init(hdl, 2); 577 578 /* Use the same lock for controls as for everything else */ 579 hdl->lock = &dev->input_lock; 580 dev->sd.ctrl_handler = hdl; 581 582 dev->ctrls.exposure = 583 v4l2_ctrl_new_std(hdl, &ctrl_ops, V4L2_CID_EXPOSURE, 0, 4095, 1, 1023); 584 585 /* 32 steps at base gain 1 + 64 half steps at base gain 2 */ 586 dev->ctrls.gain = 587 v4l2_ctrl_new_std(hdl, &ctrl_ops, V4L2_CID_GAIN, 0, 95, 1, 31); 588 589 return hdl->error; 590 } 591 592 static void gc0310_remove(struct i2c_client *client) 593 { 594 struct v4l2_subdev *sd = i2c_get_clientdata(client); 595 struct gc0310_device *dev = to_gc0310_sensor(sd); 596 597 dev_dbg(&client->dev, "gc0310_remove...\n"); 598 599 v4l2_async_unregister_subdev(sd); 600 media_entity_cleanup(&dev->sd.entity); 601 v4l2_ctrl_handler_free(&dev->ctrls.handler); 602 mutex_destroy(&dev->input_lock); 603 pm_runtime_disable(&client->dev); 604 } 605 606 static int gc0310_probe(struct i2c_client *client) 607 { 608 struct fwnode_handle *ep_fwnode; 609 struct gc0310_device *dev; 610 int ret; 611 612 /* 613 * Sometimes the fwnode graph is initialized by the bridge driver. 614 * Bridge drivers doing this may also add GPIO mappings, wait for this. 615 */ 616 ep_fwnode = fwnode_graph_get_next_endpoint(dev_fwnode(&client->dev), NULL); 617 if (!ep_fwnode) 618 return dev_err_probe(&client->dev, -EPROBE_DEFER, "waiting for fwnode graph endpoint\n"); 619 620 fwnode_handle_put(ep_fwnode); 621 622 dev = devm_kzalloc(&client->dev, sizeof(*dev), GFP_KERNEL); 623 if (!dev) 624 return -ENOMEM; 625 626 dev->reset = devm_gpiod_get(&client->dev, "reset", GPIOD_OUT_HIGH); 627 if (IS_ERR(dev->reset)) { 628 return dev_err_probe(&client->dev, PTR_ERR(dev->reset), 629 "getting reset GPIO\n"); 630 } 631 632 dev->powerdown = devm_gpiod_get(&client->dev, "powerdown", GPIOD_OUT_HIGH); 633 if (IS_ERR(dev->powerdown)) { 634 return dev_err_probe(&client->dev, PTR_ERR(dev->powerdown), 635 "getting powerdown GPIO\n"); 636 } 637 638 mutex_init(&dev->input_lock); 639 v4l2_i2c_subdev_init(&dev->sd, client, &gc0310_ops); 640 gc0310_fill_format(&dev->mode.fmt); 641 642 pm_runtime_set_suspended(&client->dev); 643 pm_runtime_enable(&client->dev); 644 pm_runtime_set_autosuspend_delay(&client->dev, 1000); 645 pm_runtime_use_autosuspend(&client->dev); 646 647 ret = gc0310_detect(client); 648 if (ret) { 649 gc0310_remove(client); 650 return ret; 651 } 652 653 dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 654 dev->pad.flags = MEDIA_PAD_FL_SOURCE; 655 dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 656 657 ret = gc0310_init_controls(dev); 658 if (ret) { 659 gc0310_remove(client); 660 return ret; 661 } 662 663 ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); 664 if (ret) { 665 gc0310_remove(client); 666 return ret; 667 } 668 669 ret = v4l2_async_register_subdev_sensor(&dev->sd); 670 if (ret) { 671 gc0310_remove(client); 672 return ret; 673 } 674 675 return 0; 676 } 677 678 static int gc0310_suspend(struct device *dev) 679 { 680 struct v4l2_subdev *sd = dev_get_drvdata(dev); 681 struct gc0310_device *gc0310_dev = to_gc0310_sensor(sd); 682 683 gpiod_set_value_cansleep(gc0310_dev->powerdown, 1); 684 gpiod_set_value_cansleep(gc0310_dev->reset, 1); 685 return 0; 686 } 687 688 static int gc0310_resume(struct device *dev) 689 { 690 struct v4l2_subdev *sd = dev_get_drvdata(dev); 691 struct gc0310_device *gc0310_dev = to_gc0310_sensor(sd); 692 693 usleep_range(10000, 15000); 694 gpiod_set_value_cansleep(gc0310_dev->reset, 0); 695 usleep_range(10000, 15000); 696 gpiod_set_value_cansleep(gc0310_dev->powerdown, 0); 697 698 return 0; 699 } 700 701 static DEFINE_RUNTIME_DEV_PM_OPS(gc0310_pm_ops, gc0310_suspend, gc0310_resume, NULL); 702 703 static const struct acpi_device_id gc0310_acpi_match[] = { 704 {"INT0310"}, 705 {}, 706 }; 707 MODULE_DEVICE_TABLE(acpi, gc0310_acpi_match); 708 709 static struct i2c_driver gc0310_driver = { 710 .driver = { 711 .name = "gc0310", 712 .pm = pm_sleep_ptr(&gc0310_pm_ops), 713 .acpi_match_table = gc0310_acpi_match, 714 }, 715 .probe = gc0310_probe, 716 .remove = gc0310_remove, 717 }; 718 module_i2c_driver(gc0310_driver); 719 720 MODULE_AUTHOR("Lai, Angie <angie.lai@intel.com>"); 721 MODULE_DESCRIPTION("A low-level driver for GalaxyCore GC0310 sensors"); 722 MODULE_LICENSE("GPL"); 723