1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for OmniVision OV2722 1080p HD camera sensor. 4 * 5 * Copyright (c) 2013 Intel Corporation. All Rights Reserved. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License version 9 * 2 as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * 17 */ 18 19 #ifndef __OV2722_H__ 20 #define __OV2722_H__ 21 #include <linux/kernel.h> 22 #include <linux/types.h> 23 #include <linux/i2c.h> 24 #include <linux/delay.h> 25 #include <linux/videodev2.h> 26 #include <linux/spinlock.h> 27 #include <media/v4l2-subdev.h> 28 #include <media/v4l2-device.h> 29 #include <linux/v4l2-mediabus.h> 30 #include <media/media-entity.h> 31 #include <media/v4l2-ctrls.h> 32 33 #include "../include/linux/atomisp_platform.h" 34 35 #define OV2722_POWER_UP_RETRY_NUM 5 36 37 /* Defines for register writes and register array processing */ 38 #define I2C_MSG_LENGTH 0x2 39 #define I2C_RETRY_COUNT 5 40 41 #define OV2722_FOCAL_LENGTH_NUM 278 /*2.78mm*/ 42 #define OV2722_FOCAL_LENGTH_DEM 100 43 #define OV2722_F_NUMBER_DEFAULT_NUM 26 44 #define OV2722_F_NUMBER_DEM 10 45 46 #define MAX_FMTS 1 47 48 /* 49 * focal length bits definition: 50 * bits 31-16: numerator, bits 15-0: denominator 51 */ 52 #define OV2722_FOCAL_LENGTH_DEFAULT 0x1160064 53 54 /* 55 * current f-number bits definition: 56 * bits 31-16: numerator, bits 15-0: denominator 57 */ 58 #define OV2722_F_NUMBER_DEFAULT 0x1a000a 59 60 /* 61 * f-number range bits definition: 62 * bits 31-24: max f-number numerator 63 * bits 23-16: max f-number denominator 64 * bits 15-8: min f-number numerator 65 * bits 7-0: min f-number denominator 66 */ 67 #define OV2722_F_NUMBER_RANGE 0x1a0a1a0a 68 #define OV2720_ID 0x2720 69 #define OV2722_ID 0x2722 70 71 #define OV2722_FINE_INTG_TIME_MIN 0 72 #define OV2722_FINE_INTG_TIME_MAX_MARGIN 0 73 #define OV2722_COARSE_INTG_TIME_MIN 1 74 #define OV2722_COARSE_INTG_TIME_MAX_MARGIN 4 75 76 /* 77 * OV2722 System control registers 78 */ 79 #define OV2722_SW_SLEEP 0x0100 80 #define OV2722_SW_RESET 0x0103 81 #define OV2722_SW_STREAM 0x0100 82 83 #define OV2722_SC_CMMN_CHIP_ID_H 0x300A 84 #define OV2722_SC_CMMN_CHIP_ID_L 0x300B 85 #define OV2722_SC_CMMN_SCCB_ID 0x300C 86 #define OV2722_SC_CMMN_SUB_ID 0x302A /* process, version*/ 87 88 #define OV2722_SC_CMMN_PAD_OEN0 0x3000 89 #define OV2722_SC_CMMN_PAD_OEN1 0x3001 90 #define OV2722_SC_CMMN_PAD_OEN2 0x3002 91 #define OV2722_SC_CMMN_PAD_OUT0 0x3008 92 #define OV2722_SC_CMMN_PAD_OUT1 0x3009 93 #define OV2722_SC_CMMN_PAD_OUT2 0x300D 94 #define OV2722_SC_CMMN_PAD_SEL0 0x300E 95 #define OV2722_SC_CMMN_PAD_SEL1 0x300F 96 #define OV2722_SC_CMMN_PAD_SEL2 0x3010 97 98 #define OV2722_SC_CMMN_PAD_PK 0x3011 99 #define OV2722_SC_CMMN_A_PWC_PK_O_13 0x3013 100 #define OV2722_SC_CMMN_A_PWC_PK_O_14 0x3014 101 102 #define OV2722_SC_CMMN_CLKRST0 0x301A 103 #define OV2722_SC_CMMN_CLKRST1 0x301B 104 #define OV2722_SC_CMMN_CLKRST2 0x301C 105 #define OV2722_SC_CMMN_CLKRST3 0x301D 106 #define OV2722_SC_CMMN_CLKRST4 0x301E 107 #define OV2722_SC_CMMN_CLKRST5 0x3005 108 #define OV2722_SC_CMMN_PCLK_DIV_CTRL 0x3007 109 #define OV2722_SC_CMMN_CLOCK_SEL 0x3020 110 #define OV2722_SC_SOC_CLKRST5 0x3040 111 112 #define OV2722_SC_CMMN_PLL_CTRL0 0x3034 113 #define OV2722_SC_CMMN_PLL_CTRL1 0x3035 114 #define OV2722_SC_CMMN_PLL_CTRL2 0x3039 115 #define OV2722_SC_CMMN_PLL_CTRL3 0x3037 116 #define OV2722_SC_CMMN_PLL_MULTIPLIER 0x3036 117 #define OV2722_SC_CMMN_PLL_DEBUG_OPT 0x3038 118 #define OV2722_SC_CMMN_PLLS_CTRL0 0x303A 119 #define OV2722_SC_CMMN_PLLS_CTRL1 0x303B 120 #define OV2722_SC_CMMN_PLLS_CTRL2 0x303C 121 #define OV2722_SC_CMMN_PLLS_CTRL3 0x303D 122 123 #define OV2722_SC_CMMN_MIPI_PHY_16 0x3016 124 #define OV2722_SC_CMMN_MIPI_PHY_17 0x3017 125 #define OV2722_SC_CMMN_MIPI_SC_CTRL_18 0x3018 126 #define OV2722_SC_CMMN_MIPI_SC_CTRL_19 0x3019 127 #define OV2722_SC_CMMN_MIPI_SC_CTRL_21 0x3021 128 #define OV2722_SC_CMMN_MIPI_SC_CTRL_22 0x3022 129 130 #define OV2722_AEC_PK_EXPO_H 0x3500 131 #define OV2722_AEC_PK_EXPO_M 0x3501 132 #define OV2722_AEC_PK_EXPO_L 0x3502 133 #define OV2722_AEC_MANUAL_CTRL 0x3503 134 #define OV2722_AGC_ADJ_H 0x3508 135 #define OV2722_AGC_ADJ_L 0x3509 136 #define OV2722_VTS_DIFF_H 0x350c 137 #define OV2722_VTS_DIFF_L 0x350d 138 #define OV2722_GROUP_ACCESS 0x3208 139 #define OV2722_HTS_H 0x380c 140 #define OV2722_HTS_L 0x380d 141 #define OV2722_VTS_H 0x380e 142 #define OV2722_VTS_L 0x380f 143 144 #define OV2722_MWB_GAIN_R_H 0x5186 145 #define OV2722_MWB_GAIN_R_L 0x5187 146 #define OV2722_MWB_GAIN_G_H 0x5188 147 #define OV2722_MWB_GAIN_G_L 0x5189 148 #define OV2722_MWB_GAIN_B_H 0x518a 149 #define OV2722_MWB_GAIN_B_L 0x518b 150 151 #define OV2722_H_CROP_START_H 0x3800 152 #define OV2722_H_CROP_START_L 0x3801 153 #define OV2722_V_CROP_START_H 0x3802 154 #define OV2722_V_CROP_START_L 0x3803 155 #define OV2722_H_CROP_END_H 0x3804 156 #define OV2722_H_CROP_END_L 0x3805 157 #define OV2722_V_CROP_END_H 0x3806 158 #define OV2722_V_CROP_END_L 0x3807 159 #define OV2722_H_OUTSIZE_H 0x3808 160 #define OV2722_H_OUTSIZE_L 0x3809 161 #define OV2722_V_OUTSIZE_H 0x380a 162 #define OV2722_V_OUTSIZE_L 0x380b 163 164 #define OV2722_START_STREAMING 0x01 165 #define OV2722_STOP_STREAMING 0x00 166 167 struct regval_list { 168 u16 reg_num; 169 u8 value; 170 }; 171 172 struct ov2722_resolution { 173 u8 *desc; 174 const struct ov2722_reg *regs; 175 int res; 176 int width; 177 int height; 178 int fps; 179 int pix_clk_freq; 180 u32 skip_frames; 181 u16 pixels_per_line; 182 u16 lines_per_frame; 183 u8 bin_factor_x; 184 u8 bin_factor_y; 185 u8 bin_mode; 186 bool used; 187 int mipi_freq; 188 }; 189 190 struct ov2722_format { 191 u8 *desc; 192 u32 pixelformat; 193 struct ov2722_reg *regs; 194 }; 195 196 /* 197 * ov2722 device structure. 198 */ 199 struct ov2722_device { 200 struct v4l2_subdev sd; 201 struct media_pad pad; 202 struct v4l2_mbus_framefmt format; 203 struct mutex input_lock; 204 struct ov2722_resolution *res; 205 206 struct camera_sensor_platform_data *platform_data; 207 int vt_pix_clk_freq_mhz; 208 int run_mode; 209 u16 pixels_per_line; 210 u16 lines_per_frame; 211 u8 type; 212 213 struct v4l2_ctrl_handler ctrl_handler; 214 struct v4l2_ctrl *link_freq; 215 }; 216 217 enum ov2722_tok_type { 218 OV2722_8BIT = 0x0001, 219 OV2722_16BIT = 0x0002, 220 OV2722_32BIT = 0x0004, 221 OV2722_TOK_TERM = 0xf000, /* terminating token for reg list */ 222 OV2722_TOK_DELAY = 0xfe00, /* delay token for reg list */ 223 OV2722_TOK_MASK = 0xfff0 224 }; 225 226 /** 227 * struct ov2722_reg - MI sensor register format 228 * @type: type of the register 229 * @reg: 16-bit offset to register 230 * @val: 8/16/32-bit register value 231 * 232 * Define a structure for sensor register initialization values 233 */ 234 struct ov2722_reg { 235 enum ov2722_tok_type type; 236 u16 reg; 237 u32 val; /* @set value for read/mod/write, @mask */ 238 }; 239 240 #define to_ov2722_sensor(x) container_of(x, struct ov2722_device, sd) 241 242 #define OV2722_MAX_WRITE_BUF_SIZE 30 243 244 struct ov2722_write_buffer { 245 u16 addr; 246 u8 data[OV2722_MAX_WRITE_BUF_SIZE]; 247 }; 248 249 struct ov2722_write_ctrl { 250 int index; 251 struct ov2722_write_buffer buffer; 252 }; 253 254 /* 255 * Register settings for various resolution 256 */ 257 #if 0 258 static struct ov2722_reg const ov2722_QVGA_30fps[] = { 259 {OV2722_8BIT, 0x3718, 0x10}, 260 {OV2722_8BIT, 0x3702, 0x0c}, 261 {OV2722_8BIT, 0x373a, 0x1c}, 262 {OV2722_8BIT, 0x3715, 0x01}, 263 {OV2722_8BIT, 0x3703, 0x0c}, 264 {OV2722_8BIT, 0x3705, 0x06}, 265 {OV2722_8BIT, 0x3730, 0x0e}, 266 {OV2722_8BIT, 0x3704, 0x1c}, 267 {OV2722_8BIT, 0x3f06, 0x00}, 268 {OV2722_8BIT, 0x371c, 0x00}, 269 {OV2722_8BIT, 0x371d, 0x46}, 270 {OV2722_8BIT, 0x371e, 0x00}, 271 {OV2722_8BIT, 0x371f, 0x63}, 272 {OV2722_8BIT, 0x3708, 0x61}, 273 {OV2722_8BIT, 0x3709, 0x12}, 274 {OV2722_8BIT, 0x3800, 0x01}, 275 {OV2722_8BIT, 0x3801, 0x42}, /* H crop start: 322 */ 276 {OV2722_8BIT, 0x3802, 0x00}, 277 {OV2722_8BIT, 0x3803, 0x20}, /* V crop start: 32 */ 278 {OV2722_8BIT, 0x3804, 0x06}, 279 {OV2722_8BIT, 0x3805, 0x95}, /* H crop end: 1685 */ 280 {OV2722_8BIT, 0x3806, 0x04}, 281 {OV2722_8BIT, 0x3807, 0x27}, /* V crop end: 1063 */ 282 {OV2722_8BIT, 0x3808, 0x01}, 283 {OV2722_8BIT, 0x3809, 0x50}, /* H output size: 336 */ 284 {OV2722_8BIT, 0x380a, 0x01}, 285 {OV2722_8BIT, 0x380b, 0x00}, /* V output size: 256 */ 286 287 /* H blank timing */ 288 {OV2722_8BIT, 0x380c, 0x08}, 289 {OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */ 290 {OV2722_8BIT, 0x380e, 0x04}, 291 {OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */ 292 {OV2722_8BIT, 0x3810, 0x00}, 293 {OV2722_8BIT, 0x3811, 0x04}, /* H window offset: 5 */ 294 {OV2722_8BIT, 0x3812, 0x00}, 295 {OV2722_8BIT, 0x3813, 0x01}, /* V window offset: 2 */ 296 {OV2722_8BIT, 0x3820, 0xc0}, 297 {OV2722_8BIT, 0x3821, 0x06}, /* flip isp*/ 298 {OV2722_8BIT, 0x3814, 0x71}, 299 {OV2722_8BIT, 0x3815, 0x71}, 300 {OV2722_8BIT, 0x3612, 0x49}, 301 {OV2722_8BIT, 0x3618, 0x00}, 302 {OV2722_8BIT, 0x3a08, 0x01}, 303 {OV2722_8BIT, 0x3a09, 0xc3}, 304 {OV2722_8BIT, 0x3a0a, 0x01}, 305 {OV2722_8BIT, 0x3a0b, 0x77}, 306 {OV2722_8BIT, 0x3a0d, 0x00}, 307 {OV2722_8BIT, 0x3a0e, 0x00}, 308 {OV2722_8BIT, 0x4520, 0x09}, 309 {OV2722_8BIT, 0x4837, 0x1b}, 310 {OV2722_8BIT, 0x3000, 0xff}, 311 {OV2722_8BIT, 0x3001, 0xff}, 312 {OV2722_8BIT, 0x3002, 0xf0}, 313 {OV2722_8BIT, 0x3600, 0x08}, 314 {OV2722_8BIT, 0x3621, 0xc0}, 315 {OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */ 316 {OV2722_8BIT, 0x3633, 0x63}, 317 {OV2722_8BIT, 0x3634, 0x24}, 318 {OV2722_8BIT, 0x3f01, 0x0c}, 319 {OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */ 320 {OV2722_8BIT, 0x3614, 0xf0}, 321 {OV2722_8BIT, 0x3630, 0x2d}, 322 {OV2722_8BIT, 0x370b, 0x62}, 323 {OV2722_8BIT, 0x3706, 0x61}, 324 {OV2722_8BIT, 0x4000, 0x02}, 325 {OV2722_8BIT, 0x4002, 0xc5}, 326 {OV2722_8BIT, 0x4005, 0x08}, 327 {OV2722_8BIT, 0x404f, 0x84}, 328 {OV2722_8BIT, 0x4051, 0x00}, 329 {OV2722_8BIT, 0x5000, 0xff}, 330 {OV2722_8BIT, 0x3a18, 0x00}, 331 {OV2722_8BIT, 0x3a19, 0x80}, 332 {OV2722_8BIT, 0x4521, 0x00}, 333 {OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */ 334 {OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */ 335 {OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */ 336 {OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */ 337 {OV2722_8BIT, 0x370c, 0x0c}, 338 {OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */ 339 {OV2722_8BIT, 0x3035, 0x00}, 340 {OV2722_8BIT, 0x3036, 0x26}, 341 {OV2722_8BIT, 0x3037, 0xa1}, 342 {OV2722_8BIT, 0x303e, 0x19}, 343 {OV2722_8BIT, 0x3038, 0x06}, 344 {OV2722_8BIT, 0x3018, 0x04}, 345 346 /* Added for power optimization */ 347 {OV2722_8BIT, 0x3000, 0x00}, 348 {OV2722_8BIT, 0x3001, 0x00}, 349 {OV2722_8BIT, 0x3002, 0x00}, 350 {OV2722_8BIT, 0x3a0f, 0x40}, 351 {OV2722_8BIT, 0x3a10, 0x38}, 352 {OV2722_8BIT, 0x3a1b, 0x48}, 353 {OV2722_8BIT, 0x3a1e, 0x30}, 354 {OV2722_8BIT, 0x3a11, 0x90}, 355 {OV2722_8BIT, 0x3a1f, 0x10}, 356 {OV2722_8BIT, 0x3011, 0x22}, 357 {OV2722_8BIT, 0x3a00, 0x58}, 358 {OV2722_8BIT, 0x3503, 0x17}, 359 {OV2722_8BIT, 0x3500, 0x00}, 360 {OV2722_8BIT, 0x3501, 0x46}, 361 {OV2722_8BIT, 0x3502, 0x00}, 362 {OV2722_8BIT, 0x3508, 0x00}, 363 {OV2722_8BIT, 0x3509, 0x10}, 364 {OV2722_TOK_TERM, 0, 0}, 365 366 }; 367 368 static struct ov2722_reg const ov2722_480P_30fps[] = { 369 {OV2722_8BIT, 0x3718, 0x10}, 370 {OV2722_8BIT, 0x3702, 0x18}, 371 {OV2722_8BIT, 0x373a, 0x3c}, 372 {OV2722_8BIT, 0x3715, 0x01}, 373 {OV2722_8BIT, 0x3703, 0x1d}, 374 {OV2722_8BIT, 0x3705, 0x12}, 375 {OV2722_8BIT, 0x3730, 0x1f}, 376 {OV2722_8BIT, 0x3704, 0x3f}, 377 {OV2722_8BIT, 0x3f06, 0x1d}, 378 {OV2722_8BIT, 0x371c, 0x00}, 379 {OV2722_8BIT, 0x371d, 0x83}, 380 {OV2722_8BIT, 0x371e, 0x00}, 381 {OV2722_8BIT, 0x371f, 0xbd}, 382 {OV2722_8BIT, 0x3708, 0x63}, 383 {OV2722_8BIT, 0x3709, 0x52}, 384 {OV2722_8BIT, 0x3800, 0x00}, 385 {OV2722_8BIT, 0x3801, 0xf2}, /* H crop start: 322 - 80 = 242*/ 386 {OV2722_8BIT, 0x3802, 0x00}, 387 {OV2722_8BIT, 0x3803, 0x20}, /* V crop start: 32*/ 388 {OV2722_8BIT, 0x3804, 0x06}, 389 {OV2722_8BIT, 0x3805, 0xBB}, /* H crop end: 1643 + 80 = 1723*/ 390 {OV2722_8BIT, 0x3806, 0x04}, 391 {OV2722_8BIT, 0x3807, 0x03}, /* V crop end: 1027*/ 392 {OV2722_8BIT, 0x3808, 0x02}, 393 {OV2722_8BIT, 0x3809, 0xE0}, /* H output size: 656 +80 = 736*/ 394 {OV2722_8BIT, 0x380a, 0x01}, 395 {OV2722_8BIT, 0x380b, 0xF0}, /* V output size: 496 */ 396 397 /* H blank timing */ 398 {OV2722_8BIT, 0x380c, 0x08}, 399 {OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */ 400 {OV2722_8BIT, 0x380e, 0x04}, 401 {OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */ 402 {OV2722_8BIT, 0x3810, 0x00}, 403 {OV2722_8BIT, 0x3811, 0x04}, /* H window offset: 5 */ 404 {OV2722_8BIT, 0x3812, 0x00}, 405 {OV2722_8BIT, 0x3813, 0x01}, /* V window offset: 2 */ 406 {OV2722_8BIT, 0x3820, 0x80}, 407 {OV2722_8BIT, 0x3821, 0x06}, /* flip isp*/ 408 {OV2722_8BIT, 0x3814, 0x31}, 409 {OV2722_8BIT, 0x3815, 0x31}, 410 {OV2722_8BIT, 0x3612, 0x4b}, 411 {OV2722_8BIT, 0x3618, 0x04}, 412 {OV2722_8BIT, 0x3a08, 0x02}, 413 {OV2722_8BIT, 0x3a09, 0x67}, 414 {OV2722_8BIT, 0x3a0a, 0x02}, 415 {OV2722_8BIT, 0x3a0b, 0x00}, 416 {OV2722_8BIT, 0x3a0d, 0x00}, 417 {OV2722_8BIT, 0x3a0e, 0x00}, 418 {OV2722_8BIT, 0x4520, 0x0a}, 419 {OV2722_8BIT, 0x4837, 0x1b}, 420 {OV2722_8BIT, 0x3000, 0xff}, 421 {OV2722_8BIT, 0x3001, 0xff}, 422 {OV2722_8BIT, 0x3002, 0xf0}, 423 {OV2722_8BIT, 0x3600, 0x08}, 424 {OV2722_8BIT, 0x3621, 0xc0}, 425 {OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */ 426 {OV2722_8BIT, 0x3633, 0x63}, 427 {OV2722_8BIT, 0x3634, 0x24}, 428 {OV2722_8BIT, 0x3f01, 0x0c}, 429 {OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */ 430 {OV2722_8BIT, 0x3614, 0xf0}, 431 {OV2722_8BIT, 0x3630, 0x2d}, 432 {OV2722_8BIT, 0x370b, 0x62}, 433 {OV2722_8BIT, 0x3706, 0x61}, 434 {OV2722_8BIT, 0x4000, 0x02}, 435 {OV2722_8BIT, 0x4002, 0xc5}, 436 {OV2722_8BIT, 0x4005, 0x08}, 437 {OV2722_8BIT, 0x404f, 0x84}, 438 {OV2722_8BIT, 0x4051, 0x00}, 439 {OV2722_8BIT, 0x5000, 0xff}, 440 {OV2722_8BIT, 0x3a18, 0x00}, 441 {OV2722_8BIT, 0x3a19, 0x80}, 442 {OV2722_8BIT, 0x4521, 0x00}, 443 {OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */ 444 {OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */ 445 {OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */ 446 {OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */ 447 {OV2722_8BIT, 0x370c, 0x0c}, 448 {OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */ 449 {OV2722_8BIT, 0x3035, 0x00}, 450 {OV2722_8BIT, 0x3036, 0x26}, 451 {OV2722_8BIT, 0x3037, 0xa1}, 452 {OV2722_8BIT, 0x303e, 0x19}, 453 {OV2722_8BIT, 0x3038, 0x06}, 454 {OV2722_8BIT, 0x3018, 0x04}, 455 456 /* Added for power optimization */ 457 {OV2722_8BIT, 0x3000, 0x00}, 458 {OV2722_8BIT, 0x3001, 0x00}, 459 {OV2722_8BIT, 0x3002, 0x00}, 460 {OV2722_8BIT, 0x3a0f, 0x40}, 461 {OV2722_8BIT, 0x3a10, 0x38}, 462 {OV2722_8BIT, 0x3a1b, 0x48}, 463 {OV2722_8BIT, 0x3a1e, 0x30}, 464 {OV2722_8BIT, 0x3a11, 0x90}, 465 {OV2722_8BIT, 0x3a1f, 0x10}, 466 {OV2722_8BIT, 0x3011, 0x22}, 467 {OV2722_8BIT, 0x3a00, 0x58}, 468 {OV2722_8BIT, 0x3503, 0x17}, 469 {OV2722_8BIT, 0x3500, 0x00}, 470 {OV2722_8BIT, 0x3501, 0x46}, 471 {OV2722_8BIT, 0x3502, 0x00}, 472 {OV2722_8BIT, 0x3508, 0x00}, 473 {OV2722_8BIT, 0x3509, 0x10}, 474 {OV2722_TOK_TERM, 0, 0}, 475 }; 476 477 static struct ov2722_reg const ov2722_VGA_30fps[] = { 478 {OV2722_8BIT, 0x3718, 0x10}, 479 {OV2722_8BIT, 0x3702, 0x18}, 480 {OV2722_8BIT, 0x373a, 0x3c}, 481 {OV2722_8BIT, 0x3715, 0x01}, 482 {OV2722_8BIT, 0x3703, 0x1d}, 483 {OV2722_8BIT, 0x3705, 0x12}, 484 {OV2722_8BIT, 0x3730, 0x1f}, 485 {OV2722_8BIT, 0x3704, 0x3f}, 486 {OV2722_8BIT, 0x3f06, 0x1d}, 487 {OV2722_8BIT, 0x371c, 0x00}, 488 {OV2722_8BIT, 0x371d, 0x83}, 489 {OV2722_8BIT, 0x371e, 0x00}, 490 {OV2722_8BIT, 0x371f, 0xbd}, 491 {OV2722_8BIT, 0x3708, 0x63}, 492 {OV2722_8BIT, 0x3709, 0x52}, 493 {OV2722_8BIT, 0x3800, 0x01}, 494 {OV2722_8BIT, 0x3801, 0x42}, /* H crop start: 322 */ 495 {OV2722_8BIT, 0x3802, 0x00}, 496 {OV2722_8BIT, 0x3803, 0x20}, /* V crop start: 32*/ 497 {OV2722_8BIT, 0x3804, 0x06}, 498 {OV2722_8BIT, 0x3805, 0x6B}, /* H crop end: 1643*/ 499 {OV2722_8BIT, 0x3806, 0x04}, 500 {OV2722_8BIT, 0x3807, 0x03}, /* V crop end: 1027*/ 501 {OV2722_8BIT, 0x3808, 0x02}, 502 {OV2722_8BIT, 0x3809, 0x90}, /* H output size: 656 */ 503 {OV2722_8BIT, 0x380a, 0x01}, 504 {OV2722_8BIT, 0x380b, 0xF0}, /* V output size: 496 */ 505 506 /* H blank timing */ 507 {OV2722_8BIT, 0x380c, 0x08}, 508 {OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */ 509 {OV2722_8BIT, 0x380e, 0x04}, 510 {OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */ 511 {OV2722_8BIT, 0x3810, 0x00}, 512 {OV2722_8BIT, 0x3811, 0x04}, /* H window offset: 5 */ 513 {OV2722_8BIT, 0x3812, 0x00}, 514 {OV2722_8BIT, 0x3813, 0x01}, /* V window offset: 2 */ 515 {OV2722_8BIT, 0x3820, 0x80}, 516 {OV2722_8BIT, 0x3821, 0x06}, /* flip isp*/ 517 {OV2722_8BIT, 0x3814, 0x31}, 518 {OV2722_8BIT, 0x3815, 0x31}, 519 {OV2722_8BIT, 0x3612, 0x4b}, 520 {OV2722_8BIT, 0x3618, 0x04}, 521 {OV2722_8BIT, 0x3a08, 0x02}, 522 {OV2722_8BIT, 0x3a09, 0x67}, 523 {OV2722_8BIT, 0x3a0a, 0x02}, 524 {OV2722_8BIT, 0x3a0b, 0x00}, 525 {OV2722_8BIT, 0x3a0d, 0x00}, 526 {OV2722_8BIT, 0x3a0e, 0x00}, 527 {OV2722_8BIT, 0x4520, 0x0a}, 528 {OV2722_8BIT, 0x4837, 0x29}, 529 {OV2722_8BIT, 0x3000, 0xff}, 530 {OV2722_8BIT, 0x3001, 0xff}, 531 {OV2722_8BIT, 0x3002, 0xf0}, 532 {OV2722_8BIT, 0x3600, 0x08}, 533 {OV2722_8BIT, 0x3621, 0xc0}, 534 {OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */ 535 {OV2722_8BIT, 0x3633, 0x63}, 536 {OV2722_8BIT, 0x3634, 0x24}, 537 {OV2722_8BIT, 0x3f01, 0x0c}, 538 {OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */ 539 {OV2722_8BIT, 0x3614, 0xf0}, 540 {OV2722_8BIT, 0x3630, 0x2d}, 541 {OV2722_8BIT, 0x370b, 0x62}, 542 {OV2722_8BIT, 0x3706, 0x61}, 543 {OV2722_8BIT, 0x4000, 0x02}, 544 {OV2722_8BIT, 0x4002, 0xc5}, 545 {OV2722_8BIT, 0x4005, 0x08}, 546 {OV2722_8BIT, 0x404f, 0x84}, 547 {OV2722_8BIT, 0x4051, 0x00}, 548 {OV2722_8BIT, 0x5000, 0xff}, 549 {OV2722_8BIT, 0x3a18, 0x00}, 550 {OV2722_8BIT, 0x3a19, 0x80}, 551 {OV2722_8BIT, 0x4521, 0x00}, 552 {OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */ 553 {OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */ 554 {OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */ 555 {OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */ 556 {OV2722_8BIT, 0x370c, 0x0c}, 557 {OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */ 558 {OV2722_8BIT, 0x3035, 0x00}, 559 {OV2722_8BIT, 0x3036, 0x26}, 560 {OV2722_8BIT, 0x3037, 0xa1}, 561 {OV2722_8BIT, 0x303e, 0x19}, 562 {OV2722_8BIT, 0x3038, 0x06}, 563 {OV2722_8BIT, 0x3018, 0x04}, 564 565 /* Added for power optimization */ 566 {OV2722_8BIT, 0x3000, 0x00}, 567 {OV2722_8BIT, 0x3001, 0x00}, 568 {OV2722_8BIT, 0x3002, 0x00}, 569 {OV2722_8BIT, 0x3a0f, 0x40}, 570 {OV2722_8BIT, 0x3a10, 0x38}, 571 {OV2722_8BIT, 0x3a1b, 0x48}, 572 {OV2722_8BIT, 0x3a1e, 0x30}, 573 {OV2722_8BIT, 0x3a11, 0x90}, 574 {OV2722_8BIT, 0x3a1f, 0x10}, 575 {OV2722_8BIT, 0x3011, 0x22}, 576 {OV2722_8BIT, 0x3a00, 0x58}, 577 {OV2722_8BIT, 0x3503, 0x17}, 578 {OV2722_8BIT, 0x3500, 0x00}, 579 {OV2722_8BIT, 0x3501, 0x46}, 580 {OV2722_8BIT, 0x3502, 0x00}, 581 {OV2722_8BIT, 0x3508, 0x00}, 582 {OV2722_8BIT, 0x3509, 0x10}, 583 {OV2722_TOK_TERM, 0, 0}, 584 }; 585 #endif 586 587 static struct ov2722_reg const ov2722_1632_1092_30fps[] = { 588 {OV2722_8BIT, 0x3021, 0x03}, /* For stand wait for 589 a whole frame complete.(vblank) */ 590 {OV2722_8BIT, 0x3718, 0x10}, 591 {OV2722_8BIT, 0x3702, 0x24}, 592 {OV2722_8BIT, 0x373a, 0x60}, 593 {OV2722_8BIT, 0x3715, 0x01}, 594 {OV2722_8BIT, 0x3703, 0x2e}, 595 {OV2722_8BIT, 0x3705, 0x10}, 596 {OV2722_8BIT, 0x3730, 0x30}, 597 {OV2722_8BIT, 0x3704, 0x62}, 598 {OV2722_8BIT, 0x3f06, 0x3a}, 599 {OV2722_8BIT, 0x371c, 0x00}, 600 {OV2722_8BIT, 0x371d, 0xc4}, 601 {OV2722_8BIT, 0x371e, 0x01}, 602 {OV2722_8BIT, 0x371f, 0x0d}, 603 {OV2722_8BIT, 0x3708, 0x61}, 604 {OV2722_8BIT, 0x3709, 0x12}, 605 {OV2722_8BIT, 0x3800, 0x00}, 606 {OV2722_8BIT, 0x3801, 0x9E}, /* H crop start: 158 */ 607 {OV2722_8BIT, 0x3802, 0x00}, 608 {OV2722_8BIT, 0x3803, 0x01}, /* V crop start: 1 */ 609 {OV2722_8BIT, 0x3804, 0x07}, 610 {OV2722_8BIT, 0x3805, 0x05}, /* H crop end: 1797 */ 611 {OV2722_8BIT, 0x3806, 0x04}, 612 {OV2722_8BIT, 0x3807, 0x45}, /* V crop end: 1093 */ 613 614 {OV2722_8BIT, 0x3808, 0x06}, 615 {OV2722_8BIT, 0x3809, 0x60}, /* H output size: 1632 */ 616 {OV2722_8BIT, 0x380a, 0x04}, 617 {OV2722_8BIT, 0x380b, 0x44}, /* V output size: 1092 */ 618 {OV2722_8BIT, 0x380c, 0x08}, 619 {OV2722_8BIT, 0x380d, 0xd4}, /* H timing: 2260 */ 620 {OV2722_8BIT, 0x380e, 0x04}, 621 {OV2722_8BIT, 0x380f, 0xdc}, /* V timing: 1244 */ 622 {OV2722_8BIT, 0x3810, 0x00}, 623 {OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */ 624 {OV2722_8BIT, 0x3812, 0x00}, 625 {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ 626 {OV2722_8BIT, 0x3820, 0x80}, 627 {OV2722_8BIT, 0x3821, 0x06}, /* mirror */ 628 {OV2722_8BIT, 0x3814, 0x11}, 629 {OV2722_8BIT, 0x3815, 0x11}, 630 {OV2722_8BIT, 0x3612, 0x0b}, 631 {OV2722_8BIT, 0x3618, 0x04}, 632 {OV2722_8BIT, 0x3a08, 0x01}, 633 {OV2722_8BIT, 0x3a09, 0x50}, 634 {OV2722_8BIT, 0x3a0a, 0x01}, 635 {OV2722_8BIT, 0x3a0b, 0x18}, 636 {OV2722_8BIT, 0x3a0d, 0x03}, 637 {OV2722_8BIT, 0x3a0e, 0x03}, 638 {OV2722_8BIT, 0x4520, 0x00}, 639 {OV2722_8BIT, 0x4837, 0x1b}, 640 {OV2722_8BIT, 0x3600, 0x08}, 641 {OV2722_8BIT, 0x3621, 0xc0}, 642 {OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */ 643 {OV2722_8BIT, 0x3633, 0x23}, 644 {OV2722_8BIT, 0x3634, 0x54}, 645 {OV2722_8BIT, 0x3f01, 0x0c}, 646 {OV2722_8BIT, 0x5001, 0xc1}, 647 {OV2722_8BIT, 0x3614, 0xf0}, 648 {OV2722_8BIT, 0x3630, 0x2d}, 649 {OV2722_8BIT, 0x370b, 0x62}, 650 {OV2722_8BIT, 0x3706, 0x61}, 651 {OV2722_8BIT, 0x4000, 0x02}, 652 {OV2722_8BIT, 0x4002, 0xc5}, 653 {OV2722_8BIT, 0x4005, 0x08}, 654 {OV2722_8BIT, 0x404f, 0x84}, 655 {OV2722_8BIT, 0x4051, 0x00}, 656 {OV2722_8BIT, 0x5000, 0xcf}, /* manual 3a */ 657 {OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */ 658 {OV2722_8BIT, 0x3a18, 0x00}, 659 {OV2722_8BIT, 0x3a19, 0x80}, 660 {OV2722_8BIT, 0x4521, 0x00}, 661 {OV2722_8BIT, 0x5183, 0xb0}, 662 {OV2722_8BIT, 0x5184, 0xb0}, 663 {OV2722_8BIT, 0x5185, 0xb0}, 664 {OV2722_8BIT, 0x370c, 0x0c}, 665 {OV2722_8BIT, 0x3035, 0x00}, 666 {OV2722_8BIT, 0x3036, 0x2c}, /* 422.4 MHz */ 667 {OV2722_8BIT, 0x3037, 0xa1}, 668 {OV2722_8BIT, 0x303e, 0x19}, 669 {OV2722_8BIT, 0x3038, 0x06}, 670 {OV2722_8BIT, 0x3018, 0x04}, 671 {OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */ 672 {OV2722_8BIT, 0x3001, 0x00}, 673 {OV2722_8BIT, 0x3002, 0x00}, 674 {OV2722_8BIT, 0x3a0f, 0x40}, 675 {OV2722_8BIT, 0x3a10, 0x38}, 676 {OV2722_8BIT, 0x3a1b, 0x48}, 677 {OV2722_8BIT, 0x3a1e, 0x30}, 678 {OV2722_8BIT, 0x3a11, 0x90}, 679 {OV2722_8BIT, 0x3a1f, 0x10}, 680 {OV2722_8BIT, 0x3503, 0x17}, /* manual 3a */ 681 {OV2722_8BIT, 0x3500, 0x00}, 682 {OV2722_8BIT, 0x3501, 0x3F}, 683 {OV2722_8BIT, 0x3502, 0x00}, 684 {OV2722_8BIT, 0x3508, 0x00}, 685 {OV2722_8BIT, 0x3509, 0x00}, 686 {OV2722_TOK_TERM, 0, 0} 687 }; 688 689 static struct ov2722_reg const ov2722_1452_1092_30fps[] = { 690 {OV2722_8BIT, 0x3021, 0x03}, /* For stand wait for 691 a whole frame complete.(vblank) */ 692 {OV2722_8BIT, 0x3718, 0x10}, 693 {OV2722_8BIT, 0x3702, 0x24}, 694 {OV2722_8BIT, 0x373a, 0x60}, 695 {OV2722_8BIT, 0x3715, 0x01}, 696 {OV2722_8BIT, 0x3703, 0x2e}, 697 {OV2722_8BIT, 0x3705, 0x10}, 698 {OV2722_8BIT, 0x3730, 0x30}, 699 {OV2722_8BIT, 0x3704, 0x62}, 700 {OV2722_8BIT, 0x3f06, 0x3a}, 701 {OV2722_8BIT, 0x371c, 0x00}, 702 {OV2722_8BIT, 0x371d, 0xc4}, 703 {OV2722_8BIT, 0x371e, 0x01}, 704 {OV2722_8BIT, 0x371f, 0x0d}, 705 {OV2722_8BIT, 0x3708, 0x61}, 706 {OV2722_8BIT, 0x3709, 0x12}, 707 {OV2722_8BIT, 0x3800, 0x00}, 708 {OV2722_8BIT, 0x3801, 0xF8}, /* H crop start: 248 */ 709 {OV2722_8BIT, 0x3802, 0x00}, 710 {OV2722_8BIT, 0x3803, 0x01}, /* V crop start: 1 */ 711 {OV2722_8BIT, 0x3804, 0x06}, 712 {OV2722_8BIT, 0x3805, 0xab}, /* H crop end: 1707 */ 713 {OV2722_8BIT, 0x3806, 0x04}, 714 {OV2722_8BIT, 0x3807, 0x45}, /* V crop end: 1093 */ 715 {OV2722_8BIT, 0x3808, 0x05}, 716 {OV2722_8BIT, 0x3809, 0xac}, /* H output size: 1452 */ 717 {OV2722_8BIT, 0x380a, 0x04}, 718 {OV2722_8BIT, 0x380b, 0x44}, /* V output size: 1092 */ 719 {OV2722_8BIT, 0x380c, 0x08}, 720 {OV2722_8BIT, 0x380d, 0xd4}, /* H timing: 2260 */ 721 {OV2722_8BIT, 0x380e, 0x04}, 722 {OV2722_8BIT, 0x380f, 0xdc}, /* V timing: 1244 */ 723 {OV2722_8BIT, 0x3810, 0x00}, 724 {OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */ 725 {OV2722_8BIT, 0x3812, 0x00}, 726 {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ 727 {OV2722_8BIT, 0x3820, 0x80}, 728 {OV2722_8BIT, 0x3821, 0x06}, /* mirror */ 729 {OV2722_8BIT, 0x3814, 0x11}, 730 {OV2722_8BIT, 0x3815, 0x11}, 731 {OV2722_8BIT, 0x3612, 0x0b}, 732 {OV2722_8BIT, 0x3618, 0x04}, 733 {OV2722_8BIT, 0x3a08, 0x01}, 734 {OV2722_8BIT, 0x3a09, 0x50}, 735 {OV2722_8BIT, 0x3a0a, 0x01}, 736 {OV2722_8BIT, 0x3a0b, 0x18}, 737 {OV2722_8BIT, 0x3a0d, 0x03}, 738 {OV2722_8BIT, 0x3a0e, 0x03}, 739 {OV2722_8BIT, 0x4520, 0x00}, 740 {OV2722_8BIT, 0x4837, 0x1b}, 741 {OV2722_8BIT, 0x3600, 0x08}, 742 {OV2722_8BIT, 0x3621, 0xc0}, 743 {OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */ 744 {OV2722_8BIT, 0x3633, 0x23}, 745 {OV2722_8BIT, 0x3634, 0x54}, 746 {OV2722_8BIT, 0x3f01, 0x0c}, 747 {OV2722_8BIT, 0x5001, 0xc1}, 748 {OV2722_8BIT, 0x3614, 0xf0}, 749 {OV2722_8BIT, 0x3630, 0x2d}, 750 {OV2722_8BIT, 0x370b, 0x62}, 751 {OV2722_8BIT, 0x3706, 0x61}, 752 {OV2722_8BIT, 0x4000, 0x02}, 753 {OV2722_8BIT, 0x4002, 0xc5}, 754 {OV2722_8BIT, 0x4005, 0x08}, 755 {OV2722_8BIT, 0x404f, 0x84}, 756 {OV2722_8BIT, 0x4051, 0x00}, 757 {OV2722_8BIT, 0x5000, 0xcf}, /* manual 3a */ 758 {OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */ 759 {OV2722_8BIT, 0x3a18, 0x00}, 760 {OV2722_8BIT, 0x3a19, 0x80}, 761 {OV2722_8BIT, 0x4521, 0x00}, 762 {OV2722_8BIT, 0x5183, 0xb0}, 763 {OV2722_8BIT, 0x5184, 0xb0}, 764 {OV2722_8BIT, 0x5185, 0xb0}, 765 {OV2722_8BIT, 0x370c, 0x0c}, 766 {OV2722_8BIT, 0x3035, 0x00}, 767 {OV2722_8BIT, 0x3036, 0x2c}, /* 422.4 MHz */ 768 {OV2722_8BIT, 0x3037, 0xa1}, 769 {OV2722_8BIT, 0x303e, 0x19}, 770 {OV2722_8BIT, 0x3038, 0x06}, 771 {OV2722_8BIT, 0x3018, 0x04}, 772 {OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */ 773 {OV2722_8BIT, 0x3001, 0x00}, 774 {OV2722_8BIT, 0x3002, 0x00}, 775 {OV2722_8BIT, 0x3a0f, 0x40}, 776 {OV2722_8BIT, 0x3a10, 0x38}, 777 {OV2722_8BIT, 0x3a1b, 0x48}, 778 {OV2722_8BIT, 0x3a1e, 0x30}, 779 {OV2722_8BIT, 0x3a11, 0x90}, 780 {OV2722_8BIT, 0x3a1f, 0x10}, 781 {OV2722_8BIT, 0x3503, 0x17}, /* manual 3a */ 782 {OV2722_8BIT, 0x3500, 0x00}, 783 {OV2722_8BIT, 0x3501, 0x3F}, 784 {OV2722_8BIT, 0x3502, 0x00}, 785 {OV2722_8BIT, 0x3508, 0x00}, 786 {OV2722_8BIT, 0x3509, 0x00}, 787 {OV2722_TOK_TERM, 0, 0} 788 }; 789 790 #if 0 791 static struct ov2722_reg const ov2722_1M3_30fps[] = { 792 {OV2722_8BIT, 0x3718, 0x10}, 793 {OV2722_8BIT, 0x3702, 0x24}, 794 {OV2722_8BIT, 0x373a, 0x60}, 795 {OV2722_8BIT, 0x3715, 0x01}, 796 {OV2722_8BIT, 0x3703, 0x2e}, 797 {OV2722_8BIT, 0x3705, 0x10}, 798 {OV2722_8BIT, 0x3730, 0x30}, 799 {OV2722_8BIT, 0x3704, 0x62}, 800 {OV2722_8BIT, 0x3f06, 0x3a}, 801 {OV2722_8BIT, 0x371c, 0x00}, 802 {OV2722_8BIT, 0x371d, 0xc4}, 803 {OV2722_8BIT, 0x371e, 0x01}, 804 {OV2722_8BIT, 0x371f, 0x0d}, 805 {OV2722_8BIT, 0x3708, 0x61}, 806 {OV2722_8BIT, 0x3709, 0x12}, 807 {OV2722_8BIT, 0x3800, 0x01}, 808 {OV2722_8BIT, 0x3801, 0x4a}, /* H crop start: 330 */ 809 {OV2722_8BIT, 0x3802, 0x00}, 810 {OV2722_8BIT, 0x3803, 0x03}, /* V crop start: 3 */ 811 {OV2722_8BIT, 0x3804, 0x06}, 812 {OV2722_8BIT, 0x3805, 0xe1}, /* H crop end: 1761 */ 813 {OV2722_8BIT, 0x3806, 0x04}, 814 {OV2722_8BIT, 0x3807, 0x47}, /* V crop end: 1095 */ 815 {OV2722_8BIT, 0x3808, 0x05}, 816 {OV2722_8BIT, 0x3809, 0x88}, /* H output size: 1416 */ 817 {OV2722_8BIT, 0x380a, 0x04}, 818 {OV2722_8BIT, 0x380b, 0x0a}, /* V output size: 1034 */ 819 820 /* H blank timing */ 821 {OV2722_8BIT, 0x380c, 0x08}, 822 {OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */ 823 {OV2722_8BIT, 0x380e, 0x04}, 824 {OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */ 825 {OV2722_8BIT, 0x3810, 0x00}, 826 {OV2722_8BIT, 0x3811, 0x05}, /* H window offset: 5 */ 827 {OV2722_8BIT, 0x3812, 0x00}, 828 {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ 829 {OV2722_8BIT, 0x3820, 0x80}, 830 {OV2722_8BIT, 0x3821, 0x06}, /* flip isp */ 831 {OV2722_8BIT, 0x3814, 0x11}, 832 {OV2722_8BIT, 0x3815, 0x11}, 833 {OV2722_8BIT, 0x3612, 0x0b}, 834 {OV2722_8BIT, 0x3618, 0x04}, 835 {OV2722_8BIT, 0x3a08, 0x01}, 836 {OV2722_8BIT, 0x3a09, 0x50}, 837 {OV2722_8BIT, 0x3a0a, 0x01}, 838 {OV2722_8BIT, 0x3a0b, 0x18}, 839 {OV2722_8BIT, 0x3a0d, 0x03}, 840 {OV2722_8BIT, 0x3a0e, 0x03}, 841 {OV2722_8BIT, 0x4520, 0x00}, 842 {OV2722_8BIT, 0x4837, 0x1b}, 843 {OV2722_8BIT, 0x3000, 0xff}, 844 {OV2722_8BIT, 0x3001, 0xff}, 845 {OV2722_8BIT, 0x3002, 0xf0}, 846 {OV2722_8BIT, 0x3600, 0x08}, 847 {OV2722_8BIT, 0x3621, 0xc0}, 848 {OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */ 849 {OV2722_8BIT, 0x3633, 0x23}, 850 {OV2722_8BIT, 0x3634, 0x54}, 851 {OV2722_8BIT, 0x3f01, 0x0c}, 852 {OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */ 853 {OV2722_8BIT, 0x3614, 0xf0}, 854 {OV2722_8BIT, 0x3630, 0x2d}, 855 {OV2722_8BIT, 0x370b, 0x62}, 856 {OV2722_8BIT, 0x3706, 0x61}, 857 {OV2722_8BIT, 0x4000, 0x02}, 858 {OV2722_8BIT, 0x4002, 0xc5}, 859 {OV2722_8BIT, 0x4005, 0x08}, 860 {OV2722_8BIT, 0x404f, 0x84}, 861 {OV2722_8BIT, 0x4051, 0x00}, 862 {OV2722_8BIT, 0x5000, 0xcf}, 863 {OV2722_8BIT, 0x3a18, 0x00}, 864 {OV2722_8BIT, 0x3a19, 0x80}, 865 {OV2722_8BIT, 0x4521, 0x00}, 866 {OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */ 867 {OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */ 868 {OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */ 869 {OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */ 870 {OV2722_8BIT, 0x370c, 0x0c}, 871 {OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */ 872 {OV2722_8BIT, 0x3035, 0x00}, 873 {OV2722_8BIT, 0x3036, 0x26}, 874 {OV2722_8BIT, 0x3037, 0xa1}, 875 {OV2722_8BIT, 0x303e, 0x19}, 876 {OV2722_8BIT, 0x3038, 0x06}, 877 {OV2722_8BIT, 0x3018, 0x04}, 878 879 /* Added for power optimization */ 880 {OV2722_8BIT, 0x3000, 0x00}, 881 {OV2722_8BIT, 0x3001, 0x00}, 882 {OV2722_8BIT, 0x3002, 0x00}, 883 {OV2722_8BIT, 0x3a0f, 0x40}, 884 {OV2722_8BIT, 0x3a10, 0x38}, 885 {OV2722_8BIT, 0x3a1b, 0x48}, 886 {OV2722_8BIT, 0x3a1e, 0x30}, 887 {OV2722_8BIT, 0x3a11, 0x90}, 888 {OV2722_8BIT, 0x3a1f, 0x10}, 889 {OV2722_8BIT, 0x3503, 0x17}, 890 {OV2722_8BIT, 0x3500, 0x00}, 891 {OV2722_8BIT, 0x3501, 0x46}, 892 {OV2722_8BIT, 0x3502, 0x00}, 893 {OV2722_8BIT, 0x3508, 0x00}, 894 {OV2722_8BIT, 0x3509, 0x10}, 895 {OV2722_TOK_TERM, 0, 0}, 896 }; 897 #endif 898 899 static struct ov2722_reg const ov2722_1080p_30fps[] = { 900 {OV2722_8BIT, 0x3021, 0x03}, /* For stand wait for a whole 901 frame complete.(vblank) */ 902 {OV2722_8BIT, 0x3718, 0x10}, 903 {OV2722_8BIT, 0x3702, 0x24}, 904 {OV2722_8BIT, 0x373a, 0x60}, 905 {OV2722_8BIT, 0x3715, 0x01}, 906 {OV2722_8BIT, 0x3703, 0x2e}, 907 {OV2722_8BIT, 0x3705, 0x2b}, 908 {OV2722_8BIT, 0x3730, 0x30}, 909 {OV2722_8BIT, 0x3704, 0x62}, 910 {OV2722_8BIT, 0x3f06, 0x3a}, 911 {OV2722_8BIT, 0x371c, 0x00}, 912 {OV2722_8BIT, 0x371d, 0xc4}, 913 {OV2722_8BIT, 0x371e, 0x01}, 914 {OV2722_8BIT, 0x371f, 0x28}, 915 {OV2722_8BIT, 0x3708, 0x61}, 916 {OV2722_8BIT, 0x3709, 0x12}, 917 {OV2722_8BIT, 0x3800, 0x00}, 918 {OV2722_8BIT, 0x3801, 0x08}, /* H crop start: 8 */ 919 {OV2722_8BIT, 0x3802, 0x00}, 920 {OV2722_8BIT, 0x3803, 0x01}, /* V crop start: 1 */ 921 {OV2722_8BIT, 0x3804, 0x07}, 922 {OV2722_8BIT, 0x3805, 0x9b}, /* H crop end: 1947 */ 923 {OV2722_8BIT, 0x3806, 0x04}, 924 {OV2722_8BIT, 0x3807, 0x45}, /* V crop end: 1093 */ 925 {OV2722_8BIT, 0x3808, 0x07}, 926 {OV2722_8BIT, 0x3809, 0x8c}, /* H output size: 1932 */ 927 {OV2722_8BIT, 0x380a, 0x04}, 928 {OV2722_8BIT, 0x380b, 0x44}, /* V output size: 1092 */ 929 {OV2722_8BIT, 0x380c, 0x08}, 930 {OV2722_8BIT, 0x380d, 0x14}, /* H timing: 2068 */ 931 {OV2722_8BIT, 0x380e, 0x04}, 932 {OV2722_8BIT, 0x380f, 0x5a}, /* V timing: 1114 */ 933 {OV2722_8BIT, 0x3810, 0x00}, 934 {OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */ 935 {OV2722_8BIT, 0x3812, 0x00}, 936 {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ 937 {OV2722_8BIT, 0x3820, 0x80}, 938 {OV2722_8BIT, 0x3821, 0x06}, /* mirror */ 939 {OV2722_8BIT, 0x3814, 0x11}, 940 {OV2722_8BIT, 0x3815, 0x11}, 941 {OV2722_8BIT, 0x3612, 0x4b}, 942 {OV2722_8BIT, 0x3618, 0x04}, 943 {OV2722_8BIT, 0x3a08, 0x01}, 944 {OV2722_8BIT, 0x3a09, 0x50}, 945 {OV2722_8BIT, 0x3a0a, 0x01}, 946 {OV2722_8BIT, 0x3a0b, 0x18}, 947 {OV2722_8BIT, 0x3a0d, 0x03}, 948 {OV2722_8BIT, 0x3a0e, 0x03}, 949 {OV2722_8BIT, 0x4520, 0x00}, 950 {OV2722_8BIT, 0x4837, 0x1b}, 951 {OV2722_8BIT, 0x3000, 0xff}, 952 {OV2722_8BIT, 0x3001, 0xff}, 953 {OV2722_8BIT, 0x3002, 0xf0}, 954 {OV2722_8BIT, 0x3600, 0x08}, 955 {OV2722_8BIT, 0x3621, 0xc0}, 956 {OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */ 957 {OV2722_8BIT, 0x3633, 0x63}, 958 {OV2722_8BIT, 0x3634, 0x24}, 959 {OV2722_8BIT, 0x3f01, 0x0c}, 960 {OV2722_8BIT, 0x5001, 0xc1}, 961 {OV2722_8BIT, 0x3614, 0xf0}, 962 {OV2722_8BIT, 0x3630, 0x2d}, 963 {OV2722_8BIT, 0x370b, 0x62}, 964 {OV2722_8BIT, 0x3706, 0x61}, 965 {OV2722_8BIT, 0x4000, 0x02}, 966 {OV2722_8BIT, 0x4002, 0xc5}, 967 {OV2722_8BIT, 0x4005, 0x08}, 968 {OV2722_8BIT, 0x404f, 0x84}, 969 {OV2722_8BIT, 0x4051, 0x00}, 970 {OV2722_8BIT, 0x5000, 0xcd}, /* manual 3a */ 971 {OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */ 972 {OV2722_8BIT, 0x3a18, 0x00}, 973 {OV2722_8BIT, 0x3a19, 0x80}, 974 {OV2722_8BIT, 0x3503, 0x17}, 975 {OV2722_8BIT, 0x4521, 0x00}, 976 {OV2722_8BIT, 0x5183, 0xb0}, 977 {OV2722_8BIT, 0x5184, 0xb0}, 978 {OV2722_8BIT, 0x5185, 0xb0}, 979 {OV2722_8BIT, 0x370c, 0x0c}, 980 {OV2722_8BIT, 0x3035, 0x00}, 981 {OV2722_8BIT, 0x3036, 0x24}, /* 345.6 MHz */ 982 {OV2722_8BIT, 0x3037, 0xa1}, 983 {OV2722_8BIT, 0x303e, 0x19}, 984 {OV2722_8BIT, 0x3038, 0x06}, 985 {OV2722_8BIT, 0x3018, 0x04}, 986 {OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */ 987 {OV2722_8BIT, 0x3001, 0x00}, 988 {OV2722_8BIT, 0x3002, 0x00}, 989 {OV2722_8BIT, 0x3a0f, 0x40}, 990 {OV2722_8BIT, 0x3a10, 0x38}, 991 {OV2722_8BIT, 0x3a1b, 0x48}, 992 {OV2722_8BIT, 0x3a1e, 0x30}, 993 {OV2722_8BIT, 0x3a11, 0x90}, 994 {OV2722_8BIT, 0x3a1f, 0x10}, 995 {OV2722_8BIT, 0x3011, 0x22}, 996 {OV2722_8BIT, 0x3500, 0x00}, 997 {OV2722_8BIT, 0x3501, 0x3F}, 998 {OV2722_8BIT, 0x3502, 0x00}, 999 {OV2722_8BIT, 0x3508, 0x00}, 1000 {OV2722_8BIT, 0x3509, 0x00}, 1001 {OV2722_TOK_TERM, 0, 0} 1002 }; 1003 1004 #if 0 /* Currently unused */ 1005 static struct ov2722_reg const ov2722_720p_30fps[] = { 1006 {OV2722_8BIT, 0x3021, 0x03}, 1007 {OV2722_8BIT, 0x3718, 0x10}, 1008 {OV2722_8BIT, 0x3702, 0x24}, 1009 {OV2722_8BIT, 0x373a, 0x60}, 1010 {OV2722_8BIT, 0x3715, 0x01}, 1011 {OV2722_8BIT, 0x3703, 0x2e}, 1012 {OV2722_8BIT, 0x3705, 0x10}, 1013 {OV2722_8BIT, 0x3730, 0x30}, 1014 {OV2722_8BIT, 0x3704, 0x62}, 1015 {OV2722_8BIT, 0x3f06, 0x3a}, 1016 {OV2722_8BIT, 0x371c, 0x00}, 1017 {OV2722_8BIT, 0x371d, 0xc4}, 1018 {OV2722_8BIT, 0x371e, 0x01}, 1019 {OV2722_8BIT, 0x371f, 0x0d}, 1020 {OV2722_8BIT, 0x3708, 0x61}, 1021 {OV2722_8BIT, 0x3709, 0x12}, 1022 {OV2722_8BIT, 0x3800, 0x01}, 1023 {OV2722_8BIT, 0x3801, 0x40}, /* H crop start: 320 */ 1024 {OV2722_8BIT, 0x3802, 0x00}, 1025 {OV2722_8BIT, 0x3803, 0xb1}, /* V crop start: 177 */ 1026 {OV2722_8BIT, 0x3804, 0x06}, 1027 {OV2722_8BIT, 0x3805, 0x55}, /* H crop end: 1621 */ 1028 {OV2722_8BIT, 0x3806, 0x03}, 1029 {OV2722_8BIT, 0x3807, 0x95}, /* V crop end: 918 */ 1030 {OV2722_8BIT, 0x3808, 0x05}, 1031 {OV2722_8BIT, 0x3809, 0x10}, /* H output size: 0x0788==1928 */ 1032 {OV2722_8BIT, 0x380a, 0x02}, 1033 {OV2722_8BIT, 0x380b, 0xe0}, /* output size: 0x02DE==734 */ 1034 {OV2722_8BIT, 0x380c, 0x08}, 1035 {OV2722_8BIT, 0x380d, 0x00}, /* H timing: 2048 */ 1036 {OV2722_8BIT, 0x380e, 0x04}, 1037 {OV2722_8BIT, 0x380f, 0xa3}, /* V timing: 1187 */ 1038 {OV2722_8BIT, 0x3810, 0x00}, 1039 {OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */ 1040 {OV2722_8BIT, 0x3812, 0x00}, 1041 {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ 1042 {OV2722_8BIT, 0x3820, 0x80}, 1043 {OV2722_8BIT, 0x3821, 0x06}, /* mirror */ 1044 {OV2722_8BIT, 0x3814, 0x11}, 1045 {OV2722_8BIT, 0x3815, 0x11}, 1046 {OV2722_8BIT, 0x3612, 0x0b}, 1047 {OV2722_8BIT, 0x3618, 0x04}, 1048 {OV2722_8BIT, 0x3a08, 0x01}, 1049 {OV2722_8BIT, 0x3a09, 0x50}, 1050 {OV2722_8BIT, 0x3a0a, 0x01}, 1051 {OV2722_8BIT, 0x3a0b, 0x18}, 1052 {OV2722_8BIT, 0x3a0d, 0x03}, 1053 {OV2722_8BIT, 0x3a0e, 0x03}, 1054 {OV2722_8BIT, 0x4520, 0x00}, 1055 {OV2722_8BIT, 0x4837, 0x1b}, 1056 {OV2722_8BIT, 0x3600, 0x08}, 1057 {OV2722_8BIT, 0x3621, 0xc0}, 1058 {OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */ 1059 {OV2722_8BIT, 0x3633, 0x23}, 1060 {OV2722_8BIT, 0x3634, 0x54}, 1061 {OV2722_8BIT, 0x3f01, 0x0c}, 1062 {OV2722_8BIT, 0x5001, 0xc1}, 1063 {OV2722_8BIT, 0x3614, 0xf0}, 1064 {OV2722_8BIT, 0x3630, 0x2d}, 1065 {OV2722_8BIT, 0x370b, 0x62}, 1066 {OV2722_8BIT, 0x3706, 0x61}, 1067 {OV2722_8BIT, 0x4000, 0x02}, 1068 {OV2722_8BIT, 0x4002, 0xc5}, 1069 {OV2722_8BIT, 0x4005, 0x08}, 1070 {OV2722_8BIT, 0x404f, 0x84}, 1071 {OV2722_8BIT, 0x4051, 0x00}, 1072 {OV2722_8BIT, 0x5000, 0xcf}, /* manual 3a */ 1073 {OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */ 1074 {OV2722_8BIT, 0x3a18, 0x00}, 1075 {OV2722_8BIT, 0x3a19, 0x80}, 1076 {OV2722_8BIT, 0x4521, 0x00}, 1077 {OV2722_8BIT, 0x5183, 0xb0}, 1078 {OV2722_8BIT, 0x5184, 0xb0}, 1079 {OV2722_8BIT, 0x5185, 0xb0}, 1080 {OV2722_8BIT, 0x370c, 0x0c}, 1081 {OV2722_8BIT, 0x3035, 0x00}, 1082 {OV2722_8BIT, 0x3036, 0x26}, /* {0x3036, 0x2c}, //422.4 MHz */ 1083 {OV2722_8BIT, 0x3037, 0xa1}, 1084 {OV2722_8BIT, 0x303e, 0x19}, 1085 {OV2722_8BIT, 0x3038, 0x06}, 1086 {OV2722_8BIT, 0x3018, 0x04}, 1087 {OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */ 1088 {OV2722_8BIT, 0x3001, 0x00}, 1089 {OV2722_8BIT, 0x3002, 0x00}, 1090 {OV2722_8BIT, 0x3a0f, 0x40}, 1091 {OV2722_8BIT, 0x3a10, 0x38}, 1092 {OV2722_8BIT, 0x3a1b, 0x48}, 1093 {OV2722_8BIT, 0x3a1e, 0x30}, 1094 {OV2722_8BIT, 0x3a11, 0x90}, 1095 {OV2722_8BIT, 0x3a1f, 0x10}, 1096 {OV2722_8BIT, 0x3503, 0x17}, /* manual 3a */ 1097 {OV2722_8BIT, 0x3500, 0x00}, 1098 {OV2722_8BIT, 0x3501, 0x3F}, 1099 {OV2722_8BIT, 0x3502, 0x00}, 1100 {OV2722_8BIT, 0x3508, 0x00}, 1101 {OV2722_8BIT, 0x3509, 0x00}, 1102 {OV2722_TOK_TERM, 0, 0}, 1103 }; 1104 #endif 1105 1106 static struct ov2722_resolution ov2722_res_preview[] = { 1107 { 1108 .desc = "ov2722_1632_1092_30fps", 1109 .width = 1632, 1110 .height = 1092, 1111 .fps = 30, 1112 .pix_clk_freq = 85, 1113 .used = 0, 1114 .pixels_per_line = 2260, 1115 .lines_per_frame = 1244, 1116 .bin_factor_x = 1, 1117 .bin_factor_y = 1, 1118 .bin_mode = 0, 1119 .skip_frames = 3, 1120 .regs = ov2722_1632_1092_30fps, 1121 .mipi_freq = 422400, 1122 }, 1123 { 1124 .desc = "ov2722_1452_1092_30fps", 1125 .width = 1452, 1126 .height = 1092, 1127 .fps = 30, 1128 .pix_clk_freq = 85, 1129 .used = 0, 1130 .pixels_per_line = 2260, 1131 .lines_per_frame = 1244, 1132 .bin_factor_x = 1, 1133 .bin_factor_y = 1, 1134 .bin_mode = 0, 1135 .skip_frames = 3, 1136 .regs = ov2722_1452_1092_30fps, 1137 .mipi_freq = 422400, 1138 }, 1139 { 1140 .desc = "ov2722_1080P_30fps", 1141 .width = 1932, 1142 .height = 1092, 1143 .pix_clk_freq = 69, 1144 .fps = 30, 1145 .used = 0, 1146 .pixels_per_line = 2068, 1147 .lines_per_frame = 1114, 1148 .bin_factor_x = 1, 1149 .bin_factor_y = 1, 1150 .bin_mode = 0, 1151 .skip_frames = 3, 1152 .regs = ov2722_1080p_30fps, 1153 .mipi_freq = 345600, 1154 }, 1155 }; 1156 1157 #define N_RES_PREVIEW (ARRAY_SIZE(ov2722_res_preview)) 1158 1159 /* 1160 * Disable non-preview configurations until the configuration selection is 1161 * improved. 1162 */ 1163 #if 0 1164 struct ov2722_resolution ov2722_res_still[] = { 1165 { 1166 .desc = "ov2722_480P_30fps", 1167 .width = 1632, 1168 .height = 1092, 1169 .fps = 30, 1170 .pix_clk_freq = 85, 1171 .used = 0, 1172 .pixels_per_line = 2260, 1173 .lines_per_frame = 1244, 1174 .bin_factor_x = 1, 1175 .bin_factor_y = 1, 1176 .bin_mode = 0, 1177 .skip_frames = 3, 1178 .regs = ov2722_1632_1092_30fps, 1179 .mipi_freq = 422400, 1180 }, 1181 { 1182 .desc = "ov2722_1452_1092_30fps", 1183 .width = 1452, 1184 .height = 1092, 1185 .fps = 30, 1186 .pix_clk_freq = 85, 1187 .used = 0, 1188 .pixels_per_line = 2260, 1189 .lines_per_frame = 1244, 1190 .bin_factor_x = 1, 1191 .bin_factor_y = 1, 1192 .bin_mode = 0, 1193 .skip_frames = 3, 1194 .regs = ov2722_1452_1092_30fps, 1195 .mipi_freq = 422400, 1196 }, 1197 { 1198 .desc = "ov2722_1080P_30fps", 1199 .width = 1932, 1200 .height = 1092, 1201 .pix_clk_freq = 69, 1202 .fps = 30, 1203 .used = 0, 1204 .pixels_per_line = 2068, 1205 .lines_per_frame = 1114, 1206 .bin_factor_x = 1, 1207 .bin_factor_y = 1, 1208 .bin_mode = 0, 1209 .skip_frames = 3, 1210 .regs = ov2722_1080p_30fps, 1211 .mipi_freq = 345600, 1212 }, 1213 }; 1214 1215 #define N_RES_STILL (ARRAY_SIZE(ov2722_res_still)) 1216 1217 struct ov2722_resolution ov2722_res_video[] = { 1218 { 1219 .desc = "ov2722_QVGA_30fps", 1220 .width = 336, 1221 .height = 256, 1222 .fps = 30, 1223 .pix_clk_freq = 73, 1224 .used = 0, 1225 .pixels_per_line = 2048, 1226 .lines_per_frame = 1184, 1227 .bin_factor_x = 1, 1228 .bin_factor_y = 1, 1229 .bin_mode = 0, 1230 .skip_frames = 3, 1231 .regs = ov2722_QVGA_30fps, 1232 .mipi_freq = 364800, 1233 }, 1234 { 1235 .desc = "ov2722_480P_30fps", 1236 .width = 736, 1237 .height = 496, 1238 .fps = 30, 1239 .pix_clk_freq = 73, 1240 .used = 0, 1241 .pixels_per_line = 2048, 1242 .lines_per_frame = 1184, 1243 .bin_factor_x = 1, 1244 .bin_factor_y = 1, 1245 .bin_mode = 0, 1246 .skip_frames = 3, 1247 .regs = ov2722_480P_30fps, 1248 }, 1249 { 1250 .desc = "ov2722_1080P_30fps", 1251 .width = 1932, 1252 .height = 1092, 1253 .pix_clk_freq = 69, 1254 .fps = 30, 1255 .used = 0, 1256 .pixels_per_line = 2068, 1257 .lines_per_frame = 1114, 1258 .bin_factor_x = 1, 1259 .bin_factor_y = 1, 1260 .bin_mode = 0, 1261 .skip_frames = 3, 1262 .regs = ov2722_1080p_30fps, 1263 .mipi_freq = 345600, 1264 }, 1265 }; 1266 1267 #define N_RES_VIDEO (ARRAY_SIZE(ov2722_res_video)) 1268 #endif 1269 1270 static struct ov2722_resolution *ov2722_res = ov2722_res_preview; 1271 static unsigned long N_RES = N_RES_PREVIEW; 1272 #endif 1273