1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Support for Medifield PNW Camera Imaging ISP subsystem. 4 * 5 * Copyright (c) 2010-2017 Intel Corporation. All Rights Reserved. 6 * 7 * Copyright (c) 2010 Silicon Hive www.siliconhive.com. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License version 11 * 2 as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * 19 */ 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/pm_qos.h> 24 #include <linux/timer.h> 25 #include <linux/delay.h> 26 #include <linux/dmi.h> 27 #include <linux/interrupt.h> 28 #include <linux/bits.h> 29 30 #include <asm/iosf_mbi.h> 31 32 #include "../../include/linux/atomisp_gmin_platform.h" 33 34 #include "atomisp_cmd.h" 35 #include "atomisp_common.h" 36 #include "atomisp_fops.h" 37 #include "atomisp_ioctl.h" 38 #include "atomisp_internal.h" 39 #include "atomisp-regs.h" 40 #include "atomisp_dfs_tables.h" 41 #include "atomisp_drvfs.h" 42 #include "hmm/hmm.h" 43 #include "atomisp_trace_event.h" 44 45 #include "sh_css_firmware.h" 46 47 #include "device_access.h" 48 49 /* Timeouts to wait for all subdevs to be registered */ 50 #define SUBDEV_WAIT_TIMEOUT 50 /* ms */ 51 #define SUBDEV_WAIT_TIMEOUT_MAX_COUNT 40 /* up to 2 seconds */ 52 53 /* G-Min addition: pull this in from intel_mid_pm.h */ 54 #define CSTATE_EXIT_LATENCY_C1 1 55 56 static uint skip_fwload; 57 module_param(skip_fwload, uint, 0644); 58 MODULE_PARM_DESC(skip_fwload, "Skip atomisp firmware load"); 59 60 /* memory optimization: deferred firmware loading */ 61 bool defer_fw_load; 62 module_param(defer_fw_load, bool, 0644); 63 MODULE_PARM_DESC(defer_fw_load, 64 "Defer FW loading until device is opened (default:disable)"); 65 66 /* cross componnet debug message flag */ 67 int dbg_level; 68 module_param(dbg_level, int, 0644); 69 MODULE_PARM_DESC(dbg_level, "debug message level (default:0)"); 70 71 /* log function switch */ 72 int dbg_func = 2; 73 module_param(dbg_func, int, 0644); 74 MODULE_PARM_DESC(dbg_func, 75 "log function switch non/trace_printk/printk (default:printk)"); 76 77 int mipicsi_flag; 78 module_param(mipicsi_flag, int, 0644); 79 MODULE_PARM_DESC(mipicsi_flag, "mipi csi compression predictor algorithm"); 80 81 static char firmware_name[256]; 82 module_param_string(firmware_name, firmware_name, sizeof(firmware_name), 0); 83 MODULE_PARM_DESC(firmware_name, "Firmware file name. Allows overriding the default firmware name."); 84 85 /*set to 16x16 since this is the amount of lines and pixels the sensor 86 exports extra. If these are kept at the 10x8 that they were on, in yuv 87 downscaling modes incorrect resolutions where requested to the sensor 88 driver with strange outcomes as a result. The proper way tot do this 89 would be to have a list of tables the specify the sensor res, mipi rec, 90 output res, and isp output res. however since we do not have this yet, 91 the chosen solution is the next best thing. */ 92 int pad_w = 16; 93 module_param(pad_w, int, 0644); 94 MODULE_PARM_DESC(pad_w, "extra data for ISP processing"); 95 96 int pad_h = 16; 97 module_param(pad_h, int, 0644); 98 MODULE_PARM_DESC(pad_h, "extra data for ISP processing"); 99 100 /* 101 * FIXME: this is a hack to make easier to support ISP2401 variant. 102 * As a given system will either be ISP2401 or not, we can just use 103 * a boolean, in order to replace existing #ifdef ISP2401 everywhere. 104 * 105 * Once this driver gets into a better shape, however, the best would 106 * be to replace this to something stored inside atomisp allocated 107 * structures. 108 */ 109 110 struct device *atomisp_dev; 111 112 static const struct atomisp_freq_scaling_rule dfs_rules_merr[] = { 113 { 114 .width = ISP_FREQ_RULE_ANY, 115 .height = ISP_FREQ_RULE_ANY, 116 .fps = ISP_FREQ_RULE_ANY, 117 .isp_freq = ISP_FREQ_400MHZ, 118 .run_mode = ATOMISP_RUN_MODE_VIDEO, 119 }, 120 { 121 .width = ISP_FREQ_RULE_ANY, 122 .height = ISP_FREQ_RULE_ANY, 123 .fps = ISP_FREQ_RULE_ANY, 124 .isp_freq = ISP_FREQ_400MHZ, 125 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 126 }, 127 { 128 .width = ISP_FREQ_RULE_ANY, 129 .height = ISP_FREQ_RULE_ANY, 130 .fps = ISP_FREQ_RULE_ANY, 131 .isp_freq = ISP_FREQ_400MHZ, 132 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 133 }, 134 { 135 .width = ISP_FREQ_RULE_ANY, 136 .height = ISP_FREQ_RULE_ANY, 137 .fps = ISP_FREQ_RULE_ANY, 138 .isp_freq = ISP_FREQ_400MHZ, 139 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 140 }, 141 { 142 .width = ISP_FREQ_RULE_ANY, 143 .height = ISP_FREQ_RULE_ANY, 144 .fps = ISP_FREQ_RULE_ANY, 145 .isp_freq = ISP_FREQ_457MHZ, 146 .run_mode = ATOMISP_RUN_MODE_SDV, 147 }, 148 }; 149 150 /* Merrifield and Moorefield DFS rules */ 151 static const struct atomisp_dfs_config dfs_config_merr = { 152 .lowest_freq = ISP_FREQ_200MHZ, 153 .max_freq_at_vmin = ISP_FREQ_400MHZ, 154 .highest_freq = ISP_FREQ_457MHZ, 155 .dfs_table = dfs_rules_merr, 156 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr), 157 }; 158 159 static const struct atomisp_freq_scaling_rule dfs_rules_merr_1179[] = { 160 { 161 .width = ISP_FREQ_RULE_ANY, 162 .height = ISP_FREQ_RULE_ANY, 163 .fps = ISP_FREQ_RULE_ANY, 164 .isp_freq = ISP_FREQ_400MHZ, 165 .run_mode = ATOMISP_RUN_MODE_VIDEO, 166 }, 167 { 168 .width = ISP_FREQ_RULE_ANY, 169 .height = ISP_FREQ_RULE_ANY, 170 .fps = ISP_FREQ_RULE_ANY, 171 .isp_freq = ISP_FREQ_400MHZ, 172 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 173 }, 174 { 175 .width = ISP_FREQ_RULE_ANY, 176 .height = ISP_FREQ_RULE_ANY, 177 .fps = ISP_FREQ_RULE_ANY, 178 .isp_freq = ISP_FREQ_400MHZ, 179 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 180 }, 181 { 182 .width = ISP_FREQ_RULE_ANY, 183 .height = ISP_FREQ_RULE_ANY, 184 .fps = ISP_FREQ_RULE_ANY, 185 .isp_freq = ISP_FREQ_400MHZ, 186 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 187 }, 188 { 189 .width = ISP_FREQ_RULE_ANY, 190 .height = ISP_FREQ_RULE_ANY, 191 .fps = ISP_FREQ_RULE_ANY, 192 .isp_freq = ISP_FREQ_400MHZ, 193 .run_mode = ATOMISP_RUN_MODE_SDV, 194 }, 195 }; 196 197 static const struct atomisp_dfs_config dfs_config_merr_1179 = { 198 .lowest_freq = ISP_FREQ_200MHZ, 199 .max_freq_at_vmin = ISP_FREQ_400MHZ, 200 .highest_freq = ISP_FREQ_400MHZ, 201 .dfs_table = dfs_rules_merr_1179, 202 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_1179), 203 }; 204 205 static const struct atomisp_freq_scaling_rule dfs_rules_merr_117a[] = { 206 { 207 .width = 1920, 208 .height = 1080, 209 .fps = 30, 210 .isp_freq = ISP_FREQ_266MHZ, 211 .run_mode = ATOMISP_RUN_MODE_VIDEO, 212 }, 213 { 214 .width = 1080, 215 .height = 1920, 216 .fps = 30, 217 .isp_freq = ISP_FREQ_266MHZ, 218 .run_mode = ATOMISP_RUN_MODE_VIDEO, 219 }, 220 { 221 .width = 1920, 222 .height = 1080, 223 .fps = 45, 224 .isp_freq = ISP_FREQ_320MHZ, 225 .run_mode = ATOMISP_RUN_MODE_VIDEO, 226 }, 227 { 228 .width = 1080, 229 .height = 1920, 230 .fps = 45, 231 .isp_freq = ISP_FREQ_320MHZ, 232 .run_mode = ATOMISP_RUN_MODE_VIDEO, 233 }, 234 { 235 .width = ISP_FREQ_RULE_ANY, 236 .height = ISP_FREQ_RULE_ANY, 237 .fps = 60, 238 .isp_freq = ISP_FREQ_356MHZ, 239 .run_mode = ATOMISP_RUN_MODE_VIDEO, 240 }, 241 { 242 .width = ISP_FREQ_RULE_ANY, 243 .height = ISP_FREQ_RULE_ANY, 244 .fps = ISP_FREQ_RULE_ANY, 245 .isp_freq = ISP_FREQ_200MHZ, 246 .run_mode = ATOMISP_RUN_MODE_VIDEO, 247 }, 248 { 249 .width = ISP_FREQ_RULE_ANY, 250 .height = ISP_FREQ_RULE_ANY, 251 .fps = ISP_FREQ_RULE_ANY, 252 .isp_freq = ISP_FREQ_400MHZ, 253 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 254 }, 255 { 256 .width = ISP_FREQ_RULE_ANY, 257 .height = ISP_FREQ_RULE_ANY, 258 .fps = ISP_FREQ_RULE_ANY, 259 .isp_freq = ISP_FREQ_400MHZ, 260 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 261 }, 262 { 263 .width = ISP_FREQ_RULE_ANY, 264 .height = ISP_FREQ_RULE_ANY, 265 .fps = ISP_FREQ_RULE_ANY, 266 .isp_freq = ISP_FREQ_200MHZ, 267 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 268 }, 269 { 270 .width = ISP_FREQ_RULE_ANY, 271 .height = ISP_FREQ_RULE_ANY, 272 .fps = ISP_FREQ_RULE_ANY, 273 .isp_freq = ISP_FREQ_400MHZ, 274 .run_mode = ATOMISP_RUN_MODE_SDV, 275 }, 276 }; 277 278 static struct atomisp_dfs_config dfs_config_merr_117a = { 279 .lowest_freq = ISP_FREQ_200MHZ, 280 .max_freq_at_vmin = ISP_FREQ_200MHZ, 281 .highest_freq = ISP_FREQ_400MHZ, 282 .dfs_table = dfs_rules_merr_117a, 283 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_117a), 284 }; 285 286 static const struct atomisp_freq_scaling_rule dfs_rules_byt[] = { 287 { 288 .width = ISP_FREQ_RULE_ANY, 289 .height = ISP_FREQ_RULE_ANY, 290 .fps = ISP_FREQ_RULE_ANY, 291 .isp_freq = ISP_FREQ_400MHZ, 292 .run_mode = ATOMISP_RUN_MODE_VIDEO, 293 }, 294 { 295 .width = ISP_FREQ_RULE_ANY, 296 .height = ISP_FREQ_RULE_ANY, 297 .fps = ISP_FREQ_RULE_ANY, 298 .isp_freq = ISP_FREQ_400MHZ, 299 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 300 }, 301 { 302 .width = ISP_FREQ_RULE_ANY, 303 .height = ISP_FREQ_RULE_ANY, 304 .fps = ISP_FREQ_RULE_ANY, 305 .isp_freq = ISP_FREQ_400MHZ, 306 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 307 }, 308 { 309 .width = ISP_FREQ_RULE_ANY, 310 .height = ISP_FREQ_RULE_ANY, 311 .fps = ISP_FREQ_RULE_ANY, 312 .isp_freq = ISP_FREQ_400MHZ, 313 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 314 }, 315 { 316 .width = ISP_FREQ_RULE_ANY, 317 .height = ISP_FREQ_RULE_ANY, 318 .fps = ISP_FREQ_RULE_ANY, 319 .isp_freq = ISP_FREQ_400MHZ, 320 .run_mode = ATOMISP_RUN_MODE_SDV, 321 }, 322 }; 323 324 static const struct atomisp_dfs_config dfs_config_byt = { 325 .lowest_freq = ISP_FREQ_200MHZ, 326 .max_freq_at_vmin = ISP_FREQ_400MHZ, 327 .highest_freq = ISP_FREQ_400MHZ, 328 .dfs_table = dfs_rules_byt, 329 .dfs_table_size = ARRAY_SIZE(dfs_rules_byt), 330 }; 331 332 static const struct atomisp_freq_scaling_rule dfs_rules_cht[] = { 333 { 334 .width = ISP_FREQ_RULE_ANY, 335 .height = ISP_FREQ_RULE_ANY, 336 .fps = ISP_FREQ_RULE_ANY, 337 .isp_freq = ISP_FREQ_320MHZ, 338 .run_mode = ATOMISP_RUN_MODE_VIDEO, 339 }, 340 { 341 .width = ISP_FREQ_RULE_ANY, 342 .height = ISP_FREQ_RULE_ANY, 343 .fps = ISP_FREQ_RULE_ANY, 344 .isp_freq = ISP_FREQ_356MHZ, 345 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 346 }, 347 { 348 .width = ISP_FREQ_RULE_ANY, 349 .height = ISP_FREQ_RULE_ANY, 350 .fps = ISP_FREQ_RULE_ANY, 351 .isp_freq = ISP_FREQ_320MHZ, 352 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 353 }, 354 { 355 .width = ISP_FREQ_RULE_ANY, 356 .height = ISP_FREQ_RULE_ANY, 357 .fps = ISP_FREQ_RULE_ANY, 358 .isp_freq = ISP_FREQ_320MHZ, 359 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 360 }, 361 { 362 .width = 1280, 363 .height = 720, 364 .fps = ISP_FREQ_RULE_ANY, 365 .isp_freq = ISP_FREQ_320MHZ, 366 .run_mode = ATOMISP_RUN_MODE_SDV, 367 }, 368 { 369 .width = ISP_FREQ_RULE_ANY, 370 .height = ISP_FREQ_RULE_ANY, 371 .fps = ISP_FREQ_RULE_ANY, 372 .isp_freq = ISP_FREQ_356MHZ, 373 .run_mode = ATOMISP_RUN_MODE_SDV, 374 }, 375 }; 376 377 static const struct atomisp_freq_scaling_rule dfs_rules_cht_soc[] = { 378 { 379 .width = ISP_FREQ_RULE_ANY, 380 .height = ISP_FREQ_RULE_ANY, 381 .fps = ISP_FREQ_RULE_ANY, 382 .isp_freq = ISP_FREQ_356MHZ, 383 .run_mode = ATOMISP_RUN_MODE_VIDEO, 384 }, 385 { 386 .width = ISP_FREQ_RULE_ANY, 387 .height = ISP_FREQ_RULE_ANY, 388 .fps = ISP_FREQ_RULE_ANY, 389 .isp_freq = ISP_FREQ_356MHZ, 390 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 391 }, 392 { 393 .width = ISP_FREQ_RULE_ANY, 394 .height = ISP_FREQ_RULE_ANY, 395 .fps = ISP_FREQ_RULE_ANY, 396 .isp_freq = ISP_FREQ_320MHZ, 397 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 398 }, 399 { 400 .width = ISP_FREQ_RULE_ANY, 401 .height = ISP_FREQ_RULE_ANY, 402 .fps = ISP_FREQ_RULE_ANY, 403 .isp_freq = ISP_FREQ_320MHZ, 404 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 405 }, 406 { 407 .width = ISP_FREQ_RULE_ANY, 408 .height = ISP_FREQ_RULE_ANY, 409 .fps = ISP_FREQ_RULE_ANY, 410 .isp_freq = ISP_FREQ_356MHZ, 411 .run_mode = ATOMISP_RUN_MODE_SDV, 412 }, 413 }; 414 415 static const struct atomisp_dfs_config dfs_config_cht = { 416 .lowest_freq = ISP_FREQ_100MHZ, 417 .max_freq_at_vmin = ISP_FREQ_356MHZ, 418 .highest_freq = ISP_FREQ_356MHZ, 419 .dfs_table = dfs_rules_cht, 420 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht), 421 }; 422 423 /* This one should be visible also by atomisp_cmd.c */ 424 const struct atomisp_dfs_config dfs_config_cht_soc = { 425 .lowest_freq = ISP_FREQ_100MHZ, 426 .max_freq_at_vmin = ISP_FREQ_356MHZ, 427 .highest_freq = ISP_FREQ_356MHZ, 428 .dfs_table = dfs_rules_cht_soc, 429 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht_soc), 430 }; 431 432 int atomisp_video_init(struct atomisp_video_pipe *video, const char *name, 433 unsigned int run_mode) 434 { 435 int ret; 436 const char *direction; 437 438 switch (video->type) { 439 case V4L2_BUF_TYPE_VIDEO_CAPTURE: 440 direction = "output"; 441 video->pad.flags = MEDIA_PAD_FL_SINK; 442 video->vdev.fops = &atomisp_fops; 443 video->vdev.ioctl_ops = &atomisp_ioctl_ops; 444 video->vdev.lock = &video->isp->mutex; 445 break; 446 default: 447 return -EINVAL; 448 } 449 450 ret = media_entity_pads_init(&video->vdev.entity, 1, &video->pad); 451 if (ret < 0) 452 return ret; 453 454 /* Initialize the video device. */ 455 snprintf(video->vdev.name, sizeof(video->vdev.name), 456 "ATOMISP ISP %s %s", name, direction); 457 video->vdev.release = video_device_release_empty; 458 video_set_drvdata(&video->vdev, video->isp); 459 video->default_run_mode = run_mode; 460 461 return 0; 462 } 463 464 void atomisp_video_unregister(struct atomisp_video_pipe *video) 465 { 466 if (video_is_registered(&video->vdev)) { 467 media_entity_cleanup(&video->vdev.entity); 468 video_unregister_device(&video->vdev); 469 } 470 } 471 472 static int atomisp_save_iunit_reg(struct atomisp_device *isp) 473 { 474 struct pci_dev *pdev = to_pci_dev(isp->dev); 475 476 dev_dbg(isp->dev, "%s\n", __func__); 477 478 pci_read_config_word(pdev, PCI_COMMAND, &isp->saved_regs.pcicmdsts); 479 /* isp->saved_regs.ispmmadr is set from the atomisp_pci_probe() */ 480 pci_read_config_dword(pdev, PCI_MSI_CAPID, &isp->saved_regs.msicap); 481 pci_read_config_dword(pdev, PCI_MSI_ADDR, &isp->saved_regs.msi_addr); 482 pci_read_config_word(pdev, PCI_MSI_DATA, &isp->saved_regs.msi_data); 483 pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &isp->saved_regs.intr); 484 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &isp->saved_regs.interrupt_control); 485 486 pci_read_config_dword(pdev, MRFLD_PCI_PMCS, &isp->saved_regs.pmcs); 487 /* Ensure read/write combining is enabled. */ 488 pci_read_config_dword(pdev, PCI_I_CONTROL, &isp->saved_regs.i_control); 489 isp->saved_regs.i_control |= 490 MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING | 491 MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING; 492 pci_read_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL, 493 &isp->saved_regs.csi_access_viol); 494 pci_read_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL, 495 &isp->saved_regs.csi_rcomp_config); 496 /* 497 * Hardware bugs require setting CSI_HS_OVR_CLK_GATE_ON_UPDATE. 498 * ANN/CHV: RCOMP updates do not happen when using CSI2+ path 499 * and sensor sending "continuous clock". 500 * TNG/ANN/CHV: MIPI packets are lost if the HS entry sequence 501 * is missed, and IUNIT can hang. 502 * For both issues, setting this bit is a workaround. 503 */ 504 isp->saved_regs.csi_rcomp_config |= MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE; 505 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, 506 &isp->saved_regs.csi_afe_dly); 507 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, 508 &isp->saved_regs.csi_control); 509 if (isp->media_dev.hw_revision >= 510 (ATOMISP_HW_REVISION_ISP2401 << ATOMISP_HW_REVISION_SHIFT)) 511 isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_PARPATHEN; 512 /* 513 * On CHT CSI_READY bit should be enabled before stream on 514 */ 515 if (IS_CHT && (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 << 516 ATOMISP_HW_REVISION_SHIFT) | ATOMISP_HW_STEPPING_B0))) 517 isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_CSI_READY; 518 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL, 519 &isp->saved_regs.csi_afe_rcomp_config); 520 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL, 521 &isp->saved_regs.csi_afe_hs_control); 522 pci_read_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL, 523 &isp->saved_regs.csi_deadline_control); 524 return 0; 525 } 526 527 static int __maybe_unused atomisp_restore_iunit_reg(struct atomisp_device *isp) 528 { 529 struct pci_dev *pdev = to_pci_dev(isp->dev); 530 531 dev_dbg(isp->dev, "%s\n", __func__); 532 533 pci_write_config_word(pdev, PCI_COMMAND, isp->saved_regs.pcicmdsts); 534 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, isp->saved_regs.ispmmadr); 535 pci_write_config_dword(pdev, PCI_MSI_CAPID, isp->saved_regs.msicap); 536 pci_write_config_dword(pdev, PCI_MSI_ADDR, isp->saved_regs.msi_addr); 537 pci_write_config_word(pdev, PCI_MSI_DATA, isp->saved_regs.msi_data); 538 pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, isp->saved_regs.intr); 539 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, isp->saved_regs.interrupt_control); 540 pci_write_config_dword(pdev, PCI_I_CONTROL, isp->saved_regs.i_control); 541 542 pci_write_config_dword(pdev, MRFLD_PCI_PMCS, isp->saved_regs.pmcs); 543 pci_write_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL, 544 isp->saved_regs.csi_access_viol); 545 pci_write_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL, 546 isp->saved_regs.csi_rcomp_config); 547 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, 548 isp->saved_regs.csi_afe_dly); 549 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, 550 isp->saved_regs.csi_control); 551 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL, 552 isp->saved_regs.csi_afe_rcomp_config); 553 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL, 554 isp->saved_regs.csi_afe_hs_control); 555 pci_write_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL, 556 isp->saved_regs.csi_deadline_control); 557 558 /* 559 * for MRFLD, Software/firmware needs to write a 1 to bit0 560 * of the register at CSI_RECEIVER_SELECTION_REG to enable 561 * SH CSI backend write 0 will enable Arasan CSI backend, 562 * which has bugs(like sighting:4567697 and 4567699) and 563 * will be removed in B0 564 */ 565 atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1); 566 return 0; 567 } 568 569 static int atomisp_mrfld_pre_power_down(struct atomisp_device *isp) 570 { 571 struct pci_dev *pdev = to_pci_dev(isp->dev); 572 u32 irq; 573 unsigned long flags; 574 575 spin_lock_irqsave(&isp->lock, flags); 576 if (isp->sw_contex.power_state == ATOM_ISP_POWER_DOWN) { 577 spin_unlock_irqrestore(&isp->lock, flags); 578 dev_dbg(isp->dev, "<%s %d.\n", __func__, __LINE__); 579 return 0; 580 } 581 /* 582 * MRFLD HAS requirement: cannot power off i-unit if 583 * ISP has IRQ not serviced. 584 * So, here we need to check if there is any pending 585 * IRQ, if so, waiting for it to be served 586 */ 587 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 588 irq &= BIT(INTR_IIR); 589 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq); 590 591 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 592 if (!(irq & BIT(INTR_IIR))) 593 goto done; 594 595 atomisp_css2_hw_store_32(MRFLD_INTR_CLEAR_REG, 0xFFFFFFFF); 596 atomisp_load_uint32(MRFLD_INTR_STATUS_REG, &irq); 597 if (irq != 0) { 598 dev_err(isp->dev, 599 "%s: fail to clear isp interrupt status reg=0x%x\n", 600 __func__, irq); 601 spin_unlock_irqrestore(&isp->lock, flags); 602 return -EAGAIN; 603 } else { 604 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 605 irq &= BIT(INTR_IIR); 606 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq); 607 608 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 609 if (!(irq & BIT(INTR_IIR))) { 610 atomisp_css2_hw_store_32(MRFLD_INTR_ENABLE_REG, 0x0); 611 goto done; 612 } 613 dev_err(isp->dev, 614 "%s: error in iunit interrupt. status reg=0x%x\n", 615 __func__, irq); 616 spin_unlock_irqrestore(&isp->lock, flags); 617 return -EAGAIN; 618 } 619 done: 620 /* 621 * MRFLD WORKAROUND: 622 * before powering off IUNIT, clear the pending interrupts 623 * and disable the interrupt. driver should avoid writing 0 624 * to IIR. It could block subsequent interrupt messages. 625 * HW sighting:4568410. 626 */ 627 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 628 irq &= ~BIT(INTR_IER); 629 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq); 630 631 atomisp_msi_irq_uninit(isp); 632 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true); 633 spin_unlock_irqrestore(&isp->lock, flags); 634 635 return 0; 636 } 637 638 /* 639 * WA for DDR DVFS enable/disable 640 * By default, ISP will force DDR DVFS 1600MHz before disable DVFS 641 */ 642 static void punit_ddr_dvfs_enable(bool enable) 643 { 644 int door_bell = 1 << 8; 645 int max_wait = 30; 646 int reg; 647 648 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSDVFS, ®); 649 if (enable) { 650 reg &= ~(MRFLD_BIT0 | MRFLD_BIT1); 651 } else { 652 reg |= (MRFLD_BIT1 | door_bell); 653 reg &= ~(MRFLD_BIT0); 654 } 655 iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE, MRFLD_ISPSSDVFS, reg); 656 657 /* Check Req_ACK to see freq status, wait until door_bell is cleared */ 658 while ((reg & door_bell) && max_wait--) { 659 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSDVFS, ®); 660 usleep_range(100, 500); 661 } 662 663 if (max_wait == -1) 664 pr_info("DDR DVFS, door bell is not cleared within 3ms\n"); 665 } 666 667 static int atomisp_mrfld_power(struct atomisp_device *isp, bool enable) 668 { 669 unsigned long timeout; 670 u32 val = enable ? MRFLD_ISPSSPM0_IUNIT_POWER_ON : 671 MRFLD_ISPSSPM0_IUNIT_POWER_OFF; 672 673 dev_dbg(isp->dev, "IUNIT power-%s.\n", enable ? "on" : "off"); 674 675 /* WA for P-Unit, if DVFS enabled, ISP timeout observed */ 676 if (IS_CHT && enable) 677 punit_ddr_dvfs_enable(false); 678 679 /* 680 * FIXME:WA for ECS28A, with this sleep, CTS 681 * android.hardware.camera2.cts.CameraDeviceTest#testCameraDeviceAbort 682 * PASS, no impact on other platforms 683 */ 684 if (IS_BYT && enable) 685 msleep(10); 686 687 /* Write to ISPSSPM0 bit[1:0] to power on/off the IUNIT */ 688 iosf_mbi_modify(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0, 689 val, MRFLD_ISPSSPM0_ISPSSC_MASK); 690 691 /* WA:Enable DVFS */ 692 if (IS_CHT && !enable) 693 punit_ddr_dvfs_enable(true); 694 695 /* 696 * There should be no IUNIT access while power-down is 697 * in progress. HW sighting: 4567865. 698 * Wait up to 50 ms for the IUNIT to shut down. 699 * And we do the same for power on. 700 */ 701 timeout = jiffies + msecs_to_jiffies(50); 702 do { 703 u32 tmp; 704 705 /* Wait until ISPSSPM0 bit[25:24] shows the right value */ 706 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0, &tmp); 707 tmp = (tmp >> MRFLD_ISPSSPM0_ISPSSS_OFFSET) & MRFLD_ISPSSPM0_ISPSSC_MASK; 708 if (tmp == val) { 709 trace_ipu_cstate(enable); 710 return 0; 711 } 712 713 if (time_after(jiffies, timeout)) 714 break; 715 716 /* FIXME: experienced value for delay */ 717 usleep_range(100, 150); 718 } while (1); 719 720 if (enable) 721 msleep(10); 722 723 dev_err(isp->dev, "IUNIT power-%s timeout.\n", enable ? "on" : "off"); 724 return -EBUSY; 725 } 726 727 /* Workaround for pmu_nc_set_power_state not ready in MRFLD */ 728 int atomisp_mrfld_power_down(struct atomisp_device *isp) 729 { 730 return atomisp_mrfld_power(isp, false); 731 } 732 733 /* Workaround for pmu_nc_set_power_state not ready in MRFLD */ 734 int atomisp_mrfld_power_up(struct atomisp_device *isp) 735 { 736 return atomisp_mrfld_power(isp, true); 737 } 738 739 int atomisp_runtime_suspend(struct device *dev) 740 { 741 struct atomisp_device *isp = (struct atomisp_device *) 742 dev_get_drvdata(dev); 743 int ret; 744 745 ret = atomisp_mrfld_pre_power_down(isp); 746 if (ret) 747 return ret; 748 749 /*Turn off the ISP d-phy*/ 750 ret = atomisp_ospm_dphy_down(isp); 751 if (ret) 752 return ret; 753 cpu_latency_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE); 754 return atomisp_mrfld_power_down(isp); 755 } 756 757 int atomisp_runtime_resume(struct device *dev) 758 { 759 struct atomisp_device *isp = (struct atomisp_device *) 760 dev_get_drvdata(dev); 761 int ret; 762 763 ret = atomisp_mrfld_power_up(isp); 764 if (ret) 765 return ret; 766 767 cpu_latency_qos_update_request(&isp->pm_qos, isp->max_isr_latency); 768 if (isp->sw_contex.power_state == ATOM_ISP_POWER_DOWN) { 769 /*Turn on ISP d-phy */ 770 ret = atomisp_ospm_dphy_up(isp); 771 if (ret) { 772 dev_err(isp->dev, "Failed to power up ISP!.\n"); 773 return -EINVAL; 774 } 775 } 776 777 /*restore register values for iUnit and iUnitPHY registers*/ 778 if (isp->saved_regs.pcicmdsts) 779 atomisp_restore_iunit_reg(isp); 780 781 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true); 782 return 0; 783 } 784 785 static int __maybe_unused atomisp_suspend(struct device *dev) 786 { 787 struct atomisp_device *isp = (struct atomisp_device *) 788 dev_get_drvdata(dev); 789 /* FIXME: only has one isp_subdev at present */ 790 struct atomisp_sub_device *asd = &isp->asd[0]; 791 unsigned long flags; 792 int ret; 793 794 /* 795 * FIXME: Suspend is not supported by sensors. Abort if any video 796 * node was opened. 797 */ 798 if (atomisp_dev_users(isp)) 799 return -EBUSY; 800 801 spin_lock_irqsave(&isp->lock, flags); 802 if (asd->streaming != ATOMISP_DEVICE_STREAMING_DISABLED) { 803 spin_unlock_irqrestore(&isp->lock, flags); 804 dev_err(isp->dev, "atomisp cannot suspend at this time.\n"); 805 return -EINVAL; 806 } 807 spin_unlock_irqrestore(&isp->lock, flags); 808 809 ret = atomisp_mrfld_pre_power_down(isp); 810 if (ret) 811 return ret; 812 813 /*Turn off the ISP d-phy */ 814 ret = atomisp_ospm_dphy_down(isp); 815 if (ret) { 816 dev_err(isp->dev, "fail to power off ISP\n"); 817 return ret; 818 } 819 cpu_latency_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE); 820 return atomisp_mrfld_power_down(isp); 821 } 822 823 static int __maybe_unused atomisp_resume(struct device *dev) 824 { 825 struct atomisp_device *isp = (struct atomisp_device *) 826 dev_get_drvdata(dev); 827 int ret; 828 829 ret = atomisp_mrfld_power_up(isp); 830 if (ret) 831 return ret; 832 833 cpu_latency_qos_update_request(&isp->pm_qos, isp->max_isr_latency); 834 835 /*Turn on ISP d-phy */ 836 ret = atomisp_ospm_dphy_up(isp); 837 if (ret) { 838 dev_err(isp->dev, "Failed to power up ISP!.\n"); 839 return -EINVAL; 840 } 841 842 /*restore register values for iUnit and iUnitPHY registers*/ 843 if (isp->saved_regs.pcicmdsts) 844 atomisp_restore_iunit_reg(isp); 845 846 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true); 847 return 0; 848 } 849 850 int atomisp_csi_lane_config(struct atomisp_device *isp) 851 { 852 struct pci_dev *pdev = to_pci_dev(isp->dev); 853 static const struct { 854 u8 code; 855 u8 lanes[MRFLD_PORT_NUM]; 856 } portconfigs[] = { 857 /* Tangier/Merrifield available lane configurations */ 858 { 0x00, { 4, 1, 0 } }, /* 00000 */ 859 { 0x01, { 3, 1, 0 } }, /* 00001 */ 860 { 0x02, { 2, 1, 0 } }, /* 00010 */ 861 { 0x03, { 1, 1, 0 } }, /* 00011 */ 862 { 0x04, { 2, 1, 2 } }, /* 00100 */ 863 { 0x08, { 3, 1, 1 } }, /* 01000 */ 864 { 0x09, { 2, 1, 1 } }, /* 01001 */ 865 { 0x0a, { 1, 1, 1 } }, /* 01010 */ 866 867 /* Anniedale/Moorefield only configurations */ 868 { 0x10, { 4, 2, 0 } }, /* 10000 */ 869 { 0x11, { 3, 2, 0 } }, /* 10001 */ 870 { 0x12, { 2, 2, 0 } }, /* 10010 */ 871 { 0x13, { 1, 2, 0 } }, /* 10011 */ 872 { 0x14, { 2, 2, 2 } }, /* 10100 */ 873 { 0x18, { 3, 2, 1 } }, /* 11000 */ 874 { 0x19, { 2, 2, 1 } }, /* 11001 */ 875 { 0x1a, { 1, 2, 1 } }, /* 11010 */ 876 }; 877 878 unsigned int i, j; 879 u8 sensor_lanes[MRFLD_PORT_NUM] = { 0 }; 880 u32 csi_control; 881 int nportconfigs; 882 u32 port_config_mask; 883 int port3_lanes_shift; 884 885 if (isp->media_dev.hw_revision < 886 ATOMISP_HW_REVISION_ISP2401_LEGACY << 887 ATOMISP_HW_REVISION_SHIFT) { 888 /* Merrifield */ 889 port_config_mask = MRFLD_PORT_CONFIG_MASK; 890 port3_lanes_shift = MRFLD_PORT3_LANES_SHIFT; 891 } else { 892 /* Moorefield / Cherryview */ 893 port_config_mask = CHV_PORT_CONFIG_MASK; 894 port3_lanes_shift = CHV_PORT3_LANES_SHIFT; 895 } 896 897 if (isp->media_dev.hw_revision < 898 ATOMISP_HW_REVISION_ISP2401 << 899 ATOMISP_HW_REVISION_SHIFT) { 900 /* Merrifield / Moorefield legacy input system */ 901 nportconfigs = MRFLD_PORT_CONFIG_NUM; 902 } else { 903 /* Moorefield / Cherryview new input system */ 904 nportconfigs = ARRAY_SIZE(portconfigs); 905 } 906 907 for (i = 0; i < isp->input_cnt; i++) { 908 struct camera_mipi_info *mipi_info; 909 910 if (isp->inputs[i].type != RAW_CAMERA && 911 isp->inputs[i].type != SOC_CAMERA) 912 continue; 913 914 mipi_info = atomisp_to_sensor_mipi_info(isp->inputs[i].camera); 915 if (!mipi_info) 916 continue; 917 918 switch (mipi_info->port) { 919 case ATOMISP_CAMERA_PORT_PRIMARY: 920 sensor_lanes[0] = mipi_info->num_lanes; 921 break; 922 case ATOMISP_CAMERA_PORT_SECONDARY: 923 sensor_lanes[1] = mipi_info->num_lanes; 924 break; 925 case ATOMISP_CAMERA_PORT_TERTIARY: 926 sensor_lanes[2] = mipi_info->num_lanes; 927 break; 928 default: 929 dev_err(isp->dev, 930 "%s: invalid port: %d for the %dth sensor\n", 931 __func__, mipi_info->port, i); 932 return -EINVAL; 933 } 934 } 935 936 for (i = 0; i < nportconfigs; i++) { 937 for (j = 0; j < MRFLD_PORT_NUM; j++) 938 if (sensor_lanes[j] && 939 sensor_lanes[j] != portconfigs[i].lanes[j]) 940 break; 941 942 if (j == MRFLD_PORT_NUM) 943 break; /* Found matching setting */ 944 } 945 946 if (i >= nportconfigs) { 947 dev_err(isp->dev, 948 "%s: could not find the CSI port setting for %d-%d-%d\n", 949 __func__, 950 sensor_lanes[0], sensor_lanes[1], sensor_lanes[2]); 951 return -EINVAL; 952 } 953 954 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, &csi_control); 955 csi_control &= ~port_config_mask; 956 csi_control |= (portconfigs[i].code << MRFLD_PORT_CONFIGCODE_SHIFT) 957 | (portconfigs[i].lanes[0] ? 0 : (1 << MRFLD_PORT1_ENABLE_SHIFT)) 958 | (portconfigs[i].lanes[1] ? 0 : (1 << MRFLD_PORT2_ENABLE_SHIFT)) 959 | (portconfigs[i].lanes[2] ? 0 : (1 << MRFLD_PORT3_ENABLE_SHIFT)) 960 | (((1 << portconfigs[i].lanes[0]) - 1) << MRFLD_PORT1_LANES_SHIFT) 961 | (((1 << portconfigs[i].lanes[1]) - 1) << MRFLD_PORT2_LANES_SHIFT) 962 | (((1 << portconfigs[i].lanes[2]) - 1) << port3_lanes_shift); 963 964 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, csi_control); 965 966 dev_dbg(isp->dev, 967 "%s: the portconfig is %d-%d-%d, CSI_CONTROL is 0x%08X\n", 968 __func__, portconfigs[i].lanes[0], portconfigs[i].lanes[1], 969 portconfigs[i].lanes[2], csi_control); 970 971 return 0; 972 } 973 974 static int atomisp_subdev_probe(struct atomisp_device *isp) 975 { 976 const struct atomisp_platform_data *pdata; 977 struct intel_v4l2_subdev_table *subdevs; 978 int ret, raw_index = -1, count; 979 980 pdata = atomisp_get_platform_data(); 981 if (!pdata) { 982 dev_err(isp->dev, "no platform data available\n"); 983 return 0; 984 } 985 986 /* FIXME: should return -EPROBE_DEFER if not all subdevs were probed */ 987 for (count = 0; count < SUBDEV_WAIT_TIMEOUT_MAX_COUNT; count++) { 988 int camera_count = 0; 989 990 for (subdevs = pdata->subdevs; subdevs->type; ++subdevs) { 991 if (subdevs->type == RAW_CAMERA || 992 subdevs->type == SOC_CAMERA) 993 camera_count++; 994 } 995 if (camera_count) 996 break; 997 msleep(SUBDEV_WAIT_TIMEOUT); 998 } 999 /* Wait more time to give more time for subdev init code to finish */ 1000 msleep(5 * SUBDEV_WAIT_TIMEOUT); 1001 1002 /* FIXME: should, instead, use I2C probe */ 1003 1004 for (subdevs = pdata->subdevs; subdevs->type; ++subdevs) { 1005 struct v4l2_subdev *subdev; 1006 struct i2c_board_info *board_info = 1007 &subdevs->v4l2_subdev.board_info; 1008 struct i2c_adapter *adapter = 1009 i2c_get_adapter(subdevs->v4l2_subdev.i2c_adapter_id); 1010 1011 dev_info(isp->dev, "Probing Subdev %s\n", board_info->type); 1012 1013 if (!adapter) { 1014 dev_err(isp->dev, 1015 "Failed to find i2c adapter for subdev %s\n", 1016 board_info->type); 1017 break; 1018 } 1019 1020 /* In G-Min, the sensor devices will already be probed 1021 * (via ACPI) and registered, do not create new 1022 * ones */ 1023 subdev = atomisp_gmin_find_subdev(adapter, board_info); 1024 if (!subdev) { 1025 dev_warn(isp->dev, "Subdev %s not found\n", 1026 board_info->type); 1027 continue; 1028 } 1029 ret = v4l2_device_register_subdev(&isp->v4l2_dev, subdev); 1030 if (ret) { 1031 dev_warn(isp->dev, "Subdev %s detection fail\n", 1032 board_info->type); 1033 continue; 1034 } 1035 1036 if (!subdev) { 1037 dev_warn(isp->dev, "Subdev %s detection fail\n", 1038 board_info->type); 1039 continue; 1040 } 1041 1042 dev_info(isp->dev, "Subdev %s successfully register\n", 1043 board_info->type); 1044 1045 switch (subdevs->type) { 1046 case RAW_CAMERA: 1047 dev_dbg(isp->dev, "raw_index: %d\n", raw_index); 1048 raw_index = isp->input_cnt; 1049 fallthrough; 1050 case SOC_CAMERA: 1051 dev_dbg(isp->dev, "SOC_INDEX: %d\n", isp->input_cnt); 1052 if (isp->input_cnt >= ATOM_ISP_MAX_INPUTS) { 1053 dev_warn(isp->dev, 1054 "too many atomisp inputs, ignored\n"); 1055 break; 1056 } 1057 1058 isp->inputs[isp->input_cnt].type = subdevs->type; 1059 isp->inputs[isp->input_cnt].port = subdevs->port; 1060 isp->inputs[isp->input_cnt].camera = subdev; 1061 isp->inputs[isp->input_cnt].sensor_index = 0; 1062 /* 1063 * initialize the subdev frame size, then next we can 1064 * judge whether frame_size store effective value via 1065 * pixel_format. 1066 */ 1067 isp->inputs[isp->input_cnt].frame_size.pixel_format = 0; 1068 isp->input_cnt++; 1069 break; 1070 case CAMERA_MOTOR: 1071 if (isp->motor) { 1072 dev_warn(isp->dev, 1073 "too many atomisp motors, ignored %s\n", 1074 board_info->type); 1075 continue; 1076 } 1077 isp->motor = subdev; 1078 break; 1079 case LED_FLASH: 1080 case XENON_FLASH: 1081 if (isp->flash) { 1082 dev_warn(isp->dev, 1083 "too many atomisp flash devices, ignored %s\n", 1084 board_info->type); 1085 continue; 1086 } 1087 isp->flash = subdev; 1088 break; 1089 default: 1090 dev_dbg(isp->dev, "unknown subdev probed\n"); 1091 break; 1092 } 1093 } 1094 1095 /* 1096 * HACK: Currently VCM belongs to primary sensor only, but correct 1097 * approach must be to acquire from platform code which sensor 1098 * owns it. 1099 */ 1100 if (isp->motor && raw_index >= 0) 1101 isp->inputs[raw_index].motor = isp->motor; 1102 1103 /* Proceed even if no modules detected. For COS mode and no modules. */ 1104 if (!isp->input_cnt) 1105 dev_warn(isp->dev, "no camera attached or fail to detect\n"); 1106 else 1107 dev_info(isp->dev, "detected %d camera sensors\n", 1108 isp->input_cnt); 1109 1110 return atomisp_csi_lane_config(isp); 1111 } 1112 1113 static void atomisp_unregister_entities(struct atomisp_device *isp) 1114 { 1115 unsigned int i; 1116 struct v4l2_subdev *sd, *next; 1117 1118 for (i = 0; i < isp->num_of_streams; i++) 1119 atomisp_subdev_unregister_entities(&isp->asd[i]); 1120 atomisp_tpg_unregister_entities(&isp->tpg); 1121 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) 1122 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]); 1123 1124 list_for_each_entry_safe(sd, next, &isp->v4l2_dev.subdevs, list) 1125 v4l2_device_unregister_subdev(sd); 1126 1127 v4l2_device_unregister(&isp->v4l2_dev); 1128 media_device_unregister(&isp->media_dev); 1129 media_device_cleanup(&isp->media_dev); 1130 } 1131 1132 static int atomisp_register_entities(struct atomisp_device *isp) 1133 { 1134 int ret = 0; 1135 unsigned int i; 1136 1137 isp->media_dev.dev = isp->dev; 1138 1139 strscpy(isp->media_dev.model, "Intel Atom ISP", 1140 sizeof(isp->media_dev.model)); 1141 1142 media_device_init(&isp->media_dev); 1143 isp->v4l2_dev.mdev = &isp->media_dev; 1144 ret = v4l2_device_register(isp->dev, &isp->v4l2_dev); 1145 if (ret < 0) { 1146 dev_err(isp->dev, "%s: V4L2 device registration failed (%d)\n", 1147 __func__, ret); 1148 goto v4l2_device_failed; 1149 } 1150 1151 ret = atomisp_subdev_probe(isp); 1152 if (ret < 0) 1153 goto csi_and_subdev_probe_failed; 1154 1155 /* Register internal entities */ 1156 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) { 1157 ret = atomisp_mipi_csi2_register_entities(&isp->csi2_port[i], 1158 &isp->v4l2_dev); 1159 if (ret == 0) 1160 continue; 1161 1162 /* error case */ 1163 dev_err(isp->dev, "failed to register the CSI port: %d\n", i); 1164 /* deregister all registered CSI ports */ 1165 while (i--) 1166 atomisp_mipi_csi2_unregister_entities( 1167 &isp->csi2_port[i]); 1168 1169 goto csi_and_subdev_probe_failed; 1170 } 1171 1172 ret = atomisp_tpg_register_entities(&isp->tpg, &isp->v4l2_dev); 1173 if (ret < 0) { 1174 dev_err(isp->dev, "atomisp_tpg_register_entities\n"); 1175 goto tpg_register_failed; 1176 } 1177 1178 for (i = 0; i < isp->num_of_streams; i++) { 1179 struct atomisp_sub_device *asd = &isp->asd[i]; 1180 1181 ret = atomisp_subdev_register_subdev(asd, &isp->v4l2_dev); 1182 if (ret < 0) { 1183 dev_err(isp->dev, "atomisp_subdev_register_subdev fail\n"); 1184 for (; i > 0; i--) 1185 atomisp_subdev_unregister_entities( 1186 &isp->asd[i - 1]); 1187 goto subdev_register_failed; 1188 } 1189 } 1190 1191 for (i = 0; i < isp->num_of_streams; i++) { 1192 struct atomisp_sub_device *asd = &isp->asd[i]; 1193 1194 init_completion(&asd->init_done); 1195 1196 asd->delayed_init_workq = 1197 alloc_workqueue(isp->v4l2_dev.name, WQ_CPU_INTENSIVE, 1198 1); 1199 if (!asd->delayed_init_workq) { 1200 dev_err(isp->dev, 1201 "Failed to initialize delayed init workq\n"); 1202 ret = -ENOMEM; 1203 1204 for (; i > 0; i--) 1205 destroy_workqueue(isp->asd[i - 1]. 1206 delayed_init_workq); 1207 goto wq_alloc_failed; 1208 } 1209 INIT_WORK(&asd->delayed_init_work, atomisp_delayed_init_work); 1210 } 1211 1212 for (i = 0; i < isp->input_cnt; i++) { 1213 if (isp->inputs[i].port >= ATOMISP_CAMERA_NR_PORTS) { 1214 dev_err(isp->dev, "isp->inputs port %d not supported\n", 1215 isp->inputs[i].port); 1216 ret = -EINVAL; 1217 goto link_failed; 1218 } 1219 } 1220 1221 if (isp->input_cnt < ATOM_ISP_MAX_INPUTS) { 1222 dev_dbg(isp->dev, 1223 "TPG detected, camera_cnt: %d\n", isp->input_cnt); 1224 isp->inputs[isp->input_cnt].type = TEST_PATTERN; 1225 isp->inputs[isp->input_cnt].port = -1; 1226 isp->inputs[isp->input_cnt++].camera = &isp->tpg.sd; 1227 } else { 1228 dev_warn(isp->dev, "too many atomisp inputs, TPG ignored.\n"); 1229 } 1230 1231 return 0; 1232 1233 link_failed: 1234 for (i = 0; i < isp->num_of_streams; i++) 1235 destroy_workqueue(isp->asd[i]. 1236 delayed_init_workq); 1237 wq_alloc_failed: 1238 for (i = 0; i < isp->num_of_streams; i++) 1239 atomisp_subdev_unregister_entities( 1240 &isp->asd[i]); 1241 subdev_register_failed: 1242 atomisp_tpg_unregister_entities(&isp->tpg); 1243 tpg_register_failed: 1244 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) 1245 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]); 1246 csi_and_subdev_probe_failed: 1247 v4l2_device_unregister(&isp->v4l2_dev); 1248 v4l2_device_failed: 1249 media_device_unregister(&isp->media_dev); 1250 media_device_cleanup(&isp->media_dev); 1251 return ret; 1252 } 1253 1254 static int atomisp_register_device_nodes(struct atomisp_device *isp) 1255 { 1256 int i, err; 1257 1258 for (i = 0; i < isp->num_of_streams; i++) { 1259 err = atomisp_subdev_register_video_nodes(&isp->asd[i], &isp->v4l2_dev); 1260 if (err) 1261 return err; 1262 } 1263 1264 err = atomisp_create_pads_links(isp); 1265 if (err) 1266 return err; 1267 1268 err = v4l2_device_register_subdev_nodes(&isp->v4l2_dev); 1269 if (err) 1270 return err; 1271 1272 return media_device_register(&isp->media_dev); 1273 } 1274 1275 static int atomisp_initialize_modules(struct atomisp_device *isp) 1276 { 1277 int ret; 1278 1279 ret = atomisp_mipi_csi2_init(isp); 1280 if (ret < 0) { 1281 dev_err(isp->dev, "mipi csi2 initialization failed\n"); 1282 goto error_mipi_csi2; 1283 } 1284 1285 ret = atomisp_tpg_init(isp); 1286 if (ret < 0) { 1287 dev_err(isp->dev, "tpg initialization failed\n"); 1288 goto error_tpg; 1289 } 1290 1291 ret = atomisp_subdev_init(isp); 1292 if (ret < 0) { 1293 dev_err(isp->dev, "ISP subdev initialization failed\n"); 1294 goto error_isp_subdev; 1295 } 1296 1297 return 0; 1298 1299 error_isp_subdev: 1300 error_tpg: 1301 atomisp_tpg_cleanup(isp); 1302 error_mipi_csi2: 1303 atomisp_mipi_csi2_cleanup(isp); 1304 return ret; 1305 } 1306 1307 static void atomisp_uninitialize_modules(struct atomisp_device *isp) 1308 { 1309 atomisp_tpg_cleanup(isp); 1310 atomisp_mipi_csi2_cleanup(isp); 1311 } 1312 1313 const struct firmware * 1314 atomisp_load_firmware(struct atomisp_device *isp) 1315 { 1316 const struct firmware *fw; 1317 int rc; 1318 char *fw_path = NULL; 1319 1320 if (skip_fwload) 1321 return NULL; 1322 1323 if (firmware_name[0] != '\0') { 1324 fw_path = firmware_name; 1325 } else { 1326 if ((isp->media_dev.hw_revision >> ATOMISP_HW_REVISION_SHIFT) 1327 == ATOMISP_HW_REVISION_ISP2401) 1328 fw_path = "shisp_2401a0_v21.bin"; 1329 1330 if (isp->media_dev.hw_revision == 1331 ((ATOMISP_HW_REVISION_ISP2401_LEGACY << ATOMISP_HW_REVISION_SHIFT) 1332 | ATOMISP_HW_STEPPING_A0)) 1333 fw_path = "shisp_2401a0_legacy_v21.bin"; 1334 1335 if (isp->media_dev.hw_revision == 1336 ((ATOMISP_HW_REVISION_ISP2400 << ATOMISP_HW_REVISION_SHIFT) 1337 | ATOMISP_HW_STEPPING_B0)) 1338 fw_path = "shisp_2400b0_v21.bin"; 1339 } 1340 1341 if (!fw_path) { 1342 dev_err(isp->dev, "Unsupported hw_revision 0x%x\n", 1343 isp->media_dev.hw_revision); 1344 return NULL; 1345 } 1346 1347 rc = request_firmware(&fw, fw_path, isp->dev); 1348 if (rc) { 1349 dev_err(isp->dev, 1350 "atomisp: Error %d while requesting firmware %s\n", 1351 rc, fw_path); 1352 return NULL; 1353 } 1354 1355 return fw; 1356 } 1357 1358 /* 1359 * Check for flags the driver was compiled with against the PCI 1360 * device. Always returns true on other than ISP 2400. 1361 */ 1362 static bool is_valid_device(struct pci_dev *pdev, const struct pci_device_id *id) 1363 { 1364 const char *name; 1365 const char *product; 1366 1367 product = dmi_get_system_info(DMI_PRODUCT_NAME); 1368 1369 switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) { 1370 case ATOMISP_PCI_DEVICE_SOC_MRFLD: 1371 name = "Merrifield"; 1372 break; 1373 case ATOMISP_PCI_DEVICE_SOC_BYT: 1374 name = "Baytrail"; 1375 break; 1376 case ATOMISP_PCI_DEVICE_SOC_ANN: 1377 name = "Anniedale"; 1378 break; 1379 case ATOMISP_PCI_DEVICE_SOC_CHT: 1380 name = "Cherrytrail"; 1381 break; 1382 default: 1383 dev_err(&pdev->dev, "%s: unknown device ID %x04:%x04\n", 1384 product, id->vendor, id->device); 1385 return false; 1386 } 1387 1388 if (pdev->revision <= ATOMISP_PCI_REV_BYT_A0_MAX) { 1389 dev_err(&pdev->dev, "%s revision %d is not unsupported\n", 1390 name, pdev->revision); 1391 return false; 1392 } 1393 1394 /* 1395 * FIXME: 1396 * remove the if once the driver become generic 1397 */ 1398 1399 #ifndef ISP2401 1400 if (IS_ISP2401) { 1401 dev_err(&pdev->dev, "Support for %s (ISP2401) was disabled at compile time\n", 1402 name); 1403 return false; 1404 } 1405 #else 1406 if (!IS_ISP2401) { 1407 dev_err(&pdev->dev, "Support for %s (ISP2400) was disabled at compile time\n", 1408 name); 1409 return false; 1410 } 1411 #endif 1412 1413 dev_info(&pdev->dev, "Detected %s version %d (ISP240%c) on %s\n", 1414 name, pdev->revision, IS_ISP2401 ? '1' : '0', product); 1415 1416 return true; 1417 } 1418 1419 #define ATOM_ISP_PCI_BAR 0 1420 1421 static int atomisp_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1422 { 1423 const struct atomisp_platform_data *pdata; 1424 struct atomisp_device *isp; 1425 unsigned int start; 1426 int err, val; 1427 u32 irq; 1428 1429 if (!is_valid_device(pdev, id)) 1430 return -ENODEV; 1431 1432 /* Pointer to struct device. */ 1433 atomisp_dev = &pdev->dev; 1434 1435 pdata = atomisp_get_platform_data(); 1436 if (!pdata) 1437 dev_warn(&pdev->dev, "no platform data available\n"); 1438 1439 err = pcim_enable_device(pdev); 1440 if (err) { 1441 dev_err(&pdev->dev, "Failed to enable CI ISP device (%d)\n", err); 1442 return err; 1443 } 1444 1445 start = pci_resource_start(pdev, ATOM_ISP_PCI_BAR); 1446 dev_dbg(&pdev->dev, "start: 0x%x\n", start); 1447 1448 err = pcim_iomap_regions(pdev, BIT(ATOM_ISP_PCI_BAR), pci_name(pdev)); 1449 if (err) { 1450 dev_err(&pdev->dev, "Failed to I/O memory remapping (%d)\n", err); 1451 goto ioremap_fail; 1452 } 1453 1454 isp = devm_kzalloc(&pdev->dev, sizeof(*isp), GFP_KERNEL); 1455 if (!isp) { 1456 err = -ENOMEM; 1457 goto atomisp_dev_alloc_fail; 1458 } 1459 1460 isp->dev = &pdev->dev; 1461 isp->base = pcim_iomap_table(pdev)[ATOM_ISP_PCI_BAR]; 1462 isp->sw_contex.power_state = ATOM_ISP_POWER_UP; 1463 isp->saved_regs.ispmmadr = start; 1464 1465 dev_dbg(&pdev->dev, "atomisp mmio base: %p\n", isp->base); 1466 1467 mutex_init(&isp->mutex); 1468 spin_lock_init(&isp->lock); 1469 1470 /* This is not a true PCI device on SoC, so the delay is not needed. */ 1471 pdev->d3hot_delay = 0; 1472 1473 pci_set_drvdata(pdev, isp); 1474 1475 switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) { 1476 case ATOMISP_PCI_DEVICE_SOC_MRFLD: 1477 isp->media_dev.hw_revision = 1478 (ATOMISP_HW_REVISION_ISP2400 1479 << ATOMISP_HW_REVISION_SHIFT) | 1480 ATOMISP_HW_STEPPING_B0; 1481 1482 switch (id->device) { 1483 case ATOMISP_PCI_DEVICE_SOC_MRFLD_1179: 1484 isp->dfs = &dfs_config_merr_1179; 1485 break; 1486 case ATOMISP_PCI_DEVICE_SOC_MRFLD_117A: 1487 isp->dfs = &dfs_config_merr_117a; 1488 1489 break; 1490 default: 1491 isp->dfs = &dfs_config_merr; 1492 break; 1493 } 1494 isp->hpll_freq = HPLL_FREQ_1600MHZ; 1495 break; 1496 case ATOMISP_PCI_DEVICE_SOC_BYT: 1497 isp->media_dev.hw_revision = 1498 (ATOMISP_HW_REVISION_ISP2400 1499 << ATOMISP_HW_REVISION_SHIFT) | 1500 ATOMISP_HW_STEPPING_B0; 1501 1502 /* 1503 * Note: some Intel-based tablets with Android use a different 1504 * DFS table. Based on the comments at the Yocto Aero meta 1505 * version of this driver (at the ssid.h header), they're 1506 * identified via a "spid" var: 1507 * 1508 * androidboot.spid=vend:cust:manu:plat:prod:hard 1509 * 1510 * As we don't have this upstream, nor we know enough details 1511 * to use a DMI or PCI match table, the old code was just 1512 * removed, but let's keep a note here as a reminder that, 1513 * for certain devices, we may need to limit the max DFS 1514 * frequency to be below certain values, adjusting the 1515 * resolution accordingly. 1516 */ 1517 isp->dfs = &dfs_config_byt; 1518 1519 /* 1520 * HPLL frequency is known to be device-specific, but we don't 1521 * have specs yet for exactly how it varies. Default to 1522 * BYT-CR but let provisioning set it via EFI variable 1523 */ 1524 isp->hpll_freq = gmin_get_var_int(&pdev->dev, false, "HpllFreq", HPLL_FREQ_2000MHZ); 1525 1526 /* 1527 * for BYT/CHT we are put isp into D3cold to avoid pci registers access 1528 * in power off. Set d3cold_delay to 0 since default 100ms is not 1529 * necessary. 1530 */ 1531 pdev->d3cold_delay = 0; 1532 break; 1533 case ATOMISP_PCI_DEVICE_SOC_ANN: 1534 isp->media_dev.hw_revision = ( ATOMISP_HW_REVISION_ISP2401 1535 << ATOMISP_HW_REVISION_SHIFT); 1536 isp->media_dev.hw_revision |= pdev->revision < 2 ? 1537 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0; 1538 isp->dfs = &dfs_config_merr; 1539 isp->hpll_freq = HPLL_FREQ_1600MHZ; 1540 break; 1541 case ATOMISP_PCI_DEVICE_SOC_CHT: 1542 isp->media_dev.hw_revision = ( ATOMISP_HW_REVISION_ISP2401 1543 << ATOMISP_HW_REVISION_SHIFT); 1544 isp->media_dev.hw_revision |= pdev->revision < 2 ? 1545 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0; 1546 1547 isp->dfs = &dfs_config_cht; 1548 pdev->d3cold_delay = 0; 1549 1550 iosf_mbi_read(BT_MBI_UNIT_CCK, MBI_REG_READ, CCK_FUSE_REG_0, &val); 1551 switch (val & CCK_FUSE_HPLL_FREQ_MASK) { 1552 case 0x00: 1553 isp->hpll_freq = HPLL_FREQ_800MHZ; 1554 break; 1555 case 0x01: 1556 isp->hpll_freq = HPLL_FREQ_1600MHZ; 1557 break; 1558 case 0x02: 1559 isp->hpll_freq = HPLL_FREQ_2000MHZ; 1560 break; 1561 default: 1562 isp->hpll_freq = HPLL_FREQ_1600MHZ; 1563 dev_warn(&pdev->dev, "read HPLL from cck failed. Default to 1600 MHz.\n"); 1564 } 1565 break; 1566 default: 1567 dev_err(&pdev->dev, "un-supported IUNIT device\n"); 1568 err = -ENODEV; 1569 goto atomisp_dev_alloc_fail; 1570 } 1571 1572 dev_info(&pdev->dev, "ISP HPLL frequency base = %d MHz\n", isp->hpll_freq); 1573 1574 isp->max_isr_latency = ATOMISP_MAX_ISR_LATENCY; 1575 1576 /* Load isp firmware from user space */ 1577 if (!defer_fw_load) { 1578 isp->firmware = atomisp_load_firmware(isp); 1579 if (!isp->firmware) { 1580 err = -ENOENT; 1581 dev_dbg(&pdev->dev, "Firmware load failed\n"); 1582 goto load_fw_fail; 1583 } 1584 1585 err = sh_css_check_firmware_version(isp->dev, isp->firmware->data); 1586 if (err) { 1587 dev_dbg(&pdev->dev, "Firmware version check failed\n"); 1588 goto fw_validation_fail; 1589 } 1590 } else { 1591 dev_info(&pdev->dev, "Firmware load will be deferred\n"); 1592 } 1593 1594 pci_set_master(pdev); 1595 1596 err = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 1597 if (err < 0) { 1598 dev_err(&pdev->dev, "Failed to enable msi (%d)\n", err); 1599 goto enable_msi_fail; 1600 } 1601 1602 atomisp_msi_irq_init(isp); 1603 1604 cpu_latency_qos_add_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE); 1605 1606 /* 1607 * for MRFLD, Software/firmware needs to write a 1 to bit 0 of 1608 * the register at CSI_RECEIVER_SELECTION_REG to enable SH CSI 1609 * backend write 0 will enable Arasan CSI backend, which has 1610 * bugs(like sighting:4567697 and 4567699) and will be removed 1611 * in B0 1612 */ 1613 atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1); 1614 1615 if ((id->device & ATOMISP_PCI_DEVICE_SOC_MASK) == 1616 ATOMISP_PCI_DEVICE_SOC_MRFLD) { 1617 u32 csi_afe_trim; 1618 1619 /* 1620 * Workaround for imbalance data eye issue which is observed 1621 * on TNG B0. 1622 */ 1623 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, &csi_afe_trim); 1624 csi_afe_trim &= ~((MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << 1625 MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) | 1626 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << 1627 MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) | 1628 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << 1629 MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT)); 1630 csi_afe_trim |= (MRFLD_PCI_CSI1_HSRXCLKTRIM << 1631 MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) | 1632 (MRFLD_PCI_CSI2_HSRXCLKTRIM << 1633 MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) | 1634 (MRFLD_PCI_CSI3_HSRXCLKTRIM << 1635 MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT); 1636 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, csi_afe_trim); 1637 } 1638 1639 err = atomisp_initialize_modules(isp); 1640 if (err < 0) { 1641 dev_err(&pdev->dev, "atomisp_initialize_modules (%d)\n", err); 1642 goto initialize_modules_fail; 1643 } 1644 1645 err = atomisp_register_entities(isp); 1646 if (err < 0) { 1647 dev_err(&pdev->dev, "atomisp_register_entities failed (%d)\n", err); 1648 goto register_entities_fail; 1649 } 1650 1651 INIT_WORK(&isp->assert_recovery_work, atomisp_assert_recovery_work); 1652 1653 /* save the iunit context only once after all the values are init'ed. */ 1654 atomisp_save_iunit_reg(isp); 1655 1656 pm_runtime_put_noidle(&pdev->dev); 1657 pm_runtime_allow(&pdev->dev); 1658 1659 /* Init ISP memory management */ 1660 hmm_init(); 1661 1662 err = devm_request_threaded_irq(&pdev->dev, pdev->irq, 1663 atomisp_isr, atomisp_isr_thread, 1664 IRQF_SHARED, "isp_irq", isp); 1665 if (err) { 1666 dev_err(&pdev->dev, "Failed to request irq (%d)\n", err); 1667 goto request_irq_fail; 1668 } 1669 1670 /* Load firmware into ISP memory */ 1671 if (!defer_fw_load) { 1672 err = atomisp_css_load_firmware(isp); 1673 if (err) { 1674 dev_err(&pdev->dev, "Failed to init css.\n"); 1675 goto css_init_fail; 1676 } 1677 } else { 1678 dev_dbg(&pdev->dev, "Skip css init.\n"); 1679 } 1680 /* Clear FW image from memory */ 1681 release_firmware(isp->firmware); 1682 isp->firmware = NULL; 1683 isp->css_env.isp_css_fw.data = NULL; 1684 1685 err = atomisp_register_device_nodes(isp); 1686 if (err) 1687 goto css_init_fail; 1688 1689 atomisp_drvfs_init(isp); 1690 1691 return 0; 1692 1693 css_init_fail: 1694 devm_free_irq(&pdev->dev, pdev->irq, isp); 1695 request_irq_fail: 1696 hmm_cleanup(); 1697 pm_runtime_get_noresume(&pdev->dev); 1698 atomisp_unregister_entities(isp); 1699 register_entities_fail: 1700 atomisp_uninitialize_modules(isp); 1701 initialize_modules_fail: 1702 cpu_latency_qos_remove_request(&isp->pm_qos); 1703 atomisp_msi_irq_uninit(isp); 1704 pci_free_irq_vectors(pdev); 1705 enable_msi_fail: 1706 fw_validation_fail: 1707 release_firmware(isp->firmware); 1708 load_fw_fail: 1709 /* 1710 * Switch off ISP, as keeping it powered on would prevent 1711 * reaching S0ix states. 1712 * 1713 * The following lines have been copied from atomisp suspend path 1714 */ 1715 1716 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 1717 irq &= BIT(INTR_IIR); 1718 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq); 1719 1720 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 1721 irq &= ~BIT(INTR_IER); 1722 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq); 1723 1724 atomisp_msi_irq_uninit(isp); 1725 1726 atomisp_ospm_dphy_down(isp); 1727 1728 /* Address later when we worry about the ...field chips */ 1729 if (IS_ENABLED(CONFIG_PM) && atomisp_mrfld_power_down(isp)) 1730 dev_err(&pdev->dev, "Failed to switch off ISP\n"); 1731 1732 atomisp_dev_alloc_fail: 1733 pcim_iounmap_regions(pdev, BIT(ATOM_ISP_PCI_BAR)); 1734 1735 ioremap_fail: 1736 return err; 1737 } 1738 1739 static void atomisp_pci_remove(struct pci_dev *pdev) 1740 { 1741 struct atomisp_device *isp = pci_get_drvdata(pdev); 1742 1743 dev_info(&pdev->dev, "Removing atomisp driver\n"); 1744 1745 atomisp_drvfs_exit(); 1746 1747 ia_css_unload_firmware(); 1748 hmm_cleanup(); 1749 1750 pm_runtime_forbid(&pdev->dev); 1751 pm_runtime_get_noresume(&pdev->dev); 1752 cpu_latency_qos_remove_request(&isp->pm_qos); 1753 1754 atomisp_msi_irq_uninit(isp); 1755 atomisp_unregister_entities(isp); 1756 1757 release_firmware(isp->firmware); 1758 } 1759 1760 static const struct pci_device_id atomisp_pci_tbl[] = { 1761 /* Merrifield */ 1762 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD)}, 1763 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_1179)}, 1764 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_117A)}, 1765 /* Baytrail */ 1766 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_BYT)}, 1767 /* Anniedale (Merrifield+ / Moorefield) */ 1768 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_ANN)}, 1769 /* Cherrytrail */ 1770 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_CHT)}, 1771 {0,} 1772 }; 1773 1774 MODULE_DEVICE_TABLE(pci, atomisp_pci_tbl); 1775 1776 static const struct dev_pm_ops atomisp_pm_ops = { 1777 .runtime_suspend = atomisp_runtime_suspend, 1778 .runtime_resume = atomisp_runtime_resume, 1779 .suspend = atomisp_suspend, 1780 .resume = atomisp_resume, 1781 }; 1782 1783 static struct pci_driver atomisp_pci_driver = { 1784 .driver = { 1785 .pm = &atomisp_pm_ops, 1786 }, 1787 .name = "atomisp-isp2", 1788 .id_table = atomisp_pci_tbl, 1789 .probe = atomisp_pci_probe, 1790 .remove = atomisp_pci_remove, 1791 }; 1792 1793 module_pci_driver(atomisp_pci_driver); 1794 1795 MODULE_AUTHOR("Wen Wang <wen.w.wang@intel.com>"); 1796 MODULE_AUTHOR("Xiaolin Zhang <xiaolin.zhang@intel.com>"); 1797 MODULE_LICENSE("GPL"); 1798 MODULE_DESCRIPTION("Intel ATOM Platform ISP Driver"); 1799