1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Support for Intel Camera Imaging ISP subsystem.
4 * Copyright (c) 2015, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16 #ifndef _SH_CSS_INTERNAL_H_
17 #define _SH_CSS_INTERNAL_H_
18
19 #include <system_global.h>
20 #include <math_support.h>
21 #include <type_support.h>
22 #include <platform_support.h>
23 #include <linux/stdarg.h>
24
25 #include "input_formatter.h"
26 #include "input_system.h"
27
28 #include "ia_css_types.h"
29 #include "ia_css_acc_types.h"
30 #include "ia_css_buffer.h"
31
32 #include "ia_css_binary.h"
33 #include "sh_css_firmware.h" /* not needed/desired on SP/ISP */
34 #include "sh_css_legacy.h"
35 #include "sh_css_defs.h"
36 #include "sh_css_uds.h"
37 #include "dma.h" /* N_DMA_CHANNEL_ID */
38 #include "ia_css_circbuf_comm.h" /* Circular buffer */
39 #include "ia_css_frame_comm.h"
40 #include "ia_css_3a.h"
41 #include "ia_css_dvs.h"
42 #include "ia_css_metadata.h"
43 #include "runtime/bufq/interface/ia_css_bufq.h"
44 #include "ia_css_timer.h"
45
46 /* TODO: Move to a more suitable place when sp pipeline design is done. */
47 #define IA_CSS_NUM_CB_SEM_READ_RESOURCE 2
48 #define IA_CSS_NUM_CB_SEM_WRITE_RESOURCE 1
49 #define IA_CSS_NUM_CBS 2
50 #define IA_CSS_CB_MAX_ELEMS 2
51
52 /* Use case specific. index limited to IA_CSS_NUM_CB_SEM_READ_RESOURCE or
53 * IA_CSS_NUM_CB_SEM_WRITE_RESOURCE for read and write respectively.
54 * TODO: Enforce the limitation above.
55 */
56 #define IA_CSS_COPYSINK_SEM_INDEX 0
57 #define IA_CSS_TAGGER_SEM_INDEX 1
58
59 /* Force generation of output event. Used by acceleration pipe. */
60 #define IA_CSS_POST_OUT_EVENT_FORCE 2
61
62 #define SH_CSS_MAX_BINARY_NAME 64
63
64 #define SP_DEBUG_NONE (0)
65 #define SP_DEBUG_DUMP (1)
66 #define SP_DEBUG_COPY (2)
67 #define SP_DEBUG_TRACE (3)
68 #define SP_DEBUG_MINIMAL (4)
69
70 #define SP_DEBUG SP_DEBUG_NONE
71 #define SP_DEBUG_MINIMAL_OVERWRITE 1
72
73 #define SH_CSS_TNR_BIT_DEPTH 8
74 #define SH_CSS_REF_BIT_DEPTH 8
75
76 /* keep next up to date with the definition for MAX_CB_ELEMS_FOR_TAGGER in tagger.sp.c */
77 #define NUM_CONTINUOUS_FRAMES 15
78 #define NUM_MIPI_FRAMES_PER_STREAM 2
79
80 #define NUM_ONLINE_INIT_CONTINUOUS_FRAMES 2
81
82 #define NR_OF_PIPELINES IA_CSS_PIPE_ID_NUM /* Must match with IA_CSS_PIPE_ID_NUM */
83
84 #define SH_CSS_MAX_IF_CONFIGS 3 /* Must match with IA_CSS_NR_OF_CONFIGS (not defined yet).*/
85 #define SH_CSS_IF_CONFIG_NOT_NEEDED 0xFF
86
87 #define SH_CSS_MAX_SP_THREADS 5
88
89 /**
90 * The C99 standard does not specify the exact object representation of structs;
91 * the representation is compiler dependent.
92 *
93 * The structs that are communicated between host and SP/ISP should have the
94 * exact same object representation. The compiler that is used to compile the
95 * firmware is hivecc.
96 *
97 * To check if a different compiler, used to compile a host application, uses
98 * another object representation, macros are defined specifying the size of
99 * the structs as expected by the firmware.
100 *
101 * A host application shall verify that a sizeof( ) of the struct is equal to
102 * the SIZE_OF_XXX macro of the corresponding struct. If they are not
103 * equal, functionality will break.
104 */
105 #define CALC_ALIGNMENT_MEMBER(x, y) (CEIL_MUL(x, y) - x)
106 #define SIZE_OF_HRT_VADDRESS sizeof(hive_uint32)
107 #define SIZE_OF_IA_CSS_PTR sizeof(uint32_t)
108
109 /* Number of SP's */
110 #define NUM_OF_SPS 1
111
112 #define NUM_OF_BLS 0
113
114 /* Enum for order of Binaries */
115 enum sh_css_order_binaries {
116 SP_FIRMWARE = 0,
117 ISP_FIRMWARE
118 };
119
120 /*
121 * JB: keep next enum in sync with thread id's
122 * and pipe id's
123 */
124 enum sh_css_pipe_config_override {
125 SH_CSS_PIPE_CONFIG_OVRD_NONE = 0,
126 SH_CSS_PIPE_CONFIG_OVRD_NO_OVRD = 0xffff
127 };
128
129 enum host2sp_commands {
130 host2sp_cmd_error = 0,
131 /*
132 * The host2sp_cmd_ready command is the only command written by the SP
133 * It acknowledges that is previous command has been received.
134 * (this does not mean that the command has been executed)
135 * It also indicates that a new command can be send (it is a queue
136 * with depth 1).
137 */
138 host2sp_cmd_ready = 1,
139 /* Command written by the Host */
140 host2sp_cmd_dummy, /* No action, can be used as watchdog */
141 host2sp_cmd_start_flash, /* Request SP to start the flash */
142 host2sp_cmd_terminate, /* SP should terminate itself */
143 N_host2sp_cmd
144 };
145
146 /* Enumeration used to indicate the events that are produced by
147 * the SP and consumed by the Host.
148 *
149 * !!!IMPORTANT!!! KEEP THE FOLLOWING IN SYNC:
150 * 1) "enum ia_css_event_type" (ia_css_event_public.h)
151 * 2) "enum sh_css_sp_event_type" (sh_css_internal.h)
152 * 3) "enum ia_css_event_type event_id_2_event_mask" (event_handler.sp.c)
153 * 4) "enum ia_css_event_type convert_event_sp_to_host_domain" (sh_css.c)
154 */
155 enum sh_css_sp_event_type {
156 SH_CSS_SP_EVENT_OUTPUT_FRAME_DONE,
157 SH_CSS_SP_EVENT_SECOND_OUTPUT_FRAME_DONE,
158 SH_CSS_SP_EVENT_VF_OUTPUT_FRAME_DONE,
159 SH_CSS_SP_EVENT_SECOND_VF_OUTPUT_FRAME_DONE,
160 SH_CSS_SP_EVENT_3A_STATISTICS_DONE,
161 SH_CSS_SP_EVENT_DIS_STATISTICS_DONE,
162 SH_CSS_SP_EVENT_PIPELINE_DONE,
163 SH_CSS_SP_EVENT_FRAME_TAGGED,
164 SH_CSS_SP_EVENT_INPUT_FRAME_DONE,
165 SH_CSS_SP_EVENT_METADATA_DONE,
166 SH_CSS_SP_EVENT_LACE_STATISTICS_DONE,
167 SH_CSS_SP_EVENT_ACC_STAGE_COMPLETE,
168 SH_CSS_SP_EVENT_TIMER,
169 SH_CSS_SP_EVENT_PORT_EOF,
170 SH_CSS_SP_EVENT_FW_WARNING,
171 SH_CSS_SP_EVENT_FW_ASSERT,
172 SH_CSS_SP_EVENT_NR_OF_TYPES /* must be last */
173 };
174
175 /* xmem address map allocation per pipeline, css pointers */
176 /* Note that the struct below should only consist of ia_css_ptr-es
177 Otherwise this will cause a fail in the function ref_sh_css_ddr_address_map
178 */
179 struct sh_css_ddr_address_map {
180 ia_css_ptr isp_param;
181 ia_css_ptr isp_mem_param[SH_CSS_MAX_STAGES][IA_CSS_NUM_MEMORIES];
182 ia_css_ptr macc_tbl;
183 ia_css_ptr fpn_tbl;
184 ia_css_ptr sc_tbl;
185 ia_css_ptr tetra_r_x;
186 ia_css_ptr tetra_r_y;
187 ia_css_ptr tetra_gr_x;
188 ia_css_ptr tetra_gr_y;
189 ia_css_ptr tetra_gb_x;
190 ia_css_ptr tetra_gb_y;
191 ia_css_ptr tetra_b_x;
192 ia_css_ptr tetra_b_y;
193 ia_css_ptr tetra_ratb_x;
194 ia_css_ptr tetra_ratb_y;
195 ia_css_ptr tetra_batr_x;
196 ia_css_ptr tetra_batr_y;
197 ia_css_ptr dvs_6axis_params_y;
198 };
199
200 #define SIZE_OF_SH_CSS_DDR_ADDRESS_MAP_STRUCT \
201 (SIZE_OF_HRT_VADDRESS + \
202 (SH_CSS_MAX_STAGES * IA_CSS_NUM_MEMORIES * SIZE_OF_HRT_VADDRESS) + \
203 (16 * SIZE_OF_HRT_VADDRESS))
204
205 /* xmem address map allocation per pipeline */
206 struct sh_css_ddr_address_map_size {
207 size_t isp_param;
208 size_t isp_mem_param[SH_CSS_MAX_STAGES][IA_CSS_NUM_MEMORIES];
209 size_t macc_tbl;
210 size_t fpn_tbl;
211 size_t sc_tbl;
212 size_t tetra_r_x;
213 size_t tetra_r_y;
214 size_t tetra_gr_x;
215 size_t tetra_gr_y;
216 size_t tetra_gb_x;
217 size_t tetra_gb_y;
218 size_t tetra_b_x;
219 size_t tetra_b_y;
220 size_t tetra_ratb_x;
221 size_t tetra_ratb_y;
222 size_t tetra_batr_x;
223 size_t tetra_batr_y;
224 size_t dvs_6axis_params_y;
225 };
226
227 struct sh_css_ddr_address_map_compound {
228 struct sh_css_ddr_address_map map;
229 struct sh_css_ddr_address_map_size size;
230 };
231
232 struct ia_css_isp_parameter_set_info {
233 struct sh_css_ddr_address_map
234 mem_map;/** pointers to Parameters in ISP format IMPT:
235 This should be first member of this struct */
236 u32
237 isp_parameters_id;/** Unique ID to track which config was actually applied to a particular frame */
238 ia_css_ptr
239 output_frame_ptr;/** Output frame to which this config has to be applied (optional) */
240 };
241
242 /* this struct contains all arguments that can be passed to
243 a binary. It depends on the binary which ones are used. */
244 struct sh_css_binary_args {
245 struct ia_css_frame *in_frame; /* input frame */
246 const struct ia_css_frame
247 *delay_frames[MAX_NUM_VIDEO_DELAY_FRAMES]; /* reference input frame */
248 const struct ia_css_frame *tnr_frames[NUM_VIDEO_TNR_FRAMES]; /* tnr frames */
249 struct ia_css_frame
250 *out_frame[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; /* output frame */
251 struct ia_css_frame *out_vf_frame; /* viewfinder output frame */
252 bool copy_vf;
253 bool copy_output;
254 unsigned int vf_downscale_log2;
255 };
256
257 #if SP_DEBUG == SP_DEBUG_DUMP
258
259 #define SH_CSS_NUM_SP_DEBUG 48
260
261 struct sh_css_sp_debug_state {
262 unsigned int error;
263 unsigned int debug[SH_CSS_NUM_SP_DEBUG];
264 };
265
266 #elif SP_DEBUG == SP_DEBUG_COPY
267
268 #define SH_CSS_SP_DBG_TRACE_DEPTH (40)
269
270 struct sh_css_sp_debug_trace {
271 u16 frame;
272 u16 line;
273 u16 pixel_distance;
274 u16 mipi_used_dword;
275 u16 sp_index;
276 };
277
278 struct sh_css_sp_debug_state {
279 u16 if_start_line;
280 u16 if_start_column;
281 u16 if_cropped_height;
282 u16 if_cropped_width;
283 unsigned int index;
284 struct sh_css_sp_debug_trace
285 trace[SH_CSS_SP_DBG_TRACE_DEPTH];
286 };
287
288 #elif SP_DEBUG == SP_DEBUG_TRACE
289
290 /* Example of just one global trace */
291 #define SH_CSS_SP_DBG_NR_OF_TRACES (1)
292 #define SH_CSS_SP_DBG_TRACE_DEPTH (40)
293
294 #define SH_CSS_SP_DBG_TRACE_FILE_ID_BIT_POS (13)
295
296 struct sh_css_sp_debug_trace {
297 u16 time_stamp;
298 u16 location; /* bit 15..13 = file_id, 12..0 = line nr. */
299 u32 data;
300 };
301
302 struct sh_css_sp_debug_state {
303 struct sh_css_sp_debug_trace
304 trace[SH_CSS_SP_DBG_NR_OF_TRACES][SH_CSS_SP_DBG_TRACE_DEPTH];
305 u16 index_last[SH_CSS_SP_DBG_NR_OF_TRACES];
306 u8 index[SH_CSS_SP_DBG_NR_OF_TRACES];
307 };
308
309 #elif SP_DEBUG == SP_DEBUG_MINIMAL
310
311 #define SH_CSS_NUM_SP_DEBUG 128
312
313 struct sh_css_sp_debug_state {
314 unsigned int error;
315 unsigned int debug[SH_CSS_NUM_SP_DEBUG];
316 };
317
318 #endif
319
320 struct sh_css_sp_debug_command {
321 /*
322 * The DMA software-mask,
323 * Bit 31...24: unused.
324 * Bit 23...16: unused.
325 * Bit 15...08: reading-request enabling bits for DMA channel 7..0
326 * Bit 07...00: writing-request enabling bits for DMA channel 7..0
327 *
328 * For example, "0...0 0...0 11111011 11111101" indicates that the
329 * writing request through DMA Channel 1 and the reading request
330 * through DMA channel 2 are both disabled. The others are enabled.
331 */
332 u32 dma_sw_reg;
333 };
334
335 /* SP input formatter configuration.*/
336 struct sh_css_sp_input_formatter_set {
337 u32 stream_format;
338 input_formatter_cfg_t config_a;
339 input_formatter_cfg_t config_b;
340 };
341
342 #define IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT (3)
343
344 /* SP configuration information */
345 struct sh_css_sp_config {
346 u8 no_isp_sync; /* Signal host immediately after start */
347 u8 enable_raw_pool_locking; /** Enable Raw Buffer Locking for HALv3 Support */
348 u8 lock_all;
349 /** If raw buffer locking is enabled, this flag indicates whether raw
350 frames are locked when their EOF event is successfully sent to the
351 host (true) or when they are passed to the preview/video pipe
352 (false). */
353
354 struct {
355 u8 a_changed;
356 u8 b_changed;
357 u8 isp_2ppc;
358 struct sh_css_sp_input_formatter_set
359 set[SH_CSS_MAX_IF_CONFIGS]; /* CSI-2 port is used as index. */
360 } input_formatter;
361
362 sync_generator_cfg_t sync_gen;
363 prbs_cfg_t prbs;
364 input_system_cfg_t input_circuit;
365 u8 input_circuit_cfg_changed;
366 u32 mipi_sizes_for_check[N_CSI_PORTS][IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT];
367 u8 enable_isys_event_queue;
368 u8 disable_cont_vf;
369 };
370
371 enum sh_css_stage_type {
372 SH_CSS_SP_STAGE_TYPE = 0,
373 SH_CSS_ISP_STAGE_TYPE = 1
374 };
375
376 #define SH_CSS_NUM_STAGE_TYPES 2
377
378 #define SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS BIT(0)
379 #define SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS_MASK \
380 ((SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS << SH_CSS_MAX_SP_THREADS) - 1)
381
382 struct sh_css_sp_pipeline_terminal {
383 union {
384 /* Input System 2401 */
385 virtual_input_system_stream_t
386 virtual_input_system_stream[IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH];
387 } context;
388 /*
389 * TODO
390 * - Remove "virtual_input_system_cfg" when the ISYS2401 DLI is ready.
391 */
392 union {
393 /* Input System 2401 */
394 virtual_input_system_stream_cfg_t
395 virtual_input_system_stream_cfg[IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH];
396 } ctrl;
397 };
398
399 struct sh_css_sp_pipeline_io {
400 struct sh_css_sp_pipeline_terminal input;
401 /* pqiao: comment out temporarily to save dmem */
402 /*struct sh_css_sp_pipeline_terminal output;*/
403 };
404
405 /* This struct tracks how many streams are registered per CSI port.
406 * This is used to track which streams have already been configured.
407 * Only when all streams are configured, the CSI RX is started for that port.
408 */
409 struct sh_css_sp_pipeline_io_status {
410 u32 active[N_INPUT_SYSTEM_CSI_PORT]; /** registered streams */
411 u32 running[N_INPUT_SYSTEM_CSI_PORT]; /** configured streams */
412 };
413
414 enum sh_css_port_dir {
415 SH_CSS_PORT_INPUT = 0,
416 SH_CSS_PORT_OUTPUT = 1
417 };
418
419 enum sh_css_port_type {
420 SH_CSS_HOST_TYPE = 0,
421 SH_CSS_COPYSINK_TYPE = 1,
422 SH_CSS_TAGGERSINK_TYPE = 2
423 };
424
425 /* Pipe inout settings: output port on 7-4bits, input port on 3-0bits */
426 #define SH_CSS_PORT_FLD_WIDTH_IN_BITS (4)
427 #define SH_CSS_PORT_TYPE_BIT_FLD(pt) (0x1 << (pt))
428 #define SH_CSS_PORT_FLD(pd) ((pd) ? SH_CSS_PORT_FLD_WIDTH_IN_BITS : 0)
429 #define SH_CSS_PIPE_PORT_CONFIG_ON(p, pd, pt) ((p) |= (SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd)))
430 #define SH_CSS_PIPE_PORT_CONFIG_OFF(p, pd, pt) ((p) &= ~(SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd)))
431 #define SH_CSS_PIPE_PORT_CONFIG_SET(p, pd, pt, val) ((val) ? \
432 SH_CSS_PIPE_PORT_CONFIG_ON(p, pd, pt) : SH_CSS_PIPE_PORT_CONFIG_OFF(p, pd, pt))
433 #define SH_CSS_PIPE_PORT_CONFIG_GET(p, pd, pt) ((p) & (SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd)))
434 #define SH_CSS_PIPE_PORT_CONFIG_IS_CONTINUOUS(p) \
435 (!(SH_CSS_PIPE_PORT_CONFIG_GET(p, SH_CSS_PORT_INPUT, SH_CSS_HOST_TYPE) && \
436 SH_CSS_PIPE_PORT_CONFIG_GET(p, SH_CSS_PORT_OUTPUT, SH_CSS_HOST_TYPE)))
437
438 #define IA_CSS_ACQUIRE_ISP_POS 31
439
440 /* Flags for metadata processing */
441 #define SH_CSS_METADATA_ENABLED 0x01
442 #define SH_CSS_METADATA_PROCESSED 0x02
443 #define SH_CSS_METADATA_OFFLINE_MODE 0x04
444 #define SH_CSS_METADATA_WAIT_INPUT 0x08
445
446 /* @brief Free an array of metadata buffers.
447 *
448 * @param[in] num_bufs Number of metadata buffers to be freed.
449 * @param[in] bufs Pointer of array of metadata buffers.
450 *
451 * This function frees an array of metadata buffers.
452 */
453 void
454 ia_css_metadata_free_multiple(unsigned int num_bufs,
455 struct ia_css_metadata **bufs);
456
457 /* Macro for handling pipe_qos_config */
458 #define QOS_INVALID (~0U)
459
460 /* Information for a pipeline */
461 struct sh_css_sp_pipeline {
462 u32 pipe_id; /* the pipe ID */
463 u32 pipe_num; /* the dynamic pipe number */
464 u32 thread_id; /* the sp thread ID */
465 u32 pipe_config; /* the pipe config */
466 u32 pipe_qos_config; /* Bitmap of multiple QOS extension fw state.
467 (0xFFFFFFFF) indicates non QOS pipe.*/
468 u32 inout_port_config;
469 u32 required_bds_factor;
470 u32 dvs_frame_delay;
471 u32 input_system_mode; /* enum ia_css_input_mode */
472 u32 port_id; /* port_id for input system */
473 u32 num_stages; /* the pipe config */
474 u32 running; /* needed for pipe termination */
475 ia_css_ptr sp_stage_addr[SH_CSS_MAX_STAGES];
476 ia_css_ptr scaler_pp_lut; /* Early bound LUT */
477 u32 dummy; /* stage ptr is only used on sp but lives in
478 this struct; needs cleanup */
479 s32 num_execs; /* number of times to run if this is
480 an acceleration pipe. */
481 struct {
482 u32 format; /* Metadata format in hrt format */
483 u32 width; /* Width of a line */
484 u32 height; /* Number of lines */
485 u32 stride; /* Stride (in bytes) per line */
486 u32 size; /* Total size (in bytes) */
487 ia_css_ptr cont_buf; /* Address of continuous buffer */
488 } metadata;
489 u32 output_frame_queue_id;
490 union {
491 struct {
492 u32 bytes_available;
493 } bin;
494 struct {
495 u32 height;
496 u32 width;
497 u32 padded_width;
498 u32 max_input_width;
499 u32 raw_bit_depth;
500 } raw;
501 } copy;
502 };
503
504 /*
505 * The first frames (with comment Dynamic) can be dynamic or static
506 * The other frames (ref_in and below) can only be static
507 * Static means that the data address will not change during the life time
508 * of the associated pipe. Dynamic means that the data address can
509 * change with every (frame) iteration of the associated pipe
510 *
511 * s3a and dis are now also dynamic but (stil) handled separately
512 */
513 #define SH_CSS_NUM_DYNAMIC_FRAME_IDS (3)
514
515 struct ia_css_frames_sp {
516 struct ia_css_frame_sp in;
517 struct ia_css_frame_sp out[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
518 struct ia_css_resolution effective_in_res;
519 struct ia_css_frame_sp out_vf;
520 struct ia_css_frame_sp_info internal_frame_info;
521 struct ia_css_buffer_sp s3a_buf;
522 struct ia_css_buffer_sp dvs_buf;
523 struct ia_css_buffer_sp metadata_buf;
524 };
525
526 /* Information for a single pipeline stage for an ISP */
527 struct sh_css_isp_stage {
528 /*
529 * For compatibility and portabilty, only types
530 * from "stdint.h" are allowed
531 *
532 * Use of "enum" and "bool" is prohibited
533 * Multiple boolean flags can be stored in an
534 * integer
535 */
536 struct ia_css_blob_info blob_info;
537 struct ia_css_binary_info binary_info;
538 char binary_name[SH_CSS_MAX_BINARY_NAME];
539 struct ia_css_isp_param_css_segments mem_initializers;
540 };
541
542 /* Information for a single pipeline stage */
543 struct sh_css_sp_stage {
544 /*
545 * For compatibility and portabilty, only types
546 * from "stdint.h" are allowed
547 *
548 * Use of "enum" and "bool" is prohibited
549 * Multiple boolean flags can be stored in an
550 * integer
551 */
552 u8 num; /* Stage number */
553 u8 isp_online;
554 u8 isp_copy_vf;
555 u8 isp_copy_output;
556 u8 sp_enable_xnr;
557 u8 isp_deci_log_factor;
558 u8 isp_vf_downscale_bits;
559 u8 deinterleaved;
560 /*
561 * NOTE: Programming the input circuit can only be done at the
562 * start of a session. It is illegal to program it during execution
563 * The input circuit defines the connectivity
564 */
565 u8 program_input_circuit;
566 /* enum ia_css_pipeline_stage_sp_func func; */
567 u8 func;
568 /* The type of the pipe-stage */
569 /* enum sh_css_stage_type stage_type; */
570 u8 stage_type;
571 u8 num_stripes;
572 u8 isp_pipe_version;
573 struct {
574 u8 vf_output;
575 u8 s3a;
576 u8 sdis;
577 u8 dvs_stats;
578 u8 lace_stats;
579 } enable;
580 /* Add padding to come to a word boundary */
581 /* unsigned char padding[0]; */
582
583 struct sh_css_crop_pos sp_out_crop_pos;
584 struct ia_css_frames_sp frames;
585 struct ia_css_resolution dvs_envelope;
586 struct sh_css_uds_info uds;
587 ia_css_ptr isp_stage_addr;
588 ia_css_ptr xmem_bin_addr;
589 ia_css_ptr xmem_map_addr;
590
591 u16 top_cropping;
592 u16 row_stripes_height;
593 u16 row_stripes_overlap_lines;
594 u8 if_config_index; /* Which should be applied by this stage. */
595 };
596
597 /*
598 * Time: 2012-07-19, 17:40.
599 * Note: Add a new data memeber "debug" in "sh_css_sp_group". This
600 * data member is used to pass the debugging command from the
601 * Host to the SP.
602 *
603 * Time: Before 2012-07-19.
604 * Note:
605 * Group all host initialized SP variables into this struct.
606 * This is initialized every stage through dma.
607 * The stage part itself is transferred through sh_css_sp_stage.
608 */
609 struct sh_css_sp_group {
610 struct sh_css_sp_config config;
611 struct sh_css_sp_pipeline pipe[SH_CSS_MAX_SP_THREADS];
612 struct sh_css_sp_pipeline_io pipe_io[SH_CSS_MAX_SP_THREADS];
613 struct sh_css_sp_pipeline_io_status pipe_io_status;
614 struct sh_css_sp_debug_command debug;
615 };
616
617 /* Data in SP dmem that is set from the host every stage. */
618 struct sh_css_sp_per_frame_data {
619 /* ddr address of sp_group and sp_stage */
620 ia_css_ptr sp_group_addr;
621 };
622
623 #define SH_CSS_NUM_SDW_IRQS 3
624
625 /* Output data from SP to css */
626 struct sh_css_sp_output {
627 unsigned int bin_copy_bytes_copied;
628 #if SP_DEBUG != SP_DEBUG_NONE
629 struct sh_css_sp_debug_state debug;
630 #endif
631 unsigned int sw_interrupt_value[SH_CSS_NUM_SDW_IRQS];
632 };
633
634 /**
635 * @brief Data structure for the circular buffer.
636 * The circular buffer is empty if "start == end". The
637 * circular buffer is full if "(end + 1) % size == start".
638 */
639 /* Variable Sized Buffer Queue Elements */
640
641 #define IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE 6
642 #define IA_CSS_NUM_ELEMS_HOST2SP_PARAM_QUEUE 3
643 #define IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE 6
644
645 /* sp-to-host queue is expected to be emptied in ISR since
646 * it is used instead of HW interrupts (due to HW design issue).
647 * We need one queue element per CSI port. */
648 #define IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE (2 * N_CSI_PORTS)
649 /* The host-to-sp queue needs to allow for some delay
650 * in the emptying of this queue in the SP since there is no
651 * separate SP thread for this. */
652 #define IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE (2 * N_CSI_PORTS)
653
654 #define IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE 13
655 #define IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE 19
656 #define IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE 26 /* holds events for all type of buffers, hence deeper */
657
658 struct sh_css_hmm_buffer {
659 union {
660 struct ia_css_isp_3a_statistics s3a;
661 struct ia_css_isp_dvs_statistics dis;
662 ia_css_ptr skc_dvs_statistics;
663 ia_css_ptr lace_stat;
664 struct ia_css_metadata metadata;
665 struct frame_data_wrapper {
666 ia_css_ptr frame_data;
667 u32 flashed;
668 u32 exp_id;
669 u32 isp_parameters_id; /** Unique ID to track which config was
670 actually applied to a particular frame */
671 } frame;
672 ia_css_ptr ddr_ptrs;
673 } payload;
674 /*
675 * kernel_ptr is present for host administration purposes only.
676 * type is uint64_t in order to be 64-bit host compatible.
677 * uint64_t does not exist on SP/ISP.
678 * Size of the struct is checked by sp.hive.c.
679 */
680 CSS_ALIGN(u64 cookie_ptr, 8); /* TODO: check if this alignment is needed */
681 u64 kernel_ptr;
682 struct ia_css_time_meas timing_data;
683 clock_value_t isys_eof_clock_tick;
684 };
685
686 #define SIZE_OF_FRAME_STRUCT \
687 (SIZE_OF_HRT_VADDRESS + \
688 (3 * sizeof(uint32_t)))
689
690 #define SIZE_OF_PAYLOAD_UNION \
691 (MAX(MAX(MAX(MAX( \
692 SIZE_OF_IA_CSS_ISP_3A_STATISTICS_STRUCT, \
693 SIZE_OF_IA_CSS_ISP_DVS_STATISTICS_STRUCT), \
694 SIZE_OF_IA_CSS_METADATA_STRUCT), \
695 SIZE_OF_FRAME_STRUCT), \
696 SIZE_OF_HRT_VADDRESS))
697
698 /* Do not use sizeof(uint64_t) since that does not exist of SP */
699 #define SIZE_OF_SH_CSS_HMM_BUFFER_STRUCT \
700 (SIZE_OF_PAYLOAD_UNION + \
701 CALC_ALIGNMENT_MEMBER(SIZE_OF_PAYLOAD_UNION, 8) + \
702 8 + \
703 8 + \
704 SIZE_OF_IA_CSS_TIME_MEAS_STRUCT + \
705 SIZE_OF_IA_CSS_CLOCK_TICK_STRUCT + \
706 CALC_ALIGNMENT_MEMBER(SIZE_OF_IA_CSS_CLOCK_TICK_STRUCT, 8))
707
708 enum sh_css_queue_type {
709 sh_css_invalid_queue_type = -1,
710 sh_css_host2sp_buffer_queue,
711 sh_css_sp2host_buffer_queue,
712 sh_css_host2sp_psys_event_queue,
713 sh_css_sp2host_psys_event_queue,
714 sh_css_sp2host_isys_event_queue,
715 sh_css_host2sp_isys_event_queue,
716 sh_css_host2sp_tag_cmd_queue,
717 };
718
719 struct sh_css_event_irq_mask {
720 u16 or_mask;
721 u16 and_mask;
722 };
723
724 #define SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT \
725 (2 * sizeof(uint16_t))
726
727 struct host_sp_communication {
728 /*
729 * Don't use enum host2sp_commands, because the sizeof an enum is
730 * compiler dependent and thus non-portable
731 */
732 u32 host2sp_command;
733
734 /*
735 * The frame buffers that are reused by the
736 * copy pipe in the offline preview mode.
737 *
738 * host2sp_offline_frames[0]: the input frame of the preview pipe.
739 * host2sp_offline_frames[1]: the output frame of the copy pipe.
740 *
741 * TODO:
742 * Remove it when the Host and the SP is decoupled.
743 */
744 ia_css_ptr host2sp_offline_frames[NUM_CONTINUOUS_FRAMES];
745 ia_css_ptr host2sp_offline_metadata[NUM_CONTINUOUS_FRAMES];
746
747 ia_css_ptr host2sp_mipi_frames[N_CSI_PORTS][NUM_MIPI_FRAMES_PER_STREAM];
748 ia_css_ptr host2sp_mipi_metadata[N_CSI_PORTS][NUM_MIPI_FRAMES_PER_STREAM];
749 u32 host2sp_num_mipi_frames[N_CSI_PORTS];
750 u32 host2sp_cont_avail_num_raw_frames;
751 u32 host2sp_cont_extra_num_raw_frames;
752 u32 host2sp_cont_target_num_raw_frames;
753 struct sh_css_event_irq_mask host2sp_event_irq_mask[NR_OF_PIPELINES];
754
755 };
756
757 #define SIZE_OF_HOST_SP_COMMUNICATION_STRUCT \
758 (sizeof(uint32_t) + \
759 (NUM_CONTINUOUS_FRAMES * SIZE_OF_HRT_VADDRESS * 2) + \
760 (N_CSI_PORTS * NUM_MIPI_FRAMES_PER_STREAM * SIZE_OF_HRT_VADDRESS * 2) + \
761 ((3 + N_CSI_PORTS) * sizeof(uint32_t)) + \
762 (NR_OF_PIPELINES * SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT))
763
764 struct host_sp_queues {
765 /*
766 * Queues for the dynamic frame information,
767 * i.e. the "in_frame" buffer, the "out_frame"
768 * buffer and the "vf_out_frame" buffer.
769 */
770 ia_css_circbuf_desc_t host2sp_buffer_queues_desc
771 [SH_CSS_MAX_SP_THREADS][SH_CSS_MAX_NUM_QUEUES];
772 ia_css_circbuf_elem_t host2sp_buffer_queues_elems
773 [SH_CSS_MAX_SP_THREADS][SH_CSS_MAX_NUM_QUEUES]
774 [IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE];
775 ia_css_circbuf_desc_t sp2host_buffer_queues_desc
776 [SH_CSS_MAX_NUM_QUEUES];
777 ia_css_circbuf_elem_t sp2host_buffer_queues_elems
778 [SH_CSS_MAX_NUM_QUEUES][IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE];
779
780 /*
781 * The queues for the events.
782 */
783 ia_css_circbuf_desc_t host2sp_psys_event_queue_desc;
784
785 ia_css_circbuf_elem_t host2sp_psys_event_queue_elems
786 [IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE];
787 ia_css_circbuf_desc_t sp2host_psys_event_queue_desc;
788
789 ia_css_circbuf_elem_t sp2host_psys_event_queue_elems
790 [IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE];
791
792 /*
793 * The queues for the ISYS events.
794 */
795 ia_css_circbuf_desc_t host2sp_isys_event_queue_desc;
796
797 ia_css_circbuf_elem_t host2sp_isys_event_queue_elems
798 [IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE];
799 ia_css_circbuf_desc_t sp2host_isys_event_queue_desc;
800
801 ia_css_circbuf_elem_t sp2host_isys_event_queue_elems
802 [IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE];
803 /*
804 * The queue for the tagger commands.
805 * CHECK: are these last two present on the 2401 ?
806 */
807 ia_css_circbuf_desc_t host2sp_tag_cmd_queue_desc;
808
809 ia_css_circbuf_elem_t host2sp_tag_cmd_queue_elems
810 [IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE];
811 };
812
813 #define SIZE_OF_QUEUES_ELEMS \
814 (SIZE_OF_IA_CSS_CIRCBUF_ELEM_S_STRUCT * \
815 ((SH_CSS_MAX_SP_THREADS * SH_CSS_MAX_NUM_QUEUES * IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE) + \
816 (SH_CSS_MAX_NUM_QUEUES * IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE) + \
817 (IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE) + \
818 (IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE) + \
819 (IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE) + \
820 (IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE) + \
821 (IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE)))
822
823 #define IA_CSS_NUM_CIRCBUF_DESCS 5
824
825 #define SIZE_OF_QUEUES_DESC \
826 ((SH_CSS_MAX_SP_THREADS * SH_CSS_MAX_NUM_QUEUES * \
827 SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT) + \
828 (SH_CSS_MAX_NUM_QUEUES * SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT) + \
829 (IA_CSS_NUM_CIRCBUF_DESCS * SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT))
830
831 #define SIZE_OF_HOST_SP_QUEUES_STRUCT \
832 (SIZE_OF_QUEUES_ELEMS + SIZE_OF_QUEUES_DESC)
833
834 extern int __printf(1, 0) (*sh_css_printf)(const char *fmt, va_list args);
835
sh_css_print(const char * fmt,...)836 static inline void __printf(1, 2) sh_css_print(const char *fmt, ...)
837 {
838 va_list ap;
839
840 if (sh_css_printf) {
841 va_start(ap, fmt);
842 sh_css_printf(fmt, ap);
843 va_end(ap);
844 }
845 }
846
sh_css_vprint(const char * fmt,va_list args)847 static inline void __printf(1, 0) sh_css_vprint(const char *fmt, va_list args)
848 {
849 if (sh_css_printf)
850 sh_css_printf(fmt, args);
851 }
852
853 /* The following #if is there because this header file is also included
854 by SP and ISP code but they do not need this data and HIVECC has alignment
855 issue with the firmware struct/union's.
856 More permanent solution will be to refactor this include.
857 */
858 ia_css_ptr sh_css_params_ddr_address_map(void);
859
860 int
861 sh_css_params_init(void);
862
863 void
864 sh_css_params_uninit(void);
865
866 void
867 sh_css_binary_args_reset(struct sh_css_binary_args *args);
868
869 /* Check two frames for equality (format, resolution, bits per element) */
870 bool
871 sh_css_frame_equal_types(const struct ia_css_frame *frame_a,
872 const struct ia_css_frame *frame_b);
873
874 bool
875 sh_css_frame_info_equal_resolution(const struct ia_css_frame_info *info_a,
876 const struct ia_css_frame_info *info_b);
877
878 void
879 sh_css_capture_enable_bayer_downscaling(bool enable);
880
881 void
882 sh_css_binary_print(const struct ia_css_binary *binary);
883
884 /* aligned argument of sh_css_frame_info_set_width can be used for an extra alignment requirement.
885 When 0, no extra alignment is done. */
886 void
887 sh_css_frame_info_set_width(struct ia_css_frame_info *info,
888 unsigned int width,
889 unsigned int aligned);
890
891
892 unsigned int
893 sh_css_get_mipi_sizes_for_check(const unsigned int port,
894 const unsigned int idx);
895
896
897 ia_css_ptr
898 sh_css_store_sp_group_to_ddr(void);
899
900 ia_css_ptr
901 sh_css_store_sp_stage_to_ddr(unsigned int pipe, unsigned int stage);
902
903 ia_css_ptr
904 sh_css_store_isp_stage_to_ddr(unsigned int pipe, unsigned int stage);
905
906 void
907 sh_css_update_uds_and_crop_info(
908 const struct ia_css_binary_info *info,
909 const struct ia_css_frame_info *in_frame_info,
910 const struct ia_css_frame_info *out_frame_info,
911 const struct ia_css_resolution *dvs_env,
912 const struct ia_css_dz_config *zoom,
913 const struct ia_css_vector *motion_vector,
914 struct sh_css_uds_info *uds, /* out */
915 struct sh_css_crop_pos *sp_out_crop_pos, /* out */
916
917 bool enable_zoom
918 );
919
920 void
921 sh_css_invalidate_shading_tables(struct ia_css_stream *stream);
922
923 struct ia_css_pipeline *
924 ia_css_pipe_get_pipeline(const struct ia_css_pipe *pipe);
925
926 unsigned int
927 ia_css_pipe_get_pipe_num(const struct ia_css_pipe *pipe);
928
929 unsigned int
930 ia_css_pipe_get_isp_pipe_version(const struct ia_css_pipe *pipe);
931
932 bool
933 sh_css_continuous_is_enabled(uint8_t pipe_num);
934
935 struct ia_css_pipe *
936 find_pipe_by_num(uint32_t pipe_num);
937
938 void
939 ia_css_get_crop_offsets(
940 struct ia_css_pipe *pipe,
941 struct ia_css_frame_info *in_frame);
942
943 #endif /* _SH_CSS_INTERNAL_H_ */
944