1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Cedrus VPU driver 4 * 5 * Copyright (c) 2013-2016 Jens Kuske <jenskuske@gmail.com> 6 * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com> 7 * Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com> 8 */ 9 10 #ifndef _CEDRUS_REGS_H_ 11 #define _CEDRUS_REGS_H_ 12 13 /* 14 * Common acronyms and contractions used in register descriptions: 15 * * VLD : Variable-Length Decoder 16 * * IQ: Inverse Quantization 17 * * IDCT: Inverse Discrete Cosine Transform 18 * * MC: Motion Compensation 19 * * STCD: Start Code Detect 20 * * SDRT: Scale Down and Rotate 21 */ 22 23 #define VE_ENGINE_DEC_MPEG 0x100 24 #define VE_ENGINE_DEC_H264 0x200 25 26 #define VE_MODE 0x00 27 28 #define VE_MODE_REC_WR_MODE_2MB (0x01 << 20) 29 #define VE_MODE_REC_WR_MODE_1MB (0x00 << 20) 30 #define VE_MODE_DDR_MODE_BW_128 (0x03 << 16) 31 #define VE_MODE_DDR_MODE_BW_256 (0x02 << 16) 32 #define VE_MODE_DISABLED (0x07 << 0) 33 #define VE_MODE_DEC_H265 (0x04 << 0) 34 #define VE_MODE_DEC_H264 (0x01 << 0) 35 #define VE_MODE_DEC_MPEG (0x00 << 0) 36 37 #define VE_PRIMARY_CHROMA_BUF_LEN 0xc4 38 #define VE_PRIMARY_FB_LINE_STRIDE 0xc8 39 40 #define VE_PRIMARY_FB_LINE_STRIDE_CHROMA(s) (((s) << 16) & GENMASK(31, 16)) 41 #define VE_PRIMARY_FB_LINE_STRIDE_LUMA(s) (((s) << 0) & GENMASK(15, 0)) 42 43 #define VE_CHROMA_BUF_LEN 0xe8 44 45 #define VE_SECONDARY_OUT_FMT_TILED_32_NV12 (0x00 << 30) 46 #define VE_SECONDARY_OUT_FMT_EXT (0x01 << 30) 47 #define VE_SECONDARY_OUT_FMT_YU12 (0x02 << 30) 48 #define VE_SECONDARY_OUT_FMT_YV12 (0x03 << 30) 49 #define VE_CHROMA_BUF_LEN_SDRT(l) ((l) & GENMASK(27, 0)) 50 51 #define VE_PRIMARY_OUT_FMT 0xec 52 53 #define VE_PRIMARY_OUT_FMT_TILED_32_NV12 (0x00 << 4) 54 #define VE_PRIMARY_OUT_FMT_TILED_128_NV12 (0x01 << 4) 55 #define VE_PRIMARY_OUT_FMT_YU12 (0x02 << 4) 56 #define VE_PRIMARY_OUT_FMT_YV12 (0x03 << 4) 57 #define VE_PRIMARY_OUT_FMT_NV12 (0x04 << 4) 58 #define VE_PRIMARY_OUT_FMT_NV21 (0x05 << 4) 59 #define VE_SECONDARY_OUT_FMT_EXT_TILED_32_NV12 (0x00 << 0) 60 #define VE_SECONDARY_OUT_FMT_EXT_TILED_128_NV12 (0x01 << 0) 61 #define VE_SECONDARY_OUT_FMT_EXT_YU12 (0x02 << 0) 62 #define VE_SECONDARY_OUT_FMT_EXT_YV12 (0x03 << 0) 63 #define VE_SECONDARY_OUT_FMT_EXT_NV12 (0x04 << 0) 64 #define VE_SECONDARY_OUT_FMT_EXT_NV21 (0x05 << 0) 65 66 #define VE_VERSION 0xf0 67 68 #define VE_VERSION_SHIFT 16 69 70 #define VE_DEC_MPEG_MP12HDR (VE_ENGINE_DEC_MPEG + 0x00) 71 72 #define VE_DEC_MPEG_MP12HDR_SLICE_TYPE(t) (((t) << 28) & GENMASK(30, 28)) 73 #define VE_DEC_MPEG_MP12HDR_F_CODE_SHIFT(x, y) (24 - 4 * (y) - 8 * (x)) 74 #define VE_DEC_MPEG_MP12HDR_F_CODE(__x, __y, __v) \ 75 (((__v) & GENMASK(3, 0)) << VE_DEC_MPEG_MP12HDR_F_CODE_SHIFT(__x, __y)) 76 77 #define VE_DEC_MPEG_MP12HDR_INTRA_DC_PRECISION(p) \ 78 (((p) << 10) & GENMASK(11, 10)) 79 #define VE_DEC_MPEG_MP12HDR_INTRA_PICTURE_STRUCTURE(s) \ 80 (((s) << 8) & GENMASK(9, 8)) 81 #define VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(v) \ 82 ((v) ? BIT(7) : 0) 83 #define VE_DEC_MPEG_MP12HDR_FRAME_PRED_FRAME_DCT(v) \ 84 ((v) ? BIT(6) : 0) 85 #define VE_DEC_MPEG_MP12HDR_CONCEALMENT_MOTION_VECTORS(v) \ 86 ((v) ? BIT(5) : 0) 87 #define VE_DEC_MPEG_MP12HDR_Q_SCALE_TYPE(v) \ 88 ((v) ? BIT(4) : 0) 89 #define VE_DEC_MPEG_MP12HDR_INTRA_VLC_FORMAT(v) \ 90 ((v) ? BIT(3) : 0) 91 #define VE_DEC_MPEG_MP12HDR_ALTERNATE_SCAN(v) \ 92 ((v) ? BIT(2) : 0) 93 #define VE_DEC_MPEG_MP12HDR_FULL_PEL_FORWARD_VECTOR(v) \ 94 ((v) ? BIT(1) : 0) 95 #define VE_DEC_MPEG_MP12HDR_FULL_PEL_BACKWARD_VECTOR(v) \ 96 ((v) ? BIT(0) : 0) 97 98 #define VE_DEC_MPEG_PICCODEDSIZE (VE_ENGINE_DEC_MPEG + 0x08) 99 100 #define VE_DEC_MPEG_PICCODEDSIZE_WIDTH(w) \ 101 ((DIV_ROUND_UP((w), 16) << 8) & GENMASK(15, 8)) 102 #define VE_DEC_MPEG_PICCODEDSIZE_HEIGHT(h) \ 103 ((DIV_ROUND_UP((h), 16) << 0) & GENMASK(7, 0)) 104 105 #define VE_DEC_MPEG_PICBOUNDSIZE (VE_ENGINE_DEC_MPEG + 0x0c) 106 107 #define VE_DEC_MPEG_PICBOUNDSIZE_WIDTH(w) (((w) << 16) & GENMASK(27, 16)) 108 #define VE_DEC_MPEG_PICBOUNDSIZE_HEIGHT(h) (((h) << 0) & GENMASK(11, 0)) 109 110 #define VE_DEC_MPEG_MBADDR (VE_ENGINE_DEC_MPEG + 0x10) 111 112 #define VE_DEC_MPEG_MBADDR_X(w) (((w) << 8) & GENMASK(15, 8)) 113 #define VE_DEC_MPEG_MBADDR_Y(h) (((h) << 0) & GENMASK(7, 0)) 114 115 #define VE_DEC_MPEG_CTRL (VE_ENGINE_DEC_MPEG + 0x14) 116 117 #define VE_DEC_MPEG_CTRL_MC_CACHE_EN BIT(31) 118 #define VE_DEC_MPEG_CTRL_SW_VLD BIT(27) 119 #define VE_DEC_MPEG_CTRL_SW_IQ_IS BIT(17) 120 #define VE_DEC_MPEG_CTRL_QP_AC_DC_OUT_EN BIT(14) 121 #define VE_DEC_MPEG_CTRL_ROTATE_SCALE_OUT_EN BIT(8) 122 #define VE_DEC_MPEG_CTRL_MC_NO_WRITEBACK BIT(7) 123 #define VE_DEC_MPEG_CTRL_ROTATE_IRQ_EN BIT(6) 124 #define VE_DEC_MPEG_CTRL_VLD_DATA_REQ_IRQ_EN BIT(5) 125 #define VE_DEC_MPEG_CTRL_ERROR_IRQ_EN BIT(4) 126 #define VE_DEC_MPEG_CTRL_FINISH_IRQ_EN BIT(3) 127 #define VE_DEC_MPEG_CTRL_IRQ_MASK \ 128 (VE_DEC_MPEG_CTRL_FINISH_IRQ_EN | VE_DEC_MPEG_CTRL_ERROR_IRQ_EN | \ 129 VE_DEC_MPEG_CTRL_VLD_DATA_REQ_IRQ_EN) 130 131 #define VE_DEC_MPEG_TRIGGER (VE_ENGINE_DEC_MPEG + 0x18) 132 133 #define VE_DEC_MPEG_TRIGGER_MB_BOUNDARY BIT(31) 134 135 #define VE_DEC_MPEG_TRIGGER_CHROMA_FMT_420 (0x00 << 27) 136 #define VE_DEC_MPEG_TRIGGER_CHROMA_FMT_411 (0x01 << 27) 137 #define VE_DEC_MPEG_TRIGGER_CHROMA_FMT_422 (0x02 << 27) 138 #define VE_DEC_MPEG_TRIGGER_CHROMA_FMT_444 (0x03 << 27) 139 #define VE_DEC_MPEG_TRIGGER_CHROMA_FMT_422T (0x04 << 27) 140 141 #define VE_DEC_MPEG_TRIGGER_MPEG1 (0x01 << 24) 142 #define VE_DEC_MPEG_TRIGGER_MPEG2 (0x02 << 24) 143 #define VE_DEC_MPEG_TRIGGER_JPEG (0x03 << 24) 144 #define VE_DEC_MPEG_TRIGGER_MPEG4 (0x04 << 24) 145 #define VE_DEC_MPEG_TRIGGER_VP62 (0x05 << 24) 146 147 #define VE_DEC_MPEG_TRIGGER_VP62_AC_GET_BITS BIT(7) 148 149 #define VE_DEC_MPEG_TRIGGER_STCD_VC1 (0x02 << 4) 150 #define VE_DEC_MPEG_TRIGGER_STCD_MPEG2 (0x01 << 4) 151 #define VE_DEC_MPEG_TRIGGER_STCD_AVC (0x00 << 4) 152 153 #define VE_DEC_MPEG_TRIGGER_HW_MPEG_VLD (0x0f << 0) 154 #define VE_DEC_MPEG_TRIGGER_HW_JPEG_VLD (0x0e << 0) 155 #define VE_DEC_MPEG_TRIGGER_HW_MB (0x0d << 0) 156 #define VE_DEC_MPEG_TRIGGER_HW_ROTATE (0x0c << 0) 157 #define VE_DEC_MPEG_TRIGGER_HW_VP6_VLD (0x0b << 0) 158 #define VE_DEC_MPEG_TRIGGER_HW_MAF (0x0a << 0) 159 #define VE_DEC_MPEG_TRIGGER_HW_STCD_END (0x09 << 0) 160 #define VE_DEC_MPEG_TRIGGER_HW_STCD_BEGIN (0x08 << 0) 161 #define VE_DEC_MPEG_TRIGGER_SW_MC (0x07 << 0) 162 #define VE_DEC_MPEG_TRIGGER_SW_IQ (0x06 << 0) 163 #define VE_DEC_MPEG_TRIGGER_SW_IDCT (0x05 << 0) 164 #define VE_DEC_MPEG_TRIGGER_SW_SCALE (0x04 << 0) 165 #define VE_DEC_MPEG_TRIGGER_SW_VP6 (0x03 << 0) 166 #define VE_DEC_MPEG_TRIGGER_SW_VP62_AC_GET_BITS (0x02 << 0) 167 168 #define VE_DEC_MPEG_STATUS (VE_ENGINE_DEC_MPEG + 0x1c) 169 170 #define VE_DEC_MPEG_STATUS_START_DETECT_BUSY BIT(27) 171 #define VE_DEC_MPEG_STATUS_VP6_BIT BIT(26) 172 #define VE_DEC_MPEG_STATUS_VP6_BIT_BUSY BIT(25) 173 #define VE_DEC_MPEG_STATUS_MAF_BUSY BIT(23) 174 #define VE_DEC_MPEG_STATUS_VP6_MVP_BUSY BIT(22) 175 #define VE_DEC_MPEG_STATUS_JPEG_BIT_END BIT(21) 176 #define VE_DEC_MPEG_STATUS_JPEG_RESTART_ERROR BIT(20) 177 #define VE_DEC_MPEG_STATUS_JPEG_MARKER BIT(19) 178 #define VE_DEC_MPEG_STATUS_ROTATE_BUSY BIT(18) 179 #define VE_DEC_MPEG_STATUS_DEBLOCKING_BUSY BIT(17) 180 #define VE_DEC_MPEG_STATUS_SCALE_DOWN_BUSY BIT(16) 181 #define VE_DEC_MPEG_STATUS_IQIS_BUF_EMPTY BIT(15) 182 #define VE_DEC_MPEG_STATUS_IDCT_BUF_EMPTY BIT(14) 183 #define VE_DEC_MPEG_STATUS_VE_BUSY BIT(13) 184 #define VE_DEC_MPEG_STATUS_MC_BUSY BIT(12) 185 #define VE_DEC_MPEG_STATUS_IDCT_BUSY BIT(11) 186 #define VE_DEC_MPEG_STATUS_IQIS_BUSY BIT(10) 187 #define VE_DEC_MPEG_STATUS_DCAC_BUSY BIT(9) 188 #define VE_DEC_MPEG_STATUS_VLD_BUSY BIT(8) 189 #define VE_DEC_MPEG_STATUS_ROTATE_SUCCESS BIT(3) 190 #define VE_DEC_MPEG_STATUS_VLD_DATA_REQ BIT(2) 191 #define VE_DEC_MPEG_STATUS_ERROR BIT(1) 192 #define VE_DEC_MPEG_STATUS_SUCCESS BIT(0) 193 #define VE_DEC_MPEG_STATUS_CHECK_MASK \ 194 (VE_DEC_MPEG_STATUS_SUCCESS | VE_DEC_MPEG_STATUS_ERROR | \ 195 VE_DEC_MPEG_STATUS_VLD_DATA_REQ) 196 #define VE_DEC_MPEG_STATUS_CHECK_ERROR \ 197 (VE_DEC_MPEG_STATUS_ERROR | VE_DEC_MPEG_STATUS_VLD_DATA_REQ) 198 199 #define VE_DEC_MPEG_VLD_ADDR (VE_ENGINE_DEC_MPEG + 0x28) 200 201 #define VE_DEC_MPEG_VLD_ADDR_FIRST_PIC_DATA BIT(30) 202 #define VE_DEC_MPEG_VLD_ADDR_LAST_PIC_DATA BIT(29) 203 #define VE_DEC_MPEG_VLD_ADDR_VALID_PIC_DATA BIT(28) 204 #define VE_DEC_MPEG_VLD_ADDR_BASE(a) \ 205 ({ \ 206 u32 _tmp = (a); \ 207 u32 _lo = _tmp & GENMASK(27, 4); \ 208 u32 _hi = (_tmp >> 28) & GENMASK(3, 0); \ 209 (_lo | _hi); \ 210 }) 211 212 #define VE_DEC_MPEG_VLD_OFFSET (VE_ENGINE_DEC_MPEG + 0x2c) 213 #define VE_DEC_MPEG_VLD_LEN (VE_ENGINE_DEC_MPEG + 0x30) 214 #define VE_DEC_MPEG_VLD_END_ADDR (VE_ENGINE_DEC_MPEG + 0x34) 215 216 #define VE_DEC_MPEG_REC_LUMA (VE_ENGINE_DEC_MPEG + 0x48) 217 #define VE_DEC_MPEG_REC_CHROMA (VE_ENGINE_DEC_MPEG + 0x4c) 218 #define VE_DEC_MPEG_FWD_REF_LUMA_ADDR (VE_ENGINE_DEC_MPEG + 0x50) 219 #define VE_DEC_MPEG_FWD_REF_CHROMA_ADDR (VE_ENGINE_DEC_MPEG + 0x54) 220 #define VE_DEC_MPEG_BWD_REF_LUMA_ADDR (VE_ENGINE_DEC_MPEG + 0x58) 221 #define VE_DEC_MPEG_BWD_REF_CHROMA_ADDR (VE_ENGINE_DEC_MPEG + 0x5c) 222 223 #define VE_DEC_MPEG_IQMINPUT (VE_ENGINE_DEC_MPEG + 0x80) 224 225 #define VE_DEC_MPEG_IQMINPUT_FLAG_INTRA (0x01 << 14) 226 #define VE_DEC_MPEG_IQMINPUT_FLAG_NON_INTRA (0x00 << 14) 227 #define VE_DEC_MPEG_IQMINPUT_WEIGHT(i, v) \ 228 (((v) & GENMASK(7, 0)) | (((i) << 8) & GENMASK(13, 8))) 229 230 #define VE_DEC_MPEG_ERROR (VE_ENGINE_DEC_MPEG + 0xc4) 231 #define VE_DEC_MPEG_CRTMBADDR (VE_ENGINE_DEC_MPEG + 0xc8) 232 #define VE_DEC_MPEG_ROT_LUMA (VE_ENGINE_DEC_MPEG + 0xcc) 233 #define VE_DEC_MPEG_ROT_CHROMA (VE_ENGINE_DEC_MPEG + 0xd0) 234 235 #define VE_H264_SPS 0x200 236 #define VE_H264_SPS_MBS_ONLY BIT(18) 237 #define VE_H264_SPS_MB_ADAPTIVE_FRAME_FIELD BIT(17) 238 #define VE_H264_SPS_DIRECT_8X8_INFERENCE BIT(16) 239 240 #define VE_H264_PPS 0x204 241 #define VE_H264_PPS_ENTROPY_CODING_MODE BIT(15) 242 #define VE_H264_PPS_WEIGHTED_PRED BIT(4) 243 #define VE_H264_PPS_CONSTRAINED_INTRA_PRED BIT(1) 244 #define VE_H264_PPS_TRANSFORM_8X8_MODE BIT(0) 245 246 #define VE_H264_SHS 0x208 247 #define VE_H264_SHS_FIRST_SLICE_IN_PIC BIT(5) 248 #define VE_H264_SHS_FIELD_PIC BIT(4) 249 #define VE_H264_SHS_BOTTOM_FIELD BIT(3) 250 #define VE_H264_SHS_DIRECT_SPATIAL_MV_PRED BIT(2) 251 252 #define VE_H264_SHS2 0x20c 253 #define VE_H264_SHS2_NUM_REF_IDX_ACTIVE_OVRD BIT(12) 254 255 #define VE_H264_SHS_WP 0x210 256 257 #define VE_H264_SHS_QP 0x21c 258 #define VE_H264_SHS_QP_SCALING_MATRIX_DEFAULT BIT(24) 259 260 #define VE_H264_CTRL 0x220 261 #define VE_H264_CTRL_VLD_DATA_REQ_INT BIT(2) 262 #define VE_H264_CTRL_DECODE_ERR_INT BIT(1) 263 #define VE_H264_CTRL_SLICE_DECODE_INT BIT(0) 264 265 #define VE_H264_CTRL_INT_MASK (VE_H264_CTRL_VLD_DATA_REQ_INT | \ 266 VE_H264_CTRL_DECODE_ERR_INT | \ 267 VE_H264_CTRL_SLICE_DECODE_INT) 268 269 #define VE_H264_TRIGGER_TYPE 0x224 270 #define VE_H264_TRIGGER_TYPE_AVC_SLICE_DECODE (8 << 0) 271 #define VE_H264_TRIGGER_TYPE_INIT_SWDEC (7 << 0) 272 273 #define VE_H264_STATUS 0x228 274 #define VE_H264_STATUS_VLD_DATA_REQ_INT VE_H264_CTRL_VLD_DATA_REQ_INT 275 #define VE_H264_STATUS_DECODE_ERR_INT VE_H264_CTRL_DECODE_ERR_INT 276 #define VE_H264_STATUS_SLICE_DECODE_INT VE_H264_CTRL_SLICE_DECODE_INT 277 278 #define VE_H264_STATUS_INT_MASK VE_H264_CTRL_INT_MASK 279 280 #define VE_H264_CUR_MB_NUM 0x22c 281 282 #define VE_H264_VLD_ADDR 0x230 283 #define VE_H264_VLD_ADDR_FIRST BIT(30) 284 #define VE_H264_VLD_ADDR_LAST BIT(29) 285 #define VE_H264_VLD_ADDR_VALID BIT(28) 286 #define VE_H264_VLD_ADDR_VAL(x) (((x) & 0x0ffffff0) | ((x) >> 28)) 287 288 #define VE_H264_VLD_OFFSET 0x234 289 #define VE_H264_VLD_LEN 0x238 290 #define VE_H264_VLD_END 0x23c 291 #define VE_H264_SDROT_CTRL 0x240 292 #define VE_H264_OUTPUT_FRAME_IDX 0x24c 293 #define VE_H264_EXTRA_BUFFER1 0x250 294 #define VE_H264_EXTRA_BUFFER2 0x254 295 #define VE_H264_BASIC_BITS 0x2dc 296 #define VE_AVC_SRAM_PORT_OFFSET 0x2e0 297 #define VE_AVC_SRAM_PORT_DATA 0x2e4 298 299 #define VE_ISP_INPUT_SIZE 0xa00 300 #define VE_ISP_INPUT_STRIDE 0xa04 301 #define VE_ISP_CTRL 0xa08 302 #define VE_ISP_INPUT_LUMA 0xa78 303 #define VE_ISP_INPUT_CHROMA 0xa7c 304 305 #define VE_AVC_PARAM 0xb04 306 #define VE_AVC_QP 0xb08 307 #define VE_AVC_MOTION_EST 0xb10 308 #define VE_AVC_CTRL 0xb14 309 #define VE_AVC_TRIGGER 0xb18 310 #define VE_AVC_STATUS 0xb1c 311 #define VE_AVC_BASIC_BITS 0xb20 312 #define VE_AVC_UNK_BUF 0xb60 313 #define VE_AVC_VLE_ADDR 0xb80 314 #define VE_AVC_VLE_END 0xb84 315 #define VE_AVC_VLE_OFFSET 0xb88 316 #define VE_AVC_VLE_MAX 0xb8c 317 #define VE_AVC_VLE_LENGTH 0xb90 318 #define VE_AVC_REF_LUMA 0xba0 319 #define VE_AVC_REF_CHROMA 0xba4 320 #define VE_AVC_REC_LUMA 0xbb0 321 #define VE_AVC_REC_CHROMA 0xbb4 322 #define VE_AVC_REF_SLUMA 0xbb8 323 #define VE_AVC_REC_SLUMA 0xbbc 324 #define VE_AVC_MB_INFO 0xbc0 325 326 #endif 327