1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. 4 * 5 * Based on the r8180 driver, which is: 6 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al. 7 * 8 * Contact Information: wlanfae <wlanfae@realtek.com> 9 */ 10 #include "rtl_core.h" 11 #include "r8192E_phy.h" 12 #include "r8192E_phyreg.h" 13 #include "r8190P_rtl8256.h" 14 #include "r8192E_cmdpkt.h" 15 #include "rtl_dm.h" 16 #include "rtl_wx.h" 17 18 static int WDCAPARA_ADD[] = {EDCAPARA_BE, EDCAPARA_BK, EDCAPARA_VI, 19 EDCAPARA_VO}; 20 21 void rtl92e_start_beacon(struct net_device *dev) 22 { 23 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); 24 struct rtllib_network *net = &priv->rtllib->current_network; 25 u16 BcnTimeCfg = 0; 26 u16 BcnCW = 6; 27 u16 BcnIFS = 0xf; 28 29 rtl92e_irq_disable(dev); 30 31 rtl92e_writew(dev, ATIMWND, 2); 32 33 rtl92e_writew(dev, BCN_INTERVAL, net->beacon_interval); 34 rtl92e_writew(dev, BCN_DRV_EARLY_INT, 10); 35 rtl92e_writew(dev, BCN_DMATIME, 256); 36 37 rtl92e_writeb(dev, BCN_ERR_THRESH, 100); 38 39 BcnTimeCfg |= BcnCW<<BCN_TCFG_CW_SHIFT; 40 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS; 41 rtl92e_writew(dev, BCN_TCFG, BcnTimeCfg); 42 rtl92e_irq_enable(dev); 43 } 44 45 static void _rtl92e_update_msr(struct net_device *dev) 46 { 47 struct r8192_priv *priv = rtllib_priv(dev); 48 u8 msr; 49 enum led_ctl_mode LedAction = LED_CTL_NO_LINK; 50 51 msr = rtl92e_readb(dev, MSR); 52 msr &= ~MSR_LINK_MASK; 53 54 switch (priv->rtllib->iw_mode) { 55 case IW_MODE_INFRA: 56 if (priv->rtllib->state == RTLLIB_LINKED) 57 msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT); 58 else 59 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT); 60 LedAction = LED_CTL_LINK; 61 break; 62 case IW_MODE_ADHOC: 63 if (priv->rtllib->state == RTLLIB_LINKED) 64 msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT); 65 else 66 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT); 67 break; 68 case IW_MODE_MASTER: 69 if (priv->rtllib->state == RTLLIB_LINKED) 70 msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT); 71 else 72 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT); 73 break; 74 default: 75 break; 76 } 77 78 rtl92e_writeb(dev, MSR, msr); 79 if (priv->rtllib->LedControlHandler) 80 priv->rtllib->LedControlHandler(dev, LedAction); 81 } 82 83 void rtl92e_set_reg(struct net_device *dev, u8 variable, u8 *val) 84 { 85 struct r8192_priv *priv = rtllib_priv(dev); 86 87 switch (variable) { 88 case HW_VAR_BSSID: 89 /* BSSIDR 2 byte alignment */ 90 rtl92e_writew(dev, BSSIDR, *(u16 *)val); 91 rtl92e_writel(dev, BSSIDR + 2, *(u32 *)(val + 2)); 92 break; 93 94 case HW_VAR_MEDIA_STATUS: 95 { 96 enum rt_op_mode OpMode = *((enum rt_op_mode *)(val)); 97 u8 btMsr = rtl92e_readb(dev, MSR); 98 99 btMsr &= 0xfc; 100 101 switch (OpMode) { 102 case RT_OP_MODE_INFRASTRUCTURE: 103 btMsr |= MSR_INFRA; 104 break; 105 106 case RT_OP_MODE_IBSS: 107 btMsr |= MSR_ADHOC; 108 break; 109 110 case RT_OP_MODE_AP: 111 btMsr |= MSR_AP; 112 break; 113 114 default: 115 btMsr |= MSR_NOLINK; 116 break; 117 } 118 119 rtl92e_writeb(dev, MSR, btMsr); 120 121 } 122 break; 123 124 case HW_VAR_CECHK_BSSID: 125 { 126 u32 RegRCR, Type; 127 128 Type = val[0]; 129 RegRCR = rtl92e_readl(dev, RCR); 130 priv->ReceiveConfig = RegRCR; 131 132 if (Type) 133 RegRCR |= (RCR_CBSSID); 134 else 135 RegRCR &= (~RCR_CBSSID); 136 137 rtl92e_writel(dev, RCR, RegRCR); 138 priv->ReceiveConfig = RegRCR; 139 140 } 141 break; 142 143 case HW_VAR_SLOT_TIME: 144 145 priv->slot_time = val[0]; 146 rtl92e_writeb(dev, SLOT_TIME, val[0]); 147 148 break; 149 150 case HW_VAR_ACK_PREAMBLE: 151 { 152 u32 regTmp; 153 154 priv->short_preamble = (bool)*val; 155 regTmp = priv->basic_rate; 156 if (priv->short_preamble) 157 regTmp |= BRSR_AckShortPmb; 158 rtl92e_writel(dev, RRSR, regTmp); 159 break; 160 } 161 162 case HW_VAR_CPU_RST: 163 rtl92e_writel(dev, CPU_GEN, ((u32 *)(val))[0]); 164 break; 165 166 case HW_VAR_AC_PARAM: 167 { 168 u8 pAcParam = *val; 169 u32 eACI = pAcParam; 170 u8 u1bAIFS; 171 u32 u4bAcParam; 172 u8 mode = priv->rtllib->mode; 173 struct rtllib_qos_parameters *qop = 174 &priv->rtllib->current_network.qos_data.parameters; 175 176 u1bAIFS = qop->aifs[pAcParam] * 177 ((mode&(IEEE_G|IEEE_N_24G)) ? 9 : 20) + aSifsTime; 178 179 rtl92e_dm_init_edca_turbo(dev); 180 181 u4bAcParam = (le16_to_cpu(qop->tx_op_limit[pAcParam]) << 182 AC_PARAM_TXOP_LIMIT_OFFSET) | 183 ((le16_to_cpu(qop->cw_max[pAcParam])) << 184 AC_PARAM_ECW_MAX_OFFSET) | 185 ((le16_to_cpu(qop->cw_min[pAcParam])) << 186 AC_PARAM_ECW_MIN_OFFSET) | 187 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET); 188 189 RT_TRACE(COMP_DBG, "%s():HW_VAR_AC_PARAM eACI:%x:%x\n", 190 __func__, eACI, u4bAcParam); 191 switch (eACI) { 192 case AC1_BK: 193 rtl92e_writel(dev, EDCAPARA_BK, u4bAcParam); 194 break; 195 196 case AC0_BE: 197 rtl92e_writel(dev, EDCAPARA_BE, u4bAcParam); 198 break; 199 200 case AC2_VI: 201 rtl92e_writel(dev, EDCAPARA_VI, u4bAcParam); 202 break; 203 204 case AC3_VO: 205 rtl92e_writel(dev, EDCAPARA_VO, u4bAcParam); 206 break; 207 208 default: 209 netdev_info(dev, "SetHwReg8185(): invalid ACI: %d !\n", 210 eACI); 211 break; 212 } 213 priv->rtllib->SetHwRegHandler(dev, HW_VAR_ACM_CTRL, 214 &pAcParam); 215 break; 216 } 217 218 case HW_VAR_ACM_CTRL: 219 { 220 struct rtllib_qos_parameters *qos_parameters = 221 &priv->rtllib->current_network.qos_data.parameters; 222 u8 pAcParam = *val; 223 u32 eACI = pAcParam; 224 union aci_aifsn *pAciAifsn = (union aci_aifsn *)& 225 (qos_parameters->aifs[0]); 226 u8 acm = pAciAifsn->f.acm; 227 u8 AcmCtrl = rtl92e_readb(dev, AcmHwCtrl); 228 229 RT_TRACE(COMP_DBG, "===========>%s():HW_VAR_ACM_CTRL:%x\n", 230 __func__, eACI); 231 AcmCtrl = AcmCtrl | ((priv->AcmMethod == 2) ? 0x0 : 0x1); 232 233 if (acm) { 234 switch (eACI) { 235 case AC0_BE: 236 AcmCtrl |= AcmHw_BeqEn; 237 break; 238 239 case AC2_VI: 240 AcmCtrl |= AcmHw_ViqEn; 241 break; 242 243 case AC3_VO: 244 AcmCtrl |= AcmHw_VoqEn; 245 break; 246 247 default: 248 RT_TRACE(COMP_QOS, 249 "SetHwReg8185(): [HW_VAR_ACM_CTRL] acm set failed: eACI is %d\n", 250 eACI); 251 break; 252 } 253 } else { 254 switch (eACI) { 255 case AC0_BE: 256 AcmCtrl &= (~AcmHw_BeqEn); 257 break; 258 259 case AC2_VI: 260 AcmCtrl &= (~AcmHw_ViqEn); 261 break; 262 263 case AC3_VO: 264 AcmCtrl &= (~AcmHw_BeqEn); 265 break; 266 267 default: 268 break; 269 } 270 } 271 272 RT_TRACE(COMP_QOS, 273 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", 274 AcmCtrl); 275 rtl92e_writeb(dev, AcmHwCtrl, AcmCtrl); 276 break; 277 } 278 279 case HW_VAR_SIFS: 280 rtl92e_writeb(dev, SIFS, val[0]); 281 rtl92e_writeb(dev, SIFS+1, val[0]); 282 break; 283 284 case HW_VAR_RF_TIMING: 285 { 286 u8 Rf_Timing = *val; 287 288 rtl92e_writeb(dev, rFPGA0_RFTiming1, Rf_Timing); 289 break; 290 } 291 292 default: 293 break; 294 } 295 296 } 297 298 static void _rtl92e_read_eeprom_info(struct net_device *dev) 299 { 300 struct r8192_priv *priv = rtllib_priv(dev); 301 const u8 bMac_Tmp_Addr[ETH_ALEN] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x01}; 302 u8 tempval; 303 u8 ICVer8192, ICVer8256; 304 u16 i, usValue, IC_Version; 305 u16 EEPROMId; 306 307 RT_TRACE(COMP_INIT, "====> %s\n", __func__); 308 309 EEPROMId = rtl92e_eeprom_read(dev, 0); 310 if (EEPROMId != RTL8190_EEPROM_ID) { 311 netdev_err(dev, "%s(): Invalid EEPROM ID: %x\n", __func__, 312 EEPROMId); 313 priv->AutoloadFailFlag = true; 314 } else { 315 priv->AutoloadFailFlag = false; 316 } 317 318 if (!priv->AutoloadFailFlag) { 319 priv->eeprom_vid = rtl92e_eeprom_read(dev, EEPROM_VID >> 1); 320 priv->eeprom_did = rtl92e_eeprom_read(dev, EEPROM_DID >> 1); 321 322 usValue = rtl92e_eeprom_read(dev, 323 (EEPROM_Customer_ID >> 1)) >> 8; 324 priv->eeprom_CustomerID = usValue & 0xff; 325 usValue = rtl92e_eeprom_read(dev, 326 EEPROM_ICVersion_ChannelPlan>>1); 327 priv->eeprom_ChannelPlan = usValue&0xff; 328 IC_Version = (usValue & 0xff00)>>8; 329 330 ICVer8192 = IC_Version & 0xf; 331 ICVer8256 = (IC_Version & 0xf0)>>4; 332 RT_TRACE(COMP_INIT, "\nICVer8192 = 0x%x\n", ICVer8192); 333 RT_TRACE(COMP_INIT, "\nICVer8256 = 0x%x\n", ICVer8256); 334 if (ICVer8192 == 0x2) { 335 if (ICVer8256 == 0x5) 336 priv->card_8192_version = VERSION_8190_BE; 337 } 338 switch (priv->card_8192_version) { 339 case VERSION_8190_BD: 340 case VERSION_8190_BE: 341 break; 342 default: 343 priv->card_8192_version = VERSION_8190_BD; 344 break; 345 } 346 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n", 347 priv->card_8192_version); 348 } else { 349 priv->card_8192_version = VERSION_8190_BD; 350 priv->eeprom_vid = 0; 351 priv->eeprom_did = 0; 352 priv->eeprom_CustomerID = 0; 353 priv->eeprom_ChannelPlan = 0; 354 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n", 0xff); 355 } 356 357 RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid); 358 RT_TRACE(COMP_INIT, "EEPROM DID = 0x%4x\n", priv->eeprom_did); 359 RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n", 360 priv->eeprom_CustomerID); 361 362 if (!priv->AutoloadFailFlag) { 363 u8 addr[ETH_ALEN]; 364 365 for (i = 0; i < 6; i += 2) { 366 usValue = rtl92e_eeprom_read(dev, 367 (EEPROM_NODE_ADDRESS_BYTE_0 + i) >> 1); 368 *(u16 *)(&addr[i]) = usValue; 369 } 370 eth_hw_addr_set(dev, addr); 371 } else { 372 eth_hw_addr_set(dev, bMac_Tmp_Addr); 373 } 374 375 RT_TRACE(COMP_INIT, "Permanent Address = %pM\n", 376 dev->dev_addr); 377 378 if (priv->card_8192_version > VERSION_8190_BD) 379 priv->bTXPowerDataReadFromEEPORM = true; 380 else 381 priv->bTXPowerDataReadFromEEPORM = false; 382 383 priv->rf_type = RTL819X_DEFAULT_RF_TYPE; 384 385 if (priv->card_8192_version > VERSION_8190_BD) { 386 if (!priv->AutoloadFailFlag) { 387 tempval = (rtl92e_eeprom_read(dev, 388 (EEPROM_RFInd_PowerDiff >> 1))) & 0xff; 389 priv->EEPROMLegacyHTTxPowerDiff = tempval & 0xf; 390 391 if (tempval&0x80) 392 priv->rf_type = RF_1T2R; 393 else 394 priv->rf_type = RF_2T4R; 395 } else { 396 priv->EEPROMLegacyHTTxPowerDiff = 0x04; 397 } 398 RT_TRACE(COMP_INIT, "EEPROMLegacyHTTxPowerDiff = %d\n", 399 priv->EEPROMLegacyHTTxPowerDiff); 400 401 if (!priv->AutoloadFailFlag) 402 priv->EEPROMThermalMeter = ((rtl92e_eeprom_read(dev, 403 (EEPROM_ThermalMeter>>1))) & 404 0xff00) >> 8; 405 else 406 priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter; 407 RT_TRACE(COMP_INIT, "ThermalMeter = %d\n", 408 priv->EEPROMThermalMeter); 409 priv->TSSI_13dBm = priv->EEPROMThermalMeter * 100; 410 411 if (priv->epromtype == EEPROM_93C46) { 412 if (!priv->AutoloadFailFlag) { 413 usValue = rtl92e_eeprom_read(dev, 414 EEPROM_TxPwDiff_CrystalCap >> 1); 415 priv->EEPROMAntPwDiff = usValue & 0x0fff; 416 priv->EEPROMCrystalCap = (usValue & 0xf000) 417 >> 12; 418 } else { 419 priv->EEPROMAntPwDiff = 420 EEPROM_Default_AntTxPowerDiff; 421 priv->EEPROMCrystalCap = 422 EEPROM_Default_TxPwDiff_CrystalCap; 423 } 424 RT_TRACE(COMP_INIT, "EEPROMAntPwDiff = %d\n", 425 priv->EEPROMAntPwDiff); 426 RT_TRACE(COMP_INIT, "EEPROMCrystalCap = %d\n", 427 priv->EEPROMCrystalCap); 428 429 for (i = 0; i < 14; i += 2) { 430 if (!priv->AutoloadFailFlag) 431 usValue = rtl92e_eeprom_read(dev, 432 (EEPROM_TxPwIndex_CCK + i) >> 1); 433 else 434 usValue = EEPROM_Default_TxPower; 435 *((u16 *)(&priv->EEPROMTxPowerLevelCCK[i])) = 436 usValue; 437 RT_TRACE(COMP_INIT, 438 "CCK Tx Power Level, Index %d = 0x%02x\n", 439 i, priv->EEPROMTxPowerLevelCCK[i]); 440 RT_TRACE(COMP_INIT, 441 "CCK Tx Power Level, Index %d = 0x%02x\n", 442 i+1, priv->EEPROMTxPowerLevelCCK[i+1]); 443 } 444 for (i = 0; i < 14; i += 2) { 445 if (!priv->AutoloadFailFlag) 446 usValue = rtl92e_eeprom_read(dev, 447 (EEPROM_TxPwIndex_OFDM_24G + i) >> 1); 448 else 449 usValue = EEPROM_Default_TxPower; 450 *((u16 *)(&priv->EEPROMTxPowerLevelOFDM24G[i])) 451 = usValue; 452 RT_TRACE(COMP_INIT, 453 "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n", 454 i, priv->EEPROMTxPowerLevelOFDM24G[i]); 455 RT_TRACE(COMP_INIT, 456 "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n", 457 i + 1, 458 priv->EEPROMTxPowerLevelOFDM24G[i+1]); 459 } 460 } 461 if (priv->epromtype == EEPROM_93C46) { 462 for (i = 0; i < 14; i++) { 463 priv->TxPowerLevelCCK[i] = 464 priv->EEPROMTxPowerLevelCCK[i]; 465 priv->TxPowerLevelOFDM24G[i] = 466 priv->EEPROMTxPowerLevelOFDM24G[i]; 467 } 468 priv->LegacyHTTxPowerDiff = 469 priv->EEPROMLegacyHTTxPowerDiff; 470 priv->AntennaTxPwDiff[0] = priv->EEPROMAntPwDiff & 0xf; 471 priv->AntennaTxPwDiff[1] = (priv->EEPROMAntPwDiff & 472 0xf0) >> 4; 473 priv->AntennaTxPwDiff[2] = (priv->EEPROMAntPwDiff & 474 0xf00) >> 8; 475 priv->CrystalCap = priv->EEPROMCrystalCap; 476 priv->ThermalMeter[0] = priv->EEPROMThermalMeter & 0xf; 477 priv->ThermalMeter[1] = (priv->EEPROMThermalMeter & 478 0xf0) >> 4; 479 } else if (priv->epromtype == EEPROM_93C56) { 480 481 for (i = 0; i < 3; i++) { 482 priv->TxPowerLevelCCK_A[i] = 483 priv->EEPROMRfACCKChnl1TxPwLevel[0]; 484 priv->TxPowerLevelOFDM24G_A[i] = 485 priv->EEPROMRfAOfdmChnlTxPwLevel[0]; 486 priv->TxPowerLevelCCK_C[i] = 487 priv->EEPROMRfCCCKChnl1TxPwLevel[0]; 488 priv->TxPowerLevelOFDM24G_C[i] = 489 priv->EEPROMRfCOfdmChnlTxPwLevel[0]; 490 } 491 for (i = 3; i < 9; i++) { 492 priv->TxPowerLevelCCK_A[i] = 493 priv->EEPROMRfACCKChnl1TxPwLevel[1]; 494 priv->TxPowerLevelOFDM24G_A[i] = 495 priv->EEPROMRfAOfdmChnlTxPwLevel[1]; 496 priv->TxPowerLevelCCK_C[i] = 497 priv->EEPROMRfCCCKChnl1TxPwLevel[1]; 498 priv->TxPowerLevelOFDM24G_C[i] = 499 priv->EEPROMRfCOfdmChnlTxPwLevel[1]; 500 } 501 for (i = 9; i < 14; i++) { 502 priv->TxPowerLevelCCK_A[i] = 503 priv->EEPROMRfACCKChnl1TxPwLevel[2]; 504 priv->TxPowerLevelOFDM24G_A[i] = 505 priv->EEPROMRfAOfdmChnlTxPwLevel[2]; 506 priv->TxPowerLevelCCK_C[i] = 507 priv->EEPROMRfCCCKChnl1TxPwLevel[2]; 508 priv->TxPowerLevelOFDM24G_C[i] = 509 priv->EEPROMRfCOfdmChnlTxPwLevel[2]; 510 } 511 for (i = 0; i < 14; i++) 512 RT_TRACE(COMP_INIT, 513 "priv->TxPowerLevelCCK_A[%d] = 0x%x\n", 514 i, priv->TxPowerLevelCCK_A[i]); 515 for (i = 0; i < 14; i++) 516 RT_TRACE(COMP_INIT, 517 "priv->TxPowerLevelOFDM24G_A[%d] = 0x%x\n", 518 i, priv->TxPowerLevelOFDM24G_A[i]); 519 for (i = 0; i < 14; i++) 520 RT_TRACE(COMP_INIT, 521 "priv->TxPowerLevelCCK_C[%d] = 0x%x\n", 522 i, priv->TxPowerLevelCCK_C[i]); 523 for (i = 0; i < 14; i++) 524 RT_TRACE(COMP_INIT, 525 "priv->TxPowerLevelOFDM24G_C[%d] = 0x%x\n", 526 i, priv->TxPowerLevelOFDM24G_C[i]); 527 priv->LegacyHTTxPowerDiff = 528 priv->EEPROMLegacyHTTxPowerDiff; 529 priv->AntennaTxPwDiff[0] = 0; 530 priv->AntennaTxPwDiff[1] = 0; 531 priv->AntennaTxPwDiff[2] = 0; 532 priv->CrystalCap = priv->EEPROMCrystalCap; 533 priv->ThermalMeter[0] = priv->EEPROMThermalMeter & 0xf; 534 priv->ThermalMeter[1] = (priv->EEPROMThermalMeter & 535 0xf0) >> 4; 536 } 537 } 538 539 if (priv->rf_type == RF_1T2R) { 540 /* no matter what checkpatch says, the braces are needed */ 541 RT_TRACE(COMP_INIT, "\n1T2R config\n"); 542 } else if (priv->rf_type == RF_2T4R) { 543 RT_TRACE(COMP_INIT, "\n2T4R config\n"); 544 } 545 546 rtl92e_init_adaptive_rate(dev); 547 548 priv->rf_chip = RF_8256; 549 550 if (priv->RegChannelPlan == 0xf) 551 priv->ChannelPlan = priv->eeprom_ChannelPlan; 552 else 553 priv->ChannelPlan = priv->RegChannelPlan; 554 555 if (priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304) 556 priv->CustomerID = RT_CID_DLINK; 557 558 switch (priv->eeprom_CustomerID) { 559 case EEPROM_CID_DEFAULT: 560 priv->CustomerID = RT_CID_DEFAULT; 561 break; 562 case EEPROM_CID_CAMEO: 563 priv->CustomerID = RT_CID_819x_CAMEO; 564 break; 565 case EEPROM_CID_RUNTOP: 566 priv->CustomerID = RT_CID_819x_RUNTOP; 567 break; 568 case EEPROM_CID_NetCore: 569 priv->CustomerID = RT_CID_819x_Netcore; 570 break; 571 case EEPROM_CID_TOSHIBA: 572 priv->CustomerID = RT_CID_TOSHIBA; 573 if (priv->eeprom_ChannelPlan&0x80) 574 priv->ChannelPlan = priv->eeprom_ChannelPlan&0x7f; 575 else 576 priv->ChannelPlan = 0x0; 577 RT_TRACE(COMP_INIT, "Toshiba ChannelPlan = 0x%x\n", 578 priv->ChannelPlan); 579 break; 580 case EEPROM_CID_Nettronix: 581 priv->ScanDelay = 100; 582 priv->CustomerID = RT_CID_Nettronix; 583 break; 584 case EEPROM_CID_Pronet: 585 priv->CustomerID = RT_CID_PRONET; 586 break; 587 case EEPROM_CID_DLINK: 588 priv->CustomerID = RT_CID_DLINK; 589 break; 590 591 case EEPROM_CID_WHQL: 592 break; 593 default: 594 break; 595 } 596 597 if (priv->ChannelPlan > CHANNEL_PLAN_LEN - 1) 598 priv->ChannelPlan = 0; 599 priv->ChannelPlan = COUNTRY_CODE_WORLD_WIDE_13; 600 601 if (priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304) 602 priv->rtllib->bSupportRemoteWakeUp = true; 603 else 604 priv->rtllib->bSupportRemoteWakeUp = false; 605 606 RT_TRACE(COMP_INIT, "RegChannelPlan(%d)\n", priv->RegChannelPlan); 607 RT_TRACE(COMP_INIT, "ChannelPlan = %d\n", priv->ChannelPlan); 608 RT_TRACE(COMP_TRACE, "<==== ReadAdapterInfo\n"); 609 } 610 611 void rtl92e_get_eeprom_size(struct net_device *dev) 612 { 613 u16 curCR; 614 struct r8192_priv *priv = rtllib_priv(dev); 615 616 RT_TRACE(COMP_INIT, "===========>%s()\n", __func__); 617 curCR = rtl92e_readw(dev, EPROM_CMD); 618 RT_TRACE(COMP_INIT, "read from Reg Cmd9346CR(%x):%x\n", EPROM_CMD, 619 curCR); 620 priv->epromtype = (curCR & EPROM_CMD_9356SEL) ? EEPROM_93C56 : 621 EEPROM_93C46; 622 RT_TRACE(COMP_INIT, "<===========%s(), epromtype:%d\n", __func__, 623 priv->epromtype); 624 _rtl92e_read_eeprom_info(dev); 625 } 626 627 static void _rtl92e_hwconfig(struct net_device *dev) 628 { 629 u32 regRATR = 0, regRRSR = 0; 630 u8 regBwOpMode = 0, regTmp = 0; 631 struct r8192_priv *priv = rtllib_priv(dev); 632 633 switch (priv->rtllib->mode) { 634 case WIRELESS_MODE_B: 635 regBwOpMode = BW_OPMODE_20MHZ; 636 regRATR = RATE_ALL_CCK; 637 regRRSR = RATE_ALL_CCK; 638 break; 639 case WIRELESS_MODE_A: 640 regBwOpMode = BW_OPMODE_5G | BW_OPMODE_20MHZ; 641 regRATR = RATE_ALL_OFDM_AG; 642 regRRSR = RATE_ALL_OFDM_AG; 643 break; 644 case WIRELESS_MODE_G: 645 regBwOpMode = BW_OPMODE_20MHZ; 646 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 647 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 648 break; 649 case WIRELESS_MODE_AUTO: 650 case WIRELESS_MODE_N_24G: 651 regBwOpMode = BW_OPMODE_20MHZ; 652 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | 653 RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS; 654 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 655 break; 656 case WIRELESS_MODE_N_5G: 657 regBwOpMode = BW_OPMODE_5G; 658 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | 659 RATE_ALL_OFDM_2SS; 660 regRRSR = RATE_ALL_OFDM_AG; 661 break; 662 default: 663 regBwOpMode = BW_OPMODE_20MHZ; 664 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 665 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 666 break; 667 } 668 669 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode); 670 { 671 u32 ratr_value; 672 673 ratr_value = regRATR; 674 if (priv->rf_type == RF_1T2R) 675 ratr_value &= ~(RATE_ALL_OFDM_2SS); 676 rtl92e_writel(dev, RATR0, ratr_value); 677 rtl92e_writeb(dev, UFWP, 1); 678 } 679 regTmp = rtl92e_readb(dev, 0x313); 680 regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff); 681 rtl92e_writel(dev, RRSR, regRRSR); 682 683 rtl92e_writew(dev, RETRY_LIMIT, 684 priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT | 685 priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT); 686 } 687 688 bool rtl92e_start_adapter(struct net_device *dev) 689 { 690 struct r8192_priv *priv = rtllib_priv(dev); 691 u32 ulRegRead; 692 bool rtStatus = true; 693 u8 tmpvalue; 694 u8 ICVersion, SwitchingRegulatorOutput; 695 bool bfirmwareok = true; 696 u32 tmpRegA, TempCCk; 697 int i = 0; 698 u32 retry_times = 0; 699 700 RT_TRACE(COMP_INIT, "====>%s()\n", __func__); 701 priv->being_init_adapter = true; 702 703 start: 704 rtl92e_reset_desc_ring(dev); 705 priv->Rf_Mode = RF_OP_By_SW_3wire; 706 if (priv->ResetProgress == RESET_TYPE_NORESET) { 707 rtl92e_writeb(dev, ANAPAR, 0x37); 708 mdelay(500); 709 } 710 priv->pFirmware->status = FW_STATUS_0_INIT; 711 712 if (priv->RegRfOff) 713 priv->rtllib->eRFPowerState = eRfOff; 714 715 ulRegRead = rtl92e_readl(dev, CPU_GEN); 716 if (priv->pFirmware->status == FW_STATUS_0_INIT) 717 ulRegRead |= CPU_GEN_SYSTEM_RESET; 718 else if (priv->pFirmware->status == FW_STATUS_5_READY) 719 ulRegRead |= CPU_GEN_FIRMWARE_RESET; 720 else 721 netdev_err(dev, "%s(): undefined firmware state: %d.\n", 722 __func__, priv->pFirmware->status); 723 724 rtl92e_writel(dev, CPU_GEN, ulRegRead); 725 726 ICVersion = rtl92e_readb(dev, IC_VERRSION); 727 if (ICVersion >= 0x4) { 728 SwitchingRegulatorOutput = rtl92e_readb(dev, SWREGULATOR); 729 if (SwitchingRegulatorOutput != 0xb8) { 730 rtl92e_writeb(dev, SWREGULATOR, 0xa8); 731 mdelay(1); 732 rtl92e_writeb(dev, SWREGULATOR, 0xb8); 733 } 734 } 735 RT_TRACE(COMP_INIT, "BB Config Start!\n"); 736 rtStatus = rtl92e_config_bb(dev); 737 if (!rtStatus) { 738 netdev_warn(dev, "%s(): Failed to configure BB\n", __func__); 739 return rtStatus; 740 } 741 RT_TRACE(COMP_INIT, "BB Config Finished!\n"); 742 743 priv->LoopbackMode = RTL819X_NO_LOOPBACK; 744 if (priv->ResetProgress == RESET_TYPE_NORESET) { 745 ulRegRead = rtl92e_readl(dev, CPU_GEN); 746 if (priv->LoopbackMode == RTL819X_NO_LOOPBACK) 747 ulRegRead = (ulRegRead & CPU_GEN_NO_LOOPBACK_MSK) | 748 CPU_GEN_NO_LOOPBACK_SET; 749 else if (priv->LoopbackMode == RTL819X_MAC_LOOPBACK) 750 ulRegRead |= CPU_CCK_LOOPBACK; 751 else 752 netdev_err(dev, "%s: Invalid loopback mode setting.\n", 753 __func__); 754 755 rtl92e_writel(dev, CPU_GEN, ulRegRead); 756 757 udelay(500); 758 } 759 _rtl92e_hwconfig(dev); 760 rtl92e_writeb(dev, CMDR, CR_RE | CR_TE); 761 762 rtl92e_writeb(dev, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) | 763 (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT))); 764 rtl92e_writel(dev, MAC0, ((u32 *)dev->dev_addr)[0]); 765 rtl92e_writew(dev, MAC4, ((u16 *)(dev->dev_addr + 4))[0]); 766 rtl92e_writel(dev, RCR, priv->ReceiveConfig); 767 768 rtl92e_writel(dev, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK << 769 RSVD_FW_QUEUE_PAGE_BK_SHIFT | 770 NUM_OF_PAGE_IN_FW_QUEUE_BE << 771 RSVD_FW_QUEUE_PAGE_BE_SHIFT | 772 NUM_OF_PAGE_IN_FW_QUEUE_VI << 773 RSVD_FW_QUEUE_PAGE_VI_SHIFT | 774 NUM_OF_PAGE_IN_FW_QUEUE_VO << 775 RSVD_FW_QUEUE_PAGE_VO_SHIFT); 776 rtl92e_writel(dev, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT << 777 RSVD_FW_QUEUE_PAGE_MGNT_SHIFT); 778 rtl92e_writel(dev, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW | 779 NUM_OF_PAGE_IN_FW_QUEUE_BCN << 780 RSVD_FW_QUEUE_PAGE_BCN_SHIFT| 781 NUM_OF_PAGE_IN_FW_QUEUE_PUB << 782 RSVD_FW_QUEUE_PAGE_PUB_SHIFT); 783 784 rtl92e_tx_enable(dev); 785 rtl92e_rx_enable(dev); 786 ulRegRead = (0xFFF00000 & rtl92e_readl(dev, RRSR)) | 787 RATE_ALL_OFDM_AG | RATE_ALL_CCK; 788 rtl92e_writel(dev, RRSR, ulRegRead); 789 rtl92e_writel(dev, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK)); 790 791 rtl92e_writeb(dev, ACK_TIMEOUT, 0x30); 792 793 if (priv->ResetProgress == RESET_TYPE_NORESET) 794 rtl92e_set_wireless_mode(dev, priv->rtllib->mode); 795 rtl92e_cam_reset(dev); 796 { 797 u8 SECR_value = 0x0; 798 799 SECR_value |= SCR_TxEncEnable; 800 SECR_value |= SCR_RxDecEnable; 801 SECR_value |= SCR_NoSKMC; 802 rtl92e_writeb(dev, SECR, SECR_value); 803 } 804 rtl92e_writew(dev, ATIMWND, 2); 805 rtl92e_writew(dev, BCN_INTERVAL, 100); 806 807 for (i = 0; i < QOS_QUEUE_NUM; i++) 808 rtl92e_writel(dev, WDCAPARA_ADD[i], 0x005e4332); 809 810 rtl92e_writeb(dev, 0xbe, 0xc0); 811 812 rtl92e_config_mac(dev); 813 814 if (priv->card_8192_version > VERSION_8190_BD) { 815 rtl92e_get_tx_power(dev); 816 rtl92e_set_tx_power(dev, priv->chan); 817 } 818 819 tmpvalue = rtl92e_readb(dev, IC_VERRSION); 820 priv->IC_Cut = tmpvalue; 821 RT_TRACE(COMP_INIT, "priv->IC_Cut= 0x%x\n", priv->IC_Cut); 822 if (priv->IC_Cut >= IC_VersionCut_D) { 823 if (priv->IC_Cut == IC_VersionCut_D) { 824 /* no matter what checkpatch says, braces are needed */ 825 RT_TRACE(COMP_INIT, "D-cut\n"); 826 } else if (priv->IC_Cut == IC_VersionCut_E) { 827 RT_TRACE(COMP_INIT, "E-cut\n"); 828 } 829 } else { 830 RT_TRACE(COMP_INIT, "Before C-cut\n"); 831 } 832 833 RT_TRACE(COMP_INIT, "Load Firmware!\n"); 834 bfirmwareok = rtl92e_init_fw(dev); 835 if (!bfirmwareok) { 836 if (retry_times < 10) { 837 retry_times++; 838 goto start; 839 } else { 840 rtStatus = false; 841 goto end; 842 } 843 } 844 RT_TRACE(COMP_INIT, "Load Firmware finished!\n"); 845 if (priv->ResetProgress == RESET_TYPE_NORESET) { 846 RT_TRACE(COMP_INIT, "RF Config Started!\n"); 847 rtStatus = rtl92e_config_phy(dev); 848 if (!rtStatus) { 849 netdev_info(dev, "RF Config failed\n"); 850 return rtStatus; 851 } 852 RT_TRACE(COMP_INIT, "RF Config Finished!\n"); 853 } 854 855 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn, 0x1); 856 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1); 857 858 rtl92e_writeb(dev, 0x87, 0x0); 859 860 if (priv->RegRfOff) { 861 RT_TRACE((COMP_INIT | COMP_RF | COMP_POWER), 862 "%s(): Turn off RF for RegRfOff ----------\n", 863 __func__); 864 rtl92e_set_rf_state(dev, eRfOff, RF_CHANGE_BY_SW); 865 } else if (priv->rtllib->RfOffReason > RF_CHANGE_BY_PS) { 866 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), 867 "%s(): Turn off RF for RfOffReason(%d) ----------\n", 868 __func__, priv->rtllib->RfOffReason); 869 rtl92e_set_rf_state(dev, eRfOff, priv->rtllib->RfOffReason); 870 } else if (priv->rtllib->RfOffReason >= RF_CHANGE_BY_IPS) { 871 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), 872 "%s(): Turn off RF for RfOffReason(%d) ----------\n", 873 __func__, priv->rtllib->RfOffReason); 874 rtl92e_set_rf_state(dev, eRfOff, priv->rtllib->RfOffReason); 875 } else { 876 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): RF-ON\n", 877 __func__); 878 priv->rtllib->eRFPowerState = eRfOn; 879 priv->rtllib->RfOffReason = 0; 880 } 881 882 if (priv->rtllib->FwRWRF) 883 priv->Rf_Mode = RF_OP_By_FW; 884 else 885 priv->Rf_Mode = RF_OP_By_SW_3wire; 886 887 if (priv->ResetProgress == RESET_TYPE_NORESET) { 888 rtl92e_dm_init_txpower_tracking(dev); 889 890 if (priv->IC_Cut >= IC_VersionCut_D) { 891 tmpRegA = rtl92e_get_bb_reg(dev, rOFDM0_XATxIQImbalance, 892 bMaskDWord); 893 rtl92e_get_bb_reg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord); 894 895 for (i = 0; i < TxBBGainTableLength; i++) { 896 if (tmpRegA == dm_tx_bb_gain[i]) { 897 priv->rfa_txpowertrackingindex = i; 898 priv->rfa_txpowertrackingindex_real = i; 899 priv->rfa_txpowertracking_default = 900 priv->rfa_txpowertrackingindex; 901 break; 902 } 903 } 904 905 TempCCk = rtl92e_get_bb_reg(dev, rCCK0_TxFilter1, 906 bMaskByte2); 907 908 for (i = 0; i < CCKTxBBGainTableLength; i++) { 909 if (TempCCk == dm_cck_tx_bb_gain[i][0]) { 910 priv->CCKPresentAttentuation_20Mdefault = i; 911 break; 912 } 913 } 914 priv->CCKPresentAttentuation_40Mdefault = 0; 915 priv->CCKPresentAttentuation_difference = 0; 916 priv->CCKPresentAttentuation = 917 priv->CCKPresentAttentuation_20Mdefault; 918 RT_TRACE(COMP_POWER_TRACKING, 919 "priv->rfa_txpowertrackingindex_initial = %d\n", 920 priv->rfa_txpowertrackingindex); 921 RT_TRACE(COMP_POWER_TRACKING, 922 "priv->rfa_txpowertrackingindex_real__initial = %d\n", 923 priv->rfa_txpowertrackingindex_real); 924 RT_TRACE(COMP_POWER_TRACKING, 925 "priv->CCKPresentAttentuation_difference_initial = %d\n", 926 priv->CCKPresentAttentuation_difference); 927 RT_TRACE(COMP_POWER_TRACKING, 928 "priv->CCKPresentAttentuation_initial = %d\n", 929 priv->CCKPresentAttentuation); 930 priv->btxpower_tracking = false; 931 } 932 } 933 rtl92e_irq_enable(dev); 934 end: 935 priv->being_init_adapter = false; 936 return rtStatus; 937 } 938 939 static void _rtl92e_net_update(struct net_device *dev) 940 { 941 942 struct r8192_priv *priv = rtllib_priv(dev); 943 struct rtllib_network *net; 944 u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf; 945 u16 rate_config = 0; 946 947 net = &priv->rtllib->current_network; 948 rtl92e_config_rate(dev, &rate_config); 949 priv->dot11CurrentPreambleMode = PREAMBLE_AUTO; 950 priv->basic_rate = rate_config &= 0x15f; 951 rtl92e_writew(dev, BSSIDR, *(u16 *)net->bssid); 952 rtl92e_writel(dev, BSSIDR + 2, *(u32 *)(net->bssid + 2)); 953 954 if (priv->rtllib->iw_mode == IW_MODE_ADHOC) { 955 rtl92e_writew(dev, ATIMWND, 2); 956 rtl92e_writew(dev, BCN_DMATIME, 256); 957 rtl92e_writew(dev, BCN_INTERVAL, net->beacon_interval); 958 rtl92e_writew(dev, BCN_DRV_EARLY_INT, 10); 959 rtl92e_writeb(dev, BCN_ERR_THRESH, 100); 960 961 BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT); 962 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS; 963 964 rtl92e_writew(dev, BCN_TCFG, BcnTimeCfg); 965 } 966 } 967 968 void rtl92e_link_change(struct net_device *dev) 969 { 970 struct r8192_priv *priv = rtllib_priv(dev); 971 struct rtllib_device *ieee = priv->rtllib; 972 973 if (!priv->up) 974 return; 975 976 if (ieee->state == RTLLIB_LINKED) { 977 _rtl92e_net_update(dev); 978 priv->ops->update_ratr_table(dev); 979 if ((ieee->pairwise_key_type == KEY_TYPE_WEP40) || 980 (ieee->pairwise_key_type == KEY_TYPE_WEP104)) 981 rtl92e_enable_hw_security_config(dev); 982 } else { 983 rtl92e_writeb(dev, 0x173, 0); 984 } 985 _rtl92e_update_msr(dev); 986 987 if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC) { 988 u32 reg; 989 990 reg = rtl92e_readl(dev, RCR); 991 if (priv->rtllib->state == RTLLIB_LINKED) { 992 if (ieee->IntelPromiscuousModeInfo.bPromiscuousOn) 993 ; 994 else 995 priv->ReceiveConfig = reg |= RCR_CBSSID; 996 } else 997 priv->ReceiveConfig = reg &= ~RCR_CBSSID; 998 999 rtl92e_writel(dev, RCR, reg); 1000 } 1001 } 1002 1003 void rtl92e_set_monitor_mode(struct net_device *dev, bool bAllowAllDA, 1004 bool WriteIntoReg) 1005 { 1006 struct r8192_priv *priv = rtllib_priv(dev); 1007 1008 if (bAllowAllDA) 1009 priv->ReceiveConfig |= RCR_AAP; 1010 else 1011 priv->ReceiveConfig &= ~RCR_AAP; 1012 1013 if (WriteIntoReg) 1014 rtl92e_writel(dev, RCR, priv->ReceiveConfig); 1015 } 1016 1017 static u8 _rtl92e_rate_mgn_to_hw(u8 rate) 1018 { 1019 u8 ret = DESC90_RATE1M; 1020 1021 switch (rate) { 1022 case MGN_1M: 1023 ret = DESC90_RATE1M; 1024 break; 1025 case MGN_2M: 1026 ret = DESC90_RATE2M; 1027 break; 1028 case MGN_5_5M: 1029 ret = DESC90_RATE5_5M; 1030 break; 1031 case MGN_11M: 1032 ret = DESC90_RATE11M; 1033 break; 1034 case MGN_6M: 1035 ret = DESC90_RATE6M; 1036 break; 1037 case MGN_9M: 1038 ret = DESC90_RATE9M; 1039 break; 1040 case MGN_12M: 1041 ret = DESC90_RATE12M; 1042 break; 1043 case MGN_18M: 1044 ret = DESC90_RATE18M; 1045 break; 1046 case MGN_24M: 1047 ret = DESC90_RATE24M; 1048 break; 1049 case MGN_36M: 1050 ret = DESC90_RATE36M; 1051 break; 1052 case MGN_48M: 1053 ret = DESC90_RATE48M; 1054 break; 1055 case MGN_54M: 1056 ret = DESC90_RATE54M; 1057 break; 1058 case MGN_MCS0: 1059 ret = DESC90_RATEMCS0; 1060 break; 1061 case MGN_MCS1: 1062 ret = DESC90_RATEMCS1; 1063 break; 1064 case MGN_MCS2: 1065 ret = DESC90_RATEMCS2; 1066 break; 1067 case MGN_MCS3: 1068 ret = DESC90_RATEMCS3; 1069 break; 1070 case MGN_MCS4: 1071 ret = DESC90_RATEMCS4; 1072 break; 1073 case MGN_MCS5: 1074 ret = DESC90_RATEMCS5; 1075 break; 1076 case MGN_MCS6: 1077 ret = DESC90_RATEMCS6; 1078 break; 1079 case MGN_MCS7: 1080 ret = DESC90_RATEMCS7; 1081 break; 1082 case MGN_MCS8: 1083 ret = DESC90_RATEMCS8; 1084 break; 1085 case MGN_MCS9: 1086 ret = DESC90_RATEMCS9; 1087 break; 1088 case MGN_MCS10: 1089 ret = DESC90_RATEMCS10; 1090 break; 1091 case MGN_MCS11: 1092 ret = DESC90_RATEMCS11; 1093 break; 1094 case MGN_MCS12: 1095 ret = DESC90_RATEMCS12; 1096 break; 1097 case MGN_MCS13: 1098 ret = DESC90_RATEMCS13; 1099 break; 1100 case MGN_MCS14: 1101 ret = DESC90_RATEMCS14; 1102 break; 1103 case MGN_MCS15: 1104 ret = DESC90_RATEMCS15; 1105 break; 1106 case (0x80|0x20): 1107 ret = DESC90_RATEMCS32; 1108 break; 1109 default: 1110 break; 1111 } 1112 return ret; 1113 } 1114 1115 static u8 _rtl92e_hw_queue_to_fw_queue(struct net_device *dev, u8 QueueID, 1116 u8 priority) 1117 { 1118 u8 QueueSelect = 0x0; 1119 1120 switch (QueueID) { 1121 case BE_QUEUE: 1122 QueueSelect = QSLT_BE; 1123 break; 1124 1125 case BK_QUEUE: 1126 QueueSelect = QSLT_BK; 1127 break; 1128 1129 case VO_QUEUE: 1130 QueueSelect = QSLT_VO; 1131 break; 1132 1133 case VI_QUEUE: 1134 QueueSelect = QSLT_VI; 1135 break; 1136 case MGNT_QUEUE: 1137 QueueSelect = QSLT_MGNT; 1138 break; 1139 case BEACON_QUEUE: 1140 QueueSelect = QSLT_BEACON; 1141 break; 1142 case TXCMD_QUEUE: 1143 QueueSelect = QSLT_CMD; 1144 break; 1145 case HIGH_QUEUE: 1146 QueueSelect = QSLT_HIGH; 1147 break; 1148 default: 1149 netdev_warn(dev, "%s(): Impossible Queue Selection: %d\n", 1150 __func__, QueueID); 1151 break; 1152 } 1153 return QueueSelect; 1154 } 1155 1156 static u8 _rtl92e_query_is_short(u8 TxHT, u8 TxRate, struct cb_desc *tcb_desc) 1157 { 1158 u8 tmp_Short; 1159 1160 tmp_Short = (TxHT == 1) ? ((tcb_desc->bUseShortGI) ? 1 : 0) : 1161 ((tcb_desc->bUseShortPreamble) ? 1 : 0); 1162 if (TxHT == 1 && TxRate != DESC90_RATEMCS15) 1163 tmp_Short = 0; 1164 1165 return tmp_Short; 1166 } 1167 1168 void rtl92e_fill_tx_desc(struct net_device *dev, struct tx_desc *pdesc, 1169 struct cb_desc *cb_desc, struct sk_buff *skb) 1170 { 1171 struct r8192_priv *priv = rtllib_priv(dev); 1172 dma_addr_t mapping; 1173 struct tx_fwinfo_8190pci *pTxFwInfo; 1174 1175 pTxFwInfo = (struct tx_fwinfo_8190pci *)skb->data; 1176 memset(pTxFwInfo, 0, sizeof(struct tx_fwinfo_8190pci)); 1177 pTxFwInfo->TxHT = (cb_desc->data_rate & 0x80) ? 1 : 0; 1178 pTxFwInfo->TxRate = _rtl92e_rate_mgn_to_hw(cb_desc->data_rate); 1179 pTxFwInfo->EnableCPUDur = cb_desc->bTxEnableFwCalcDur; 1180 pTxFwInfo->Short = _rtl92e_query_is_short(pTxFwInfo->TxHT, 1181 pTxFwInfo->TxRate, cb_desc); 1182 1183 if (cb_desc->bAMPDUEnable) { 1184 pTxFwInfo->AllowAggregation = 1; 1185 pTxFwInfo->RxMF = cb_desc->ampdu_factor; 1186 pTxFwInfo->RxAMD = cb_desc->ampdu_density; 1187 } else { 1188 pTxFwInfo->AllowAggregation = 0; 1189 pTxFwInfo->RxMF = 0; 1190 pTxFwInfo->RxAMD = 0; 1191 } 1192 1193 pTxFwInfo->RtsEnable = (cb_desc->bRTSEnable) ? 1 : 0; 1194 pTxFwInfo->CtsEnable = (cb_desc->bCTSEnable) ? 1 : 0; 1195 pTxFwInfo->RtsSTBC = (cb_desc->bRTSSTBC) ? 1 : 0; 1196 pTxFwInfo->RtsHT = (cb_desc->rts_rate&0x80) ? 1 : 0; 1197 pTxFwInfo->RtsRate = _rtl92e_rate_mgn_to_hw(cb_desc->rts_rate); 1198 pTxFwInfo->RtsBandwidth = 0; 1199 pTxFwInfo->RtsSubcarrier = cb_desc->RTSSC; 1200 pTxFwInfo->RtsShort = (pTxFwInfo->RtsHT == 0) ? 1201 (cb_desc->bRTSUseShortPreamble ? 1 : 0) : 1202 (cb_desc->bRTSUseShortGI ? 1 : 0); 1203 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) { 1204 if (cb_desc->bPacketBW) { 1205 pTxFwInfo->TxBandwidth = 1; 1206 pTxFwInfo->TxSubCarrier = 0; 1207 } else { 1208 pTxFwInfo->TxBandwidth = 0; 1209 pTxFwInfo->TxSubCarrier = priv->nCur40MhzPrimeSC; 1210 } 1211 } else { 1212 pTxFwInfo->TxBandwidth = 0; 1213 pTxFwInfo->TxSubCarrier = 0; 1214 } 1215 1216 memset((u8 *)pdesc, 0, 12); 1217 1218 mapping = dma_map_single(&priv->pdev->dev, skb->data, skb->len, 1219 DMA_TO_DEVICE); 1220 if (dma_mapping_error(&priv->pdev->dev, mapping)) { 1221 netdev_err(dev, "%s(): DMA Mapping error\n", __func__); 1222 return; 1223 } 1224 1225 pdesc->LINIP = 0; 1226 pdesc->CmdInit = 1; 1227 pdesc->Offset = sizeof(struct tx_fwinfo_8190pci) + 8; 1228 pdesc->PktSize = skb->len - sizeof(struct tx_fwinfo_8190pci); 1229 1230 pdesc->SecCAMID = 0; 1231 pdesc->RATid = cb_desc->RATRIndex; 1232 1233 1234 pdesc->NoEnc = 1; 1235 pdesc->SecType = 0x0; 1236 if (cb_desc->bHwSec) { 1237 static u8 tmp; 1238 1239 if (!tmp) { 1240 RT_TRACE(COMP_DBG, "==>================hw sec\n"); 1241 tmp = 1; 1242 } 1243 switch (priv->rtllib->pairwise_key_type) { 1244 case KEY_TYPE_WEP40: 1245 case KEY_TYPE_WEP104: 1246 pdesc->SecType = 0x1; 1247 pdesc->NoEnc = 0; 1248 break; 1249 case KEY_TYPE_TKIP: 1250 pdesc->SecType = 0x2; 1251 pdesc->NoEnc = 0; 1252 break; 1253 case KEY_TYPE_CCMP: 1254 pdesc->SecType = 0x3; 1255 pdesc->NoEnc = 0; 1256 break; 1257 case KEY_TYPE_NA: 1258 pdesc->SecType = 0x0; 1259 pdesc->NoEnc = 1; 1260 break; 1261 } 1262 } 1263 1264 pdesc->PktId = 0x0; 1265 1266 pdesc->QueueSelect = _rtl92e_hw_queue_to_fw_queue(dev, 1267 cb_desc->queue_index, 1268 cb_desc->priority); 1269 pdesc->TxFWInfoSize = sizeof(struct tx_fwinfo_8190pci); 1270 1271 pdesc->DISFB = cb_desc->bTxDisableRateFallBack; 1272 pdesc->USERATE = cb_desc->bTxUseDriverAssingedRate; 1273 1274 pdesc->FirstSeg = 1; 1275 pdesc->LastSeg = 1; 1276 pdesc->TxBufferSize = skb->len; 1277 1278 pdesc->TxBuffAddr = mapping; 1279 } 1280 1281 void rtl92e_fill_tx_cmd_desc(struct net_device *dev, struct tx_desc_cmd *entry, 1282 struct cb_desc *cb_desc, struct sk_buff *skb) 1283 { 1284 struct r8192_priv *priv = rtllib_priv(dev); 1285 dma_addr_t mapping = dma_map_single(&priv->pdev->dev, skb->data, 1286 skb->len, DMA_TO_DEVICE); 1287 1288 if (dma_mapping_error(&priv->pdev->dev, mapping)) 1289 netdev_err(dev, "%s(): DMA Mapping error\n", __func__); 1290 memset(entry, 0, 12); 1291 entry->LINIP = cb_desc->bLastIniPkt; 1292 entry->FirstSeg = 1; 1293 entry->LastSeg = 1; 1294 if (cb_desc->bCmdOrInit == DESC_PACKET_TYPE_INIT) { 1295 entry->CmdInit = DESC_PACKET_TYPE_INIT; 1296 } else { 1297 struct tx_desc *entry_tmp = (struct tx_desc *)entry; 1298 1299 entry_tmp->CmdInit = DESC_PACKET_TYPE_NORMAL; 1300 entry_tmp->Offset = sizeof(struct tx_fwinfo_8190pci) + 8; 1301 entry_tmp->PktSize = cb_desc->pkt_size + entry_tmp->Offset; 1302 entry_tmp->QueueSelect = QSLT_CMD; 1303 entry_tmp->TxFWInfoSize = 0x08; 1304 entry_tmp->RATid = DESC_PACKET_TYPE_INIT; 1305 } 1306 entry->TxBufferSize = skb->len; 1307 entry->TxBuffAddr = mapping; 1308 entry->OWN = 1; 1309 } 1310 1311 static u8 _rtl92e_rate_hw_to_mgn(bool bIsHT, u8 rate) 1312 { 1313 u8 ret_rate = 0x02; 1314 1315 if (!bIsHT) { 1316 switch (rate) { 1317 case DESC90_RATE1M: 1318 ret_rate = MGN_1M; 1319 break; 1320 case DESC90_RATE2M: 1321 ret_rate = MGN_2M; 1322 break; 1323 case DESC90_RATE5_5M: 1324 ret_rate = MGN_5_5M; 1325 break; 1326 case DESC90_RATE11M: 1327 ret_rate = MGN_11M; 1328 break; 1329 case DESC90_RATE6M: 1330 ret_rate = MGN_6M; 1331 break; 1332 case DESC90_RATE9M: 1333 ret_rate = MGN_9M; 1334 break; 1335 case DESC90_RATE12M: 1336 ret_rate = MGN_12M; 1337 break; 1338 case DESC90_RATE18M: 1339 ret_rate = MGN_18M; 1340 break; 1341 case DESC90_RATE24M: 1342 ret_rate = MGN_24M; 1343 break; 1344 case DESC90_RATE36M: 1345 ret_rate = MGN_36M; 1346 break; 1347 case DESC90_RATE48M: 1348 ret_rate = MGN_48M; 1349 break; 1350 case DESC90_RATE54M: 1351 ret_rate = MGN_54M; 1352 break; 1353 1354 default: 1355 RT_TRACE(COMP_RECV, 1356 "%s: Non supportedRate [%x], bIsHT = %d!!!\n", 1357 __func__, rate, bIsHT); 1358 break; 1359 } 1360 1361 } else { 1362 switch (rate) { 1363 case DESC90_RATEMCS0: 1364 ret_rate = MGN_MCS0; 1365 break; 1366 case DESC90_RATEMCS1: 1367 ret_rate = MGN_MCS1; 1368 break; 1369 case DESC90_RATEMCS2: 1370 ret_rate = MGN_MCS2; 1371 break; 1372 case DESC90_RATEMCS3: 1373 ret_rate = MGN_MCS3; 1374 break; 1375 case DESC90_RATEMCS4: 1376 ret_rate = MGN_MCS4; 1377 break; 1378 case DESC90_RATEMCS5: 1379 ret_rate = MGN_MCS5; 1380 break; 1381 case DESC90_RATEMCS6: 1382 ret_rate = MGN_MCS6; 1383 break; 1384 case DESC90_RATEMCS7: 1385 ret_rate = MGN_MCS7; 1386 break; 1387 case DESC90_RATEMCS8: 1388 ret_rate = MGN_MCS8; 1389 break; 1390 case DESC90_RATEMCS9: 1391 ret_rate = MGN_MCS9; 1392 break; 1393 case DESC90_RATEMCS10: 1394 ret_rate = MGN_MCS10; 1395 break; 1396 case DESC90_RATEMCS11: 1397 ret_rate = MGN_MCS11; 1398 break; 1399 case DESC90_RATEMCS12: 1400 ret_rate = MGN_MCS12; 1401 break; 1402 case DESC90_RATEMCS13: 1403 ret_rate = MGN_MCS13; 1404 break; 1405 case DESC90_RATEMCS14: 1406 ret_rate = MGN_MCS14; 1407 break; 1408 case DESC90_RATEMCS15: 1409 ret_rate = MGN_MCS15; 1410 break; 1411 case DESC90_RATEMCS32: 1412 ret_rate = 0x80 | 0x20; 1413 break; 1414 1415 default: 1416 RT_TRACE(COMP_RECV, 1417 "%s: Non supported Rate [%x], bIsHT = %d!!!\n", 1418 __func__, rate, bIsHT); 1419 break; 1420 } 1421 } 1422 1423 return ret_rate; 1424 } 1425 1426 static long _rtl92e_signal_scale_mapping(struct r8192_priv *priv, long currsig) 1427 { 1428 long retsig; 1429 1430 if (currsig >= 61 && currsig <= 100) 1431 retsig = 90 + ((currsig - 60) / 4); 1432 else if (currsig >= 41 && currsig <= 60) 1433 retsig = 78 + ((currsig - 40) / 2); 1434 else if (currsig >= 31 && currsig <= 40) 1435 retsig = 66 + (currsig - 30); 1436 else if (currsig >= 21 && currsig <= 30) 1437 retsig = 54 + (currsig - 20); 1438 else if (currsig >= 5 && currsig <= 20) 1439 retsig = 42 + (((currsig - 5) * 2) / 3); 1440 else if (currsig == 4) 1441 retsig = 36; 1442 else if (currsig == 3) 1443 retsig = 27; 1444 else if (currsig == 2) 1445 retsig = 18; 1446 else if (currsig == 1) 1447 retsig = 9; 1448 else 1449 retsig = currsig; 1450 1451 return retsig; 1452 } 1453 1454 1455 #define rx_hal_is_cck_rate(_pdrvinfo)\ 1456 ((_pdrvinfo->RxRate == DESC90_RATE1M ||\ 1457 _pdrvinfo->RxRate == DESC90_RATE2M ||\ 1458 _pdrvinfo->RxRate == DESC90_RATE5_5M ||\ 1459 _pdrvinfo->RxRate == DESC90_RATE11M) &&\ 1460 !_pdrvinfo->RxHT) 1461 1462 static void _rtl92e_query_rxphystatus( 1463 struct r8192_priv *priv, 1464 struct rtllib_rx_stats *pstats, 1465 struct rx_desc *pdesc, 1466 struct rx_fwinfo *pdrvinfo, 1467 struct rtllib_rx_stats *precord_stats, 1468 bool bpacket_match_bssid, 1469 bool bpacket_toself, 1470 bool bPacketBeacon, 1471 bool bToSelfBA 1472 ) 1473 { 1474 struct phy_sts_ofdm_819xpci *pofdm_buf; 1475 struct phy_sts_cck_819xpci *pcck_buf; 1476 struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *prxsc; 1477 u8 *prxpkt; 1478 u8 i, max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg; 1479 s8 rx_pwr[4], rx_pwr_all = 0; 1480 s8 rx_snrX, rx_evmX; 1481 u8 evm, pwdb_all; 1482 u32 RSSI, total_rssi = 0; 1483 u8 is_cck_rate = 0; 1484 u8 rf_rx_num = 0; 1485 static u8 check_reg824; 1486 static u32 reg824_bit9; 1487 1488 priv->stats.numqry_phystatus++; 1489 1490 is_cck_rate = rx_hal_is_cck_rate(pdrvinfo); 1491 memset(precord_stats, 0, sizeof(struct rtllib_rx_stats)); 1492 pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID = 1493 bpacket_match_bssid; 1494 pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself; 1495 pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate; 1496 pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon; 1497 pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA; 1498 if (check_reg824 == 0) { 1499 reg824_bit9 = rtl92e_get_bb_reg(priv->rtllib->dev, 1500 rFPGA0_XA_HSSIParameter2, 1501 0x200); 1502 check_reg824 = 1; 1503 } 1504 1505 1506 prxpkt = (u8 *)pdrvinfo; 1507 1508 prxpkt += sizeof(struct rx_fwinfo); 1509 1510 pcck_buf = (struct phy_sts_cck_819xpci *)prxpkt; 1511 pofdm_buf = (struct phy_sts_ofdm_819xpci *)prxpkt; 1512 1513 pstats->RxMIMOSignalQuality[0] = -1; 1514 pstats->RxMIMOSignalQuality[1] = -1; 1515 precord_stats->RxMIMOSignalQuality[0] = -1; 1516 precord_stats->RxMIMOSignalQuality[1] = -1; 1517 1518 if (is_cck_rate) { 1519 u8 report; 1520 1521 priv->stats.numqry_phystatusCCK++; 1522 if (!reg824_bit9) { 1523 report = pcck_buf->cck_agc_rpt & 0xc0; 1524 report >>= 6; 1525 switch (report) { 1526 case 0x3: 1527 rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt & 1528 0x3e); 1529 break; 1530 case 0x2: 1531 rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt & 1532 0x3e); 1533 break; 1534 case 0x1: 1535 rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt & 1536 0x3e); 1537 break; 1538 case 0x0: 1539 rx_pwr_all = 8 - (pcck_buf->cck_agc_rpt & 0x3e); 1540 break; 1541 } 1542 } else { 1543 report = pcck_buf->cck_agc_rpt & 0x60; 1544 report >>= 5; 1545 switch (report) { 1546 case 0x3: 1547 rx_pwr_all = -35 - 1548 ((pcck_buf->cck_agc_rpt & 1549 0x1f) << 1); 1550 break; 1551 case 0x2: 1552 rx_pwr_all = -23 - 1553 ((pcck_buf->cck_agc_rpt & 1554 0x1f) << 1); 1555 break; 1556 case 0x1: 1557 rx_pwr_all = -11 - 1558 ((pcck_buf->cck_agc_rpt & 1559 0x1f) << 1); 1560 break; 1561 case 0x0: 1562 rx_pwr_all = -8 - 1563 ((pcck_buf->cck_agc_rpt & 1564 0x1f) << 1); 1565 break; 1566 } 1567 } 1568 1569 pwdb_all = rtl92e_rx_db_to_percent(rx_pwr_all); 1570 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all; 1571 pstats->RecvSignalPower = rx_pwr_all; 1572 1573 if (bpacket_match_bssid) { 1574 u8 sq; 1575 1576 if (pstats->RxPWDBAll > 40) { 1577 sq = 100; 1578 } else { 1579 sq = pcck_buf->sq_rpt; 1580 1581 if (pcck_buf->sq_rpt > 64) 1582 sq = 0; 1583 else if (pcck_buf->sq_rpt < 20) 1584 sq = 100; 1585 else 1586 sq = ((64-sq) * 100) / 44; 1587 } 1588 pstats->SignalQuality = sq; 1589 precord_stats->SignalQuality = sq; 1590 pstats->RxMIMOSignalQuality[0] = sq; 1591 precord_stats->RxMIMOSignalQuality[0] = sq; 1592 pstats->RxMIMOSignalQuality[1] = -1; 1593 precord_stats->RxMIMOSignalQuality[1] = -1; 1594 } 1595 } else { 1596 priv->stats.numqry_phystatusHT++; 1597 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) { 1598 if (priv->brfpath_rxenable[i]) 1599 rf_rx_num++; 1600 1601 rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i] & 0x3F) * 1602 2) - 110; 1603 1604 tmp_rxsnr = pofdm_buf->rxsnr_X[i]; 1605 rx_snrX = (s8)(tmp_rxsnr); 1606 rx_snrX /= 2; 1607 priv->stats.rxSNRdB[i] = (long)rx_snrX; 1608 1609 RSSI = rtl92e_rx_db_to_percent(rx_pwr[i]); 1610 if (priv->brfpath_rxenable[i]) 1611 total_rssi += RSSI; 1612 1613 if (bpacket_match_bssid) { 1614 pstats->RxMIMOSignalStrength[i] = RSSI; 1615 precord_stats->RxMIMOSignalStrength[i] = RSSI; 1616 } 1617 } 1618 1619 1620 rx_pwr_all = (((pofdm_buf->pwdb_all) >> 1) & 0x7f) - 106; 1621 pwdb_all = rtl92e_rx_db_to_percent(rx_pwr_all); 1622 1623 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all; 1624 pstats->RxPower = precord_stats->RxPower = rx_pwr_all; 1625 pstats->RecvSignalPower = rx_pwr_all; 1626 if (pdrvinfo->RxHT && pdrvinfo->RxRate >= DESC90_RATEMCS8 && 1627 pdrvinfo->RxRate <= DESC90_RATEMCS15) 1628 max_spatial_stream = 2; 1629 else 1630 max_spatial_stream = 1; 1631 1632 for (i = 0; i < max_spatial_stream; i++) { 1633 tmp_rxevm = pofdm_buf->rxevm_X[i]; 1634 rx_evmX = (s8)(tmp_rxevm); 1635 1636 rx_evmX /= 2; 1637 1638 evm = rtl92e_evm_db_to_percent(rx_evmX); 1639 if (bpacket_match_bssid) { 1640 if (i == 0) { 1641 pstats->SignalQuality = evm & 0xff; 1642 precord_stats->SignalQuality = evm & 0xff; 1643 } 1644 pstats->RxMIMOSignalQuality[i] = evm & 0xff; 1645 precord_stats->RxMIMOSignalQuality[i] = evm & 0xff; 1646 } 1647 } 1648 1649 1650 rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg; 1651 prxsc = (struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *) 1652 &rxsc_sgien_exflg; 1653 if (pdrvinfo->BW) 1654 priv->stats.received_bwtype[1+prxsc->rxsc]++; 1655 else 1656 priv->stats.received_bwtype[0]++; 1657 } 1658 1659 if (is_cck_rate) { 1660 pstats->SignalStrength = precord_stats->SignalStrength = 1661 _rtl92e_signal_scale_mapping(priv, 1662 (long)pwdb_all); 1663 1664 } else { 1665 if (rf_rx_num != 0) 1666 pstats->SignalStrength = precord_stats->SignalStrength = 1667 _rtl92e_signal_scale_mapping(priv, 1668 (long)(total_rssi /= rf_rx_num)); 1669 } 1670 } 1671 1672 static void _rtl92e_process_phyinfo(struct r8192_priv *priv, u8 *buffer, 1673 struct rtllib_rx_stats *prev_st, 1674 struct rtllib_rx_stats *curr_st) 1675 { 1676 bool bcheck = false; 1677 u8 rfpath; 1678 u32 ij, tmp_val; 1679 static u32 slide_rssi_index, slide_rssi_statistics; 1680 static u32 slide_evm_index, slide_evm_statistics; 1681 static u32 last_rssi, last_evm; 1682 static u32 slide_beacon_adc_pwdb_index; 1683 static u32 slide_beacon_adc_pwdb_statistics; 1684 static u32 last_beacon_adc_pwdb; 1685 struct rtllib_hdr_3addr *hdr; 1686 u16 sc; 1687 unsigned int seq; 1688 1689 hdr = (struct rtllib_hdr_3addr *)buffer; 1690 sc = le16_to_cpu(hdr->seq_ctl); 1691 seq = WLAN_GET_SEQ_SEQ(sc); 1692 curr_st->Seq_Num = seq; 1693 if (!prev_st->bIsAMPDU) 1694 bcheck = true; 1695 1696 if (slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX) { 1697 slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX; 1698 last_rssi = priv->stats.slide_signal_strength[slide_rssi_index]; 1699 priv->stats.slide_rssi_total -= last_rssi; 1700 } 1701 priv->stats.slide_rssi_total += prev_st->SignalStrength; 1702 1703 priv->stats.slide_signal_strength[slide_rssi_index++] = 1704 prev_st->SignalStrength; 1705 if (slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX) 1706 slide_rssi_index = 0; 1707 1708 tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics; 1709 priv->stats.signal_strength = rtl92e_translate_to_dbm(priv, tmp_val); 1710 curr_st->rssi = priv->stats.signal_strength; 1711 if (!prev_st->bPacketMatchBSSID) { 1712 if (!prev_st->bToSelfBA) 1713 return; 1714 } 1715 1716 if (!bcheck) 1717 return; 1718 1719 priv->stats.num_process_phyinfo++; 1720 if (!prev_st->bIsCCK && prev_st->bPacketToSelf) { 1721 for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++) { 1722 if (!rtl92e_is_legal_rf_path(priv->rtllib->dev, rfpath)) 1723 continue; 1724 RT_TRACE(COMP_DBG, 1725 "Jacken -> pPreviousstats->RxMIMOSignalStrength[rfpath] = %d\n", 1726 prev_st->RxMIMOSignalStrength[rfpath]); 1727 if (priv->stats.rx_rssi_percentage[rfpath] == 0) { 1728 priv->stats.rx_rssi_percentage[rfpath] = 1729 prev_st->RxMIMOSignalStrength[rfpath]; 1730 } 1731 if (prev_st->RxMIMOSignalStrength[rfpath] > 1732 priv->stats.rx_rssi_percentage[rfpath]) { 1733 priv->stats.rx_rssi_percentage[rfpath] = 1734 ((priv->stats.rx_rssi_percentage[rfpath] 1735 * (RX_SMOOTH - 1)) + 1736 (prev_st->RxMIMOSignalStrength 1737 [rfpath])) / (RX_SMOOTH); 1738 priv->stats.rx_rssi_percentage[rfpath] = 1739 priv->stats.rx_rssi_percentage[rfpath] 1740 + 1; 1741 } else { 1742 priv->stats.rx_rssi_percentage[rfpath] = 1743 ((priv->stats.rx_rssi_percentage[rfpath] * 1744 (RX_SMOOTH-1)) + 1745 (prev_st->RxMIMOSignalStrength[rfpath])) / 1746 (RX_SMOOTH); 1747 } 1748 RT_TRACE(COMP_DBG, 1749 "Jacken -> priv->RxStats.RxRSSIPercentage[rfPath] = %d\n", 1750 priv->stats.rx_rssi_percentage[rfpath]); 1751 } 1752 } 1753 1754 1755 if (prev_st->bPacketBeacon) { 1756 if (slide_beacon_adc_pwdb_statistics++ >= 1757 PHY_Beacon_RSSI_SLID_WIN_MAX) { 1758 slide_beacon_adc_pwdb_statistics = 1759 PHY_Beacon_RSSI_SLID_WIN_MAX; 1760 last_beacon_adc_pwdb = priv->stats.Slide_Beacon_pwdb 1761 [slide_beacon_adc_pwdb_index]; 1762 priv->stats.Slide_Beacon_Total -= last_beacon_adc_pwdb; 1763 } 1764 priv->stats.Slide_Beacon_Total += prev_st->RxPWDBAll; 1765 priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index] = 1766 prev_st->RxPWDBAll; 1767 slide_beacon_adc_pwdb_index++; 1768 if (slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX) 1769 slide_beacon_adc_pwdb_index = 0; 1770 prev_st->RxPWDBAll = priv->stats.Slide_Beacon_Total / 1771 slide_beacon_adc_pwdb_statistics; 1772 if (prev_st->RxPWDBAll >= 3) 1773 prev_st->RxPWDBAll -= 3; 1774 } 1775 1776 RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n", 1777 prev_st->bIsCCK ? "CCK" : "OFDM", 1778 prev_st->RxPWDBAll); 1779 1780 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon || 1781 prev_st->bToSelfBA) { 1782 if (priv->undecorated_smoothed_pwdb < 0) 1783 priv->undecorated_smoothed_pwdb = prev_st->RxPWDBAll; 1784 if (prev_st->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb) { 1785 priv->undecorated_smoothed_pwdb = 1786 (((priv->undecorated_smoothed_pwdb) * 1787 (RX_SMOOTH-1)) + 1788 (prev_st->RxPWDBAll)) / (RX_SMOOTH); 1789 priv->undecorated_smoothed_pwdb = 1790 priv->undecorated_smoothed_pwdb + 1; 1791 } else { 1792 priv->undecorated_smoothed_pwdb = 1793 (((priv->undecorated_smoothed_pwdb) * 1794 (RX_SMOOTH-1)) + 1795 (prev_st->RxPWDBAll)) / (RX_SMOOTH); 1796 } 1797 rtl92e_update_rx_statistics(priv, prev_st); 1798 } 1799 1800 if (prev_st->SignalQuality != 0) { 1801 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon || 1802 prev_st->bToSelfBA) { 1803 if (slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX) { 1804 slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX; 1805 last_evm = 1806 priv->stats.slide_evm[slide_evm_index]; 1807 priv->stats.slide_evm_total -= last_evm; 1808 } 1809 1810 priv->stats.slide_evm_total += prev_st->SignalQuality; 1811 1812 priv->stats.slide_evm[slide_evm_index++] = 1813 prev_st->SignalQuality; 1814 if (slide_evm_index >= PHY_RSSI_SLID_WIN_MAX) 1815 slide_evm_index = 0; 1816 1817 tmp_val = priv->stats.slide_evm_total / 1818 slide_evm_statistics; 1819 priv->stats.signal_quality = tmp_val; 1820 priv->stats.last_signal_strength_inpercent = tmp_val; 1821 } 1822 1823 if (prev_st->bPacketToSelf || 1824 prev_st->bPacketBeacon || 1825 prev_st->bToSelfBA) { 1826 for (ij = 0; ij < 2; ij++) { 1827 if (prev_st->RxMIMOSignalQuality[ij] != -1) { 1828 if (priv->stats.rx_evm_percentage[ij] == 0) 1829 priv->stats.rx_evm_percentage[ij] = 1830 prev_st->RxMIMOSignalQuality[ij]; 1831 priv->stats.rx_evm_percentage[ij] = 1832 ((priv->stats.rx_evm_percentage[ij] * 1833 (RX_SMOOTH - 1)) + 1834 (prev_st->RxMIMOSignalQuality[ij])) / 1835 (RX_SMOOTH); 1836 } 1837 } 1838 } 1839 } 1840 } 1841 1842 static void _rtl92e_translate_rx_signal_stats(struct net_device *dev, 1843 struct sk_buff *skb, 1844 struct rtllib_rx_stats *pstats, 1845 struct rx_desc *pdesc, 1846 struct rx_fwinfo *pdrvinfo) 1847 { 1848 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); 1849 bool bpacket_match_bssid, bpacket_toself; 1850 bool bPacketBeacon = false; 1851 struct rtllib_hdr_3addr *hdr; 1852 bool bToSelfBA = false; 1853 static struct rtllib_rx_stats previous_stats; 1854 u16 fc, type; 1855 u8 *tmp_buf; 1856 u8 *praddr; 1857 1858 tmp_buf = skb->data + pstats->RxDrvInfoSize + pstats->RxBufShift; 1859 1860 hdr = (struct rtllib_hdr_3addr *)tmp_buf; 1861 fc = le16_to_cpu(hdr->frame_ctl); 1862 type = WLAN_FC_GET_TYPE(fc); 1863 praddr = hdr->addr1; 1864 1865 bpacket_match_bssid = 1866 ((type != RTLLIB_FTYPE_CTL) && 1867 ether_addr_equal(priv->rtllib->current_network.bssid, 1868 (fc & RTLLIB_FCTL_TODS) ? hdr->addr1 : 1869 (fc & RTLLIB_FCTL_FROMDS) ? hdr->addr2 : 1870 hdr->addr3) && 1871 (!pstats->bHwError) && (!pstats->bCRC) && (!pstats->bICV)); 1872 bpacket_toself = bpacket_match_bssid && /* check this */ 1873 ether_addr_equal(praddr, priv->rtllib->dev->dev_addr); 1874 if (WLAN_FC_GET_FRAMETYPE(fc) == RTLLIB_STYPE_BEACON) 1875 bPacketBeacon = true; 1876 if (bpacket_match_bssid) 1877 priv->stats.numpacket_matchbssid++; 1878 if (bpacket_toself) 1879 priv->stats.numpacket_toself++; 1880 _rtl92e_process_phyinfo(priv, tmp_buf, &previous_stats, pstats); 1881 _rtl92e_query_rxphystatus(priv, pstats, pdesc, pdrvinfo, 1882 &previous_stats, bpacket_match_bssid, 1883 bpacket_toself, bPacketBeacon, bToSelfBA); 1884 rtl92e_copy_mpdu_stats(pstats, &previous_stats); 1885 } 1886 1887 static void _rtl92e_update_received_rate_histogram_stats( 1888 struct net_device *dev, 1889 struct rtllib_rx_stats *pstats) 1890 { 1891 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); 1892 u32 rcvType = 1; 1893 u32 rateIndex; 1894 u32 preamble_guardinterval; 1895 1896 if (pstats->bCRC) 1897 rcvType = 2; 1898 else if (pstats->bICV) 1899 rcvType = 3; 1900 1901 if (pstats->bShortPreamble) 1902 preamble_guardinterval = 1; 1903 else 1904 preamble_guardinterval = 0; 1905 1906 switch (pstats->rate) { 1907 case MGN_1M: 1908 rateIndex = 0; 1909 break; 1910 case MGN_2M: 1911 rateIndex = 1; 1912 break; 1913 case MGN_5_5M: 1914 rateIndex = 2; 1915 break; 1916 case MGN_11M: 1917 rateIndex = 3; 1918 break; 1919 case MGN_6M: 1920 rateIndex = 4; 1921 break; 1922 case MGN_9M: 1923 rateIndex = 5; 1924 break; 1925 case MGN_12M: 1926 rateIndex = 6; 1927 break; 1928 case MGN_18M: 1929 rateIndex = 7; 1930 break; 1931 case MGN_24M: 1932 rateIndex = 8; 1933 break; 1934 case MGN_36M: 1935 rateIndex = 9; 1936 break; 1937 case MGN_48M: 1938 rateIndex = 10; 1939 break; 1940 case MGN_54M: 1941 rateIndex = 11; 1942 break; 1943 case MGN_MCS0: 1944 rateIndex = 12; 1945 break; 1946 case MGN_MCS1: 1947 rateIndex = 13; 1948 break; 1949 case MGN_MCS2: 1950 rateIndex = 14; 1951 break; 1952 case MGN_MCS3: 1953 rateIndex = 15; 1954 break; 1955 case MGN_MCS4: 1956 rateIndex = 16; 1957 break; 1958 case MGN_MCS5: 1959 rateIndex = 17; 1960 break; 1961 case MGN_MCS6: 1962 rateIndex = 18; 1963 break; 1964 case MGN_MCS7: 1965 rateIndex = 19; 1966 break; 1967 case MGN_MCS8: 1968 rateIndex = 20; 1969 break; 1970 case MGN_MCS9: 1971 rateIndex = 21; 1972 break; 1973 case MGN_MCS10: 1974 rateIndex = 22; 1975 break; 1976 case MGN_MCS11: 1977 rateIndex = 23; 1978 break; 1979 case MGN_MCS12: 1980 rateIndex = 24; 1981 break; 1982 case MGN_MCS13: 1983 rateIndex = 25; 1984 break; 1985 case MGN_MCS14: 1986 rateIndex = 26; 1987 break; 1988 case MGN_MCS15: 1989 rateIndex = 27; 1990 break; 1991 default: 1992 rateIndex = 28; 1993 break; 1994 } 1995 priv->stats.received_preamble_GI[preamble_guardinterval][rateIndex]++; 1996 priv->stats.received_rate_histogram[0][rateIndex]++; 1997 priv->stats.received_rate_histogram[rcvType][rateIndex]++; 1998 } 1999 2000 bool rtl92e_get_rx_stats(struct net_device *dev, struct rtllib_rx_stats *stats, 2001 struct rx_desc *pdesc, struct sk_buff *skb) 2002 { 2003 struct r8192_priv *priv = rtllib_priv(dev); 2004 struct rx_fwinfo *pDrvInfo = NULL; 2005 2006 stats->bICV = pdesc->ICV; 2007 stats->bCRC = pdesc->CRC32; 2008 stats->bHwError = pdesc->CRC32 | pdesc->ICV; 2009 2010 stats->Length = pdesc->Length; 2011 if (stats->Length < 24) 2012 stats->bHwError |= 1; 2013 2014 if (stats->bHwError) { 2015 stats->bShift = false; 2016 2017 if (pdesc->CRC32) { 2018 if (pdesc->Length < 500) 2019 priv->stats.rxcrcerrmin++; 2020 else if (pdesc->Length > 1000) 2021 priv->stats.rxcrcerrmax++; 2022 else 2023 priv->stats.rxcrcerrmid++; 2024 } 2025 return false; 2026 } 2027 2028 stats->RxDrvInfoSize = pdesc->RxDrvInfoSize; 2029 stats->RxBufShift = (pdesc->Shift) & 0x03; 2030 stats->Decrypted = !pdesc->SWDec; 2031 2032 pDrvInfo = (struct rx_fwinfo *)(skb->data + stats->RxBufShift); 2033 2034 stats->rate = _rtl92e_rate_hw_to_mgn((bool)pDrvInfo->RxHT, 2035 pDrvInfo->RxRate); 2036 stats->bShortPreamble = pDrvInfo->SPLCP; 2037 2038 _rtl92e_update_received_rate_histogram_stats(dev, stats); 2039 2040 stats->bIsAMPDU = (pDrvInfo->PartAggr == 1); 2041 stats->bFirstMPDU = (pDrvInfo->PartAggr == 1) && 2042 (pDrvInfo->FirstAGGR == 1); 2043 2044 stats->TimeStampLow = pDrvInfo->TSFL; 2045 stats->TimeStampHigh = rtl92e_readl(dev, TSFR+4); 2046 2047 rtl92e_update_rx_pkt_timestamp(dev, stats); 2048 2049 if ((stats->RxBufShift + stats->RxDrvInfoSize) > 0) 2050 stats->bShift = 1; 2051 2052 stats->RxIs40MHzPacket = pDrvInfo->BW; 2053 2054 _rtl92e_translate_rx_signal_stats(dev, skb, stats, pdesc, pDrvInfo); 2055 2056 if (pDrvInfo->FirstAGGR == 1 || pDrvInfo->PartAggr == 1) 2057 RT_TRACE(COMP_RXDESC, 2058 "pDrvInfo->FirstAGGR = %d, pDrvInfo->PartAggr = %d\n", 2059 pDrvInfo->FirstAGGR, pDrvInfo->PartAggr); 2060 skb_trim(skb, skb->len - 4/*sCrcLng*/); 2061 2062 2063 stats->packetlength = stats->Length-4; 2064 stats->fraglength = stats->packetlength; 2065 stats->fragoffset = 0; 2066 stats->ntotalfrag = 1; 2067 return true; 2068 } 2069 2070 void rtl92e_stop_adapter(struct net_device *dev, bool reset) 2071 { 2072 struct r8192_priv *priv = rtllib_priv(dev); 2073 int i; 2074 u8 OpMode; 2075 u8 u1bTmp; 2076 u32 ulRegRead; 2077 2078 OpMode = RT_OP_MODE_NO_LINK; 2079 priv->rtllib->SetHwRegHandler(dev, HW_VAR_MEDIA_STATUS, &OpMode); 2080 2081 if (!priv->rtllib->bSupportRemoteWakeUp) { 2082 u1bTmp = 0x0; 2083 rtl92e_writeb(dev, CMDR, u1bTmp); 2084 } 2085 2086 mdelay(20); 2087 2088 if (!reset) { 2089 mdelay(150); 2090 2091 priv->bHwRfOffAction = 2; 2092 2093 if (!priv->rtllib->bSupportRemoteWakeUp) { 2094 rtl92e_set_rf_off(dev); 2095 ulRegRead = rtl92e_readl(dev, CPU_GEN); 2096 ulRegRead |= CPU_GEN_SYSTEM_RESET; 2097 rtl92e_writel(dev, CPU_GEN, ulRegRead); 2098 } else { 2099 rtl92e_writel(dev, WFCRC0, 0xffffffff); 2100 rtl92e_writel(dev, WFCRC1, 0xffffffff); 2101 rtl92e_writel(dev, WFCRC2, 0xffffffff); 2102 2103 2104 rtl92e_writeb(dev, PMR, 0x5); 2105 rtl92e_writeb(dev, MacBlkCtrl, 0xa); 2106 } 2107 } 2108 2109 for (i = 0; i < MAX_QUEUE_SIZE; i++) 2110 skb_queue_purge(&priv->rtllib->skb_waitQ[i]); 2111 for (i = 0; i < MAX_QUEUE_SIZE; i++) 2112 skb_queue_purge(&priv->rtllib->skb_aggQ[i]); 2113 2114 skb_queue_purge(&priv->skb_queue); 2115 } 2116 2117 void rtl92e_update_ratr_table(struct net_device *dev) 2118 { 2119 struct r8192_priv *priv = rtllib_priv(dev); 2120 struct rtllib_device *ieee = priv->rtllib; 2121 u8 *pMcsRate = ieee->dot11HTOperationalRateSet; 2122 u32 ratr_value = 0; 2123 u16 rate_config = 0; 2124 u8 rate_index = 0; 2125 2126 rtl92e_config_rate(dev, &rate_config); 2127 ratr_value = rate_config | *pMcsRate << 12; 2128 switch (ieee->mode) { 2129 case IEEE_A: 2130 ratr_value &= 0x00000FF0; 2131 break; 2132 case IEEE_B: 2133 ratr_value &= 0x0000000F; 2134 break; 2135 case IEEE_G: 2136 case IEEE_G|IEEE_B: 2137 ratr_value &= 0x00000FF7; 2138 break; 2139 case IEEE_N_24G: 2140 case IEEE_N_5G: 2141 if (ieee->pHTInfo->PeerMimoPs == 0) { 2142 ratr_value &= 0x0007F007; 2143 } else { 2144 if (priv->rf_type == RF_1T2R) 2145 ratr_value &= 0x000FF007; 2146 else 2147 ratr_value &= 0x0F81F007; 2148 } 2149 break; 2150 default: 2151 break; 2152 } 2153 ratr_value &= 0x0FFFFFFF; 2154 if (ieee->pHTInfo->bCurTxBW40MHz && 2155 ieee->pHTInfo->bCurShortGI40MHz) 2156 ratr_value |= 0x80000000; 2157 else if (!ieee->pHTInfo->bCurTxBW40MHz && 2158 ieee->pHTInfo->bCurShortGI20MHz) 2159 ratr_value |= 0x80000000; 2160 rtl92e_writel(dev, RATR0+rate_index*4, ratr_value); 2161 rtl92e_writeb(dev, UFWP, 1); 2162 } 2163 2164 void 2165 rtl92e_init_variables(struct net_device *dev) 2166 { 2167 struct r8192_priv *priv = rtllib_priv(dev); 2168 2169 strscpy(priv->nick, "rtl8192E", sizeof(priv->nick)); 2170 2171 priv->rtllib->softmac_features = IEEE_SOFTMAC_SCAN | 2172 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ | 2173 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE; 2174 2175 priv->rtllib->tx_headroom = sizeof(struct tx_fwinfo_8190pci); 2176 2177 priv->ShortRetryLimit = 0x30; 2178 priv->LongRetryLimit = 0x30; 2179 2180 priv->ReceiveConfig = RCR_ADD3 | 2181 RCR_AMF | RCR_ADF | 2182 RCR_AICV | 2183 RCR_AB | RCR_AM | RCR_APM | 2184 RCR_AAP | ((u32)7<<RCR_MXDMA_OFFSET) | 2185 ((u32)7 << RCR_FIFO_OFFSET) | RCR_ONLYERLPKT; 2186 2187 priv->irq_mask[0] = (u32)(IMR_ROK | IMR_VODOK | IMR_VIDOK | 2188 IMR_BEDOK | IMR_BKDOK | IMR_HCCADOK | 2189 IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK | 2190 IMR_BDOK | IMR_RXCMDOK | IMR_TIMEOUT0 | 2191 IMR_RDU | IMR_RXFOVW | IMR_TXFOVW | 2192 IMR_BcnInt | IMR_TBDOK | IMR_TBDER); 2193 2194 priv->PwrDomainProtect = false; 2195 2196 priv->bfirst_after_down = false; 2197 } 2198 2199 void rtl92e_enable_irq(struct net_device *dev) 2200 { 2201 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); 2202 2203 priv->irq_enabled = 1; 2204 2205 rtl92e_writel(dev, INTA_MASK, priv->irq_mask[0]); 2206 2207 } 2208 2209 void rtl92e_disable_irq(struct net_device *dev) 2210 { 2211 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); 2212 2213 rtl92e_writel(dev, INTA_MASK, 0); 2214 2215 priv->irq_enabled = 0; 2216 } 2217 2218 void rtl92e_clear_irq(struct net_device *dev) 2219 { 2220 u32 tmp; 2221 2222 tmp = rtl92e_readl(dev, ISR); 2223 rtl92e_writel(dev, ISR, tmp); 2224 } 2225 2226 2227 void rtl92e_enable_rx(struct net_device *dev) 2228 { 2229 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); 2230 2231 rtl92e_writel(dev, RDQDA, priv->rx_ring_dma[RX_MPDU_QUEUE]); 2232 } 2233 2234 static const u32 TX_DESC_BASE[] = { 2235 BKQDA, BEQDA, VIQDA, VOQDA, HCCAQDA, CQDA, MQDA, HQDA, BQDA 2236 }; 2237 2238 void rtl92e_enable_tx(struct net_device *dev) 2239 { 2240 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); 2241 u32 i; 2242 2243 for (i = 0; i < MAX_TX_QUEUE_COUNT; i++) 2244 rtl92e_writel(dev, TX_DESC_BASE[i], priv->tx_ring[i].dma); 2245 } 2246 2247 2248 void rtl92e_ack_irq(struct net_device *dev, u32 *p_inta, u32 *p_intb) 2249 { 2250 *p_inta = rtl92e_readl(dev, ISR); 2251 rtl92e_writel(dev, ISR, *p_inta); 2252 } 2253 2254 bool rtl92e_is_rx_stuck(struct net_device *dev) 2255 { 2256 struct r8192_priv *priv = rtllib_priv(dev); 2257 u16 RegRxCounter = rtl92e_readw(dev, 0x130); 2258 bool bStuck = false; 2259 static u8 rx_chk_cnt; 2260 u32 SlotIndex = 0, TotalRxStuckCount = 0; 2261 u8 i; 2262 u8 SilentResetRxSoltNum = 4; 2263 2264 RT_TRACE(COMP_RESET, "%s(): RegRxCounter is %d, RxCounter is %d\n", 2265 __func__, RegRxCounter, priv->RxCounter); 2266 2267 rx_chk_cnt++; 2268 if (priv->undecorated_smoothed_pwdb >= (RateAdaptiveTH_High+5)) { 2269 rx_chk_cnt = 0; 2270 } else if ((priv->undecorated_smoothed_pwdb < (RateAdaptiveTH_High + 5)) 2271 && (((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) && 2272 (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_40M)) 2273 || ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) && 2274 (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_20M)))) { 2275 if (rx_chk_cnt < 2) 2276 return bStuck; 2277 rx_chk_cnt = 0; 2278 } else if ((((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) && 2279 (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_40M)) || 2280 ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) && 2281 (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_20M))) && 2282 priv->undecorated_smoothed_pwdb >= VeryLowRSSI) { 2283 if (rx_chk_cnt < 4) 2284 return bStuck; 2285 rx_chk_cnt = 0; 2286 } else { 2287 if (rx_chk_cnt < 8) 2288 return bStuck; 2289 rx_chk_cnt = 0; 2290 } 2291 2292 2293 SlotIndex = (priv->SilentResetRxSlotIndex++)%SilentResetRxSoltNum; 2294 2295 if (priv->RxCounter == RegRxCounter) { 2296 priv->SilentResetRxStuckEvent[SlotIndex] = 1; 2297 2298 for (i = 0; i < SilentResetRxSoltNum; i++) 2299 TotalRxStuckCount += priv->SilentResetRxStuckEvent[i]; 2300 2301 if (TotalRxStuckCount == SilentResetRxSoltNum) { 2302 bStuck = true; 2303 for (i = 0; i < SilentResetRxSoltNum; i++) 2304 TotalRxStuckCount += 2305 priv->SilentResetRxStuckEvent[i]; 2306 } 2307 2308 2309 } else { 2310 priv->SilentResetRxStuckEvent[SlotIndex] = 0; 2311 } 2312 2313 priv->RxCounter = RegRxCounter; 2314 2315 return bStuck; 2316 } 2317 2318 bool rtl92e_is_tx_stuck(struct net_device *dev) 2319 { 2320 struct r8192_priv *priv = rtllib_priv(dev); 2321 bool bStuck = false; 2322 u16 RegTxCounter = rtl92e_readw(dev, 0x128); 2323 2324 RT_TRACE(COMP_RESET, "%s():RegTxCounter is %d,TxCounter is %d\n", 2325 __func__, RegTxCounter, priv->TxCounter); 2326 2327 if (priv->TxCounter == RegTxCounter) 2328 bStuck = true; 2329 2330 priv->TxCounter = RegTxCounter; 2331 2332 return bStuck; 2333 } 2334 2335 bool rtl92e_get_nmode_support_by_sec(struct net_device *dev) 2336 { 2337 struct r8192_priv *priv = rtllib_priv(dev); 2338 struct rtllib_device *ieee = priv->rtllib; 2339 2340 if (ieee->rtllib_ap_sec_type && 2341 (ieee->rtllib_ap_sec_type(priv->rtllib)&(SEC_ALG_WEP | 2342 SEC_ALG_TKIP))) { 2343 return false; 2344 } else { 2345 return true; 2346 } 2347 } 2348 2349 bool rtl92e_is_halfn_supported_by_ap(struct net_device *dev) 2350 { 2351 struct r8192_priv *priv = rtllib_priv(dev); 2352 struct rtllib_device *ieee = priv->rtllib; 2353 2354 return ieee->bHalfWirelessN24GMode; 2355 } 2356