1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. 4 * 5 * Based on the r8180 driver, which is: 6 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al. 7 * 8 * Contact Information: wlanfae <wlanfae@realtek.com> 9 */ 10 #include "rtl_core.h" 11 #include "r8192E_phy.h" 12 #include "r8192E_phyreg.h" 13 #include "r8190P_rtl8256.h" 14 #include "r8192E_cmdpkt.h" 15 #include "rtl_dm.h" 16 #include "rtl_wx.h" 17 18 static int WDCAPARA_ADD[] = {EDCAPARA_BE, EDCAPARA_BK, EDCAPARA_VI, 19 EDCAPARA_VO}; 20 21 void rtl92e_start_beacon(struct net_device *dev) 22 { 23 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); 24 struct rtllib_network *net = &priv->rtllib->current_network; 25 u16 BcnTimeCfg = 0; 26 u16 BcnCW = 6; 27 u16 BcnIFS = 0xf; 28 29 rtl92e_irq_disable(dev); 30 31 rtl92e_writew(dev, ATIMWND, 2); 32 33 rtl92e_writew(dev, BCN_INTERVAL, net->beacon_interval); 34 rtl92e_writew(dev, BCN_DRV_EARLY_INT, 10); 35 rtl92e_writew(dev, BCN_DMATIME, 256); 36 37 rtl92e_writeb(dev, BCN_ERR_THRESH, 100); 38 39 BcnTimeCfg |= BcnCW<<BCN_TCFG_CW_SHIFT; 40 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS; 41 rtl92e_writew(dev, BCN_TCFG, BcnTimeCfg); 42 rtl92e_irq_enable(dev); 43 } 44 45 static void _rtl92e_update_msr(struct net_device *dev) 46 { 47 struct r8192_priv *priv = rtllib_priv(dev); 48 u8 msr; 49 enum led_ctl_mode LedAction = LED_CTL_NO_LINK; 50 51 msr = rtl92e_readb(dev, MSR); 52 msr &= ~MSR_LINK_MASK; 53 54 switch (priv->rtllib->iw_mode) { 55 case IW_MODE_INFRA: 56 if (priv->rtllib->state == RTLLIB_LINKED) 57 msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT); 58 else 59 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT); 60 LedAction = LED_CTL_LINK; 61 break; 62 case IW_MODE_ADHOC: 63 if (priv->rtllib->state == RTLLIB_LINKED) 64 msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT); 65 else 66 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT); 67 break; 68 case IW_MODE_MASTER: 69 if (priv->rtllib->state == RTLLIB_LINKED) 70 msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT); 71 else 72 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT); 73 break; 74 default: 75 break; 76 } 77 78 rtl92e_writeb(dev, MSR, msr); 79 if (priv->rtllib->LedControlHandler) 80 priv->rtllib->LedControlHandler(dev, LedAction); 81 } 82 83 void rtl92e_set_reg(struct net_device *dev, u8 variable, u8 *val) 84 { 85 struct r8192_priv *priv = rtllib_priv(dev); 86 87 switch (variable) { 88 case HW_VAR_BSSID: 89 /* BSSIDR 2 byte alignment */ 90 rtl92e_writew(dev, BSSIDR, *(u16 *)val); 91 rtl92e_writel(dev, BSSIDR + 2, *(u32 *)(val + 2)); 92 break; 93 94 case HW_VAR_MEDIA_STATUS: 95 { 96 enum rt_op_mode OpMode = *((enum rt_op_mode *)(val)); 97 u8 btMsr = rtl92e_readb(dev, MSR); 98 99 btMsr &= 0xfc; 100 101 switch (OpMode) { 102 case RT_OP_MODE_INFRASTRUCTURE: 103 btMsr |= MSR_INFRA; 104 break; 105 106 case RT_OP_MODE_IBSS: 107 btMsr |= MSR_ADHOC; 108 break; 109 110 case RT_OP_MODE_AP: 111 btMsr |= MSR_AP; 112 break; 113 114 default: 115 btMsr |= MSR_NOLINK; 116 break; 117 } 118 119 rtl92e_writeb(dev, MSR, btMsr); 120 121 } 122 break; 123 124 case HW_VAR_CECHK_BSSID: 125 { 126 u32 RegRCR, Type; 127 128 Type = val[0]; 129 RegRCR = rtl92e_readl(dev, RCR); 130 priv->ReceiveConfig = RegRCR; 131 132 if (Type == true) 133 RegRCR |= (RCR_CBSSID); 134 else if (Type == false) 135 RegRCR &= (~RCR_CBSSID); 136 137 rtl92e_writel(dev, RCR, RegRCR); 138 priv->ReceiveConfig = RegRCR; 139 140 } 141 break; 142 143 case HW_VAR_SLOT_TIME: 144 145 priv->slot_time = val[0]; 146 rtl92e_writeb(dev, SLOT_TIME, val[0]); 147 148 break; 149 150 case HW_VAR_ACK_PREAMBLE: 151 { 152 u32 regTmp; 153 154 priv->short_preamble = (bool)*val; 155 regTmp = priv->basic_rate; 156 if (priv->short_preamble) 157 regTmp |= BRSR_AckShortPmb; 158 rtl92e_writel(dev, RRSR, regTmp); 159 break; 160 } 161 162 case HW_VAR_CPU_RST: 163 rtl92e_writel(dev, CPU_GEN, ((u32 *)(val))[0]); 164 break; 165 166 case HW_VAR_AC_PARAM: 167 { 168 u8 pAcParam = *val; 169 u32 eACI = pAcParam; 170 u8 u1bAIFS; 171 u32 u4bAcParam; 172 u8 mode = priv->rtllib->mode; 173 struct rtllib_qos_parameters *qop = 174 &priv->rtllib->current_network.qos_data.parameters; 175 176 u1bAIFS = qop->aifs[pAcParam] * 177 ((mode&(IEEE_G|IEEE_N_24G)) ? 9 : 20) + aSifsTime; 178 179 rtl92e_dm_init_edca_turbo(dev); 180 181 u4bAcParam = (le16_to_cpu(qop->tx_op_limit[pAcParam]) << 182 AC_PARAM_TXOP_LIMIT_OFFSET) | 183 ((le16_to_cpu(qop->cw_max[pAcParam])) << 184 AC_PARAM_ECW_MAX_OFFSET) | 185 ((le16_to_cpu(qop->cw_min[pAcParam])) << 186 AC_PARAM_ECW_MIN_OFFSET) | 187 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET); 188 189 RT_TRACE(COMP_DBG, "%s():HW_VAR_AC_PARAM eACI:%x:%x\n", 190 __func__, eACI, u4bAcParam); 191 switch (eACI) { 192 case AC1_BK: 193 rtl92e_writel(dev, EDCAPARA_BK, u4bAcParam); 194 break; 195 196 case AC0_BE: 197 rtl92e_writel(dev, EDCAPARA_BE, u4bAcParam); 198 break; 199 200 case AC2_VI: 201 rtl92e_writel(dev, EDCAPARA_VI, u4bAcParam); 202 break; 203 204 case AC3_VO: 205 rtl92e_writel(dev, EDCAPARA_VO, u4bAcParam); 206 break; 207 208 default: 209 netdev_info(dev, "SetHwReg8185(): invalid ACI: %d !\n", 210 eACI); 211 break; 212 } 213 priv->rtllib->SetHwRegHandler(dev, HW_VAR_ACM_CTRL, 214 &pAcParam); 215 break; 216 } 217 218 case HW_VAR_ACM_CTRL: 219 { 220 struct rtllib_qos_parameters *qos_parameters = 221 &priv->rtllib->current_network.qos_data.parameters; 222 u8 pAcParam = *val; 223 u32 eACI = pAcParam; 224 union aci_aifsn *pAciAifsn = (union aci_aifsn *) & 225 (qos_parameters->aifs[0]); 226 u8 acm = pAciAifsn->f.acm; 227 u8 AcmCtrl = rtl92e_readb(dev, AcmHwCtrl); 228 229 RT_TRACE(COMP_DBG, "===========>%s():HW_VAR_ACM_CTRL:%x\n", 230 __func__, eACI); 231 AcmCtrl = AcmCtrl | ((priv->AcmMethod == 2) ? 0x0 : 0x1); 232 233 if (acm) { 234 switch (eACI) { 235 case AC0_BE: 236 AcmCtrl |= AcmHw_BeqEn; 237 break; 238 239 case AC2_VI: 240 AcmCtrl |= AcmHw_ViqEn; 241 break; 242 243 case AC3_VO: 244 AcmCtrl |= AcmHw_VoqEn; 245 break; 246 247 default: 248 RT_TRACE(COMP_QOS, 249 "SetHwReg8185(): [HW_VAR_ACM_CTRL] acm set failed: eACI is %d\n", 250 eACI); 251 break; 252 } 253 } else { 254 switch (eACI) { 255 case AC0_BE: 256 AcmCtrl &= (~AcmHw_BeqEn); 257 break; 258 259 case AC2_VI: 260 AcmCtrl &= (~AcmHw_ViqEn); 261 break; 262 263 case AC3_VO: 264 AcmCtrl &= (~AcmHw_BeqEn); 265 break; 266 267 default: 268 break; 269 } 270 } 271 272 RT_TRACE(COMP_QOS, 273 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", 274 AcmCtrl); 275 rtl92e_writeb(dev, AcmHwCtrl, AcmCtrl); 276 break; 277 } 278 279 case HW_VAR_SIFS: 280 rtl92e_writeb(dev, SIFS, val[0]); 281 rtl92e_writeb(dev, SIFS+1, val[0]); 282 break; 283 284 case HW_VAR_RF_TIMING: 285 { 286 u8 Rf_Timing = *val; 287 288 rtl92e_writeb(dev, rFPGA0_RFTiming1, Rf_Timing); 289 break; 290 } 291 292 default: 293 break; 294 } 295 296 } 297 298 static void _rtl92e_read_eeprom_info(struct net_device *dev) 299 { 300 struct r8192_priv *priv = rtllib_priv(dev); 301 const u8 bMac_Tmp_Addr[ETH_ALEN] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x01}; 302 u8 tempval; 303 u8 ICVer8192, ICVer8256; 304 u16 i, usValue, IC_Version; 305 u16 EEPROMId; 306 307 RT_TRACE(COMP_INIT, "====> _rtl92e_read_eeprom_info\n"); 308 309 EEPROMId = rtl92e_eeprom_read(dev, 0); 310 if (EEPROMId != RTL8190_EEPROM_ID) { 311 netdev_err(dev, "%s(): Invalid EEPROM ID: %x\n", __func__, 312 EEPROMId); 313 priv->AutoloadFailFlag = true; 314 } else { 315 priv->AutoloadFailFlag = false; 316 } 317 318 if (!priv->AutoloadFailFlag) { 319 priv->eeprom_vid = rtl92e_eeprom_read(dev, EEPROM_VID >> 1); 320 priv->eeprom_did = rtl92e_eeprom_read(dev, EEPROM_DID >> 1); 321 322 usValue = rtl92e_eeprom_read(dev, 323 (u16)(EEPROM_Customer_ID>>1)) >> 8; 324 priv->eeprom_CustomerID = (u8)(usValue & 0xff); 325 usValue = rtl92e_eeprom_read(dev, 326 EEPROM_ICVersion_ChannelPlan>>1); 327 priv->eeprom_ChannelPlan = usValue&0xff; 328 IC_Version = (usValue & 0xff00)>>8; 329 330 ICVer8192 = IC_Version & 0xf; 331 ICVer8256 = (IC_Version & 0xf0)>>4; 332 RT_TRACE(COMP_INIT, "\nICVer8192 = 0x%x\n", ICVer8192); 333 RT_TRACE(COMP_INIT, "\nICVer8256 = 0x%x\n", ICVer8256); 334 if (ICVer8192 == 0x2) { 335 if (ICVer8256 == 0x5) 336 priv->card_8192_version = VERSION_8190_BE; 337 } 338 switch (priv->card_8192_version) { 339 case VERSION_8190_BD: 340 case VERSION_8190_BE: 341 break; 342 default: 343 priv->card_8192_version = VERSION_8190_BD; 344 break; 345 } 346 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n", 347 priv->card_8192_version); 348 } else { 349 priv->card_8192_version = VERSION_8190_BD; 350 priv->eeprom_vid = 0; 351 priv->eeprom_did = 0; 352 priv->eeprom_CustomerID = 0; 353 priv->eeprom_ChannelPlan = 0; 354 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n", 0xff); 355 } 356 357 RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid); 358 RT_TRACE(COMP_INIT, "EEPROM DID = 0x%4x\n", priv->eeprom_did); 359 RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n", 360 priv->eeprom_CustomerID); 361 362 if (!priv->AutoloadFailFlag) { 363 for (i = 0; i < 6; i += 2) { 364 usValue = rtl92e_eeprom_read(dev, 365 (EEPROM_NODE_ADDRESS_BYTE_0 + i) >> 1); 366 *(u16 *)(&dev->dev_addr[i]) = usValue; 367 } 368 } else { 369 ether_addr_copy(dev->dev_addr, bMac_Tmp_Addr); 370 } 371 372 RT_TRACE(COMP_INIT, "Permanent Address = %pM\n", 373 dev->dev_addr); 374 375 if (priv->card_8192_version > VERSION_8190_BD) 376 priv->bTXPowerDataReadFromEEPORM = true; 377 else 378 priv->bTXPowerDataReadFromEEPORM = false; 379 380 priv->rf_type = RTL819X_DEFAULT_RF_TYPE; 381 382 if (priv->card_8192_version > VERSION_8190_BD) { 383 if (!priv->AutoloadFailFlag) { 384 tempval = (rtl92e_eeprom_read(dev, 385 (EEPROM_RFInd_PowerDiff >> 1))) & 0xff; 386 priv->EEPROMLegacyHTTxPowerDiff = tempval & 0xf; 387 388 if (tempval&0x80) 389 priv->rf_type = RF_1T2R; 390 else 391 priv->rf_type = RF_2T4R; 392 } else { 393 priv->EEPROMLegacyHTTxPowerDiff = 0x04; 394 } 395 RT_TRACE(COMP_INIT, "EEPROMLegacyHTTxPowerDiff = %d\n", 396 priv->EEPROMLegacyHTTxPowerDiff); 397 398 if (!priv->AutoloadFailFlag) 399 priv->EEPROMThermalMeter = (u8)(((rtl92e_eeprom_read(dev, 400 (EEPROM_ThermalMeter>>1))) & 401 0xff00)>>8); 402 else 403 priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter; 404 RT_TRACE(COMP_INIT, "ThermalMeter = %d\n", 405 priv->EEPROMThermalMeter); 406 priv->TSSI_13dBm = priv->EEPROMThermalMeter * 100; 407 408 if (priv->epromtype == EEPROM_93C46) { 409 if (!priv->AutoloadFailFlag) { 410 usValue = rtl92e_eeprom_read(dev, 411 EEPROM_TxPwDiff_CrystalCap >> 1); 412 priv->EEPROMAntPwDiff = usValue & 0x0fff; 413 priv->EEPROMCrystalCap = (u8)((usValue & 0xf000) 414 >> 12); 415 } else { 416 priv->EEPROMAntPwDiff = 417 EEPROM_Default_AntTxPowerDiff; 418 priv->EEPROMCrystalCap = 419 EEPROM_Default_TxPwDiff_CrystalCap; 420 } 421 RT_TRACE(COMP_INIT, "EEPROMAntPwDiff = %d\n", 422 priv->EEPROMAntPwDiff); 423 RT_TRACE(COMP_INIT, "EEPROMCrystalCap = %d\n", 424 priv->EEPROMCrystalCap); 425 426 for (i = 0; i < 14; i += 2) { 427 if (!priv->AutoloadFailFlag) 428 usValue = rtl92e_eeprom_read(dev, 429 (EEPROM_TxPwIndex_CCK + i) >> 1); 430 else 431 usValue = EEPROM_Default_TxPower; 432 *((u16 *)(&priv->EEPROMTxPowerLevelCCK[i])) = 433 usValue; 434 RT_TRACE(COMP_INIT, 435 "CCK Tx Power Level, Index %d = 0x%02x\n", 436 i, priv->EEPROMTxPowerLevelCCK[i]); 437 RT_TRACE(COMP_INIT, 438 "CCK Tx Power Level, Index %d = 0x%02x\n", 439 i+1, priv->EEPROMTxPowerLevelCCK[i+1]); 440 } 441 for (i = 0; i < 14; i += 2) { 442 if (!priv->AutoloadFailFlag) 443 usValue = rtl92e_eeprom_read(dev, 444 (EEPROM_TxPwIndex_OFDM_24G + i) >> 1); 445 else 446 usValue = EEPROM_Default_TxPower; 447 *((u16 *)(&priv->EEPROMTxPowerLevelOFDM24G[i])) 448 = usValue; 449 RT_TRACE(COMP_INIT, 450 "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n", 451 i, priv->EEPROMTxPowerLevelOFDM24G[i]); 452 RT_TRACE(COMP_INIT, 453 "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n", 454 i + 1, 455 priv->EEPROMTxPowerLevelOFDM24G[i+1]); 456 } 457 } 458 if (priv->epromtype == EEPROM_93C46) { 459 for (i = 0; i < 14; i++) { 460 priv->TxPowerLevelCCK[i] = 461 priv->EEPROMTxPowerLevelCCK[i]; 462 priv->TxPowerLevelOFDM24G[i] = 463 priv->EEPROMTxPowerLevelOFDM24G[i]; 464 } 465 priv->LegacyHTTxPowerDiff = 466 priv->EEPROMLegacyHTTxPowerDiff; 467 priv->AntennaTxPwDiff[0] = priv->EEPROMAntPwDiff & 0xf; 468 priv->AntennaTxPwDiff[1] = (priv->EEPROMAntPwDiff & 469 0xf0) >> 4; 470 priv->AntennaTxPwDiff[2] = (priv->EEPROMAntPwDiff & 471 0xf00) >> 8; 472 priv->CrystalCap = priv->EEPROMCrystalCap; 473 priv->ThermalMeter[0] = priv->EEPROMThermalMeter & 0xf; 474 priv->ThermalMeter[1] = (priv->EEPROMThermalMeter & 475 0xf0) >> 4; 476 } else if (priv->epromtype == EEPROM_93C56) { 477 478 for (i = 0; i < 3; i++) { 479 priv->TxPowerLevelCCK_A[i] = 480 priv->EEPROMRfACCKChnl1TxPwLevel[0]; 481 priv->TxPowerLevelOFDM24G_A[i] = 482 priv->EEPROMRfAOfdmChnlTxPwLevel[0]; 483 priv->TxPowerLevelCCK_C[i] = 484 priv->EEPROMRfCCCKChnl1TxPwLevel[0]; 485 priv->TxPowerLevelOFDM24G_C[i] = 486 priv->EEPROMRfCOfdmChnlTxPwLevel[0]; 487 } 488 for (i = 3; i < 9; i++) { 489 priv->TxPowerLevelCCK_A[i] = 490 priv->EEPROMRfACCKChnl1TxPwLevel[1]; 491 priv->TxPowerLevelOFDM24G_A[i] = 492 priv->EEPROMRfAOfdmChnlTxPwLevel[1]; 493 priv->TxPowerLevelCCK_C[i] = 494 priv->EEPROMRfCCCKChnl1TxPwLevel[1]; 495 priv->TxPowerLevelOFDM24G_C[i] = 496 priv->EEPROMRfCOfdmChnlTxPwLevel[1]; 497 } 498 for (i = 9; i < 14; i++) { 499 priv->TxPowerLevelCCK_A[i] = 500 priv->EEPROMRfACCKChnl1TxPwLevel[2]; 501 priv->TxPowerLevelOFDM24G_A[i] = 502 priv->EEPROMRfAOfdmChnlTxPwLevel[2]; 503 priv->TxPowerLevelCCK_C[i] = 504 priv->EEPROMRfCCCKChnl1TxPwLevel[2]; 505 priv->TxPowerLevelOFDM24G_C[i] = 506 priv->EEPROMRfCOfdmChnlTxPwLevel[2]; 507 } 508 for (i = 0; i < 14; i++) 509 RT_TRACE(COMP_INIT, 510 "priv->TxPowerLevelCCK_A[%d] = 0x%x\n", 511 i, priv->TxPowerLevelCCK_A[i]); 512 for (i = 0; i < 14; i++) 513 RT_TRACE(COMP_INIT, 514 "priv->TxPowerLevelOFDM24G_A[%d] = 0x%x\n", 515 i, priv->TxPowerLevelOFDM24G_A[i]); 516 for (i = 0; i < 14; i++) 517 RT_TRACE(COMP_INIT, 518 "priv->TxPowerLevelCCK_C[%d] = 0x%x\n", 519 i, priv->TxPowerLevelCCK_C[i]); 520 for (i = 0; i < 14; i++) 521 RT_TRACE(COMP_INIT, 522 "priv->TxPowerLevelOFDM24G_C[%d] = 0x%x\n", 523 i, priv->TxPowerLevelOFDM24G_C[i]); 524 priv->LegacyHTTxPowerDiff = 525 priv->EEPROMLegacyHTTxPowerDiff; 526 priv->AntennaTxPwDiff[0] = 0; 527 priv->AntennaTxPwDiff[1] = 0; 528 priv->AntennaTxPwDiff[2] = 0; 529 priv->CrystalCap = priv->EEPROMCrystalCap; 530 priv->ThermalMeter[0] = priv->EEPROMThermalMeter & 0xf; 531 priv->ThermalMeter[1] = (priv->EEPROMThermalMeter & 532 0xf0) >> 4; 533 } 534 } 535 536 if (priv->rf_type == RF_1T2R) { 537 /* no matter what checkpatch says, the braces are needed */ 538 RT_TRACE(COMP_INIT, "\n1T2R config\n"); 539 } else if (priv->rf_type == RF_2T4R) { 540 RT_TRACE(COMP_INIT, "\n2T4R config\n"); 541 } 542 543 rtl92e_init_adaptive_rate(dev); 544 545 priv->rf_chip = RF_8256; 546 547 if (priv->RegChannelPlan == 0xf) 548 priv->ChannelPlan = priv->eeprom_ChannelPlan; 549 else 550 priv->ChannelPlan = priv->RegChannelPlan; 551 552 if (priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304) 553 priv->CustomerID = RT_CID_DLINK; 554 555 switch (priv->eeprom_CustomerID) { 556 case EEPROM_CID_DEFAULT: 557 priv->CustomerID = RT_CID_DEFAULT; 558 break; 559 case EEPROM_CID_CAMEO: 560 priv->CustomerID = RT_CID_819x_CAMEO; 561 break; 562 case EEPROM_CID_RUNTOP: 563 priv->CustomerID = RT_CID_819x_RUNTOP; 564 break; 565 case EEPROM_CID_NetCore: 566 priv->CustomerID = RT_CID_819x_Netcore; 567 break; 568 case EEPROM_CID_TOSHIBA: 569 priv->CustomerID = RT_CID_TOSHIBA; 570 if (priv->eeprom_ChannelPlan&0x80) 571 priv->ChannelPlan = priv->eeprom_ChannelPlan&0x7f; 572 else 573 priv->ChannelPlan = 0x0; 574 RT_TRACE(COMP_INIT, "Toshiba ChannelPlan = 0x%x\n", 575 priv->ChannelPlan); 576 break; 577 case EEPROM_CID_Nettronix: 578 priv->ScanDelay = 100; 579 priv->CustomerID = RT_CID_Nettronix; 580 break; 581 case EEPROM_CID_Pronet: 582 priv->CustomerID = RT_CID_PRONET; 583 break; 584 case EEPROM_CID_DLINK: 585 priv->CustomerID = RT_CID_DLINK; 586 break; 587 588 case EEPROM_CID_WHQL: 589 break; 590 default: 591 break; 592 } 593 594 if (priv->ChannelPlan > CHANNEL_PLAN_LEN - 1) 595 priv->ChannelPlan = 0; 596 priv->ChannelPlan = COUNTRY_CODE_WORLD_WIDE_13; 597 598 if (priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304) 599 priv->rtllib->bSupportRemoteWakeUp = true; 600 else 601 priv->rtllib->bSupportRemoteWakeUp = false; 602 603 RT_TRACE(COMP_INIT, "RegChannelPlan(%d)\n", priv->RegChannelPlan); 604 RT_TRACE(COMP_INIT, "ChannelPlan = %d\n", priv->ChannelPlan); 605 RT_TRACE(COMP_TRACE, "<==== ReadAdapterInfo\n"); 606 } 607 608 void rtl92e_get_eeprom_size(struct net_device *dev) 609 { 610 u16 curCR; 611 struct r8192_priv *priv = rtllib_priv(dev); 612 613 RT_TRACE(COMP_INIT, "===========>%s()\n", __func__); 614 curCR = rtl92e_readw(dev, EPROM_CMD); 615 RT_TRACE(COMP_INIT, "read from Reg Cmd9346CR(%x):%x\n", EPROM_CMD, 616 curCR); 617 priv->epromtype = (curCR & EPROM_CMD_9356SEL) ? EEPROM_93C56 : 618 EEPROM_93C46; 619 RT_TRACE(COMP_INIT, "<===========%s(), epromtype:%d\n", __func__, 620 priv->epromtype); 621 _rtl92e_read_eeprom_info(dev); 622 } 623 624 static void _rtl92e_hwconfig(struct net_device *dev) 625 { 626 u32 regRATR = 0, regRRSR = 0; 627 u8 regBwOpMode = 0, regTmp = 0; 628 struct r8192_priv *priv = rtllib_priv(dev); 629 630 switch (priv->rtllib->mode) { 631 case WIRELESS_MODE_B: 632 regBwOpMode = BW_OPMODE_20MHZ; 633 regRATR = RATE_ALL_CCK; 634 regRRSR = RATE_ALL_CCK; 635 break; 636 case WIRELESS_MODE_A: 637 regBwOpMode = BW_OPMODE_5G | BW_OPMODE_20MHZ; 638 regRATR = RATE_ALL_OFDM_AG; 639 regRRSR = RATE_ALL_OFDM_AG; 640 break; 641 case WIRELESS_MODE_G: 642 regBwOpMode = BW_OPMODE_20MHZ; 643 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 644 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 645 break; 646 case WIRELESS_MODE_AUTO: 647 case WIRELESS_MODE_N_24G: 648 regBwOpMode = BW_OPMODE_20MHZ; 649 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | 650 RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS; 651 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 652 break; 653 case WIRELESS_MODE_N_5G: 654 regBwOpMode = BW_OPMODE_5G; 655 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | 656 RATE_ALL_OFDM_2SS; 657 regRRSR = RATE_ALL_OFDM_AG; 658 break; 659 default: 660 regBwOpMode = BW_OPMODE_20MHZ; 661 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 662 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 663 break; 664 } 665 666 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode); 667 { 668 u32 ratr_value; 669 670 ratr_value = regRATR; 671 if (priv->rf_type == RF_1T2R) 672 ratr_value &= ~(RATE_ALL_OFDM_2SS); 673 rtl92e_writel(dev, RATR0, ratr_value); 674 rtl92e_writeb(dev, UFWP, 1); 675 } 676 regTmp = rtl92e_readb(dev, 0x313); 677 regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff); 678 rtl92e_writel(dev, RRSR, regRRSR); 679 680 rtl92e_writew(dev, RETRY_LIMIT, 681 priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT | 682 priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT); 683 } 684 685 bool rtl92e_start_adapter(struct net_device *dev) 686 { 687 struct r8192_priv *priv = rtllib_priv(dev); 688 u32 ulRegRead; 689 bool rtStatus = true; 690 u8 tmpvalue; 691 u8 ICVersion, SwitchingRegulatorOutput; 692 bool bfirmwareok = true; 693 u32 tmpRegA, tmpRegC, TempCCk; 694 int i = 0; 695 u32 retry_times = 0; 696 697 RT_TRACE(COMP_INIT, "====>%s()\n", __func__); 698 priv->being_init_adapter = true; 699 700 start: 701 rtl92e_reset_desc_ring(dev); 702 priv->Rf_Mode = RF_OP_By_SW_3wire; 703 if (priv->ResetProgress == RESET_TYPE_NORESET) { 704 rtl92e_writeb(dev, ANAPAR, 0x37); 705 mdelay(500); 706 } 707 priv->pFirmware->status = FW_STATUS_0_INIT; 708 709 if (priv->RegRfOff) 710 priv->rtllib->eRFPowerState = eRfOff; 711 712 ulRegRead = rtl92e_readl(dev, CPU_GEN); 713 if (priv->pFirmware->status == FW_STATUS_0_INIT) 714 ulRegRead |= CPU_GEN_SYSTEM_RESET; 715 else if (priv->pFirmware->status == FW_STATUS_5_READY) 716 ulRegRead |= CPU_GEN_FIRMWARE_RESET; 717 else 718 netdev_err(dev, "%s(): undefined firmware state: %d.\n", 719 __func__, priv->pFirmware->status); 720 721 rtl92e_writel(dev, CPU_GEN, ulRegRead); 722 723 ICVersion = rtl92e_readb(dev, IC_VERRSION); 724 if (ICVersion >= 0x4) { 725 SwitchingRegulatorOutput = rtl92e_readb(dev, SWREGULATOR); 726 if (SwitchingRegulatorOutput != 0xb8) { 727 rtl92e_writeb(dev, SWREGULATOR, 0xa8); 728 mdelay(1); 729 rtl92e_writeb(dev, SWREGULATOR, 0xb8); 730 } 731 } 732 RT_TRACE(COMP_INIT, "BB Config Start!\n"); 733 rtStatus = rtl92e_config_bb(dev); 734 if (!rtStatus) { 735 netdev_warn(dev, "%s(): Failed to configure BB\n", __func__); 736 return rtStatus; 737 } 738 RT_TRACE(COMP_INIT, "BB Config Finished!\n"); 739 740 priv->LoopbackMode = RTL819X_NO_LOOPBACK; 741 if (priv->ResetProgress == RESET_TYPE_NORESET) { 742 ulRegRead = rtl92e_readl(dev, CPU_GEN); 743 if (priv->LoopbackMode == RTL819X_NO_LOOPBACK) 744 ulRegRead = (ulRegRead & CPU_GEN_NO_LOOPBACK_MSK) | 745 CPU_GEN_NO_LOOPBACK_SET; 746 else if (priv->LoopbackMode == RTL819X_MAC_LOOPBACK) 747 ulRegRead |= CPU_CCK_LOOPBACK; 748 else 749 netdev_err(dev, "%s: Invalid loopback mode setting.\n", 750 __func__); 751 752 rtl92e_writel(dev, CPU_GEN, ulRegRead); 753 754 udelay(500); 755 } 756 _rtl92e_hwconfig(dev); 757 rtl92e_writeb(dev, CMDR, CR_RE | CR_TE); 758 759 rtl92e_writeb(dev, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) | 760 (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT))); 761 rtl92e_writel(dev, MAC0, ((u32 *)dev->dev_addr)[0]); 762 rtl92e_writew(dev, MAC4, ((u16 *)(dev->dev_addr + 4))[0]); 763 rtl92e_writel(dev, RCR, priv->ReceiveConfig); 764 765 rtl92e_writel(dev, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK << 766 RSVD_FW_QUEUE_PAGE_BK_SHIFT | 767 NUM_OF_PAGE_IN_FW_QUEUE_BE << 768 RSVD_FW_QUEUE_PAGE_BE_SHIFT | 769 NUM_OF_PAGE_IN_FW_QUEUE_VI << 770 RSVD_FW_QUEUE_PAGE_VI_SHIFT | 771 NUM_OF_PAGE_IN_FW_QUEUE_VO << 772 RSVD_FW_QUEUE_PAGE_VO_SHIFT); 773 rtl92e_writel(dev, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT << 774 RSVD_FW_QUEUE_PAGE_MGNT_SHIFT); 775 rtl92e_writel(dev, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW | 776 NUM_OF_PAGE_IN_FW_QUEUE_BCN << 777 RSVD_FW_QUEUE_PAGE_BCN_SHIFT| 778 NUM_OF_PAGE_IN_FW_QUEUE_PUB << 779 RSVD_FW_QUEUE_PAGE_PUB_SHIFT); 780 781 rtl92e_tx_enable(dev); 782 rtl92e_rx_enable(dev); 783 ulRegRead = (0xFFF00000 & rtl92e_readl(dev, RRSR)) | 784 RATE_ALL_OFDM_AG | RATE_ALL_CCK; 785 rtl92e_writel(dev, RRSR, ulRegRead); 786 rtl92e_writel(dev, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK)); 787 788 rtl92e_writeb(dev, ACK_TIMEOUT, 0x30); 789 790 if (priv->ResetProgress == RESET_TYPE_NORESET) 791 rtl92e_set_wireless_mode(dev, priv->rtllib->mode); 792 rtl92e_cam_reset(dev); 793 { 794 u8 SECR_value = 0x0; 795 796 SECR_value |= SCR_TxEncEnable; 797 SECR_value |= SCR_RxDecEnable; 798 SECR_value |= SCR_NoSKMC; 799 rtl92e_writeb(dev, SECR, SECR_value); 800 } 801 rtl92e_writew(dev, ATIMWND, 2); 802 rtl92e_writew(dev, BCN_INTERVAL, 100); 803 { 804 int i; 805 806 for (i = 0; i < QOS_QUEUE_NUM; i++) 807 rtl92e_writel(dev, WDCAPARA_ADD[i], 0x005e4332); 808 } 809 rtl92e_writeb(dev, 0xbe, 0xc0); 810 811 rtl92e_config_mac(dev); 812 813 if (priv->card_8192_version > (u8) VERSION_8190_BD) { 814 rtl92e_get_tx_power(dev); 815 rtl92e_set_tx_power(dev, priv->chan); 816 } 817 818 tmpvalue = rtl92e_readb(dev, IC_VERRSION); 819 priv->IC_Cut = tmpvalue; 820 RT_TRACE(COMP_INIT, "priv->IC_Cut= 0x%x\n", priv->IC_Cut); 821 if (priv->IC_Cut >= IC_VersionCut_D) { 822 if (priv->IC_Cut == IC_VersionCut_D) { 823 /* no matter what checkpatch says, braces are needed */ 824 RT_TRACE(COMP_INIT, "D-cut\n"); 825 } else if (priv->IC_Cut == IC_VersionCut_E) { 826 RT_TRACE(COMP_INIT, "E-cut\n"); 827 } 828 } else { 829 RT_TRACE(COMP_INIT, "Before C-cut\n"); 830 } 831 832 RT_TRACE(COMP_INIT, "Load Firmware!\n"); 833 bfirmwareok = rtl92e_init_fw(dev); 834 if (!bfirmwareok) { 835 if (retry_times < 10) { 836 retry_times++; 837 goto start; 838 } else { 839 rtStatus = false; 840 goto end; 841 } 842 } 843 RT_TRACE(COMP_INIT, "Load Firmware finished!\n"); 844 if (priv->ResetProgress == RESET_TYPE_NORESET) { 845 RT_TRACE(COMP_INIT, "RF Config Started!\n"); 846 rtStatus = rtl92e_config_phy(dev); 847 if (!rtStatus) { 848 netdev_info(dev, "RF Config failed\n"); 849 return rtStatus; 850 } 851 RT_TRACE(COMP_INIT, "RF Config Finished!\n"); 852 } 853 854 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn, 0x1); 855 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1); 856 857 rtl92e_writeb(dev, 0x87, 0x0); 858 859 if (priv->RegRfOff) { 860 RT_TRACE((COMP_INIT | COMP_RF | COMP_POWER), 861 "%s(): Turn off RF for RegRfOff ----------\n", 862 __func__); 863 rtl92e_set_rf_state(dev, eRfOff, RF_CHANGE_BY_SW); 864 } else if (priv->rtllib->RfOffReason > RF_CHANGE_BY_PS) { 865 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), 866 "%s(): Turn off RF for RfOffReason(%d) ----------\n", 867 __func__, priv->rtllib->RfOffReason); 868 rtl92e_set_rf_state(dev, eRfOff, priv->rtllib->RfOffReason); 869 } else if (priv->rtllib->RfOffReason >= RF_CHANGE_BY_IPS) { 870 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), 871 "%s(): Turn off RF for RfOffReason(%d) ----------\n", 872 __func__, priv->rtllib->RfOffReason); 873 rtl92e_set_rf_state(dev, eRfOff, priv->rtllib->RfOffReason); 874 } else { 875 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): RF-ON\n", 876 __func__); 877 priv->rtllib->eRFPowerState = eRfOn; 878 priv->rtllib->RfOffReason = 0; 879 } 880 881 if (priv->rtllib->FwRWRF) 882 priv->Rf_Mode = RF_OP_By_FW; 883 else 884 priv->Rf_Mode = RF_OP_By_SW_3wire; 885 886 if (priv->ResetProgress == RESET_TYPE_NORESET) { 887 rtl92e_dm_init_txpower_tracking(dev); 888 889 if (priv->IC_Cut >= IC_VersionCut_D) { 890 tmpRegA = rtl92e_get_bb_reg(dev, rOFDM0_XATxIQImbalance, 891 bMaskDWord); 892 tmpRegC = rtl92e_get_bb_reg(dev, rOFDM0_XCTxIQImbalance, 893 bMaskDWord); 894 for (i = 0; i < TxBBGainTableLength; i++) { 895 if (tmpRegA == dm_tx_bb_gain[i]) { 896 priv->rfa_txpowertrackingindex = (u8)i; 897 priv->rfa_txpowertrackingindex_real = 898 (u8)i; 899 priv->rfa_txpowertracking_default = 900 priv->rfa_txpowertrackingindex; 901 break; 902 } 903 } 904 905 TempCCk = rtl92e_get_bb_reg(dev, rCCK0_TxFilter1, 906 bMaskByte2); 907 908 for (i = 0; i < CCKTxBBGainTableLength; i++) { 909 if (TempCCk == dm_cck_tx_bb_gain[i][0]) { 910 priv->CCKPresentAttentuation_20Mdefault = (u8)i; 911 break; 912 } 913 } 914 priv->CCKPresentAttentuation_40Mdefault = 0; 915 priv->CCKPresentAttentuation_difference = 0; 916 priv->CCKPresentAttentuation = 917 priv->CCKPresentAttentuation_20Mdefault; 918 RT_TRACE(COMP_POWER_TRACKING, 919 "priv->rfa_txpowertrackingindex_initial = %d\n", 920 priv->rfa_txpowertrackingindex); 921 RT_TRACE(COMP_POWER_TRACKING, 922 "priv->rfa_txpowertrackingindex_real__initial = %d\n", 923 priv->rfa_txpowertrackingindex_real); 924 RT_TRACE(COMP_POWER_TRACKING, 925 "priv->CCKPresentAttentuation_difference_initial = %d\n", 926 priv->CCKPresentAttentuation_difference); 927 RT_TRACE(COMP_POWER_TRACKING, 928 "priv->CCKPresentAttentuation_initial = %d\n", 929 priv->CCKPresentAttentuation); 930 priv->btxpower_tracking = false; 931 } 932 } 933 rtl92e_irq_enable(dev); 934 end: 935 priv->being_init_adapter = false; 936 return rtStatus; 937 } 938 939 static void _rtl92e_net_update(struct net_device *dev) 940 { 941 942 struct r8192_priv *priv = rtllib_priv(dev); 943 struct rtllib_network *net; 944 u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf; 945 u16 rate_config = 0; 946 947 net = &priv->rtllib->current_network; 948 rtl92e_config_rate(dev, &rate_config); 949 priv->dot11CurrentPreambleMode = PREAMBLE_AUTO; 950 priv->basic_rate = rate_config &= 0x15f; 951 rtl92e_writew(dev, BSSIDR, *(u16 *)net->bssid); 952 rtl92e_writel(dev, BSSIDR + 2, *(u32 *)(net->bssid + 2)); 953 954 if (priv->rtllib->iw_mode == IW_MODE_ADHOC) { 955 rtl92e_writew(dev, ATIMWND, 2); 956 rtl92e_writew(dev, BCN_DMATIME, 256); 957 rtl92e_writew(dev, BCN_INTERVAL, net->beacon_interval); 958 rtl92e_writew(dev, BCN_DRV_EARLY_INT, 10); 959 rtl92e_writeb(dev, BCN_ERR_THRESH, 100); 960 961 BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT); 962 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS; 963 964 rtl92e_writew(dev, BCN_TCFG, BcnTimeCfg); 965 } 966 } 967 968 void rtl92e_link_change(struct net_device *dev) 969 { 970 struct r8192_priv *priv = rtllib_priv(dev); 971 struct rtllib_device *ieee = priv->rtllib; 972 973 if (!priv->up) 974 return; 975 976 if (ieee->state == RTLLIB_LINKED) { 977 _rtl92e_net_update(dev); 978 priv->ops->update_ratr_table(dev); 979 if ((ieee->pairwise_key_type == KEY_TYPE_WEP40) || 980 (ieee->pairwise_key_type == KEY_TYPE_WEP104)) 981 rtl92e_enable_hw_security_config(dev); 982 } else { 983 rtl92e_writeb(dev, 0x173, 0); 984 } 985 _rtl92e_update_msr(dev); 986 987 if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC) { 988 u32 reg; 989 990 reg = rtl92e_readl(dev, RCR); 991 if (priv->rtllib->state == RTLLIB_LINKED) { 992 if (ieee->IntelPromiscuousModeInfo.bPromiscuousOn) 993 ; 994 else 995 priv->ReceiveConfig = reg |= RCR_CBSSID; 996 } else 997 priv->ReceiveConfig = reg &= ~RCR_CBSSID; 998 999 rtl92e_writel(dev, RCR, reg); 1000 } 1001 } 1002 1003 void rtl92e_set_monitor_mode(struct net_device *dev, bool bAllowAllDA, 1004 bool WriteIntoReg) 1005 { 1006 struct r8192_priv *priv = rtllib_priv(dev); 1007 1008 if (bAllowAllDA) 1009 priv->ReceiveConfig |= RCR_AAP; 1010 else 1011 priv->ReceiveConfig &= ~RCR_AAP; 1012 1013 if (WriteIntoReg) 1014 rtl92e_writel(dev, RCR, priv->ReceiveConfig); 1015 } 1016 1017 static u8 _rtl92e_rate_mgn_to_hw(u8 rate) 1018 { 1019 u8 ret = DESC90_RATE1M; 1020 1021 switch (rate) { 1022 case MGN_1M: 1023 ret = DESC90_RATE1M; 1024 break; 1025 case MGN_2M: 1026 ret = DESC90_RATE2M; 1027 break; 1028 case MGN_5_5M: 1029 ret = DESC90_RATE5_5M; 1030 break; 1031 case MGN_11M: 1032 ret = DESC90_RATE11M; 1033 break; 1034 case MGN_6M: 1035 ret = DESC90_RATE6M; 1036 break; 1037 case MGN_9M: 1038 ret = DESC90_RATE9M; 1039 break; 1040 case MGN_12M: 1041 ret = DESC90_RATE12M; 1042 break; 1043 case MGN_18M: 1044 ret = DESC90_RATE18M; 1045 break; 1046 case MGN_24M: 1047 ret = DESC90_RATE24M; 1048 break; 1049 case MGN_36M: 1050 ret = DESC90_RATE36M; 1051 break; 1052 case MGN_48M: 1053 ret = DESC90_RATE48M; 1054 break; 1055 case MGN_54M: 1056 ret = DESC90_RATE54M; 1057 break; 1058 case MGN_MCS0: 1059 ret = DESC90_RATEMCS0; 1060 break; 1061 case MGN_MCS1: 1062 ret = DESC90_RATEMCS1; 1063 break; 1064 case MGN_MCS2: 1065 ret = DESC90_RATEMCS2; 1066 break; 1067 case MGN_MCS3: 1068 ret = DESC90_RATEMCS3; 1069 break; 1070 case MGN_MCS4: 1071 ret = DESC90_RATEMCS4; 1072 break; 1073 case MGN_MCS5: 1074 ret = DESC90_RATEMCS5; 1075 break; 1076 case MGN_MCS6: 1077 ret = DESC90_RATEMCS6; 1078 break; 1079 case MGN_MCS7: 1080 ret = DESC90_RATEMCS7; 1081 break; 1082 case MGN_MCS8: 1083 ret = DESC90_RATEMCS8; 1084 break; 1085 case MGN_MCS9: 1086 ret = DESC90_RATEMCS9; 1087 break; 1088 case MGN_MCS10: 1089 ret = DESC90_RATEMCS10; 1090 break; 1091 case MGN_MCS11: 1092 ret = DESC90_RATEMCS11; 1093 break; 1094 case MGN_MCS12: 1095 ret = DESC90_RATEMCS12; 1096 break; 1097 case MGN_MCS13: 1098 ret = DESC90_RATEMCS13; 1099 break; 1100 case MGN_MCS14: 1101 ret = DESC90_RATEMCS14; 1102 break; 1103 case MGN_MCS15: 1104 ret = DESC90_RATEMCS15; 1105 break; 1106 case (0x80|0x20): 1107 ret = DESC90_RATEMCS32; 1108 break; 1109 default: 1110 break; 1111 } 1112 return ret; 1113 } 1114 1115 static u8 _rtl92e_hw_queue_to_fw_queue(struct net_device *dev, u8 QueueID, 1116 u8 priority) 1117 { 1118 u8 QueueSelect = 0x0; 1119 1120 switch (QueueID) { 1121 case BE_QUEUE: 1122 QueueSelect = QSLT_BE; 1123 break; 1124 1125 case BK_QUEUE: 1126 QueueSelect = QSLT_BK; 1127 break; 1128 1129 case VO_QUEUE: 1130 QueueSelect = QSLT_VO; 1131 break; 1132 1133 case VI_QUEUE: 1134 QueueSelect = QSLT_VI; 1135 break; 1136 case MGNT_QUEUE: 1137 QueueSelect = QSLT_MGNT; 1138 break; 1139 case BEACON_QUEUE: 1140 QueueSelect = QSLT_BEACON; 1141 break; 1142 case TXCMD_QUEUE: 1143 QueueSelect = QSLT_CMD; 1144 break; 1145 case HIGH_QUEUE: 1146 QueueSelect = QSLT_HIGH; 1147 break; 1148 default: 1149 netdev_warn(dev, "%s(): Impossible Queue Selection: %d\n", 1150 __func__, QueueID); 1151 break; 1152 } 1153 return QueueSelect; 1154 } 1155 1156 static u8 _rtl92e_query_is_short(u8 TxHT, u8 TxRate, struct cb_desc *tcb_desc) 1157 { 1158 u8 tmp_Short; 1159 1160 tmp_Short = (TxHT == 1) ? ((tcb_desc->bUseShortGI) ? 1 : 0) : 1161 ((tcb_desc->bUseShortPreamble) ? 1 : 0); 1162 if (TxHT == 1 && TxRate != DESC90_RATEMCS15) 1163 tmp_Short = 0; 1164 1165 return tmp_Short; 1166 } 1167 1168 void rtl92e_fill_tx_desc(struct net_device *dev, struct tx_desc *pdesc, 1169 struct cb_desc *cb_desc, struct sk_buff *skb) 1170 { 1171 struct r8192_priv *priv = rtllib_priv(dev); 1172 dma_addr_t mapping; 1173 struct tx_fwinfo_8190pci *pTxFwInfo; 1174 1175 pTxFwInfo = (struct tx_fwinfo_8190pci *)skb->data; 1176 memset(pTxFwInfo, 0, sizeof(struct tx_fwinfo_8190pci)); 1177 pTxFwInfo->TxHT = (cb_desc->data_rate & 0x80) ? 1 : 0; 1178 pTxFwInfo->TxRate = _rtl92e_rate_mgn_to_hw((u8)cb_desc->data_rate); 1179 pTxFwInfo->EnableCPUDur = cb_desc->bTxEnableFwCalcDur; 1180 pTxFwInfo->Short = _rtl92e_query_is_short(pTxFwInfo->TxHT, 1181 pTxFwInfo->TxRate, cb_desc); 1182 1183 if (cb_desc->bAMPDUEnable) { 1184 pTxFwInfo->AllowAggregation = 1; 1185 pTxFwInfo->RxMF = cb_desc->ampdu_factor; 1186 pTxFwInfo->RxAMD = cb_desc->ampdu_density; 1187 } else { 1188 pTxFwInfo->AllowAggregation = 0; 1189 pTxFwInfo->RxMF = 0; 1190 pTxFwInfo->RxAMD = 0; 1191 } 1192 1193 pTxFwInfo->RtsEnable = (cb_desc->bRTSEnable) ? 1 : 0; 1194 pTxFwInfo->CtsEnable = (cb_desc->bCTSEnable) ? 1 : 0; 1195 pTxFwInfo->RtsSTBC = (cb_desc->bRTSSTBC) ? 1 : 0; 1196 pTxFwInfo->RtsHT = (cb_desc->rts_rate&0x80) ? 1 : 0; 1197 pTxFwInfo->RtsRate = _rtl92e_rate_mgn_to_hw((u8)cb_desc->rts_rate); 1198 pTxFwInfo->RtsBandwidth = 0; 1199 pTxFwInfo->RtsSubcarrier = cb_desc->RTSSC; 1200 pTxFwInfo->RtsShort = (pTxFwInfo->RtsHT == 0) ? 1201 (cb_desc->bRTSUseShortPreamble ? 1 : 0) : 1202 (cb_desc->bRTSUseShortGI ? 1 : 0); 1203 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) { 1204 if (cb_desc->bPacketBW) { 1205 pTxFwInfo->TxBandwidth = 1; 1206 pTxFwInfo->TxSubCarrier = 0; 1207 } else { 1208 pTxFwInfo->TxBandwidth = 0; 1209 pTxFwInfo->TxSubCarrier = priv->nCur40MhzPrimeSC; 1210 } 1211 } else { 1212 pTxFwInfo->TxBandwidth = 0; 1213 pTxFwInfo->TxSubCarrier = 0; 1214 } 1215 1216 memset((u8 *)pdesc, 0, 12); 1217 1218 mapping = pci_map_single(priv->pdev, skb->data, skb->len, 1219 PCI_DMA_TODEVICE); 1220 if (pci_dma_mapping_error(priv->pdev, mapping)) { 1221 netdev_err(dev, "%s(): DMA Mapping error\n", __func__); 1222 return; 1223 } 1224 1225 pdesc->LINIP = 0; 1226 pdesc->CmdInit = 1; 1227 pdesc->Offset = sizeof(struct tx_fwinfo_8190pci) + 8; 1228 pdesc->PktSize = (u16)skb->len-sizeof(struct tx_fwinfo_8190pci); 1229 1230 pdesc->SecCAMID = 0; 1231 pdesc->RATid = cb_desc->RATRIndex; 1232 1233 1234 pdesc->NoEnc = 1; 1235 pdesc->SecType = 0x0; 1236 if (cb_desc->bHwSec) { 1237 static u8 tmp; 1238 1239 if (!tmp) { 1240 RT_TRACE(COMP_DBG, "==>================hw sec\n"); 1241 tmp = 1; 1242 } 1243 switch (priv->rtllib->pairwise_key_type) { 1244 case KEY_TYPE_WEP40: 1245 case KEY_TYPE_WEP104: 1246 pdesc->SecType = 0x1; 1247 pdesc->NoEnc = 0; 1248 break; 1249 case KEY_TYPE_TKIP: 1250 pdesc->SecType = 0x2; 1251 pdesc->NoEnc = 0; 1252 break; 1253 case KEY_TYPE_CCMP: 1254 pdesc->SecType = 0x3; 1255 pdesc->NoEnc = 0; 1256 break; 1257 case KEY_TYPE_NA: 1258 pdesc->SecType = 0x0; 1259 pdesc->NoEnc = 1; 1260 break; 1261 } 1262 } 1263 1264 pdesc->PktId = 0x0; 1265 1266 pdesc->QueueSelect = _rtl92e_hw_queue_to_fw_queue(dev, 1267 cb_desc->queue_index, 1268 cb_desc->priority); 1269 pdesc->TxFWInfoSize = sizeof(struct tx_fwinfo_8190pci); 1270 1271 pdesc->DISFB = cb_desc->bTxDisableRateFallBack; 1272 pdesc->USERATE = cb_desc->bTxUseDriverAssingedRate; 1273 1274 pdesc->FirstSeg = 1; 1275 pdesc->LastSeg = 1; 1276 pdesc->TxBufferSize = skb->len; 1277 1278 pdesc->TxBuffAddr = mapping; 1279 } 1280 1281 void rtl92e_fill_tx_cmd_desc(struct net_device *dev, struct tx_desc_cmd *entry, 1282 struct cb_desc *cb_desc, struct sk_buff *skb) 1283 { 1284 struct r8192_priv *priv = rtllib_priv(dev); 1285 dma_addr_t mapping = pci_map_single(priv->pdev, skb->data, skb->len, 1286 PCI_DMA_TODEVICE); 1287 1288 if (pci_dma_mapping_error(priv->pdev, mapping)) 1289 netdev_err(dev, "%s(): DMA Mapping error\n", __func__); 1290 memset(entry, 0, 12); 1291 entry->LINIP = cb_desc->bLastIniPkt; 1292 entry->FirstSeg = 1; 1293 entry->LastSeg = 1; 1294 if (cb_desc->bCmdOrInit == DESC_PACKET_TYPE_INIT) { 1295 entry->CmdInit = DESC_PACKET_TYPE_INIT; 1296 } else { 1297 struct tx_desc *entry_tmp = (struct tx_desc *)entry; 1298 1299 entry_tmp->CmdInit = DESC_PACKET_TYPE_NORMAL; 1300 entry_tmp->Offset = sizeof(struct tx_fwinfo_8190pci) + 8; 1301 entry_tmp->PktSize = (u16)(cb_desc->pkt_size + 1302 entry_tmp->Offset); 1303 entry_tmp->QueueSelect = QSLT_CMD; 1304 entry_tmp->TxFWInfoSize = 0x08; 1305 entry_tmp->RATid = (u8)DESC_PACKET_TYPE_INIT; 1306 } 1307 entry->TxBufferSize = skb->len; 1308 entry->TxBuffAddr = mapping; 1309 entry->OWN = 1; 1310 } 1311 1312 static u8 _rtl92e_rate_hw_to_mgn(bool bIsHT, u8 rate) 1313 { 1314 u8 ret_rate = 0x02; 1315 1316 if (!bIsHT) { 1317 switch (rate) { 1318 case DESC90_RATE1M: 1319 ret_rate = MGN_1M; 1320 break; 1321 case DESC90_RATE2M: 1322 ret_rate = MGN_2M; 1323 break; 1324 case DESC90_RATE5_5M: 1325 ret_rate = MGN_5_5M; 1326 break; 1327 case DESC90_RATE11M: 1328 ret_rate = MGN_11M; 1329 break; 1330 case DESC90_RATE6M: 1331 ret_rate = MGN_6M; 1332 break; 1333 case DESC90_RATE9M: 1334 ret_rate = MGN_9M; 1335 break; 1336 case DESC90_RATE12M: 1337 ret_rate = MGN_12M; 1338 break; 1339 case DESC90_RATE18M: 1340 ret_rate = MGN_18M; 1341 break; 1342 case DESC90_RATE24M: 1343 ret_rate = MGN_24M; 1344 break; 1345 case DESC90_RATE36M: 1346 ret_rate = MGN_36M; 1347 break; 1348 case DESC90_RATE48M: 1349 ret_rate = MGN_48M; 1350 break; 1351 case DESC90_RATE54M: 1352 ret_rate = MGN_54M; 1353 break; 1354 1355 default: 1356 RT_TRACE(COMP_RECV, 1357 "_rtl92e_rate_hw_to_mgn(): Non supportedRate [%x], bIsHT = %d!!!\n", 1358 rate, bIsHT); 1359 break; 1360 } 1361 1362 } else { 1363 switch (rate) { 1364 case DESC90_RATEMCS0: 1365 ret_rate = MGN_MCS0; 1366 break; 1367 case DESC90_RATEMCS1: 1368 ret_rate = MGN_MCS1; 1369 break; 1370 case DESC90_RATEMCS2: 1371 ret_rate = MGN_MCS2; 1372 break; 1373 case DESC90_RATEMCS3: 1374 ret_rate = MGN_MCS3; 1375 break; 1376 case DESC90_RATEMCS4: 1377 ret_rate = MGN_MCS4; 1378 break; 1379 case DESC90_RATEMCS5: 1380 ret_rate = MGN_MCS5; 1381 break; 1382 case DESC90_RATEMCS6: 1383 ret_rate = MGN_MCS6; 1384 break; 1385 case DESC90_RATEMCS7: 1386 ret_rate = MGN_MCS7; 1387 break; 1388 case DESC90_RATEMCS8: 1389 ret_rate = MGN_MCS8; 1390 break; 1391 case DESC90_RATEMCS9: 1392 ret_rate = MGN_MCS9; 1393 break; 1394 case DESC90_RATEMCS10: 1395 ret_rate = MGN_MCS10; 1396 break; 1397 case DESC90_RATEMCS11: 1398 ret_rate = MGN_MCS11; 1399 break; 1400 case DESC90_RATEMCS12: 1401 ret_rate = MGN_MCS12; 1402 break; 1403 case DESC90_RATEMCS13: 1404 ret_rate = MGN_MCS13; 1405 break; 1406 case DESC90_RATEMCS14: 1407 ret_rate = MGN_MCS14; 1408 break; 1409 case DESC90_RATEMCS15: 1410 ret_rate = MGN_MCS15; 1411 break; 1412 case DESC90_RATEMCS32: 1413 ret_rate = 0x80 | 0x20; 1414 break; 1415 1416 default: 1417 RT_TRACE(COMP_RECV, 1418 "_rtl92e_rate_hw_to_mgn(): Non supported Rate [%x], bIsHT = %d!!!\n", 1419 rate, bIsHT); 1420 break; 1421 } 1422 } 1423 1424 return ret_rate; 1425 } 1426 1427 static long _rtl92e_signal_scale_mapping(struct r8192_priv *priv, long currsig) 1428 { 1429 long retsig; 1430 1431 if (currsig >= 61 && currsig <= 100) 1432 retsig = 90 + ((currsig - 60) / 4); 1433 else if (currsig >= 41 && currsig <= 60) 1434 retsig = 78 + ((currsig - 40) / 2); 1435 else if (currsig >= 31 && currsig <= 40) 1436 retsig = 66 + (currsig - 30); 1437 else if (currsig >= 21 && currsig <= 30) 1438 retsig = 54 + (currsig - 20); 1439 else if (currsig >= 5 && currsig <= 20) 1440 retsig = 42 + (((currsig - 5) * 2) / 3); 1441 else if (currsig == 4) 1442 retsig = 36; 1443 else if (currsig == 3) 1444 retsig = 27; 1445 else if (currsig == 2) 1446 retsig = 18; 1447 else if (currsig == 1) 1448 retsig = 9; 1449 else 1450 retsig = currsig; 1451 1452 return retsig; 1453 } 1454 1455 1456 #define rx_hal_is_cck_rate(_pdrvinfo)\ 1457 ((_pdrvinfo->RxRate == DESC90_RATE1M ||\ 1458 _pdrvinfo->RxRate == DESC90_RATE2M ||\ 1459 _pdrvinfo->RxRate == DESC90_RATE5_5M ||\ 1460 _pdrvinfo->RxRate == DESC90_RATE11M) &&\ 1461 !_pdrvinfo->RxHT) 1462 1463 static void _rtl92e_query_rxphystatus( 1464 struct r8192_priv *priv, 1465 struct rtllib_rx_stats *pstats, 1466 struct rx_desc *pdesc, 1467 struct rx_fwinfo *pdrvinfo, 1468 struct rtllib_rx_stats *precord_stats, 1469 bool bpacket_match_bssid, 1470 bool bpacket_toself, 1471 bool bPacketBeacon, 1472 bool bToSelfBA 1473 ) 1474 { 1475 struct phy_sts_ofdm_819xpci *pofdm_buf; 1476 struct phy_sts_cck_819xpci *pcck_buf; 1477 struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *prxsc; 1478 u8 *prxpkt; 1479 u8 i, max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg; 1480 s8 rx_pwr[4], rx_pwr_all = 0; 1481 s8 rx_snrX, rx_evmX; 1482 u8 evm, pwdb_all; 1483 u32 RSSI, total_rssi = 0; 1484 u8 is_cck_rate = 0; 1485 u8 rf_rx_num = 0; 1486 static u8 check_reg824; 1487 static u32 reg824_bit9; 1488 1489 priv->stats.numqry_phystatus++; 1490 1491 is_cck_rate = rx_hal_is_cck_rate(pdrvinfo); 1492 memset(precord_stats, 0, sizeof(struct rtllib_rx_stats)); 1493 pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID = 1494 bpacket_match_bssid; 1495 pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself; 1496 pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate; 1497 pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon; 1498 pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA; 1499 if (check_reg824 == 0) { 1500 reg824_bit9 = rtl92e_get_bb_reg(priv->rtllib->dev, 1501 rFPGA0_XA_HSSIParameter2, 1502 0x200); 1503 check_reg824 = 1; 1504 } 1505 1506 1507 prxpkt = (u8 *)pdrvinfo; 1508 1509 prxpkt += sizeof(struct rx_fwinfo); 1510 1511 pcck_buf = (struct phy_sts_cck_819xpci *)prxpkt; 1512 pofdm_buf = (struct phy_sts_ofdm_819xpci *)prxpkt; 1513 1514 pstats->RxMIMOSignalQuality[0] = -1; 1515 pstats->RxMIMOSignalQuality[1] = -1; 1516 precord_stats->RxMIMOSignalQuality[0] = -1; 1517 precord_stats->RxMIMOSignalQuality[1] = -1; 1518 1519 if (is_cck_rate) { 1520 u8 report; 1521 1522 priv->stats.numqry_phystatusCCK++; 1523 if (!reg824_bit9) { 1524 report = pcck_buf->cck_agc_rpt & 0xc0; 1525 report >>= 6; 1526 switch (report) { 1527 case 0x3: 1528 rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt & 1529 0x3e); 1530 break; 1531 case 0x2: 1532 rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt & 1533 0x3e); 1534 break; 1535 case 0x1: 1536 rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt & 1537 0x3e); 1538 break; 1539 case 0x0: 1540 rx_pwr_all = 8 - (pcck_buf->cck_agc_rpt & 0x3e); 1541 break; 1542 } 1543 } else { 1544 report = pcck_buf->cck_agc_rpt & 0x60; 1545 report >>= 5; 1546 switch (report) { 1547 case 0x3: 1548 rx_pwr_all = -35 - 1549 ((pcck_buf->cck_agc_rpt & 1550 0x1f) << 1); 1551 break; 1552 case 0x2: 1553 rx_pwr_all = -23 - 1554 ((pcck_buf->cck_agc_rpt & 1555 0x1f) << 1); 1556 break; 1557 case 0x1: 1558 rx_pwr_all = -11 - 1559 ((pcck_buf->cck_agc_rpt & 1560 0x1f) << 1); 1561 break; 1562 case 0x0: 1563 rx_pwr_all = -8 - 1564 ((pcck_buf->cck_agc_rpt & 1565 0x1f) << 1); 1566 break; 1567 } 1568 } 1569 1570 pwdb_all = rtl92e_rx_db_to_percent(rx_pwr_all); 1571 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all; 1572 pstats->RecvSignalPower = rx_pwr_all; 1573 1574 if (bpacket_match_bssid) { 1575 u8 sq; 1576 1577 if (pstats->RxPWDBAll > 40) { 1578 sq = 100; 1579 } else { 1580 sq = pcck_buf->sq_rpt; 1581 1582 if (pcck_buf->sq_rpt > 64) 1583 sq = 0; 1584 else if (pcck_buf->sq_rpt < 20) 1585 sq = 100; 1586 else 1587 sq = ((64-sq) * 100) / 44; 1588 } 1589 pstats->SignalQuality = sq; 1590 precord_stats->SignalQuality = sq; 1591 pstats->RxMIMOSignalQuality[0] = sq; 1592 precord_stats->RxMIMOSignalQuality[0] = sq; 1593 pstats->RxMIMOSignalQuality[1] = -1; 1594 precord_stats->RxMIMOSignalQuality[1] = -1; 1595 } 1596 } else { 1597 priv->stats.numqry_phystatusHT++; 1598 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) { 1599 if (priv->brfpath_rxenable[i]) 1600 rf_rx_num++; 1601 1602 rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i] & 0x3F) * 1603 2) - 110; 1604 1605 tmp_rxsnr = pofdm_buf->rxsnr_X[i]; 1606 rx_snrX = (s8)(tmp_rxsnr); 1607 rx_snrX /= 2; 1608 priv->stats.rxSNRdB[i] = (long)rx_snrX; 1609 1610 RSSI = rtl92e_rx_db_to_percent(rx_pwr[i]); 1611 if (priv->brfpath_rxenable[i]) 1612 total_rssi += RSSI; 1613 1614 if (bpacket_match_bssid) { 1615 pstats->RxMIMOSignalStrength[i] = (u8) RSSI; 1616 precord_stats->RxMIMOSignalStrength[i] = 1617 (u8) RSSI; 1618 } 1619 } 1620 1621 1622 rx_pwr_all = (((pofdm_buf->pwdb_all) >> 1) & 0x7f) - 106; 1623 pwdb_all = rtl92e_rx_db_to_percent(rx_pwr_all); 1624 1625 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all; 1626 pstats->RxPower = precord_stats->RxPower = rx_pwr_all; 1627 pstats->RecvSignalPower = rx_pwr_all; 1628 if (pdrvinfo->RxHT && pdrvinfo->RxRate >= DESC90_RATEMCS8 && 1629 pdrvinfo->RxRate <= DESC90_RATEMCS15) 1630 max_spatial_stream = 2; 1631 else 1632 max_spatial_stream = 1; 1633 1634 for (i = 0; i < max_spatial_stream; i++) { 1635 tmp_rxevm = pofdm_buf->rxevm_X[i]; 1636 rx_evmX = (s8)(tmp_rxevm); 1637 1638 rx_evmX /= 2; 1639 1640 evm = rtl92e_evm_db_to_percent(rx_evmX); 1641 if (bpacket_match_bssid) { 1642 if (i == 0) { 1643 pstats->SignalQuality = evm & 0xff; 1644 precord_stats->SignalQuality = evm & 0xff; 1645 } 1646 pstats->RxMIMOSignalQuality[i] = evm & 0xff; 1647 precord_stats->RxMIMOSignalQuality[i] = evm & 0xff; 1648 } 1649 } 1650 1651 1652 rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg; 1653 prxsc = (struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *) 1654 &rxsc_sgien_exflg; 1655 if (pdrvinfo->BW) 1656 priv->stats.received_bwtype[1+prxsc->rxsc]++; 1657 else 1658 priv->stats.received_bwtype[0]++; 1659 } 1660 1661 if (is_cck_rate) { 1662 pstats->SignalStrength = precord_stats->SignalStrength = 1663 (u8)(_rtl92e_signal_scale_mapping(priv, 1664 (long)pwdb_all)); 1665 1666 } else { 1667 if (rf_rx_num != 0) 1668 pstats->SignalStrength = precord_stats->SignalStrength = 1669 (u8)(_rtl92e_signal_scale_mapping(priv, 1670 (long)(total_rssi /= rf_rx_num))); 1671 } 1672 } 1673 1674 static void _rtl92e_process_phyinfo(struct r8192_priv *priv, u8 *buffer, 1675 struct rtllib_rx_stats *prev_st, 1676 struct rtllib_rx_stats *curr_st) 1677 { 1678 bool bcheck = false; 1679 u8 rfpath; 1680 u32 ij, tmp_val; 1681 static u32 slide_rssi_index, slide_rssi_statistics; 1682 static u32 slide_evm_index, slide_evm_statistics; 1683 static u32 last_rssi, last_evm; 1684 static u32 slide_beacon_adc_pwdb_index; 1685 static u32 slide_beacon_adc_pwdb_statistics; 1686 static u32 last_beacon_adc_pwdb; 1687 struct rtllib_hdr_3addr *hdr; 1688 u16 sc; 1689 unsigned int seq; 1690 1691 hdr = (struct rtllib_hdr_3addr *)buffer; 1692 sc = le16_to_cpu(hdr->seq_ctl); 1693 seq = WLAN_GET_SEQ_SEQ(sc); 1694 curr_st->Seq_Num = seq; 1695 if (!prev_st->bIsAMPDU) 1696 bcheck = true; 1697 1698 if (slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX) { 1699 slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX; 1700 last_rssi = priv->stats.slide_signal_strength[slide_rssi_index]; 1701 priv->stats.slide_rssi_total -= last_rssi; 1702 } 1703 priv->stats.slide_rssi_total += prev_st->SignalStrength; 1704 1705 priv->stats.slide_signal_strength[slide_rssi_index++] = 1706 prev_st->SignalStrength; 1707 if (slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX) 1708 slide_rssi_index = 0; 1709 1710 tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics; 1711 priv->stats.signal_strength = rtl92e_translate_to_dbm(priv, 1712 (u8)tmp_val); 1713 curr_st->rssi = priv->stats.signal_strength; 1714 if (!prev_st->bPacketMatchBSSID) { 1715 if (!prev_st->bToSelfBA) 1716 return; 1717 } 1718 1719 if (!bcheck) 1720 return; 1721 1722 priv->stats.num_process_phyinfo++; 1723 if (!prev_st->bIsCCK && prev_st->bPacketToSelf) { 1724 for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++) { 1725 if (!rtl92e_is_legal_rf_path(priv->rtllib->dev, rfpath)) 1726 continue; 1727 RT_TRACE(COMP_DBG, 1728 "Jacken -> pPreviousstats->RxMIMOSignalStrength[rfpath] = %d\n", 1729 prev_st->RxMIMOSignalStrength[rfpath]); 1730 if (priv->stats.rx_rssi_percentage[rfpath] == 0) { 1731 priv->stats.rx_rssi_percentage[rfpath] = 1732 prev_st->RxMIMOSignalStrength[rfpath]; 1733 } 1734 if (prev_st->RxMIMOSignalStrength[rfpath] > 1735 priv->stats.rx_rssi_percentage[rfpath]) { 1736 priv->stats.rx_rssi_percentage[rfpath] = 1737 ((priv->stats.rx_rssi_percentage[rfpath] 1738 * (RX_SMOOTH - 1)) + 1739 (prev_st->RxMIMOSignalStrength 1740 [rfpath])) / (RX_SMOOTH); 1741 priv->stats.rx_rssi_percentage[rfpath] = 1742 priv->stats.rx_rssi_percentage[rfpath] 1743 + 1; 1744 } else { 1745 priv->stats.rx_rssi_percentage[rfpath] = 1746 ((priv->stats.rx_rssi_percentage[rfpath] * 1747 (RX_SMOOTH-1)) + 1748 (prev_st->RxMIMOSignalStrength[rfpath])) / 1749 (RX_SMOOTH); 1750 } 1751 RT_TRACE(COMP_DBG, 1752 "Jacken -> priv->RxStats.RxRSSIPercentage[rfPath] = %d\n", 1753 priv->stats.rx_rssi_percentage[rfpath]); 1754 } 1755 } 1756 1757 1758 if (prev_st->bPacketBeacon) { 1759 if (slide_beacon_adc_pwdb_statistics++ >= 1760 PHY_Beacon_RSSI_SLID_WIN_MAX) { 1761 slide_beacon_adc_pwdb_statistics = 1762 PHY_Beacon_RSSI_SLID_WIN_MAX; 1763 last_beacon_adc_pwdb = priv->stats.Slide_Beacon_pwdb 1764 [slide_beacon_adc_pwdb_index]; 1765 priv->stats.Slide_Beacon_Total -= last_beacon_adc_pwdb; 1766 } 1767 priv->stats.Slide_Beacon_Total += prev_st->RxPWDBAll; 1768 priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index] = 1769 prev_st->RxPWDBAll; 1770 slide_beacon_adc_pwdb_index++; 1771 if (slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX) 1772 slide_beacon_adc_pwdb_index = 0; 1773 prev_st->RxPWDBAll = priv->stats.Slide_Beacon_Total / 1774 slide_beacon_adc_pwdb_statistics; 1775 if (prev_st->RxPWDBAll >= 3) 1776 prev_st->RxPWDBAll -= 3; 1777 } 1778 1779 RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n", 1780 prev_st->bIsCCK ? "CCK" : "OFDM", 1781 prev_st->RxPWDBAll); 1782 1783 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon || 1784 prev_st->bToSelfBA) { 1785 if (priv->undecorated_smoothed_pwdb < 0) 1786 priv->undecorated_smoothed_pwdb = prev_st->RxPWDBAll; 1787 if (prev_st->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb) { 1788 priv->undecorated_smoothed_pwdb = 1789 (((priv->undecorated_smoothed_pwdb) * 1790 (RX_SMOOTH-1)) + 1791 (prev_st->RxPWDBAll)) / (RX_SMOOTH); 1792 priv->undecorated_smoothed_pwdb = 1793 priv->undecorated_smoothed_pwdb + 1; 1794 } else { 1795 priv->undecorated_smoothed_pwdb = 1796 (((priv->undecorated_smoothed_pwdb) * 1797 (RX_SMOOTH-1)) + 1798 (prev_st->RxPWDBAll)) / (RX_SMOOTH); 1799 } 1800 rtl92e_update_rx_statistics(priv, prev_st); 1801 } 1802 1803 if (prev_st->SignalQuality != 0) { 1804 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon || 1805 prev_st->bToSelfBA) { 1806 if (slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX) { 1807 slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX; 1808 last_evm = 1809 priv->stats.slide_evm[slide_evm_index]; 1810 priv->stats.slide_evm_total -= last_evm; 1811 } 1812 1813 priv->stats.slide_evm_total += prev_st->SignalQuality; 1814 1815 priv->stats.slide_evm[slide_evm_index++] = 1816 prev_st->SignalQuality; 1817 if (slide_evm_index >= PHY_RSSI_SLID_WIN_MAX) 1818 slide_evm_index = 0; 1819 1820 tmp_val = priv->stats.slide_evm_total / 1821 slide_evm_statistics; 1822 priv->stats.signal_quality = tmp_val; 1823 priv->stats.last_signal_strength_inpercent = tmp_val; 1824 } 1825 1826 if (prev_st->bPacketToSelf || 1827 prev_st->bPacketBeacon || 1828 prev_st->bToSelfBA) { 1829 for (ij = 0; ij < 2; ij++) { 1830 if (prev_st->RxMIMOSignalQuality[ij] != -1) { 1831 if (priv->stats.rx_evm_percentage[ij] == 0) 1832 priv->stats.rx_evm_percentage[ij] = 1833 prev_st->RxMIMOSignalQuality[ij]; 1834 priv->stats.rx_evm_percentage[ij] = 1835 ((priv->stats.rx_evm_percentage[ij] * 1836 (RX_SMOOTH - 1)) + 1837 (prev_st->RxMIMOSignalQuality[ij])) / 1838 (RX_SMOOTH); 1839 } 1840 } 1841 } 1842 } 1843 } 1844 1845 static void _rtl92e_translate_rx_signal_stats(struct net_device *dev, 1846 struct sk_buff *skb, 1847 struct rtllib_rx_stats *pstats, 1848 struct rx_desc *pdesc, 1849 struct rx_fwinfo *pdrvinfo) 1850 { 1851 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); 1852 bool bpacket_match_bssid, bpacket_toself; 1853 bool bPacketBeacon = false; 1854 struct rtllib_hdr_3addr *hdr; 1855 bool bToSelfBA = false; 1856 static struct rtllib_rx_stats previous_stats; 1857 u16 fc, type; 1858 u8 *tmp_buf; 1859 u8 *praddr; 1860 1861 tmp_buf = skb->data + pstats->RxDrvInfoSize + pstats->RxBufShift; 1862 1863 hdr = (struct rtllib_hdr_3addr *)tmp_buf; 1864 fc = le16_to_cpu(hdr->frame_ctl); 1865 type = WLAN_FC_GET_TYPE(fc); 1866 praddr = hdr->addr1; 1867 1868 bpacket_match_bssid = 1869 ((type != RTLLIB_FTYPE_CTL) && 1870 ether_addr_equal(priv->rtllib->current_network.bssid, 1871 (fc & RTLLIB_FCTL_TODS) ? hdr->addr1 : 1872 (fc & RTLLIB_FCTL_FROMDS) ? hdr->addr2 : 1873 hdr->addr3) && 1874 (!pstats->bHwError) && (!pstats->bCRC) && (!pstats->bICV)); 1875 bpacket_toself = bpacket_match_bssid && /* check this */ 1876 ether_addr_equal(praddr, priv->rtllib->dev->dev_addr); 1877 if (WLAN_FC_GET_FRAMETYPE(fc) == RTLLIB_STYPE_BEACON) 1878 bPacketBeacon = true; 1879 if (bpacket_match_bssid) 1880 priv->stats.numpacket_matchbssid++; 1881 if (bpacket_toself) 1882 priv->stats.numpacket_toself++; 1883 _rtl92e_process_phyinfo(priv, tmp_buf, &previous_stats, pstats); 1884 _rtl92e_query_rxphystatus(priv, pstats, pdesc, pdrvinfo, 1885 &previous_stats, bpacket_match_bssid, 1886 bpacket_toself, bPacketBeacon, bToSelfBA); 1887 rtl92e_copy_mpdu_stats(pstats, &previous_stats); 1888 } 1889 1890 static void _rtl92e_update_received_rate_histogram_stats( 1891 struct net_device *dev, 1892 struct rtllib_rx_stats *pstats) 1893 { 1894 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); 1895 u32 rcvType = 1; 1896 u32 rateIndex; 1897 u32 preamble_guardinterval; 1898 1899 if (pstats->bCRC) 1900 rcvType = 2; 1901 else if (pstats->bICV) 1902 rcvType = 3; 1903 1904 if (pstats->bShortPreamble) 1905 preamble_guardinterval = 1; 1906 else 1907 preamble_guardinterval = 0; 1908 1909 switch (pstats->rate) { 1910 case MGN_1M: 1911 rateIndex = 0; 1912 break; 1913 case MGN_2M: 1914 rateIndex = 1; 1915 break; 1916 case MGN_5_5M: 1917 rateIndex = 2; 1918 break; 1919 case MGN_11M: 1920 rateIndex = 3; 1921 break; 1922 case MGN_6M: 1923 rateIndex = 4; 1924 break; 1925 case MGN_9M: 1926 rateIndex = 5; 1927 break; 1928 case MGN_12M: 1929 rateIndex = 6; 1930 break; 1931 case MGN_18M: 1932 rateIndex = 7; 1933 break; 1934 case MGN_24M: 1935 rateIndex = 8; 1936 break; 1937 case MGN_36M: 1938 rateIndex = 9; 1939 break; 1940 case MGN_48M: 1941 rateIndex = 10; 1942 break; 1943 case MGN_54M: 1944 rateIndex = 11; 1945 break; 1946 case MGN_MCS0: 1947 rateIndex = 12; 1948 break; 1949 case MGN_MCS1: 1950 rateIndex = 13; 1951 break; 1952 case MGN_MCS2: 1953 rateIndex = 14; 1954 break; 1955 case MGN_MCS3: 1956 rateIndex = 15; 1957 break; 1958 case MGN_MCS4: 1959 rateIndex = 16; 1960 break; 1961 case MGN_MCS5: 1962 rateIndex = 17; 1963 break; 1964 case MGN_MCS6: 1965 rateIndex = 18; 1966 break; 1967 case MGN_MCS7: 1968 rateIndex = 19; 1969 break; 1970 case MGN_MCS8: 1971 rateIndex = 20; 1972 break; 1973 case MGN_MCS9: 1974 rateIndex = 21; 1975 break; 1976 case MGN_MCS10: 1977 rateIndex = 22; 1978 break; 1979 case MGN_MCS11: 1980 rateIndex = 23; 1981 break; 1982 case MGN_MCS12: 1983 rateIndex = 24; 1984 break; 1985 case MGN_MCS13: 1986 rateIndex = 25; 1987 break; 1988 case MGN_MCS14: 1989 rateIndex = 26; 1990 break; 1991 case MGN_MCS15: 1992 rateIndex = 27; 1993 break; 1994 default: 1995 rateIndex = 28; 1996 break; 1997 } 1998 priv->stats.received_preamble_GI[preamble_guardinterval][rateIndex]++; 1999 priv->stats.received_rate_histogram[0][rateIndex]++; 2000 priv->stats.received_rate_histogram[rcvType][rateIndex]++; 2001 } 2002 2003 bool rtl92e_get_rx_stats(struct net_device *dev, struct rtllib_rx_stats *stats, 2004 struct rx_desc *pdesc, struct sk_buff *skb) 2005 { 2006 struct r8192_priv *priv = rtllib_priv(dev); 2007 struct rx_fwinfo *pDrvInfo = NULL; 2008 2009 stats->bICV = pdesc->ICV; 2010 stats->bCRC = pdesc->CRC32; 2011 stats->bHwError = pdesc->CRC32 | pdesc->ICV; 2012 2013 stats->Length = pdesc->Length; 2014 if (stats->Length < 24) 2015 stats->bHwError |= 1; 2016 2017 if (stats->bHwError) { 2018 stats->bShift = false; 2019 2020 if (pdesc->CRC32) { 2021 if (pdesc->Length < 500) 2022 priv->stats.rxcrcerrmin++; 2023 else if (pdesc->Length > 1000) 2024 priv->stats.rxcrcerrmax++; 2025 else 2026 priv->stats.rxcrcerrmid++; 2027 } 2028 return false; 2029 } 2030 2031 stats->RxDrvInfoSize = pdesc->RxDrvInfoSize; 2032 stats->RxBufShift = (pdesc->Shift) & 0x03; 2033 stats->Decrypted = !pdesc->SWDec; 2034 2035 pDrvInfo = (struct rx_fwinfo *)(skb->data + stats->RxBufShift); 2036 2037 stats->rate = _rtl92e_rate_hw_to_mgn((bool)pDrvInfo->RxHT, 2038 (u8)pDrvInfo->RxRate); 2039 stats->bShortPreamble = pDrvInfo->SPLCP; 2040 2041 _rtl92e_update_received_rate_histogram_stats(dev, stats); 2042 2043 stats->bIsAMPDU = (pDrvInfo->PartAggr == 1); 2044 stats->bFirstMPDU = (pDrvInfo->PartAggr == 1) && 2045 (pDrvInfo->FirstAGGR == 1); 2046 2047 stats->TimeStampLow = pDrvInfo->TSFL; 2048 stats->TimeStampHigh = rtl92e_readl(dev, TSFR+4); 2049 2050 rtl92e_update_rx_pkt_timestamp(dev, stats); 2051 2052 if ((stats->RxBufShift + stats->RxDrvInfoSize) > 0) 2053 stats->bShift = 1; 2054 2055 stats->RxIs40MHzPacket = pDrvInfo->BW; 2056 2057 _rtl92e_translate_rx_signal_stats(dev, skb, stats, pdesc, pDrvInfo); 2058 2059 if (pDrvInfo->FirstAGGR == 1 || pDrvInfo->PartAggr == 1) 2060 RT_TRACE(COMP_RXDESC, 2061 "pDrvInfo->FirstAGGR = %d, pDrvInfo->PartAggr = %d\n", 2062 pDrvInfo->FirstAGGR, pDrvInfo->PartAggr); 2063 skb_trim(skb, skb->len - 4/*sCrcLng*/); 2064 2065 2066 stats->packetlength = stats->Length-4; 2067 stats->fraglength = stats->packetlength; 2068 stats->fragoffset = 0; 2069 stats->ntotalfrag = 1; 2070 return true; 2071 } 2072 2073 void rtl92e_stop_adapter(struct net_device *dev, bool reset) 2074 { 2075 struct r8192_priv *priv = rtllib_priv(dev); 2076 int i; 2077 u8 OpMode; 2078 u8 u1bTmp; 2079 u32 ulRegRead; 2080 2081 OpMode = RT_OP_MODE_NO_LINK; 2082 priv->rtllib->SetHwRegHandler(dev, HW_VAR_MEDIA_STATUS, &OpMode); 2083 2084 if (!priv->rtllib->bSupportRemoteWakeUp) { 2085 u1bTmp = 0x0; 2086 rtl92e_writeb(dev, CMDR, u1bTmp); 2087 } 2088 2089 mdelay(20); 2090 2091 if (!reset) { 2092 mdelay(150); 2093 2094 priv->bHwRfOffAction = 2; 2095 2096 if (!priv->rtllib->bSupportRemoteWakeUp) { 2097 rtl92e_set_rf_off(dev); 2098 ulRegRead = rtl92e_readl(dev, CPU_GEN); 2099 ulRegRead |= CPU_GEN_SYSTEM_RESET; 2100 rtl92e_writel(dev, CPU_GEN, ulRegRead); 2101 } else { 2102 rtl92e_writel(dev, WFCRC0, 0xffffffff); 2103 rtl92e_writel(dev, WFCRC1, 0xffffffff); 2104 rtl92e_writel(dev, WFCRC2, 0xffffffff); 2105 2106 2107 rtl92e_writeb(dev, PMR, 0x5); 2108 rtl92e_writeb(dev, MacBlkCtrl, 0xa); 2109 } 2110 } 2111 2112 for (i = 0; i < MAX_QUEUE_SIZE; i++) 2113 skb_queue_purge(&priv->rtllib->skb_waitQ[i]); 2114 for (i = 0; i < MAX_QUEUE_SIZE; i++) 2115 skb_queue_purge(&priv->rtllib->skb_aggQ[i]); 2116 2117 skb_queue_purge(&priv->skb_queue); 2118 } 2119 2120 void rtl92e_update_ratr_table(struct net_device *dev) 2121 { 2122 struct r8192_priv *priv = rtllib_priv(dev); 2123 struct rtllib_device *ieee = priv->rtllib; 2124 u8 *pMcsRate = ieee->dot11HTOperationalRateSet; 2125 u32 ratr_value = 0; 2126 u16 rate_config = 0; 2127 u8 rate_index = 0; 2128 2129 rtl92e_config_rate(dev, &rate_config); 2130 ratr_value = rate_config | *pMcsRate << 12; 2131 switch (ieee->mode) { 2132 case IEEE_A: 2133 ratr_value &= 0x00000FF0; 2134 break; 2135 case IEEE_B: 2136 ratr_value &= 0x0000000F; 2137 break; 2138 case IEEE_G: 2139 case IEEE_G|IEEE_B: 2140 ratr_value &= 0x00000FF7; 2141 break; 2142 case IEEE_N_24G: 2143 case IEEE_N_5G: 2144 if (ieee->pHTInfo->PeerMimoPs == 0) { 2145 ratr_value &= 0x0007F007; 2146 } else { 2147 if (priv->rf_type == RF_1T2R) 2148 ratr_value &= 0x000FF007; 2149 else 2150 ratr_value &= 0x0F81F007; 2151 } 2152 break; 2153 default: 2154 break; 2155 } 2156 ratr_value &= 0x0FFFFFFF; 2157 if (ieee->pHTInfo->bCurTxBW40MHz && 2158 ieee->pHTInfo->bCurShortGI40MHz) 2159 ratr_value |= 0x80000000; 2160 else if (!ieee->pHTInfo->bCurTxBW40MHz && 2161 ieee->pHTInfo->bCurShortGI20MHz) 2162 ratr_value |= 0x80000000; 2163 rtl92e_writel(dev, RATR0+rate_index*4, ratr_value); 2164 rtl92e_writeb(dev, UFWP, 1); 2165 } 2166 2167 void 2168 rtl92e_init_variables(struct net_device *dev) 2169 { 2170 struct r8192_priv *priv = rtllib_priv(dev); 2171 2172 strcpy(priv->nick, "rtl8192E"); 2173 2174 priv->rtllib->softmac_features = IEEE_SOFTMAC_SCAN | 2175 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ | 2176 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE; 2177 2178 priv->rtllib->tx_headroom = sizeof(struct tx_fwinfo_8190pci); 2179 2180 priv->ShortRetryLimit = 0x30; 2181 priv->LongRetryLimit = 0x30; 2182 2183 priv->ReceiveConfig = RCR_ADD3 | 2184 RCR_AMF | RCR_ADF | 2185 RCR_AICV | 2186 RCR_AB | RCR_AM | RCR_APM | 2187 RCR_AAP | ((u32)7<<RCR_MXDMA_OFFSET) | 2188 ((u32)7 << RCR_FIFO_OFFSET) | RCR_ONLYERLPKT; 2189 2190 priv->irq_mask[0] = (u32)(IMR_ROK | IMR_VODOK | IMR_VIDOK | 2191 IMR_BEDOK | IMR_BKDOK | IMR_HCCADOK | 2192 IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK | 2193 IMR_BDOK | IMR_RXCMDOK | IMR_TIMEOUT0 | 2194 IMR_RDU | IMR_RXFOVW | IMR_TXFOVW | 2195 IMR_BcnInt | IMR_TBDOK | IMR_TBDER); 2196 2197 priv->PwrDomainProtect = false; 2198 2199 priv->bfirst_after_down = false; 2200 } 2201 2202 void rtl92e_enable_irq(struct net_device *dev) 2203 { 2204 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); 2205 2206 priv->irq_enabled = 1; 2207 2208 rtl92e_writel(dev, INTA_MASK, priv->irq_mask[0]); 2209 2210 } 2211 2212 void rtl92e_disable_irq(struct net_device *dev) 2213 { 2214 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); 2215 2216 rtl92e_writel(dev, INTA_MASK, 0); 2217 2218 priv->irq_enabled = 0; 2219 } 2220 2221 void rtl92e_clear_irq(struct net_device *dev) 2222 { 2223 u32 tmp; 2224 2225 tmp = rtl92e_readl(dev, ISR); 2226 rtl92e_writel(dev, ISR, tmp); 2227 } 2228 2229 2230 void rtl92e_enable_rx(struct net_device *dev) 2231 { 2232 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); 2233 2234 rtl92e_writel(dev, RDQDA, priv->rx_ring_dma[RX_MPDU_QUEUE]); 2235 } 2236 2237 static const u32 TX_DESC_BASE[] = { 2238 BKQDA, BEQDA, VIQDA, VOQDA, HCCAQDA, CQDA, MQDA, HQDA, BQDA 2239 }; 2240 2241 void rtl92e_enable_tx(struct net_device *dev) 2242 { 2243 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); 2244 u32 i; 2245 2246 for (i = 0; i < MAX_TX_QUEUE_COUNT; i++) 2247 rtl92e_writel(dev, TX_DESC_BASE[i], priv->tx_ring[i].dma); 2248 } 2249 2250 2251 void rtl92e_ack_irq(struct net_device *dev, u32 *p_inta, u32 *p_intb) 2252 { 2253 *p_inta = rtl92e_readl(dev, ISR); 2254 rtl92e_writel(dev, ISR, *p_inta); 2255 } 2256 2257 bool rtl92e_is_rx_stuck(struct net_device *dev) 2258 { 2259 struct r8192_priv *priv = rtllib_priv(dev); 2260 u16 RegRxCounter = rtl92e_readw(dev, 0x130); 2261 bool bStuck = false; 2262 static u8 rx_chk_cnt; 2263 u32 SlotIndex = 0, TotalRxStuckCount = 0; 2264 u8 i; 2265 u8 SilentResetRxSoltNum = 4; 2266 2267 RT_TRACE(COMP_RESET, "%s(): RegRxCounter is %d, RxCounter is %d\n", 2268 __func__, RegRxCounter, priv->RxCounter); 2269 2270 rx_chk_cnt++; 2271 if (priv->undecorated_smoothed_pwdb >= (RateAdaptiveTH_High+5)) { 2272 rx_chk_cnt = 0; 2273 } else if ((priv->undecorated_smoothed_pwdb < (RateAdaptiveTH_High + 5)) 2274 && (((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) && 2275 (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_40M)) 2276 || ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) && 2277 (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_20M)))) { 2278 if (rx_chk_cnt < 2) 2279 return bStuck; 2280 rx_chk_cnt = 0; 2281 } else if ((((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) && 2282 (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_40M)) || 2283 ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) && 2284 (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_20M))) && 2285 priv->undecorated_smoothed_pwdb >= VeryLowRSSI) { 2286 if (rx_chk_cnt < 4) 2287 return bStuck; 2288 rx_chk_cnt = 0; 2289 } else { 2290 if (rx_chk_cnt < 8) 2291 return bStuck; 2292 rx_chk_cnt = 0; 2293 } 2294 2295 2296 SlotIndex = (priv->SilentResetRxSlotIndex++)%SilentResetRxSoltNum; 2297 2298 if (priv->RxCounter == RegRxCounter) { 2299 priv->SilentResetRxStuckEvent[SlotIndex] = 1; 2300 2301 for (i = 0; i < SilentResetRxSoltNum; i++) 2302 TotalRxStuckCount += priv->SilentResetRxStuckEvent[i]; 2303 2304 if (TotalRxStuckCount == SilentResetRxSoltNum) { 2305 bStuck = true; 2306 for (i = 0; i < SilentResetRxSoltNum; i++) 2307 TotalRxStuckCount += 2308 priv->SilentResetRxStuckEvent[i]; 2309 } 2310 2311 2312 } else { 2313 priv->SilentResetRxStuckEvent[SlotIndex] = 0; 2314 } 2315 2316 priv->RxCounter = RegRxCounter; 2317 2318 return bStuck; 2319 } 2320 2321 bool rtl92e_is_tx_stuck(struct net_device *dev) 2322 { 2323 struct r8192_priv *priv = rtllib_priv(dev); 2324 bool bStuck = false; 2325 u16 RegTxCounter = rtl92e_readw(dev, 0x128); 2326 2327 RT_TRACE(COMP_RESET, "%s():RegTxCounter is %d,TxCounter is %d\n", 2328 __func__, RegTxCounter, priv->TxCounter); 2329 2330 if (priv->TxCounter == RegTxCounter) 2331 bStuck = true; 2332 2333 priv->TxCounter = RegTxCounter; 2334 2335 return bStuck; 2336 } 2337 2338 bool rtl92e_get_nmode_support_by_sec(struct net_device *dev) 2339 { 2340 struct r8192_priv *priv = rtllib_priv(dev); 2341 struct rtllib_device *ieee = priv->rtllib; 2342 2343 if (ieee->rtllib_ap_sec_type && 2344 (ieee->rtllib_ap_sec_type(priv->rtllib)&(SEC_ALG_WEP | 2345 SEC_ALG_TKIP))) { 2346 return false; 2347 } else { 2348 return true; 2349 } 2350 } 2351 2352 bool rtl92e_is_halfn_supported_by_ap(struct net_device *dev) 2353 { 2354 struct r8192_priv *priv = rtllib_priv(dev); 2355 struct rtllib_device *ieee = priv->rtllib; 2356 2357 return ieee->bHalfWirelessN24GMode; 2358 } 2359