1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. 4 * 5 * Contact Information: wlanfae <wlanfae@realtek.com> 6 */ 7 #include <linux/bitops.h> 8 #include "rtl_core.h" 9 #include "r8192E_hw.h" 10 #include "r8192E_phyreg.h" 11 #include "r8190P_rtl8256.h" 12 #include "r8192E_phy.h" 13 #include "rtl_dm.h" 14 15 #include "r8192E_hwimg.h" 16 17 static u32 RF_CHANNEL_TABLE_ZEBRA[] = { 18 0, 19 0x085c, 20 0x08dc, 21 0x095c, 22 0x09dc, 23 0x0a5c, 24 0x0adc, 25 0x0b5c, 26 0x0bdc, 27 0x0c5c, 28 0x0cdc, 29 0x0d5c, 30 0x0ddc, 31 0x0e5c, 32 0x0f72, 33 }; 34 35 /*************************Define local function prototype**********************/ 36 37 static u32 _rtl92e_phy_rf_fw_read(struct net_device *dev, 38 enum rf90_radio_path eRFPath, u32 Offset); 39 static void _rtl92e_phy_rf_fw_write(struct net_device *dev, 40 enum rf90_radio_path eRFPath, u32 Offset, 41 u32 Data); 42 43 static u32 _rtl92e_calculate_bit_shift(u32 dwBitMask) 44 { 45 if (!dwBitMask) 46 return 32; 47 return ffs(dwBitMask) - 1; 48 } 49 50 u8 rtl92e_is_legal_rf_path(struct net_device *dev, u32 eRFPath) 51 { 52 u8 ret = 1; 53 struct r8192_priv *priv = rtllib_priv(dev); 54 55 if (priv->rf_type == RF_2T4R) 56 ret = 0; 57 else if (priv->rf_type == RF_1T2R) { 58 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) 59 ret = 1; 60 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) 61 ret = 0; 62 } 63 return ret; 64 } 65 66 void rtl92e_set_bb_reg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask, 67 u32 dwData) 68 { 69 70 u32 OriginalValue, BitShift, NewValue; 71 72 if (dwBitMask != bMaskDWord) { 73 OriginalValue = rtl92e_readl(dev, dwRegAddr); 74 BitShift = _rtl92e_calculate_bit_shift(dwBitMask); 75 NewValue = (OriginalValue & ~dwBitMask) | (dwData << BitShift); 76 rtl92e_writel(dev, dwRegAddr, NewValue); 77 } else 78 rtl92e_writel(dev, dwRegAddr, dwData); 79 } 80 81 u32 rtl92e_get_bb_reg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask) 82 { 83 u32 OriginalValue, BitShift; 84 85 OriginalValue = rtl92e_readl(dev, dwRegAddr); 86 BitShift = _rtl92e_calculate_bit_shift(dwBitMask); 87 88 return (OriginalValue & dwBitMask) >> BitShift; 89 } 90 91 static u32 _rtl92e_phy_rf_read(struct net_device *dev, 92 enum rf90_radio_path eRFPath, u32 Offset) 93 { 94 struct r8192_priv *priv = rtllib_priv(dev); 95 u32 ret = 0; 96 u32 NewOffset = 0; 97 struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath]; 98 99 Offset &= 0x3f; 100 101 if (priv->rf_chip == RF_8256) { 102 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); 103 if (Offset >= 31) { 104 priv->RfReg0Value[eRFPath] |= 0x140; 105 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, 106 bMaskDWord, 107 (priv->RfReg0Value[eRFPath]<<16)); 108 NewOffset = Offset - 30; 109 } else if (Offset >= 16) { 110 priv->RfReg0Value[eRFPath] |= 0x100; 111 priv->RfReg0Value[eRFPath] &= (~0x40); 112 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, 113 bMaskDWord, 114 (priv->RfReg0Value[eRFPath]<<16)); 115 116 NewOffset = Offset - 15; 117 } else 118 NewOffset = Offset; 119 } else { 120 RT_TRACE((COMP_PHY|COMP_ERR), 121 "check RF type here, need to be 8256\n"); 122 NewOffset = Offset; 123 } 124 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, 125 NewOffset); 126 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); 127 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); 128 129 mdelay(1); 130 131 ret = rtl92e_get_bb_reg(dev, pPhyReg->rfLSSIReadBack, 132 bLSSIReadBackData); 133 134 if (priv->rf_chip == RF_8256) { 135 priv->RfReg0Value[eRFPath] &= 0xebf; 136 137 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, 138 (priv->RfReg0Value[eRFPath] << 16)); 139 140 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); 141 } 142 143 144 return ret; 145 146 } 147 148 static void _rtl92e_phy_rf_write(struct net_device *dev, 149 enum rf90_radio_path eRFPath, u32 Offset, 150 u32 Data) 151 { 152 struct r8192_priv *priv = rtllib_priv(dev); 153 u32 DataAndAddr = 0, NewOffset = 0; 154 struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath]; 155 156 Offset &= 0x3f; 157 if (priv->rf_chip == RF_8256) { 158 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); 159 160 if (Offset >= 31) { 161 priv->RfReg0Value[eRFPath] |= 0x140; 162 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, 163 bMaskDWord, 164 (priv->RfReg0Value[eRFPath] << 16)); 165 NewOffset = Offset - 30; 166 } else if (Offset >= 16) { 167 priv->RfReg0Value[eRFPath] |= 0x100; 168 priv->RfReg0Value[eRFPath] &= (~0x40); 169 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, 170 bMaskDWord, 171 (priv->RfReg0Value[eRFPath] << 16)); 172 NewOffset = Offset - 15; 173 } else 174 NewOffset = Offset; 175 } else { 176 RT_TRACE((COMP_PHY|COMP_ERR), 177 "check RF type here, need to be 8256\n"); 178 NewOffset = Offset; 179 } 180 181 DataAndAddr = (NewOffset & 0x3f) | (Data << 16); 182 183 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); 184 185 if (Offset == 0x0) 186 priv->RfReg0Value[eRFPath] = Data; 187 188 if (priv->rf_chip == RF_8256) { 189 if (Offset != 0) { 190 priv->RfReg0Value[eRFPath] &= 0xebf; 191 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, 192 bMaskDWord, 193 (priv->RfReg0Value[eRFPath] << 16)); 194 } 195 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); 196 } 197 } 198 199 void rtl92e_set_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath, 200 u32 RegAddr, u32 BitMask, u32 Data) 201 { 202 struct r8192_priv *priv = rtllib_priv(dev); 203 u32 Original_Value, BitShift, New_Value; 204 205 if (!rtl92e_is_legal_rf_path(dev, eRFPath)) 206 return; 207 if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter) 208 return; 209 210 RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n"); 211 if (priv->Rf_Mode == RF_OP_By_FW) { 212 if (BitMask != bMask12Bits) { 213 Original_Value = _rtl92e_phy_rf_fw_read(dev, eRFPath, 214 RegAddr); 215 BitShift = _rtl92e_calculate_bit_shift(BitMask); 216 New_Value = (Original_Value & ~BitMask) | (Data << BitShift); 217 218 _rtl92e_phy_rf_fw_write(dev, eRFPath, RegAddr, 219 New_Value); 220 } else 221 _rtl92e_phy_rf_fw_write(dev, eRFPath, RegAddr, Data); 222 udelay(200); 223 224 } else { 225 if (BitMask != bMask12Bits) { 226 Original_Value = _rtl92e_phy_rf_read(dev, eRFPath, 227 RegAddr); 228 BitShift = _rtl92e_calculate_bit_shift(BitMask); 229 New_Value = (Original_Value & ~BitMask) | (Data << BitShift); 230 231 _rtl92e_phy_rf_write(dev, eRFPath, RegAddr, New_Value); 232 } else 233 _rtl92e_phy_rf_write(dev, eRFPath, RegAddr, Data); 234 } 235 } 236 237 u32 rtl92e_get_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath, 238 u32 RegAddr, u32 BitMask) 239 { 240 u32 Original_Value, Readback_Value, BitShift; 241 struct r8192_priv *priv = rtllib_priv(dev); 242 243 if (!rtl92e_is_legal_rf_path(dev, eRFPath)) 244 return 0; 245 if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter) 246 return 0; 247 mutex_lock(&priv->rf_mutex); 248 if (priv->Rf_Mode == RF_OP_By_FW) { 249 Original_Value = _rtl92e_phy_rf_fw_read(dev, eRFPath, RegAddr); 250 udelay(200); 251 } else { 252 Original_Value = _rtl92e_phy_rf_read(dev, eRFPath, RegAddr); 253 } 254 BitShift = _rtl92e_calculate_bit_shift(BitMask); 255 Readback_Value = (Original_Value & BitMask) >> BitShift; 256 mutex_unlock(&priv->rf_mutex); 257 return Readback_Value; 258 } 259 260 static u32 _rtl92e_phy_rf_fw_read(struct net_device *dev, 261 enum rf90_radio_path eRFPath, u32 Offset) 262 { 263 u32 Data = 0; 264 u8 time = 0; 265 266 Data |= ((Offset & 0xFF) << 12); 267 Data |= ((eRFPath & 0x3) << 20); 268 Data |= 0x80000000; 269 while (rtl92e_readl(dev, QPNR) & 0x80000000) { 270 if (time++ < 100) 271 udelay(10); 272 else 273 break; 274 } 275 rtl92e_writel(dev, QPNR, Data); 276 while (rtl92e_readl(dev, QPNR) & 0x80000000) { 277 if (time++ < 100) 278 udelay(10); 279 else 280 return 0; 281 } 282 return rtl92e_readl(dev, RF_DATA); 283 284 } 285 286 static void _rtl92e_phy_rf_fw_write(struct net_device *dev, 287 enum rf90_radio_path eRFPath, u32 Offset, 288 u32 Data) 289 { 290 u8 time = 0; 291 292 Data |= ((Offset & 0xFF) << 12); 293 Data |= ((eRFPath & 0x3) << 20); 294 Data |= 0x400000; 295 Data |= 0x80000000; 296 297 while (rtl92e_readl(dev, QPNR) & 0x80000000) { 298 if (time++ < 100) 299 udelay(10); 300 else 301 break; 302 } 303 rtl92e_writel(dev, QPNR, Data); 304 305 } 306 307 308 void rtl92e_config_mac(struct net_device *dev) 309 { 310 u32 dwArrayLen = 0, i = 0; 311 u32 *pdwArray = NULL; 312 struct r8192_priv *priv = rtllib_priv(dev); 313 314 if (priv->bTXPowerDataReadFromEEPORM) { 315 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n"); 316 dwArrayLen = MACPHY_Array_PGLength; 317 pdwArray = Rtl819XMACPHY_Array_PG; 318 319 } else { 320 RT_TRACE(COMP_PHY, "Read rtl819XMACPHY_Array\n"); 321 dwArrayLen = MACPHY_ArrayLength; 322 pdwArray = Rtl819XMACPHY_Array; 323 } 324 for (i = 0; i < dwArrayLen; i += 3) { 325 RT_TRACE(COMP_DBG, 326 "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n", 327 pdwArray[i], pdwArray[i+1], pdwArray[i+2]); 328 if (pdwArray[i] == 0x318) 329 pdwArray[i+2] = 0x00000800; 330 rtl92e_set_bb_reg(dev, pdwArray[i], pdwArray[i+1], 331 pdwArray[i+2]); 332 } 333 return; 334 335 } 336 337 static void _rtl92e_phy_config_bb(struct net_device *dev, u8 ConfigType) 338 { 339 int i; 340 u32 *Rtl819XPHY_REGArray_Table = NULL; 341 u32 *Rtl819XAGCTAB_Array_Table = NULL; 342 u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0; 343 struct r8192_priv *priv = rtllib_priv(dev); 344 345 AGCTAB_ArrayLen = AGCTAB_ArrayLength; 346 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array; 347 if (priv->rf_type == RF_2T4R) { 348 PHY_REGArrayLen = PHY_REGArrayLength; 349 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray; 350 } else if (priv->rf_type == RF_1T2R) { 351 PHY_REGArrayLen = PHY_REG_1T2RArrayLength; 352 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray; 353 } 354 355 if (ConfigType == BaseBand_Config_PHY_REG) { 356 for (i = 0; i < PHY_REGArrayLen; i += 2) { 357 rtl92e_set_bb_reg(dev, Rtl819XPHY_REGArray_Table[i], 358 bMaskDWord, 359 Rtl819XPHY_REGArray_Table[i+1]); 360 RT_TRACE(COMP_DBG, 361 "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x\n", 362 i, Rtl819XPHY_REGArray_Table[i], 363 Rtl819XPHY_REGArray_Table[i+1]); 364 } 365 } else if (ConfigType == BaseBand_Config_AGC_TAB) { 366 for (i = 0; i < AGCTAB_ArrayLen; i += 2) { 367 rtl92e_set_bb_reg(dev, Rtl819XAGCTAB_Array_Table[i], 368 bMaskDWord, 369 Rtl819XAGCTAB_Array_Table[i+1]); 370 RT_TRACE(COMP_DBG, 371 "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x\n", 372 i, Rtl819XAGCTAB_Array_Table[i], 373 Rtl819XAGCTAB_Array_Table[i+1]); 374 } 375 } 376 } 377 378 static void _rtl92e_init_bb_rf_reg_def(struct net_device *dev) 379 { 380 struct r8192_priv *priv = rtllib_priv(dev); 381 382 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; 383 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; 384 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; 385 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW; 386 387 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; 388 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB; 389 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB; 390 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB; 391 392 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; 393 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; 394 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE; 395 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE; 396 397 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; 398 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; 399 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE; 400 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE; 401 402 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; 403 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; 404 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; 405 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; 406 407 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; 408 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; 409 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; 410 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; 411 412 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; 413 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; 414 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; 415 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; 416 417 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; 418 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; 419 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; 420 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; 421 422 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; 423 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; 424 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; 425 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; 426 427 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; 428 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; 429 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; 430 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; 431 432 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; 433 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; 434 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; 435 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; 436 437 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; 438 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; 439 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; 440 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; 441 442 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; 443 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; 444 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; 445 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; 446 447 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; 448 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; 449 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; 450 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; 451 452 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; 453 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; 454 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; 455 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; 456 457 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; 458 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; 459 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; 460 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; 461 462 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; 463 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; 464 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; 465 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; 466 467 } 468 469 bool rtl92e_check_bb_and_rf(struct net_device *dev, enum hw90_block CheckBlock, 470 enum rf90_radio_path eRFPath) 471 { 472 bool ret = true; 473 u32 i, CheckTimes = 4, dwRegRead = 0; 474 u32 WriteAddr[4]; 475 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f}; 476 477 WriteAddr[HW90_BLOCK_MAC] = 0x100; 478 WriteAddr[HW90_BLOCK_PHY0] = 0x900; 479 WriteAddr[HW90_BLOCK_PHY1] = 0x800; 480 WriteAddr[HW90_BLOCK_RF] = 0x3; 481 RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __func__, 482 CheckBlock); 483 484 if (CheckBlock == HW90_BLOCK_MAC) { 485 netdev_warn(dev, "%s(): No checks available for MAC block.\n", 486 __func__); 487 return ret; 488 } 489 490 for (i = 0; i < CheckTimes; i++) { 491 switch (CheckBlock) { 492 case HW90_BLOCK_PHY0: 493 case HW90_BLOCK_PHY1: 494 rtl92e_writel(dev, WriteAddr[CheckBlock], 495 WriteData[i]); 496 dwRegRead = rtl92e_readl(dev, WriteAddr[CheckBlock]); 497 break; 498 499 case HW90_BLOCK_RF: 500 WriteData[i] &= 0xfff; 501 rtl92e_set_rf_reg(dev, eRFPath, 502 WriteAddr[HW90_BLOCK_RF], 503 bMask12Bits, WriteData[i]); 504 mdelay(10); 505 dwRegRead = rtl92e_get_rf_reg(dev, eRFPath, 506 WriteAddr[HW90_BLOCK_RF], 507 bMaskDWord); 508 mdelay(10); 509 break; 510 511 default: 512 ret = false; 513 break; 514 } 515 516 517 if (dwRegRead != WriteData[i]) { 518 netdev_warn(dev, "%s(): Check failed.\n", __func__); 519 ret = false; 520 break; 521 } 522 } 523 524 return ret; 525 } 526 527 static bool _rtl92e_bb_config_para_file(struct net_device *dev) 528 { 529 struct r8192_priv *priv = rtllib_priv(dev); 530 bool rtStatus = true; 531 u8 bRegValue = 0, eCheckItem = 0; 532 u32 dwRegValue = 0; 533 534 bRegValue = rtl92e_readb(dev, BB_GLOBAL_RESET); 535 rtl92e_writeb(dev, BB_GLOBAL_RESET, (bRegValue|BB_GLOBAL_RESET_BIT)); 536 537 dwRegValue = rtl92e_readl(dev, CPU_GEN); 538 rtl92e_writel(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST))); 539 540 for (eCheckItem = (enum hw90_block)HW90_BLOCK_PHY0; 541 eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) { 542 rtStatus = rtl92e_check_bb_and_rf(dev, 543 (enum hw90_block)eCheckItem, 544 (enum rf90_radio_path)0); 545 if (!rtStatus) { 546 RT_TRACE((COMP_ERR | COMP_PHY), 547 "rtl92e_config_rf():Check PHY%d Fail!!\n", 548 eCheckItem-1); 549 return rtStatus; 550 } 551 } 552 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); 553 _rtl92e_phy_config_bb(dev, BaseBand_Config_PHY_REG); 554 555 dwRegValue = rtl92e_readl(dev, CPU_GEN); 556 rtl92e_writel(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST)); 557 558 _rtl92e_phy_config_bb(dev, BaseBand_Config_AGC_TAB); 559 560 if (priv->IC_Cut > VERSION_8190_BD) { 561 if (priv->rf_type == RF_2T4R) 562 dwRegValue = priv->AntennaTxPwDiff[2]<<8 | 563 priv->AntennaTxPwDiff[1]<<4 | 564 priv->AntennaTxPwDiff[0]; 565 else 566 dwRegValue = 0x0; 567 rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage, 568 (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue); 569 570 571 dwRegValue = priv->CrystalCap; 572 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, 573 dwRegValue); 574 } 575 576 return rtStatus; 577 } 578 bool rtl92e_config_bb(struct net_device *dev) 579 { 580 _rtl92e_init_bb_rf_reg_def(dev); 581 return _rtl92e_bb_config_para_file(dev); 582 } 583 584 void rtl92e_get_tx_power(struct net_device *dev) 585 { 586 struct r8192_priv *priv = rtllib_priv(dev); 587 588 priv->MCSTxPowerLevelOriginalOffset[0] = 589 rtl92e_readl(dev, rTxAGC_Rate18_06); 590 priv->MCSTxPowerLevelOriginalOffset[1] = 591 rtl92e_readl(dev, rTxAGC_Rate54_24); 592 priv->MCSTxPowerLevelOriginalOffset[2] = 593 rtl92e_readl(dev, rTxAGC_Mcs03_Mcs00); 594 priv->MCSTxPowerLevelOriginalOffset[3] = 595 rtl92e_readl(dev, rTxAGC_Mcs07_Mcs04); 596 priv->MCSTxPowerLevelOriginalOffset[4] = 597 rtl92e_readl(dev, rTxAGC_Mcs11_Mcs08); 598 priv->MCSTxPowerLevelOriginalOffset[5] = 599 rtl92e_readl(dev, rTxAGC_Mcs15_Mcs12); 600 601 priv->DefaultInitialGain[0] = rtl92e_readb(dev, rOFDM0_XAAGCCore1); 602 priv->DefaultInitialGain[1] = rtl92e_readb(dev, rOFDM0_XBAGCCore1); 603 priv->DefaultInitialGain[2] = rtl92e_readb(dev, rOFDM0_XCAGCCore1); 604 priv->DefaultInitialGain[3] = rtl92e_readb(dev, rOFDM0_XDAGCCore1); 605 RT_TRACE(COMP_INIT, 606 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n", 607 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1], 608 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]); 609 610 priv->framesync = rtl92e_readb(dev, rOFDM0_RxDetector3); 611 priv->framesyncC34 = rtl92e_readl(dev, rOFDM0_RxDetector2); 612 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n", 613 rOFDM0_RxDetector3, priv->framesync); 614 priv->SifsTime = rtl92e_readw(dev, SIFS); 615 } 616 617 void rtl92e_set_tx_power(struct net_device *dev, u8 channel) 618 { 619 struct r8192_priv *priv = rtllib_priv(dev); 620 u8 powerlevel = 0, powerlevelOFDM24G = 0; 621 s8 ant_pwr_diff; 622 u32 u4RegValue; 623 624 if (priv->epromtype == EEPROM_93C46) { 625 powerlevel = priv->TxPowerLevelCCK[channel-1]; 626 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; 627 } else if (priv->epromtype == EEPROM_93C56) { 628 if (priv->rf_type == RF_1T2R) { 629 powerlevel = priv->TxPowerLevelCCK_C[channel-1]; 630 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1]; 631 } else if (priv->rf_type == RF_2T4R) { 632 powerlevel = priv->TxPowerLevelCCK_A[channel-1]; 633 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1]; 634 635 ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1] 636 - priv->TxPowerLevelOFDM24G_A[channel-1]; 637 638 priv->RF_C_TxPwDiff = ant_pwr_diff; 639 640 ant_pwr_diff &= 0xf; 641 642 priv->AntennaTxPwDiff[2] = 0; 643 priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff); 644 priv->AntennaTxPwDiff[0] = 0; 645 646 u4RegValue = priv->AntennaTxPwDiff[2]<<8 | 647 priv->AntennaTxPwDiff[1]<<4 | 648 priv->AntennaTxPwDiff[0]; 649 650 rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage, 651 (bXBTxAGC|bXCTxAGC|bXDTxAGC), 652 u4RegValue); 653 } 654 } 655 switch (priv->rf_chip) { 656 case RF_8225: 657 break; 658 case RF_8256: 659 rtl92e_set_cck_tx_power(dev, powerlevel); 660 rtl92e_set_ofdm_tx_power(dev, powerlevelOFDM24G); 661 break; 662 case RF_8258: 663 break; 664 default: 665 netdev_err(dev, "Invalid RF Chip ID.\n"); 666 break; 667 } 668 } 669 670 bool rtl92e_config_phy(struct net_device *dev) 671 { 672 struct r8192_priv *priv = rtllib_priv(dev); 673 bool rtStatus = true; 674 675 switch (priv->rf_chip) { 676 case RF_8225: 677 break; 678 case RF_8256: 679 rtStatus = rtl92e_config_rf(dev); 680 break; 681 682 case RF_8258: 683 break; 684 case RF_PSEUDO_11N: 685 break; 686 687 default: 688 netdev_err(dev, "Invalid RF Chip ID.\n"); 689 break; 690 } 691 return rtStatus; 692 } 693 694 u8 rtl92e_config_rf_path(struct net_device *dev, enum rf90_radio_path eRFPath) 695 { 696 697 int i; 698 699 switch (eRFPath) { 700 case RF90_PATH_A: 701 for (i = 0; i < RadioA_ArrayLength; i += 2) { 702 if (Rtl819XRadioA_Array[i] == 0xfe) { 703 msleep(100); 704 continue; 705 } 706 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioA_Array[i], 707 bMask12Bits, 708 Rtl819XRadioA_Array[i+1]); 709 710 } 711 break; 712 case RF90_PATH_B: 713 for (i = 0; i < RadioB_ArrayLength; i += 2) { 714 if (Rtl819XRadioB_Array[i] == 0xfe) { 715 msleep(100); 716 continue; 717 } 718 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioB_Array[i], 719 bMask12Bits, 720 Rtl819XRadioB_Array[i+1]); 721 722 } 723 break; 724 case RF90_PATH_C: 725 for (i = 0; i < RadioC_ArrayLength; i += 2) { 726 if (Rtl819XRadioC_Array[i] == 0xfe) { 727 msleep(100); 728 continue; 729 } 730 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioC_Array[i], 731 bMask12Bits, 732 Rtl819XRadioC_Array[i+1]); 733 734 } 735 break; 736 case RF90_PATH_D: 737 for (i = 0; i < RadioD_ArrayLength; i += 2) { 738 if (Rtl819XRadioD_Array[i] == 0xfe) { 739 msleep(100); 740 continue; 741 } 742 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioD_Array[i], 743 bMask12Bits, 744 Rtl819XRadioD_Array[i+1]); 745 746 } 747 break; 748 default: 749 break; 750 } 751 752 return 0; 753 754 } 755 756 static void _rtl92e_set_tx_power_level(struct net_device *dev, u8 channel) 757 { 758 struct r8192_priv *priv = rtllib_priv(dev); 759 u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; 760 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; 761 762 switch (priv->rf_chip) { 763 case RF_8225: 764 break; 765 766 case RF_8256: 767 rtl92e_set_cck_tx_power(dev, powerlevel); 768 rtl92e_set_ofdm_tx_power(dev, powerlevelOFDM24G); 769 break; 770 771 case RF_8258: 772 break; 773 default: 774 netdev_warn(dev, "%s(): Invalid RF Chip ID\n", __func__); 775 break; 776 } 777 } 778 779 static u8 _rtl92e_phy_set_sw_chnl_cmd_array(struct net_device *dev, 780 struct sw_chnl_cmd *CmdTable, 781 u32 CmdTableIdx, u32 CmdTableSz, 782 enum sw_chnl_cmd_id CmdID, 783 u32 Para1, u32 Para2, u32 msDelay) 784 { 785 struct sw_chnl_cmd *pCmd; 786 787 if (CmdTable == NULL) { 788 netdev_err(dev, "%s(): CmdTable cannot be NULL.\n", __func__); 789 return false; 790 } 791 if (CmdTableIdx >= CmdTableSz) { 792 netdev_err(dev, "%s(): Invalid index requested.\n", __func__); 793 return false; 794 } 795 796 pCmd = CmdTable + CmdTableIdx; 797 pCmd->CmdID = CmdID; 798 pCmd->Para1 = Para1; 799 pCmd->Para2 = Para2; 800 pCmd->msDelay = msDelay; 801 802 return true; 803 } 804 805 static u8 _rtl92e_phy_switch_channel_step(struct net_device *dev, u8 channel, 806 u8 *stage, u8 *step, u32 *delay) 807 { 808 struct r8192_priv *priv = rtllib_priv(dev); 809 struct rtllib_device *ieee = priv->rtllib; 810 u32 PreCommonCmdCnt; 811 u32 PostCommonCmdCnt; 812 u32 RfDependCmdCnt; 813 struct sw_chnl_cmd *CurrentCmd = NULL; 814 u8 eRFPath; 815 816 RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n", 817 __func__, *stage, *step, channel); 818 819 if (!rtllib_legal_channel(priv->rtllib, channel)) { 820 netdev_err(dev, "Invalid channel requested: %d\n", channel); 821 return true; 822 } 823 824 { 825 PreCommonCmdCnt = 0; 826 _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PreCommonCmd, 827 PreCommonCmdCnt++, 828 MAX_PRECMD_CNT, 829 CmdID_SetTxPowerLevel, 830 0, 0, 0); 831 _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PreCommonCmd, 832 PreCommonCmdCnt++, 833 MAX_PRECMD_CNT, CmdID_End, 834 0, 0, 0); 835 836 PostCommonCmdCnt = 0; 837 838 _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PostCommonCmd, 839 PostCommonCmdCnt++, 840 MAX_POSTCMD_CNT, CmdID_End, 841 0, 0, 0); 842 843 RfDependCmdCnt = 0; 844 switch (priv->rf_chip) { 845 case RF_8225: 846 if (!(channel >= 1 && channel <= 14)) { 847 netdev_err(dev, 848 "Invalid channel requested for 8225: %d\n", 849 channel); 850 return false; 851 } 852 _rtl92e_phy_set_sw_chnl_cmd_array(dev, 853 ieee->RfDependCmd, 854 RfDependCmdCnt++, 855 MAX_RFDEPENDCMD_CNT, 856 CmdID_RF_WriteReg, 857 rZebra1_Channel, 858 RF_CHANNEL_TABLE_ZEBRA[channel], 859 10); 860 _rtl92e_phy_set_sw_chnl_cmd_array(dev, 861 ieee->RfDependCmd, 862 RfDependCmdCnt++, 863 MAX_RFDEPENDCMD_CNT, 864 CmdID_End, 0, 0, 0); 865 break; 866 867 case RF_8256: 868 if (!(channel >= 1 && channel <= 14)) { 869 netdev_err(dev, 870 "Invalid channel requested for 8256: %d\n", 871 channel); 872 return false; 873 } 874 _rtl92e_phy_set_sw_chnl_cmd_array(dev, 875 ieee->RfDependCmd, 876 RfDependCmdCnt++, 877 MAX_RFDEPENDCMD_CNT, 878 CmdID_RF_WriteReg, 879 rZebra1_Channel, 880 channel, 10); 881 _rtl92e_phy_set_sw_chnl_cmd_array(dev, 882 ieee->RfDependCmd, 883 RfDependCmdCnt++, 884 MAX_RFDEPENDCMD_CNT, 885 CmdID_End, 0, 0, 0); 886 break; 887 888 case RF_8258: 889 break; 890 891 default: 892 netdev_warn(dev, "Unknown RF Chip ID\n"); 893 return false; 894 } 895 896 897 do { 898 switch (*stage) { 899 case 0: 900 CurrentCmd = &ieee->PreCommonCmd[*step]; 901 break; 902 case 1: 903 CurrentCmd = &ieee->RfDependCmd[*step]; 904 break; 905 case 2: 906 CurrentCmd = &ieee->PostCommonCmd[*step]; 907 break; 908 } 909 910 if (CurrentCmd && CurrentCmd->CmdID == CmdID_End) { 911 if ((*stage) == 2) 912 return true; 913 (*stage)++; 914 (*step) = 0; 915 continue; 916 } 917 918 if (!CurrentCmd) 919 continue; 920 switch (CurrentCmd->CmdID) { 921 case CmdID_SetTxPowerLevel: 922 if (priv->IC_Cut > (u8)VERSION_8190_BD) 923 _rtl92e_set_tx_power_level(dev, 924 channel); 925 break; 926 case CmdID_WritePortUlong: 927 rtl92e_writel(dev, CurrentCmd->Para1, 928 CurrentCmd->Para2); 929 break; 930 case CmdID_WritePortUshort: 931 rtl92e_writew(dev, CurrentCmd->Para1, 932 (u16)CurrentCmd->Para2); 933 break; 934 case CmdID_WritePortUchar: 935 rtl92e_writeb(dev, CurrentCmd->Para1, 936 (u8)CurrentCmd->Para2); 937 break; 938 case CmdID_RF_WriteReg: 939 for (eRFPath = 0; eRFPath < 940 priv->NumTotalRFPath; eRFPath++) 941 rtl92e_set_rf_reg(dev, 942 (enum rf90_radio_path)eRFPath, 943 CurrentCmd->Para1, bMask12Bits, 944 CurrentCmd->Para2<<7); 945 break; 946 default: 947 break; 948 } 949 950 break; 951 } while (true); 952 } /*for (Number of RF paths)*/ 953 954 (*delay) = CurrentCmd->msDelay; 955 (*step)++; 956 return false; 957 } 958 959 static void _rtl92e_phy_switch_channel(struct net_device *dev, u8 channel) 960 { 961 struct r8192_priv *priv = rtllib_priv(dev); 962 u32 delay = 0; 963 964 while (!_rtl92e_phy_switch_channel_step(dev, channel, 965 &priv->SwChnlStage, 966 &priv->SwChnlStep, &delay)) { 967 if (delay > 0) 968 msleep(delay); 969 if (!priv->up) 970 break; 971 } 972 } 973 974 static void _rtl92e_phy_switch_channel_work_item(struct net_device *dev) 975 { 976 977 struct r8192_priv *priv = rtllib_priv(dev); 978 979 RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n"); 980 981 RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __func__, 982 priv->chan, priv); 983 984 _rtl92e_phy_switch_channel(dev, priv->chan); 985 986 RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n"); 987 } 988 989 u8 rtl92e_set_channel(struct net_device *dev, u8 channel) 990 { 991 struct r8192_priv *priv = rtllib_priv(dev); 992 993 RT_TRACE(COMP_PHY, "=====>%s()\n", __func__); 994 if (!priv->up) { 995 netdev_err(dev, "%s(): Driver is not initialized\n", __func__); 996 return false; 997 } 998 if (priv->SwChnlInProgress) 999 return false; 1000 1001 1002 switch (priv->rtllib->mode) { 1003 case WIRELESS_MODE_A: 1004 case WIRELESS_MODE_N_5G: 1005 if (channel <= 14) { 1006 netdev_warn(dev, 1007 "Channel %d not available in 802.11a.\n", 1008 channel); 1009 return false; 1010 } 1011 break; 1012 case WIRELESS_MODE_B: 1013 if (channel > 14) { 1014 netdev_warn(dev, 1015 "Channel %d not available in 802.11b.\n", 1016 channel); 1017 return false; 1018 } 1019 break; 1020 case WIRELESS_MODE_G: 1021 case WIRELESS_MODE_N_24G: 1022 if (channel > 14) { 1023 netdev_warn(dev, 1024 "Channel %d not available in 802.11g.\n", 1025 channel); 1026 return false; 1027 } 1028 break; 1029 } 1030 1031 priv->SwChnlInProgress = true; 1032 if (channel == 0) 1033 channel = 1; 1034 1035 priv->chan = channel; 1036 1037 priv->SwChnlStage = 0; 1038 priv->SwChnlStep = 0; 1039 1040 if (priv->up) 1041 _rtl92e_phy_switch_channel_work_item(dev); 1042 priv->SwChnlInProgress = false; 1043 return true; 1044 } 1045 1046 static void _rtl92e_cck_tx_power_track_bw_switch_tssi(struct net_device *dev) 1047 { 1048 struct r8192_priv *priv = rtllib_priv(dev); 1049 1050 switch (priv->CurrentChannelBW) { 1051 case HT_CHANNEL_WIDTH_20: 1052 priv->CCKPresentAttentuation = 1053 priv->CCKPresentAttentuation_20Mdefault + 1054 priv->CCKPresentAttentuation_difference; 1055 1056 if (priv->CCKPresentAttentuation > 1057 (CCKTxBBGainTableLength-1)) 1058 priv->CCKPresentAttentuation = 1059 CCKTxBBGainTableLength-1; 1060 if (priv->CCKPresentAttentuation < 0) 1061 priv->CCKPresentAttentuation = 0; 1062 1063 RT_TRACE(COMP_POWER_TRACKING, 1064 "20M, priv->CCKPresentAttentuation = %d\n", 1065 priv->CCKPresentAttentuation); 1066 1067 if (priv->rtllib->current_network.channel == 14 && 1068 !priv->bcck_in_ch14) { 1069 priv->bcck_in_ch14 = true; 1070 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1071 } else if (priv->rtllib->current_network.channel != 1072 14 && priv->bcck_in_ch14) { 1073 priv->bcck_in_ch14 = false; 1074 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1075 } else { 1076 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1077 } 1078 break; 1079 1080 case HT_CHANNEL_WIDTH_20_40: 1081 priv->CCKPresentAttentuation = 1082 priv->CCKPresentAttentuation_40Mdefault + 1083 priv->CCKPresentAttentuation_difference; 1084 1085 RT_TRACE(COMP_POWER_TRACKING, 1086 "40M, priv->CCKPresentAttentuation = %d\n", 1087 priv->CCKPresentAttentuation); 1088 if (priv->CCKPresentAttentuation > 1089 (CCKTxBBGainTableLength - 1)) 1090 priv->CCKPresentAttentuation = 1091 CCKTxBBGainTableLength-1; 1092 if (priv->CCKPresentAttentuation < 0) 1093 priv->CCKPresentAttentuation = 0; 1094 1095 if (priv->rtllib->current_network.channel == 14 && 1096 !priv->bcck_in_ch14) { 1097 priv->bcck_in_ch14 = true; 1098 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1099 } else if (priv->rtllib->current_network.channel != 14 1100 && priv->bcck_in_ch14) { 1101 priv->bcck_in_ch14 = false; 1102 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1103 } else { 1104 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1105 } 1106 break; 1107 } 1108 } 1109 1110 static void _rtl92e_cck_tx_power_track_bw_switch_thermal(struct net_device *dev) 1111 { 1112 struct r8192_priv *priv = rtllib_priv(dev); 1113 1114 if (priv->rtllib->current_network.channel == 14 && 1115 !priv->bcck_in_ch14) 1116 priv->bcck_in_ch14 = true; 1117 else if (priv->rtllib->current_network.channel != 14 && 1118 priv->bcck_in_ch14) 1119 priv->bcck_in_ch14 = false; 1120 1121 switch (priv->CurrentChannelBW) { 1122 case HT_CHANNEL_WIDTH_20: 1123 if (priv->Record_CCK_20Mindex == 0) 1124 priv->Record_CCK_20Mindex = 6; 1125 priv->CCK_index = priv->Record_CCK_20Mindex; 1126 RT_TRACE(COMP_POWER_TRACKING, 1127 "20MHz, %s,CCK_index = %d\n", __func__, 1128 priv->CCK_index); 1129 break; 1130 1131 case HT_CHANNEL_WIDTH_20_40: 1132 priv->CCK_index = priv->Record_CCK_40Mindex; 1133 RT_TRACE(COMP_POWER_TRACKING, 1134 "40MHz, %s, CCK_index = %d\n", __func__, 1135 priv->CCK_index); 1136 break; 1137 } 1138 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1139 } 1140 1141 static void _rtl92e_cck_tx_power_track_bw_switch(struct net_device *dev) 1142 { 1143 struct r8192_priv *priv = rtllib_priv(dev); 1144 1145 if (priv->IC_Cut >= IC_VersionCut_D) 1146 _rtl92e_cck_tx_power_track_bw_switch_tssi(dev); 1147 else 1148 _rtl92e_cck_tx_power_track_bw_switch_thermal(dev); 1149 } 1150 1151 static void _rtl92e_set_bw_mode_work_item(struct net_device *dev) 1152 { 1153 1154 struct r8192_priv *priv = rtllib_priv(dev); 1155 u8 regBwOpMode; 1156 1157 RT_TRACE(COMP_SWBW, 1158 "==>%s Switch to %s bandwidth\n", __func__, 1159 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ? 1160 "20MHz" : "40MHz"); 1161 1162 1163 if (priv->rf_chip == RF_PSEUDO_11N) { 1164 priv->SetBWModeInProgress = false; 1165 return; 1166 } 1167 if (!priv->up) { 1168 netdev_err(dev, "%s(): Driver is not initialized\n", __func__); 1169 return; 1170 } 1171 regBwOpMode = rtl92e_readb(dev, BW_OPMODE); 1172 1173 switch (priv->CurrentChannelBW) { 1174 case HT_CHANNEL_WIDTH_20: 1175 regBwOpMode |= BW_OPMODE_20MHZ; 1176 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode); 1177 break; 1178 1179 case HT_CHANNEL_WIDTH_20_40: 1180 regBwOpMode &= ~BW_OPMODE_20MHZ; 1181 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode); 1182 break; 1183 1184 default: 1185 netdev_err(dev, "%s(): unknown Bandwidth: %#X\n", __func__, 1186 priv->CurrentChannelBW); 1187 break; 1188 } 1189 1190 switch (priv->CurrentChannelBW) { 1191 case HT_CHANNEL_WIDTH_20: 1192 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); 1193 rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); 1194 1195 if (!priv->btxpower_tracking) { 1196 rtl92e_writel(dev, rCCK0_TxFilter1, 0x1a1b0000); 1197 rtl92e_writel(dev, rCCK0_TxFilter2, 0x090e1317); 1198 rtl92e_writel(dev, rCCK0_DebugPort, 0x00000204); 1199 } else { 1200 _rtl92e_cck_tx_power_track_bw_switch(dev); 1201 } 1202 1203 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); 1204 1205 break; 1206 case HT_CHANNEL_WIDTH_20_40: 1207 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); 1208 rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); 1209 1210 if (!priv->btxpower_tracking) { 1211 rtl92e_writel(dev, rCCK0_TxFilter1, 0x35360000); 1212 rtl92e_writel(dev, rCCK0_TxFilter2, 0x121c252e); 1213 rtl92e_writel(dev, rCCK0_DebugPort, 0x00000409); 1214 } else { 1215 _rtl92e_cck_tx_power_track_bw_switch(dev); 1216 } 1217 1218 rtl92e_set_bb_reg(dev, rCCK0_System, bCCKSideBand, 1219 (priv->nCur40MhzPrimeSC>>1)); 1220 rtl92e_set_bb_reg(dev, rOFDM1_LSTF, 0xC00, 1221 priv->nCur40MhzPrimeSC); 1222 1223 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); 1224 break; 1225 default: 1226 netdev_err(dev, "%s(): unknown Bandwidth: %#X\n", __func__, 1227 priv->CurrentChannelBW); 1228 break; 1229 1230 } 1231 1232 switch (priv->rf_chip) { 1233 case RF_8225: 1234 break; 1235 1236 case RF_8256: 1237 rtl92e_set_bandwidth(dev, priv->CurrentChannelBW); 1238 break; 1239 1240 case RF_8258: 1241 break; 1242 1243 case RF_PSEUDO_11N: 1244 break; 1245 1246 default: 1247 netdev_info(dev, "%s(): Unknown RFChipID: %d\n", __func__, 1248 priv->rf_chip); 1249 break; 1250 } 1251 1252 atomic_dec(&(priv->rtllib->atm_swbw)); 1253 priv->SetBWModeInProgress = false; 1254 1255 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()"); 1256 } 1257 1258 void rtl92e_set_bw_mode(struct net_device *dev, enum ht_channel_width Bandwidth, 1259 enum ht_extchnl_offset Offset) 1260 { 1261 struct r8192_priv *priv = rtllib_priv(dev); 1262 1263 1264 if (priv->SetBWModeInProgress) 1265 return; 1266 1267 atomic_inc(&(priv->rtllib->atm_swbw)); 1268 priv->SetBWModeInProgress = true; 1269 1270 priv->CurrentChannelBW = Bandwidth; 1271 1272 if (Offset == HT_EXTCHNL_OFFSET_LOWER) 1273 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; 1274 else if (Offset == HT_EXTCHNL_OFFSET_UPPER) 1275 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; 1276 else 1277 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; 1278 1279 _rtl92e_set_bw_mode_work_item(dev); 1280 1281 } 1282 1283 void rtl92e_init_gain(struct net_device *dev, u8 Operation) 1284 { 1285 #define SCAN_RX_INITIAL_GAIN 0x17 1286 #define POWER_DETECTION_TH 0x08 1287 struct r8192_priv *priv = rtllib_priv(dev); 1288 u32 BitMask; 1289 u8 initial_gain; 1290 1291 if (priv->up) { 1292 switch (Operation) { 1293 case IG_Backup: 1294 RT_TRACE(COMP_SCAN, 1295 "IG_Backup, backup the initial gain.\n"); 1296 initial_gain = SCAN_RX_INITIAL_GAIN; 1297 BitMask = bMaskByte0; 1298 if (dm_digtable.dig_algorithm == 1299 DIG_ALGO_BY_FALSE_ALARM) 1300 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8); 1301 priv->initgain_backup.xaagccore1 = 1302 (u8)rtl92e_get_bb_reg(dev, rOFDM0_XAAGCCore1, 1303 BitMask); 1304 priv->initgain_backup.xbagccore1 = 1305 (u8)rtl92e_get_bb_reg(dev, rOFDM0_XBAGCCore1, 1306 BitMask); 1307 priv->initgain_backup.xcagccore1 = 1308 (u8)rtl92e_get_bb_reg(dev, rOFDM0_XCAGCCore1, 1309 BitMask); 1310 priv->initgain_backup.xdagccore1 = 1311 (u8)rtl92e_get_bb_reg(dev, rOFDM0_XDAGCCore1, 1312 BitMask); 1313 BitMask = bMaskByte2; 1314 priv->initgain_backup.cca = (u8)rtl92e_get_bb_reg(dev, 1315 rCCK0_CCA, BitMask); 1316 1317 RT_TRACE(COMP_SCAN, 1318 "Scan InitialGainBackup 0xc50 is %x\n", 1319 priv->initgain_backup.xaagccore1); 1320 RT_TRACE(COMP_SCAN, 1321 "Scan InitialGainBackup 0xc58 is %x\n", 1322 priv->initgain_backup.xbagccore1); 1323 RT_TRACE(COMP_SCAN, 1324 "Scan InitialGainBackup 0xc60 is %x\n", 1325 priv->initgain_backup.xcagccore1); 1326 RT_TRACE(COMP_SCAN, 1327 "Scan InitialGainBackup 0xc68 is %x\n", 1328 priv->initgain_backup.xdagccore1); 1329 RT_TRACE(COMP_SCAN, 1330 "Scan InitialGainBackup 0xa0a is %x\n", 1331 priv->initgain_backup.cca); 1332 1333 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n", 1334 initial_gain); 1335 rtl92e_writeb(dev, rOFDM0_XAAGCCore1, initial_gain); 1336 rtl92e_writeb(dev, rOFDM0_XBAGCCore1, initial_gain); 1337 rtl92e_writeb(dev, rOFDM0_XCAGCCore1, initial_gain); 1338 rtl92e_writeb(dev, rOFDM0_XDAGCCore1, initial_gain); 1339 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n", 1340 POWER_DETECTION_TH); 1341 rtl92e_writeb(dev, 0xa0a, POWER_DETECTION_TH); 1342 break; 1343 case IG_Restore: 1344 RT_TRACE(COMP_SCAN, 1345 "IG_Restore, restore the initial gain.\n"); 1346 BitMask = 0x7f; 1347 if (dm_digtable.dig_algorithm == 1348 DIG_ALGO_BY_FALSE_ALARM) 1349 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8); 1350 1351 rtl92e_set_bb_reg(dev, rOFDM0_XAAGCCore1, BitMask, 1352 (u32)priv->initgain_backup.xaagccore1); 1353 rtl92e_set_bb_reg(dev, rOFDM0_XBAGCCore1, BitMask, 1354 (u32)priv->initgain_backup.xbagccore1); 1355 rtl92e_set_bb_reg(dev, rOFDM0_XCAGCCore1, BitMask, 1356 (u32)priv->initgain_backup.xcagccore1); 1357 rtl92e_set_bb_reg(dev, rOFDM0_XDAGCCore1, BitMask, 1358 (u32)priv->initgain_backup.xdagccore1); 1359 BitMask = bMaskByte2; 1360 rtl92e_set_bb_reg(dev, rCCK0_CCA, BitMask, 1361 (u32)priv->initgain_backup.cca); 1362 1363 RT_TRACE(COMP_SCAN, 1364 "Scan BBInitialGainRestore 0xc50 is %x\n", 1365 priv->initgain_backup.xaagccore1); 1366 RT_TRACE(COMP_SCAN, 1367 "Scan BBInitialGainRestore 0xc58 is %x\n", 1368 priv->initgain_backup.xbagccore1); 1369 RT_TRACE(COMP_SCAN, 1370 "Scan BBInitialGainRestore 0xc60 is %x\n", 1371 priv->initgain_backup.xcagccore1); 1372 RT_TRACE(COMP_SCAN, 1373 "Scan BBInitialGainRestore 0xc68 is %x\n", 1374 priv->initgain_backup.xdagccore1); 1375 RT_TRACE(COMP_SCAN, 1376 "Scan BBInitialGainRestore 0xa0a is %x\n", 1377 priv->initgain_backup.cca); 1378 1379 rtl92e_set_tx_power(dev, 1380 priv->rtllib->current_network.channel); 1381 1382 if (dm_digtable.dig_algorithm == 1383 DIG_ALGO_BY_FALSE_ALARM) 1384 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x1); 1385 break; 1386 default: 1387 RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n"); 1388 break; 1389 } 1390 } 1391 } 1392 1393 void rtl92e_set_rf_off(struct net_device *dev) 1394 { 1395 1396 rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); 1397 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0); 1398 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); 1399 rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0); 1400 rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0); 1401 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); 1402 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0); 1403 rtl92e_writeb(dev, ANAPAR_FOR_8192PciE, 0x07); 1404 1405 } 1406 1407 static bool _rtl92e_set_rf_power_state(struct net_device *dev, 1408 enum rt_rf_power_state eRFPowerState) 1409 { 1410 struct r8192_priv *priv = rtllib_priv(dev); 1411 struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *) 1412 (&(priv->rtllib->PowerSaveControl)); 1413 bool bResult = true; 1414 u8 i = 0, QueueID = 0; 1415 struct rtl8192_tx_ring *ring = NULL; 1416 1417 if (priv->SetRFPowerStateInProgress) 1418 return false; 1419 RT_TRACE(COMP_PS, "===========> %s!\n", __func__); 1420 priv->SetRFPowerStateInProgress = true; 1421 1422 switch (priv->rf_chip) { 1423 case RF_8256: 1424 switch (eRFPowerState) { 1425 case eRfOn: 1426 RT_TRACE(COMP_PS, "%s eRfOn!\n", __func__); 1427 if ((priv->rtllib->eRFPowerState == eRfOff) && 1428 RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) { 1429 bool rtstatus; 1430 u32 InitilizeCount = 3; 1431 1432 do { 1433 InitilizeCount--; 1434 priv->RegRfOff = false; 1435 rtstatus = rtl92e_enable_nic(dev); 1436 } while (!rtstatus && (InitilizeCount > 0)); 1437 1438 if (!rtstatus) { 1439 netdev_err(dev, 1440 "%s(): Failed to initialize Adapter.\n", 1441 __func__); 1442 priv->SetRFPowerStateInProgress = false; 1443 return false; 1444 } 1445 1446 RT_CLEAR_PS_LEVEL(pPSC, 1447 RT_RF_OFF_LEVL_HALT_NIC); 1448 } else { 1449 rtl92e_writeb(dev, ANAPAR, 0x37); 1450 mdelay(1); 1451 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 1452 0x4, 0x1); 1453 priv->bHwRfOffAction = 0; 1454 1455 rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE, 1456 BIT4, 0x1); 1457 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 1458 0x300, 0x3); 1459 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 1460 0x18, 0x3); 1461 rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable, 1462 0x3, 0x3); 1463 rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable, 1464 0x3, 0x3); 1465 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 1466 0x60, 0x3); 1467 1468 } 1469 1470 break; 1471 1472 case eRfSleep: 1473 if (priv->rtllib->eRFPowerState == eRfOff) 1474 break; 1475 1476 1477 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) { 1478 ring = &priv->tx_ring[QueueID]; 1479 1480 if (skb_queue_len(&ring->queue) == 0) { 1481 QueueID++; 1482 continue; 1483 } else { 1484 RT_TRACE((COMP_POWER|COMP_RF), 1485 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", 1486 (i+1), QueueID); 1487 udelay(10); 1488 i++; 1489 } 1490 1491 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 1492 RT_TRACE(COMP_POWER, "\n\n\n TimeOut!! %s: eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n", 1493 __func__, MAX_DOZE_WAITING_TIMES_9x, QueueID); 1494 break; 1495 } 1496 } 1497 rtl92e_set_rf_off(dev); 1498 break; 1499 1500 case eRfOff: 1501 RT_TRACE(COMP_PS, "%s eRfOff/Sleep !\n", __func__); 1502 1503 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) { 1504 ring = &priv->tx_ring[QueueID]; 1505 1506 if (skb_queue_len(&ring->queue) == 0) { 1507 QueueID++; 1508 continue; 1509 } else { 1510 RT_TRACE(COMP_POWER, 1511 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", 1512 (i+1), QueueID); 1513 udelay(10); 1514 i++; 1515 } 1516 1517 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 1518 RT_TRACE(COMP_POWER, 1519 "\n\n\n SetZebra: RFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n", 1520 MAX_DOZE_WAITING_TIMES_9x, 1521 QueueID); 1522 break; 1523 } 1524 } 1525 1526 if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && 1527 !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) { 1528 rtl92e_disable_nic(dev); 1529 RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); 1530 } else if (!(pPSC->RegRfPsLevel & 1531 RT_RF_OFF_LEVL_HALT_NIC)) { 1532 rtl92e_set_rf_off(dev); 1533 } 1534 1535 break; 1536 1537 default: 1538 bResult = false; 1539 netdev_warn(dev, 1540 "%s(): Unknown state requested: 0x%X.\n", 1541 __func__, eRFPowerState); 1542 break; 1543 } 1544 1545 break; 1546 1547 default: 1548 netdev_warn(dev, "%s(): Unknown RF type\n", __func__); 1549 break; 1550 } 1551 1552 if (bResult) { 1553 priv->rtllib->eRFPowerState = eRFPowerState; 1554 1555 switch (priv->rf_chip) { 1556 case RF_8256: 1557 break; 1558 1559 default: 1560 netdev_warn(dev, "%s(): Unknown RF type\n", __func__); 1561 break; 1562 } 1563 } 1564 1565 priv->SetRFPowerStateInProgress = false; 1566 RT_TRACE(COMP_PS, "<=========== %s bResult = %d!\n", __func__, bResult); 1567 return bResult; 1568 } 1569 1570 bool rtl92e_set_rf_power_state(struct net_device *dev, 1571 enum rt_rf_power_state eRFPowerState) 1572 { 1573 struct r8192_priv *priv = rtllib_priv(dev); 1574 1575 bool bResult = false; 1576 1577 RT_TRACE(COMP_PS, 1578 "---------> %s: eRFPowerState(%d)\n", __func__, eRFPowerState); 1579 if (eRFPowerState == priv->rtllib->eRFPowerState && 1580 priv->bHwRfOffAction == 0) { 1581 RT_TRACE(COMP_PS, "<--------- %s: discard the request for eRFPowerState(%d) is the same.\n", 1582 __func__, eRFPowerState); 1583 return bResult; 1584 } 1585 1586 bResult = _rtl92e_set_rf_power_state(dev, eRFPowerState); 1587 1588 RT_TRACE(COMP_PS, "<--------- %s: bResult(%d)\n", __func__, bResult); 1589 1590 return bResult; 1591 } 1592 1593 void rtl92e_scan_op_backup(struct net_device *dev, u8 Operation) 1594 { 1595 struct r8192_priv *priv = rtllib_priv(dev); 1596 1597 if (priv->up) { 1598 switch (Operation) { 1599 case SCAN_OPT_BACKUP: 1600 priv->rtllib->InitialGainHandler(dev, IG_Backup); 1601 break; 1602 1603 case SCAN_OPT_RESTORE: 1604 priv->rtllib->InitialGainHandler(dev, IG_Restore); 1605 break; 1606 1607 default: 1608 RT_TRACE(COMP_SCAN, "Unknown Scan Backup Operation.\n"); 1609 break; 1610 } 1611 } 1612 } 1613