1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. 4 * 5 * Contact Information: wlanfae <wlanfae@realtek.com> 6 */ 7 #include <linux/bitops.h> 8 #include "rtl_core.h" 9 #include "r8192E_hw.h" 10 #include "r8192E_phyreg.h" 11 #include "r8190P_rtl8256.h" 12 #include "r8192E_phy.h" 13 #include "rtl_dm.h" 14 15 #include "r8192E_hwimg.h" 16 17 static u32 RF_CHANNEL_TABLE_ZEBRA[] = { 18 0, 19 0x085c, 20 0x08dc, 21 0x095c, 22 0x09dc, 23 0x0a5c, 24 0x0adc, 25 0x0b5c, 26 0x0bdc, 27 0x0c5c, 28 0x0cdc, 29 0x0d5c, 30 0x0ddc, 31 0x0e5c, 32 0x0f72, 33 }; 34 35 /*************************Define local function prototype**********************/ 36 37 static u32 _rtl92e_phy_rf_fw_read(struct net_device *dev, 38 enum rf90_radio_path eRFPath, u32 Offset); 39 static void _rtl92e_phy_rf_fw_write(struct net_device *dev, 40 enum rf90_radio_path eRFPath, u32 Offset, 41 u32 Data); 42 43 static u32 _rtl92e_calculate_bit_shift(u32 dwBitMask) 44 { 45 if (!dwBitMask) 46 return 32; 47 return ffs(dwBitMask) - 1; 48 } 49 50 u8 rtl92e_is_legal_rf_path(struct net_device *dev, u32 eRFPath) 51 { 52 u8 ret = 1; 53 struct r8192_priv *priv = rtllib_priv(dev); 54 55 if (priv->rf_type == RF_2T4R) 56 ret = 0; 57 else if (priv->rf_type == RF_1T2R) { 58 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) 59 ret = 1; 60 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) 61 ret = 0; 62 } 63 return ret; 64 } 65 66 void rtl92e_set_bb_reg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask, 67 u32 dwData) 68 { 69 70 u32 OriginalValue, BitShift, NewValue; 71 72 if (dwBitMask != bMaskDWord) { 73 OriginalValue = rtl92e_readl(dev, dwRegAddr); 74 BitShift = _rtl92e_calculate_bit_shift(dwBitMask); 75 NewValue = (OriginalValue & ~dwBitMask) | (dwData << BitShift); 76 rtl92e_writel(dev, dwRegAddr, NewValue); 77 } else 78 rtl92e_writel(dev, dwRegAddr, dwData); 79 } 80 81 u32 rtl92e_get_bb_reg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask) 82 { 83 u32 OriginalValue, BitShift; 84 85 OriginalValue = rtl92e_readl(dev, dwRegAddr); 86 BitShift = _rtl92e_calculate_bit_shift(dwBitMask); 87 88 return (OriginalValue & dwBitMask) >> BitShift; 89 } 90 91 static u32 _rtl92e_phy_rf_read(struct net_device *dev, 92 enum rf90_radio_path eRFPath, u32 Offset) 93 { 94 struct r8192_priv *priv = rtllib_priv(dev); 95 u32 ret = 0; 96 u32 NewOffset = 0; 97 struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath]; 98 99 Offset &= 0x3f; 100 101 if (priv->rf_chip == RF_8256) { 102 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); 103 if (Offset >= 31) { 104 priv->RfReg0Value[eRFPath] |= 0x140; 105 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, 106 bMaskDWord, 107 (priv->RfReg0Value[eRFPath]<<16)); 108 NewOffset = Offset - 30; 109 } else if (Offset >= 16) { 110 priv->RfReg0Value[eRFPath] |= 0x100; 111 priv->RfReg0Value[eRFPath] &= (~0x40); 112 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, 113 bMaskDWord, 114 (priv->RfReg0Value[eRFPath]<<16)); 115 116 NewOffset = Offset - 15; 117 } else 118 NewOffset = Offset; 119 } else { 120 NewOffset = Offset; 121 } 122 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, 123 NewOffset); 124 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); 125 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); 126 127 mdelay(1); 128 129 ret = rtl92e_get_bb_reg(dev, pPhyReg->rfLSSIReadBack, 130 bLSSIReadBackData); 131 132 if (priv->rf_chip == RF_8256) { 133 priv->RfReg0Value[eRFPath] &= 0xebf; 134 135 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, 136 (priv->RfReg0Value[eRFPath] << 16)); 137 138 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); 139 } 140 141 142 return ret; 143 144 } 145 146 static void _rtl92e_phy_rf_write(struct net_device *dev, 147 enum rf90_radio_path eRFPath, u32 Offset, 148 u32 Data) 149 { 150 struct r8192_priv *priv = rtllib_priv(dev); 151 u32 DataAndAddr = 0, NewOffset = 0; 152 struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath]; 153 154 Offset &= 0x3f; 155 if (priv->rf_chip == RF_8256) { 156 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); 157 158 if (Offset >= 31) { 159 priv->RfReg0Value[eRFPath] |= 0x140; 160 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, 161 bMaskDWord, 162 (priv->RfReg0Value[eRFPath] << 16)); 163 NewOffset = Offset - 30; 164 } else if (Offset >= 16) { 165 priv->RfReg0Value[eRFPath] |= 0x100; 166 priv->RfReg0Value[eRFPath] &= (~0x40); 167 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, 168 bMaskDWord, 169 (priv->RfReg0Value[eRFPath] << 16)); 170 NewOffset = Offset - 15; 171 } else 172 NewOffset = Offset; 173 } else { 174 NewOffset = Offset; 175 } 176 177 DataAndAddr = (NewOffset & 0x3f) | (Data << 16); 178 179 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); 180 181 if (Offset == 0x0) 182 priv->RfReg0Value[eRFPath] = Data; 183 184 if (priv->rf_chip == RF_8256) { 185 if (Offset != 0) { 186 priv->RfReg0Value[eRFPath] &= 0xebf; 187 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, 188 bMaskDWord, 189 (priv->RfReg0Value[eRFPath] << 16)); 190 } 191 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); 192 } 193 } 194 195 void rtl92e_set_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath, 196 u32 RegAddr, u32 BitMask, u32 Data) 197 { 198 struct r8192_priv *priv = rtllib_priv(dev); 199 u32 Original_Value, BitShift, New_Value; 200 201 if (!rtl92e_is_legal_rf_path(dev, eRFPath)) 202 return; 203 if (priv->rtllib->rf_power_state != rf_on && !priv->being_init_adapter) 204 return; 205 206 if (priv->Rf_Mode == RF_OP_By_FW) { 207 if (BitMask != bMask12Bits) { 208 Original_Value = _rtl92e_phy_rf_fw_read(dev, eRFPath, 209 RegAddr); 210 BitShift = _rtl92e_calculate_bit_shift(BitMask); 211 New_Value = (Original_Value & ~BitMask) | (Data << BitShift); 212 213 _rtl92e_phy_rf_fw_write(dev, eRFPath, RegAddr, 214 New_Value); 215 } else 216 _rtl92e_phy_rf_fw_write(dev, eRFPath, RegAddr, Data); 217 udelay(200); 218 219 } else { 220 if (BitMask != bMask12Bits) { 221 Original_Value = _rtl92e_phy_rf_read(dev, eRFPath, 222 RegAddr); 223 BitShift = _rtl92e_calculate_bit_shift(BitMask); 224 New_Value = (Original_Value & ~BitMask) | (Data << BitShift); 225 226 _rtl92e_phy_rf_write(dev, eRFPath, RegAddr, New_Value); 227 } else 228 _rtl92e_phy_rf_write(dev, eRFPath, RegAddr, Data); 229 } 230 } 231 232 u32 rtl92e_get_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath, 233 u32 RegAddr, u32 BitMask) 234 { 235 u32 Original_Value, Readback_Value, BitShift; 236 struct r8192_priv *priv = rtllib_priv(dev); 237 238 if (!rtl92e_is_legal_rf_path(dev, eRFPath)) 239 return 0; 240 if (priv->rtllib->rf_power_state != rf_on && !priv->being_init_adapter) 241 return 0; 242 mutex_lock(&priv->rf_mutex); 243 if (priv->Rf_Mode == RF_OP_By_FW) { 244 Original_Value = _rtl92e_phy_rf_fw_read(dev, eRFPath, RegAddr); 245 udelay(200); 246 } else { 247 Original_Value = _rtl92e_phy_rf_read(dev, eRFPath, RegAddr); 248 } 249 BitShift = _rtl92e_calculate_bit_shift(BitMask); 250 Readback_Value = (Original_Value & BitMask) >> BitShift; 251 mutex_unlock(&priv->rf_mutex); 252 return Readback_Value; 253 } 254 255 static u32 _rtl92e_phy_rf_fw_read(struct net_device *dev, 256 enum rf90_radio_path eRFPath, u32 Offset) 257 { 258 u32 Data = 0; 259 u8 time = 0; 260 261 Data |= ((Offset & 0xFF) << 12); 262 Data |= ((eRFPath & 0x3) << 20); 263 Data |= 0x80000000; 264 while (rtl92e_readl(dev, QPNR) & 0x80000000) { 265 if (time++ < 100) 266 udelay(10); 267 else 268 break; 269 } 270 rtl92e_writel(dev, QPNR, Data); 271 while (rtl92e_readl(dev, QPNR) & 0x80000000) { 272 if (time++ < 100) 273 udelay(10); 274 else 275 return 0; 276 } 277 return rtl92e_readl(dev, RF_DATA); 278 279 } 280 281 static void _rtl92e_phy_rf_fw_write(struct net_device *dev, 282 enum rf90_radio_path eRFPath, u32 Offset, 283 u32 Data) 284 { 285 u8 time = 0; 286 287 Data |= ((Offset & 0xFF) << 12); 288 Data |= ((eRFPath & 0x3) << 20); 289 Data |= 0x400000; 290 Data |= 0x80000000; 291 292 while (rtl92e_readl(dev, QPNR) & 0x80000000) { 293 if (time++ < 100) 294 udelay(10); 295 else 296 break; 297 } 298 rtl92e_writel(dev, QPNR, Data); 299 300 } 301 302 303 void rtl92e_config_mac(struct net_device *dev) 304 { 305 u32 dwArrayLen = 0, i = 0; 306 u32 *pdwArray = NULL; 307 struct r8192_priv *priv = rtllib_priv(dev); 308 309 if (priv->bTXPowerDataReadFromEEPORM) { 310 dwArrayLen = MACPHY_Array_PGLength; 311 pdwArray = Rtl819XMACPHY_Array_PG; 312 313 } else { 314 dwArrayLen = MACPHY_ArrayLength; 315 pdwArray = Rtl819XMACPHY_Array; 316 } 317 for (i = 0; i < dwArrayLen; i += 3) { 318 if (pdwArray[i] == 0x318) 319 pdwArray[i+2] = 0x00000800; 320 rtl92e_set_bb_reg(dev, pdwArray[i], pdwArray[i+1], 321 pdwArray[i+2]); 322 } 323 return; 324 325 } 326 327 static void _rtl92e_phy_config_bb(struct net_device *dev, u8 ConfigType) 328 { 329 int i; 330 u32 *Rtl819XPHY_REGArray_Table = NULL; 331 u32 *Rtl819XAGCTAB_Array_Table = NULL; 332 u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0; 333 struct r8192_priv *priv = rtllib_priv(dev); 334 335 AGCTAB_ArrayLen = AGCTAB_ArrayLength; 336 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array; 337 if (priv->rf_type == RF_2T4R) { 338 PHY_REGArrayLen = PHY_REGArrayLength; 339 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray; 340 } else if (priv->rf_type == RF_1T2R) { 341 PHY_REGArrayLen = PHY_REG_1T2RArrayLength; 342 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray; 343 } 344 345 if (ConfigType == BaseBand_Config_PHY_REG) { 346 for (i = 0; i < PHY_REGArrayLen; i += 2) { 347 rtl92e_set_bb_reg(dev, Rtl819XPHY_REGArray_Table[i], 348 bMaskDWord, 349 Rtl819XPHY_REGArray_Table[i+1]); 350 } 351 } else if (ConfigType == BaseBand_Config_AGC_TAB) { 352 for (i = 0; i < AGCTAB_ArrayLen; i += 2) { 353 rtl92e_set_bb_reg(dev, Rtl819XAGCTAB_Array_Table[i], 354 bMaskDWord, 355 Rtl819XAGCTAB_Array_Table[i+1]); 356 } 357 } 358 } 359 360 static void _rtl92e_init_bb_rf_reg_def(struct net_device *dev) 361 { 362 struct r8192_priv *priv = rtllib_priv(dev); 363 364 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; 365 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; 366 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; 367 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW; 368 369 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; 370 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB; 371 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB; 372 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB; 373 374 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; 375 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; 376 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE; 377 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE; 378 379 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; 380 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; 381 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE; 382 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE; 383 384 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; 385 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; 386 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; 387 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; 388 389 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; 390 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; 391 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; 392 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; 393 394 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; 395 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; 396 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; 397 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; 398 399 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; 400 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; 401 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; 402 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; 403 404 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; 405 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; 406 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; 407 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; 408 409 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; 410 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; 411 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; 412 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; 413 414 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; 415 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; 416 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; 417 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; 418 419 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; 420 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; 421 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; 422 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; 423 424 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; 425 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; 426 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; 427 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; 428 429 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; 430 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; 431 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; 432 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; 433 434 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; 435 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; 436 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; 437 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; 438 439 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; 440 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; 441 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; 442 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; 443 444 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; 445 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; 446 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; 447 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; 448 449 } 450 451 bool rtl92e_check_bb_and_rf(struct net_device *dev, enum hw90_block CheckBlock, 452 enum rf90_radio_path eRFPath) 453 { 454 bool ret = true; 455 u32 i, CheckTimes = 4, dwRegRead = 0; 456 u32 WriteAddr[4]; 457 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f}; 458 459 WriteAddr[HW90_BLOCK_MAC] = 0x100; 460 WriteAddr[HW90_BLOCK_PHY0] = 0x900; 461 WriteAddr[HW90_BLOCK_PHY1] = 0x800; 462 WriteAddr[HW90_BLOCK_RF] = 0x3; 463 464 if (CheckBlock == HW90_BLOCK_MAC) { 465 netdev_warn(dev, "%s(): No checks available for MAC block.\n", 466 __func__); 467 return ret; 468 } 469 470 for (i = 0; i < CheckTimes; i++) { 471 switch (CheckBlock) { 472 case HW90_BLOCK_PHY0: 473 case HW90_BLOCK_PHY1: 474 rtl92e_writel(dev, WriteAddr[CheckBlock], 475 WriteData[i]); 476 dwRegRead = rtl92e_readl(dev, WriteAddr[CheckBlock]); 477 break; 478 479 case HW90_BLOCK_RF: 480 WriteData[i] &= 0xfff; 481 rtl92e_set_rf_reg(dev, eRFPath, 482 WriteAddr[HW90_BLOCK_RF], 483 bMask12Bits, WriteData[i]); 484 mdelay(10); 485 dwRegRead = rtl92e_get_rf_reg(dev, eRFPath, 486 WriteAddr[HW90_BLOCK_RF], 487 bMaskDWord); 488 mdelay(10); 489 break; 490 491 default: 492 ret = false; 493 break; 494 } 495 496 497 if (dwRegRead != WriteData[i]) { 498 netdev_warn(dev, "%s(): Check failed.\n", __func__); 499 ret = false; 500 break; 501 } 502 } 503 504 return ret; 505 } 506 507 static bool _rtl92e_bb_config_para_file(struct net_device *dev) 508 { 509 struct r8192_priv *priv = rtllib_priv(dev); 510 bool rtStatus = true; 511 u8 bRegValue = 0, eCheckItem = 0; 512 u32 dwRegValue = 0; 513 514 bRegValue = rtl92e_readb(dev, BB_GLOBAL_RESET); 515 rtl92e_writeb(dev, BB_GLOBAL_RESET, (bRegValue|BB_GLOBAL_RESET_BIT)); 516 517 dwRegValue = rtl92e_readl(dev, CPU_GEN); 518 rtl92e_writel(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST))); 519 520 for (eCheckItem = (enum hw90_block)HW90_BLOCK_PHY0; 521 eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) { 522 rtStatus = rtl92e_check_bb_and_rf(dev, 523 (enum hw90_block)eCheckItem, 524 (enum rf90_radio_path)0); 525 if (!rtStatus) { 526 return rtStatus; 527 } 528 } 529 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); 530 _rtl92e_phy_config_bb(dev, BaseBand_Config_PHY_REG); 531 532 dwRegValue = rtl92e_readl(dev, CPU_GEN); 533 rtl92e_writel(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST)); 534 535 _rtl92e_phy_config_bb(dev, BaseBand_Config_AGC_TAB); 536 537 if (priv->IC_Cut > VERSION_8190_BD) { 538 if (priv->rf_type == RF_2T4R) 539 dwRegValue = priv->AntennaTxPwDiff[2]<<8 | 540 priv->AntennaTxPwDiff[1]<<4 | 541 priv->AntennaTxPwDiff[0]; 542 else 543 dwRegValue = 0x0; 544 rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage, 545 (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue); 546 547 548 dwRegValue = priv->CrystalCap; 549 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, 550 dwRegValue); 551 } 552 553 return rtStatus; 554 } 555 bool rtl92e_config_bb(struct net_device *dev) 556 { 557 _rtl92e_init_bb_rf_reg_def(dev); 558 return _rtl92e_bb_config_para_file(dev); 559 } 560 561 void rtl92e_get_tx_power(struct net_device *dev) 562 { 563 struct r8192_priv *priv = rtllib_priv(dev); 564 565 priv->MCSTxPowerLevelOriginalOffset[0] = 566 rtl92e_readl(dev, rTxAGC_Rate18_06); 567 priv->MCSTxPowerLevelOriginalOffset[1] = 568 rtl92e_readl(dev, rTxAGC_Rate54_24); 569 priv->MCSTxPowerLevelOriginalOffset[2] = 570 rtl92e_readl(dev, rTxAGC_Mcs03_Mcs00); 571 priv->MCSTxPowerLevelOriginalOffset[3] = 572 rtl92e_readl(dev, rTxAGC_Mcs07_Mcs04); 573 priv->MCSTxPowerLevelOriginalOffset[4] = 574 rtl92e_readl(dev, rTxAGC_Mcs11_Mcs08); 575 priv->MCSTxPowerLevelOriginalOffset[5] = 576 rtl92e_readl(dev, rTxAGC_Mcs15_Mcs12); 577 578 priv->DefaultInitialGain[0] = rtl92e_readb(dev, rOFDM0_XAAGCCore1); 579 priv->DefaultInitialGain[1] = rtl92e_readb(dev, rOFDM0_XBAGCCore1); 580 priv->DefaultInitialGain[2] = rtl92e_readb(dev, rOFDM0_XCAGCCore1); 581 priv->DefaultInitialGain[3] = rtl92e_readb(dev, rOFDM0_XDAGCCore1); 582 583 priv->framesync = rtl92e_readb(dev, rOFDM0_RxDetector3); 584 priv->framesyncC34 = rtl92e_readl(dev, rOFDM0_RxDetector2); 585 priv->SifsTime = rtl92e_readw(dev, SIFS); 586 } 587 588 void rtl92e_set_tx_power(struct net_device *dev, u8 channel) 589 { 590 struct r8192_priv *priv = rtllib_priv(dev); 591 u8 powerlevel = 0, powerlevelOFDM24G = 0; 592 s8 ant_pwr_diff; 593 u32 u4RegValue; 594 595 if (priv->epromtype == EEPROM_93C46) { 596 powerlevel = priv->TxPowerLevelCCK[channel-1]; 597 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; 598 } else if (priv->epromtype == EEPROM_93C56) { 599 if (priv->rf_type == RF_1T2R) { 600 powerlevel = priv->TxPowerLevelCCK_C[channel-1]; 601 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1]; 602 } else if (priv->rf_type == RF_2T4R) { 603 powerlevel = priv->TxPowerLevelCCK_A[channel-1]; 604 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1]; 605 606 ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1] 607 - priv->TxPowerLevelOFDM24G_A[channel-1]; 608 609 priv->RF_C_TxPwDiff = ant_pwr_diff; 610 611 ant_pwr_diff &= 0xf; 612 613 priv->AntennaTxPwDiff[2] = 0; 614 priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff); 615 priv->AntennaTxPwDiff[0] = 0; 616 617 u4RegValue = priv->AntennaTxPwDiff[2]<<8 | 618 priv->AntennaTxPwDiff[1]<<4 | 619 priv->AntennaTxPwDiff[0]; 620 621 rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage, 622 (bXBTxAGC|bXCTxAGC|bXDTxAGC), 623 u4RegValue); 624 } 625 } 626 switch (priv->rf_chip) { 627 case RF_8225: 628 break; 629 case RF_8256: 630 rtl92e_set_cck_tx_power(dev, powerlevel); 631 rtl92e_set_ofdm_tx_power(dev, powerlevelOFDM24G); 632 break; 633 case RF_8258: 634 break; 635 default: 636 netdev_err(dev, "Invalid RF Chip ID.\n"); 637 break; 638 } 639 } 640 641 bool rtl92e_config_phy(struct net_device *dev) 642 { 643 struct r8192_priv *priv = rtllib_priv(dev); 644 bool rtStatus = true; 645 646 switch (priv->rf_chip) { 647 case RF_8225: 648 break; 649 case RF_8256: 650 rtStatus = rtl92e_config_rf(dev); 651 break; 652 653 case RF_8258: 654 break; 655 case RF_PSEUDO_11N: 656 break; 657 658 default: 659 netdev_err(dev, "Invalid RF Chip ID.\n"); 660 break; 661 } 662 return rtStatus; 663 } 664 665 u8 rtl92e_config_rf_path(struct net_device *dev, enum rf90_radio_path eRFPath) 666 { 667 668 int i; 669 670 switch (eRFPath) { 671 case RF90_PATH_A: 672 for (i = 0; i < RadioA_ArrayLength; i += 2) { 673 if (Rtl819XRadioA_Array[i] == 0xfe) { 674 msleep(100); 675 continue; 676 } 677 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioA_Array[i], 678 bMask12Bits, 679 Rtl819XRadioA_Array[i+1]); 680 681 } 682 break; 683 case RF90_PATH_B: 684 for (i = 0; i < RadioB_ArrayLength; i += 2) { 685 if (Rtl819XRadioB_Array[i] == 0xfe) { 686 msleep(100); 687 continue; 688 } 689 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioB_Array[i], 690 bMask12Bits, 691 Rtl819XRadioB_Array[i+1]); 692 693 } 694 break; 695 case RF90_PATH_C: 696 for (i = 0; i < RadioC_ArrayLength; i += 2) { 697 if (Rtl819XRadioC_Array[i] == 0xfe) { 698 msleep(100); 699 continue; 700 } 701 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioC_Array[i], 702 bMask12Bits, 703 Rtl819XRadioC_Array[i+1]); 704 705 } 706 break; 707 case RF90_PATH_D: 708 for (i = 0; i < RadioD_ArrayLength; i += 2) { 709 if (Rtl819XRadioD_Array[i] == 0xfe) { 710 msleep(100); 711 continue; 712 } 713 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioD_Array[i], 714 bMask12Bits, 715 Rtl819XRadioD_Array[i+1]); 716 717 } 718 break; 719 default: 720 break; 721 } 722 723 return 0; 724 725 } 726 727 static void _rtl92e_set_tx_power_level(struct net_device *dev, u8 channel) 728 { 729 struct r8192_priv *priv = rtllib_priv(dev); 730 u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; 731 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; 732 733 switch (priv->rf_chip) { 734 case RF_8225: 735 break; 736 737 case RF_8256: 738 rtl92e_set_cck_tx_power(dev, powerlevel); 739 rtl92e_set_ofdm_tx_power(dev, powerlevelOFDM24G); 740 break; 741 742 case RF_8258: 743 break; 744 default: 745 netdev_warn(dev, "%s(): Invalid RF Chip ID\n", __func__); 746 break; 747 } 748 } 749 750 static u8 _rtl92e_phy_set_sw_chnl_cmd_array(struct net_device *dev, 751 struct sw_chnl_cmd *CmdTable, 752 u32 CmdTableIdx, u32 CmdTableSz, 753 enum sw_chnl_cmd_id CmdID, 754 u32 Para1, u32 Para2, u32 msDelay) 755 { 756 struct sw_chnl_cmd *pCmd; 757 758 if (CmdTable == NULL) { 759 netdev_err(dev, "%s(): CmdTable cannot be NULL.\n", __func__); 760 return false; 761 } 762 if (CmdTableIdx >= CmdTableSz) { 763 netdev_err(dev, "%s(): Invalid index requested.\n", __func__); 764 return false; 765 } 766 767 pCmd = CmdTable + CmdTableIdx; 768 pCmd->CmdID = CmdID; 769 pCmd->Para1 = Para1; 770 pCmd->Para2 = Para2; 771 pCmd->msDelay = msDelay; 772 773 return true; 774 } 775 776 static u8 _rtl92e_phy_switch_channel_step(struct net_device *dev, u8 channel, 777 u8 *stage, u8 *step, u32 *delay) 778 { 779 struct r8192_priv *priv = rtllib_priv(dev); 780 struct rtllib_device *ieee = priv->rtllib; 781 u32 PreCommonCmdCnt; 782 u32 PostCommonCmdCnt; 783 u32 RfDependCmdCnt; 784 struct sw_chnl_cmd *CurrentCmd = NULL; 785 u8 eRFPath; 786 787 if (!rtllib_legal_channel(priv->rtllib, channel)) { 788 netdev_err(dev, "Invalid channel requested: %d\n", channel); 789 return true; 790 } 791 792 { 793 PreCommonCmdCnt = 0; 794 _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PreCommonCmd, 795 PreCommonCmdCnt++, 796 MAX_PRECMD_CNT, 797 CmdID_SetTxPowerLevel, 798 0, 0, 0); 799 _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PreCommonCmd, 800 PreCommonCmdCnt++, 801 MAX_PRECMD_CNT, CmdID_End, 802 0, 0, 0); 803 804 PostCommonCmdCnt = 0; 805 806 _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PostCommonCmd, 807 PostCommonCmdCnt++, 808 MAX_POSTCMD_CNT, CmdID_End, 809 0, 0, 0); 810 811 RfDependCmdCnt = 0; 812 switch (priv->rf_chip) { 813 case RF_8225: 814 if (!(channel >= 1 && channel <= 14)) { 815 netdev_err(dev, 816 "Invalid channel requested for 8225: %d\n", 817 channel); 818 return false; 819 } 820 _rtl92e_phy_set_sw_chnl_cmd_array(dev, 821 ieee->RfDependCmd, 822 RfDependCmdCnt++, 823 MAX_RFDEPENDCMD_CNT, 824 CmdID_RF_WriteReg, 825 rZebra1_Channel, 826 RF_CHANNEL_TABLE_ZEBRA[channel], 827 10); 828 _rtl92e_phy_set_sw_chnl_cmd_array(dev, 829 ieee->RfDependCmd, 830 RfDependCmdCnt++, 831 MAX_RFDEPENDCMD_CNT, 832 CmdID_End, 0, 0, 0); 833 break; 834 835 case RF_8256: 836 if (!(channel >= 1 && channel <= 14)) { 837 netdev_err(dev, 838 "Invalid channel requested for 8256: %d\n", 839 channel); 840 return false; 841 } 842 _rtl92e_phy_set_sw_chnl_cmd_array(dev, 843 ieee->RfDependCmd, 844 RfDependCmdCnt++, 845 MAX_RFDEPENDCMD_CNT, 846 CmdID_RF_WriteReg, 847 rZebra1_Channel, 848 channel, 10); 849 _rtl92e_phy_set_sw_chnl_cmd_array(dev, 850 ieee->RfDependCmd, 851 RfDependCmdCnt++, 852 MAX_RFDEPENDCMD_CNT, 853 CmdID_End, 0, 0, 0); 854 break; 855 856 case RF_8258: 857 break; 858 859 default: 860 netdev_warn(dev, "Unknown RF Chip ID\n"); 861 return false; 862 } 863 864 865 do { 866 switch (*stage) { 867 case 0: 868 CurrentCmd = &ieee->PreCommonCmd[*step]; 869 break; 870 case 1: 871 CurrentCmd = &ieee->RfDependCmd[*step]; 872 break; 873 case 2: 874 CurrentCmd = &ieee->PostCommonCmd[*step]; 875 break; 876 } 877 878 if (CurrentCmd && CurrentCmd->CmdID == CmdID_End) { 879 if ((*stage) == 2) 880 return true; 881 (*stage)++; 882 (*step) = 0; 883 continue; 884 } 885 886 if (!CurrentCmd) 887 continue; 888 switch (CurrentCmd->CmdID) { 889 case CmdID_SetTxPowerLevel: 890 if (priv->IC_Cut > VERSION_8190_BD) 891 _rtl92e_set_tx_power_level(dev, 892 channel); 893 break; 894 case CmdID_WritePortUlong: 895 rtl92e_writel(dev, CurrentCmd->Para1, 896 CurrentCmd->Para2); 897 break; 898 case CmdID_WritePortUshort: 899 rtl92e_writew(dev, CurrentCmd->Para1, 900 CurrentCmd->Para2); 901 break; 902 case CmdID_WritePortUchar: 903 rtl92e_writeb(dev, CurrentCmd->Para1, 904 CurrentCmd->Para2); 905 break; 906 case CmdID_RF_WriteReg: 907 for (eRFPath = 0; eRFPath < 908 priv->NumTotalRFPath; eRFPath++) 909 rtl92e_set_rf_reg(dev, 910 (enum rf90_radio_path)eRFPath, 911 CurrentCmd->Para1, bMask12Bits, 912 CurrentCmd->Para2<<7); 913 break; 914 default: 915 break; 916 } 917 918 break; 919 } while (true); 920 } /*for (Number of RF paths)*/ 921 922 (*delay) = CurrentCmd->msDelay; 923 (*step)++; 924 return false; 925 } 926 927 static void _rtl92e_phy_switch_channel(struct net_device *dev, u8 channel) 928 { 929 struct r8192_priv *priv = rtllib_priv(dev); 930 u32 delay = 0; 931 932 while (!_rtl92e_phy_switch_channel_step(dev, channel, 933 &priv->SwChnlStage, 934 &priv->SwChnlStep, &delay)) { 935 if (delay > 0) 936 msleep(delay); 937 if (!priv->up) 938 break; 939 } 940 } 941 942 static void _rtl92e_phy_switch_channel_work_item(struct net_device *dev) 943 { 944 945 struct r8192_priv *priv = rtllib_priv(dev); 946 947 _rtl92e_phy_switch_channel(dev, priv->chan); 948 } 949 950 u8 rtl92e_set_channel(struct net_device *dev, u8 channel) 951 { 952 struct r8192_priv *priv = rtllib_priv(dev); 953 954 if (!priv->up) { 955 netdev_err(dev, "%s(): Driver is not initialized\n", __func__); 956 return false; 957 } 958 if (priv->SwChnlInProgress) 959 return false; 960 961 962 switch (priv->rtllib->mode) { 963 case WIRELESS_MODE_A: 964 case WIRELESS_MODE_N_5G: 965 if (channel <= 14) { 966 netdev_warn(dev, 967 "Channel %d not available in 802.11a.\n", 968 channel); 969 return false; 970 } 971 break; 972 case WIRELESS_MODE_B: 973 if (channel > 14) { 974 netdev_warn(dev, 975 "Channel %d not available in 802.11b.\n", 976 channel); 977 return false; 978 } 979 break; 980 case WIRELESS_MODE_G: 981 case WIRELESS_MODE_N_24G: 982 if (channel > 14) { 983 netdev_warn(dev, 984 "Channel %d not available in 802.11g.\n", 985 channel); 986 return false; 987 } 988 break; 989 } 990 991 priv->SwChnlInProgress = true; 992 if (channel == 0) 993 channel = 1; 994 995 priv->chan = channel; 996 997 priv->SwChnlStage = 0; 998 priv->SwChnlStep = 0; 999 1000 if (priv->up) 1001 _rtl92e_phy_switch_channel_work_item(dev); 1002 priv->SwChnlInProgress = false; 1003 return true; 1004 } 1005 1006 static void _rtl92e_cck_tx_power_track_bw_switch_tssi(struct net_device *dev) 1007 { 1008 struct r8192_priv *priv = rtllib_priv(dev); 1009 1010 switch (priv->CurrentChannelBW) { 1011 case HT_CHANNEL_WIDTH_20: 1012 priv->CCKPresentAttentuation = 1013 priv->CCKPresentAttentuation_20Mdefault + 1014 priv->CCKPresentAttentuation_difference; 1015 1016 if (priv->CCKPresentAttentuation > 1017 (CCKTxBBGainTableLength-1)) 1018 priv->CCKPresentAttentuation = 1019 CCKTxBBGainTableLength-1; 1020 if (priv->CCKPresentAttentuation < 0) 1021 priv->CCKPresentAttentuation = 0; 1022 1023 if (priv->rtllib->current_network.channel == 14 && 1024 !priv->bcck_in_ch14) { 1025 priv->bcck_in_ch14 = true; 1026 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1027 } else if (priv->rtllib->current_network.channel != 1028 14 && priv->bcck_in_ch14) { 1029 priv->bcck_in_ch14 = false; 1030 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1031 } else { 1032 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1033 } 1034 break; 1035 1036 case HT_CHANNEL_WIDTH_20_40: 1037 priv->CCKPresentAttentuation = 1038 priv->CCKPresentAttentuation_40Mdefault + 1039 priv->CCKPresentAttentuation_difference; 1040 1041 if (priv->CCKPresentAttentuation > 1042 (CCKTxBBGainTableLength - 1)) 1043 priv->CCKPresentAttentuation = 1044 CCKTxBBGainTableLength-1; 1045 if (priv->CCKPresentAttentuation < 0) 1046 priv->CCKPresentAttentuation = 0; 1047 1048 if (priv->rtllib->current_network.channel == 14 && 1049 !priv->bcck_in_ch14) { 1050 priv->bcck_in_ch14 = true; 1051 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1052 } else if (priv->rtllib->current_network.channel != 14 1053 && priv->bcck_in_ch14) { 1054 priv->bcck_in_ch14 = false; 1055 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1056 } else { 1057 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1058 } 1059 break; 1060 } 1061 } 1062 1063 static void _rtl92e_cck_tx_power_track_bw_switch_thermal(struct net_device *dev) 1064 { 1065 struct r8192_priv *priv = rtllib_priv(dev); 1066 1067 if (priv->rtllib->current_network.channel == 14 && 1068 !priv->bcck_in_ch14) 1069 priv->bcck_in_ch14 = true; 1070 else if (priv->rtllib->current_network.channel != 14 && 1071 priv->bcck_in_ch14) 1072 priv->bcck_in_ch14 = false; 1073 1074 switch (priv->CurrentChannelBW) { 1075 case HT_CHANNEL_WIDTH_20: 1076 if (priv->Record_CCK_20Mindex == 0) 1077 priv->Record_CCK_20Mindex = 6; 1078 priv->CCK_index = priv->Record_CCK_20Mindex; 1079 break; 1080 1081 case HT_CHANNEL_WIDTH_20_40: 1082 priv->CCK_index = priv->Record_CCK_40Mindex; 1083 break; 1084 } 1085 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1086 } 1087 1088 static void _rtl92e_cck_tx_power_track_bw_switch(struct net_device *dev) 1089 { 1090 struct r8192_priv *priv = rtllib_priv(dev); 1091 1092 if (priv->IC_Cut >= IC_VersionCut_D) 1093 _rtl92e_cck_tx_power_track_bw_switch_tssi(dev); 1094 else 1095 _rtl92e_cck_tx_power_track_bw_switch_thermal(dev); 1096 } 1097 1098 static void _rtl92e_set_bw_mode_work_item(struct net_device *dev) 1099 { 1100 1101 struct r8192_priv *priv = rtllib_priv(dev); 1102 u8 regBwOpMode; 1103 1104 if (priv->rf_chip == RF_PSEUDO_11N) { 1105 priv->SetBWModeInProgress = false; 1106 return; 1107 } 1108 if (!priv->up) { 1109 netdev_err(dev, "%s(): Driver is not initialized\n", __func__); 1110 return; 1111 } 1112 regBwOpMode = rtl92e_readb(dev, BW_OPMODE); 1113 1114 switch (priv->CurrentChannelBW) { 1115 case HT_CHANNEL_WIDTH_20: 1116 regBwOpMode |= BW_OPMODE_20MHZ; 1117 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode); 1118 break; 1119 1120 case HT_CHANNEL_WIDTH_20_40: 1121 regBwOpMode &= ~BW_OPMODE_20MHZ; 1122 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode); 1123 break; 1124 1125 default: 1126 netdev_err(dev, "%s(): unknown Bandwidth: %#X\n", __func__, 1127 priv->CurrentChannelBW); 1128 break; 1129 } 1130 1131 switch (priv->CurrentChannelBW) { 1132 case HT_CHANNEL_WIDTH_20: 1133 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); 1134 rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); 1135 1136 if (!priv->btxpower_tracking) { 1137 rtl92e_writel(dev, rCCK0_TxFilter1, 0x1a1b0000); 1138 rtl92e_writel(dev, rCCK0_TxFilter2, 0x090e1317); 1139 rtl92e_writel(dev, rCCK0_DebugPort, 0x00000204); 1140 } else { 1141 _rtl92e_cck_tx_power_track_bw_switch(dev); 1142 } 1143 1144 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); 1145 1146 break; 1147 case HT_CHANNEL_WIDTH_20_40: 1148 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); 1149 rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); 1150 1151 if (!priv->btxpower_tracking) { 1152 rtl92e_writel(dev, rCCK0_TxFilter1, 0x35360000); 1153 rtl92e_writel(dev, rCCK0_TxFilter2, 0x121c252e); 1154 rtl92e_writel(dev, rCCK0_DebugPort, 0x00000409); 1155 } else { 1156 _rtl92e_cck_tx_power_track_bw_switch(dev); 1157 } 1158 1159 rtl92e_set_bb_reg(dev, rCCK0_System, bCCKSideBand, 1160 (priv->nCur40MhzPrimeSC>>1)); 1161 rtl92e_set_bb_reg(dev, rOFDM1_LSTF, 0xC00, 1162 priv->nCur40MhzPrimeSC); 1163 1164 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); 1165 break; 1166 default: 1167 netdev_err(dev, "%s(): unknown Bandwidth: %#X\n", __func__, 1168 priv->CurrentChannelBW); 1169 break; 1170 1171 } 1172 1173 switch (priv->rf_chip) { 1174 case RF_8225: 1175 break; 1176 1177 case RF_8256: 1178 rtl92e_set_bandwidth(dev, priv->CurrentChannelBW); 1179 break; 1180 1181 case RF_8258: 1182 break; 1183 1184 case RF_PSEUDO_11N: 1185 break; 1186 1187 default: 1188 netdev_info(dev, "%s(): Unknown RFChipID: %d\n", __func__, 1189 priv->rf_chip); 1190 break; 1191 } 1192 1193 atomic_dec(&(priv->rtllib->atm_swbw)); 1194 priv->SetBWModeInProgress = false; 1195 } 1196 1197 void rtl92e_set_bw_mode(struct net_device *dev, enum ht_channel_width bandwidth, 1198 enum ht_extchnl_offset Offset) 1199 { 1200 struct r8192_priv *priv = rtllib_priv(dev); 1201 1202 1203 if (priv->SetBWModeInProgress) 1204 return; 1205 1206 atomic_inc(&(priv->rtllib->atm_swbw)); 1207 priv->SetBWModeInProgress = true; 1208 1209 priv->CurrentChannelBW = bandwidth; 1210 1211 if (Offset == HT_EXTCHNL_OFFSET_LOWER) 1212 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; 1213 else if (Offset == HT_EXTCHNL_OFFSET_UPPER) 1214 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; 1215 else 1216 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; 1217 1218 _rtl92e_set_bw_mode_work_item(dev); 1219 1220 } 1221 1222 void rtl92e_init_gain(struct net_device *dev, u8 Operation) 1223 { 1224 #define SCAN_RX_INITIAL_GAIN 0x17 1225 #define POWER_DETECTION_TH 0x08 1226 struct r8192_priv *priv = rtllib_priv(dev); 1227 u32 BitMask; 1228 u8 initial_gain; 1229 1230 if (priv->up) { 1231 switch (Operation) { 1232 case IG_Backup: 1233 initial_gain = SCAN_RX_INITIAL_GAIN; 1234 BitMask = bMaskByte0; 1235 if (dm_digtable.dig_algorithm == 1236 DIG_ALGO_BY_FALSE_ALARM) 1237 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8); 1238 priv->initgain_backup.xaagccore1 = 1239 rtl92e_get_bb_reg(dev, rOFDM0_XAAGCCore1, 1240 BitMask); 1241 priv->initgain_backup.xbagccore1 = 1242 rtl92e_get_bb_reg(dev, rOFDM0_XBAGCCore1, 1243 BitMask); 1244 priv->initgain_backup.xcagccore1 = 1245 rtl92e_get_bb_reg(dev, rOFDM0_XCAGCCore1, 1246 BitMask); 1247 priv->initgain_backup.xdagccore1 = 1248 rtl92e_get_bb_reg(dev, rOFDM0_XDAGCCore1, 1249 BitMask); 1250 BitMask = bMaskByte2; 1251 priv->initgain_backup.cca = (u8)rtl92e_get_bb_reg(dev, 1252 rCCK0_CCA, BitMask); 1253 1254 rtl92e_writeb(dev, rOFDM0_XAAGCCore1, initial_gain); 1255 rtl92e_writeb(dev, rOFDM0_XBAGCCore1, initial_gain); 1256 rtl92e_writeb(dev, rOFDM0_XCAGCCore1, initial_gain); 1257 rtl92e_writeb(dev, rOFDM0_XDAGCCore1, initial_gain); 1258 rtl92e_writeb(dev, 0xa0a, POWER_DETECTION_TH); 1259 break; 1260 case IG_Restore: 1261 BitMask = 0x7f; 1262 if (dm_digtable.dig_algorithm == 1263 DIG_ALGO_BY_FALSE_ALARM) 1264 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8); 1265 1266 rtl92e_set_bb_reg(dev, rOFDM0_XAAGCCore1, BitMask, 1267 (u32)priv->initgain_backup.xaagccore1); 1268 rtl92e_set_bb_reg(dev, rOFDM0_XBAGCCore1, BitMask, 1269 (u32)priv->initgain_backup.xbagccore1); 1270 rtl92e_set_bb_reg(dev, rOFDM0_XCAGCCore1, BitMask, 1271 (u32)priv->initgain_backup.xcagccore1); 1272 rtl92e_set_bb_reg(dev, rOFDM0_XDAGCCore1, BitMask, 1273 (u32)priv->initgain_backup.xdagccore1); 1274 BitMask = bMaskByte2; 1275 rtl92e_set_bb_reg(dev, rCCK0_CCA, BitMask, 1276 (u32)priv->initgain_backup.cca); 1277 1278 rtl92e_set_tx_power(dev, 1279 priv->rtllib->current_network.channel); 1280 1281 if (dm_digtable.dig_algorithm == 1282 DIG_ALGO_BY_FALSE_ALARM) 1283 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x1); 1284 break; 1285 } 1286 } 1287 } 1288 1289 void rtl92e_set_rf_off(struct net_device *dev) 1290 { 1291 1292 rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); 1293 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0); 1294 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); 1295 rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0); 1296 rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0); 1297 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); 1298 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0); 1299 rtl92e_writeb(dev, ANAPAR_FOR_8192PciE, 0x07); 1300 1301 } 1302 1303 static bool _rtl92e_set_rf_power_state(struct net_device *dev, 1304 enum rt_rf_power_state rf_power_state) 1305 { 1306 struct r8192_priv *priv = rtllib_priv(dev); 1307 struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *) 1308 (&(priv->rtllib->PowerSaveControl)); 1309 bool bResult = true; 1310 u8 i = 0, QueueID = 0; 1311 struct rtl8192_tx_ring *ring = NULL; 1312 1313 if (priv->SetRFPowerStateInProgress) 1314 return false; 1315 priv->SetRFPowerStateInProgress = true; 1316 1317 switch (priv->rf_chip) { 1318 case RF_8256: 1319 switch (rf_power_state) { 1320 case rf_on: 1321 if ((priv->rtllib->rf_power_state == rf_off) && 1322 RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) { 1323 bool rtstatus; 1324 u32 InitilizeCount = 3; 1325 1326 do { 1327 InitilizeCount--; 1328 priv->RegRfOff = false; 1329 rtstatus = rtl92e_enable_nic(dev); 1330 } while (!rtstatus && (InitilizeCount > 0)); 1331 1332 if (!rtstatus) { 1333 netdev_err(dev, 1334 "%s(): Failed to initialize Adapter.\n", 1335 __func__); 1336 priv->SetRFPowerStateInProgress = false; 1337 return false; 1338 } 1339 1340 RT_CLEAR_PS_LEVEL(pPSC, 1341 RT_RF_OFF_LEVL_HALT_NIC); 1342 } else { 1343 rtl92e_writeb(dev, ANAPAR, 0x37); 1344 mdelay(1); 1345 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 1346 0x4, 0x1); 1347 priv->bHwRfOffAction = 0; 1348 1349 rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE, 1350 BIT4, 0x1); 1351 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 1352 0x300, 0x3); 1353 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 1354 0x18, 0x3); 1355 rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable, 1356 0x3, 0x3); 1357 rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable, 1358 0x3, 0x3); 1359 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 1360 0x60, 0x3); 1361 1362 } 1363 1364 break; 1365 1366 case rf_sleep: 1367 if (priv->rtllib->rf_power_state == rf_off) 1368 break; 1369 1370 1371 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) { 1372 ring = &priv->tx_ring[QueueID]; 1373 1374 if (skb_queue_len(&ring->queue) == 0) { 1375 QueueID++; 1376 continue; 1377 } else { 1378 udelay(10); 1379 i++; 1380 } 1381 1382 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 1383 break; 1384 } 1385 } 1386 rtl92e_set_rf_off(dev); 1387 break; 1388 1389 case rf_off: 1390 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) { 1391 ring = &priv->tx_ring[QueueID]; 1392 1393 if (skb_queue_len(&ring->queue) == 0) { 1394 QueueID++; 1395 continue; 1396 } else { 1397 udelay(10); 1398 i++; 1399 } 1400 1401 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 1402 break; 1403 } 1404 } 1405 1406 if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && 1407 !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) { 1408 rtl92e_disable_nic(dev); 1409 RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); 1410 } else if (!(pPSC->RegRfPsLevel & 1411 RT_RF_OFF_LEVL_HALT_NIC)) { 1412 rtl92e_set_rf_off(dev); 1413 } 1414 1415 break; 1416 1417 default: 1418 bResult = false; 1419 netdev_warn(dev, 1420 "%s(): Unknown state requested: 0x%X.\n", 1421 __func__, rf_power_state); 1422 break; 1423 } 1424 1425 break; 1426 1427 default: 1428 netdev_warn(dev, "%s(): Unknown RF type\n", __func__); 1429 break; 1430 } 1431 1432 if (bResult) { 1433 priv->rtllib->rf_power_state = rf_power_state; 1434 1435 switch (priv->rf_chip) { 1436 case RF_8256: 1437 break; 1438 1439 default: 1440 netdev_warn(dev, "%s(): Unknown RF type\n", __func__); 1441 break; 1442 } 1443 } 1444 1445 priv->SetRFPowerStateInProgress = false; 1446 return bResult; 1447 } 1448 1449 bool rtl92e_set_rf_power_state(struct net_device *dev, 1450 enum rt_rf_power_state rf_power_state) 1451 { 1452 struct r8192_priv *priv = rtllib_priv(dev); 1453 1454 bool bResult = false; 1455 1456 if (rf_power_state == priv->rtllib->rf_power_state && 1457 priv->bHwRfOffAction == 0) { 1458 return bResult; 1459 } 1460 1461 bResult = _rtl92e_set_rf_power_state(dev, rf_power_state); 1462 return bResult; 1463 } 1464 1465 void rtl92e_scan_op_backup(struct net_device *dev, u8 Operation) 1466 { 1467 struct r8192_priv *priv = rtllib_priv(dev); 1468 1469 if (priv->up) { 1470 switch (Operation) { 1471 case SCAN_OPT_BACKUP: 1472 priv->rtllib->InitialGainHandler(dev, IG_Backup); 1473 break; 1474 1475 case SCAN_OPT_RESTORE: 1476 priv->rtllib->InitialGainHandler(dev, IG_Restore); 1477 break; 1478 } 1479 } 1480 } 1481