1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. 4 * 5 * Contact Information: wlanfae <wlanfae@realtek.com> 6 */ 7 #include <linux/bitops.h> 8 #include "rtl_core.h" 9 #include "r8192E_hw.h" 10 #include "r8192E_phyreg.h" 11 #include "r8190P_rtl8256.h" 12 #include "r8192E_phy.h" 13 #include "rtl_dm.h" 14 15 #include "r8192E_hwimg.h" 16 17 static u32 RF_CHANNEL_TABLE_ZEBRA[] = { 18 0, 19 0x085c, 20 0x08dc, 21 0x095c, 22 0x09dc, 23 0x0a5c, 24 0x0adc, 25 0x0b5c, 26 0x0bdc, 27 0x0c5c, 28 0x0cdc, 29 0x0d5c, 30 0x0ddc, 31 0x0e5c, 32 0x0f72, 33 }; 34 35 /*************************Define local function prototype**********************/ 36 37 static u32 _rtl92e_phy_rf_fw_read(struct net_device *dev, 38 enum rf90_radio_path eRFPath, u32 Offset); 39 static void _rtl92e_phy_rf_fw_write(struct net_device *dev, 40 enum rf90_radio_path eRFPath, u32 Offset, 41 u32 Data); 42 43 static u32 _rtl92e_calculate_bit_shift(u32 dwBitMask) 44 { 45 if (!dwBitMask) 46 return 32; 47 return ffs(dwBitMask) - 1; 48 } 49 50 u8 rtl92e_is_legal_rf_path(struct net_device *dev, u32 eRFPath) 51 { 52 u8 ret = 1; 53 struct r8192_priv *priv = rtllib_priv(dev); 54 55 if (priv->rf_type == RF_2T4R) 56 ret = 0; 57 else if (priv->rf_type == RF_1T2R) { 58 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) 59 ret = 1; 60 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) 61 ret = 0; 62 } 63 return ret; 64 } 65 66 void rtl92e_set_bb_reg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask, 67 u32 dwData) 68 { 69 70 u32 OriginalValue, BitShift, NewValue; 71 72 if (dwBitMask != bMaskDWord) { 73 OriginalValue = rtl92e_readl(dev, dwRegAddr); 74 BitShift = _rtl92e_calculate_bit_shift(dwBitMask); 75 NewValue = (OriginalValue & ~dwBitMask) | (dwData << BitShift); 76 rtl92e_writel(dev, dwRegAddr, NewValue); 77 } else 78 rtl92e_writel(dev, dwRegAddr, dwData); 79 } 80 81 u32 rtl92e_get_bb_reg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask) 82 { 83 u32 OriginalValue, BitShift; 84 85 OriginalValue = rtl92e_readl(dev, dwRegAddr); 86 BitShift = _rtl92e_calculate_bit_shift(dwBitMask); 87 88 return (OriginalValue & dwBitMask) >> BitShift; 89 } 90 91 static u32 _rtl92e_phy_rf_read(struct net_device *dev, 92 enum rf90_radio_path eRFPath, u32 Offset) 93 { 94 struct r8192_priv *priv = rtllib_priv(dev); 95 u32 ret = 0; 96 u32 NewOffset = 0; 97 struct bb_reg_definition *pPhyReg = &priv->phy_reg_def[eRFPath]; 98 99 Offset &= 0x3f; 100 101 if (priv->rf_chip == RF_8256) { 102 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); 103 if (Offset >= 31) { 104 priv->rf_reg_0value[eRFPath] |= 0x140; 105 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, 106 bMaskDWord, 107 (priv->rf_reg_0value[eRFPath] << 16)); 108 NewOffset = Offset - 30; 109 } else if (Offset >= 16) { 110 priv->rf_reg_0value[eRFPath] |= 0x100; 111 priv->rf_reg_0value[eRFPath] &= (~0x40); 112 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, 113 bMaskDWord, 114 (priv->rf_reg_0value[eRFPath] << 16)); 115 116 NewOffset = Offset - 15; 117 } else 118 NewOffset = Offset; 119 } else { 120 NewOffset = Offset; 121 } 122 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, 123 NewOffset); 124 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); 125 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); 126 127 mdelay(1); 128 129 ret = rtl92e_get_bb_reg(dev, pPhyReg->rfLSSIReadBack, 130 bLSSIReadBackData); 131 132 if (priv->rf_chip == RF_8256) { 133 priv->rf_reg_0value[eRFPath] &= 0xebf; 134 135 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, 136 (priv->rf_reg_0value[eRFPath] << 16)); 137 138 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); 139 } 140 141 142 return ret; 143 144 } 145 146 static void _rtl92e_phy_rf_write(struct net_device *dev, 147 enum rf90_radio_path eRFPath, u32 Offset, 148 u32 Data) 149 { 150 struct r8192_priv *priv = rtllib_priv(dev); 151 u32 DataAndAddr = 0, NewOffset = 0; 152 struct bb_reg_definition *pPhyReg = &priv->phy_reg_def[eRFPath]; 153 154 Offset &= 0x3f; 155 if (priv->rf_chip == RF_8256) { 156 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); 157 158 if (Offset >= 31) { 159 priv->rf_reg_0value[eRFPath] |= 0x140; 160 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, 161 bMaskDWord, 162 (priv->rf_reg_0value[eRFPath] << 16)); 163 NewOffset = Offset - 30; 164 } else if (Offset >= 16) { 165 priv->rf_reg_0value[eRFPath] |= 0x100; 166 priv->rf_reg_0value[eRFPath] &= (~0x40); 167 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, 168 bMaskDWord, 169 (priv->rf_reg_0value[eRFPath] << 16)); 170 NewOffset = Offset - 15; 171 } else 172 NewOffset = Offset; 173 } else { 174 NewOffset = Offset; 175 } 176 177 DataAndAddr = (NewOffset & 0x3f) | (Data << 16); 178 179 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); 180 181 if (Offset == 0x0) 182 priv->rf_reg_0value[eRFPath] = Data; 183 184 if (priv->rf_chip == RF_8256) { 185 if (Offset != 0) { 186 priv->rf_reg_0value[eRFPath] &= 0xebf; 187 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, 188 bMaskDWord, 189 (priv->rf_reg_0value[eRFPath] << 16)); 190 } 191 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); 192 } 193 } 194 195 void rtl92e_set_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath, 196 u32 RegAddr, u32 BitMask, u32 Data) 197 { 198 struct r8192_priv *priv = rtllib_priv(dev); 199 u32 Original_Value, BitShift, New_Value; 200 201 if (!rtl92e_is_legal_rf_path(dev, eRFPath)) 202 return; 203 if (priv->rtllib->rf_power_state != rf_on && !priv->being_init_adapter) 204 return; 205 206 if (priv->rf_mode == RF_OP_By_FW) { 207 if (BitMask != bMask12Bits) { 208 Original_Value = _rtl92e_phy_rf_fw_read(dev, eRFPath, 209 RegAddr); 210 BitShift = _rtl92e_calculate_bit_shift(BitMask); 211 New_Value = (Original_Value & ~BitMask) | (Data << BitShift); 212 213 _rtl92e_phy_rf_fw_write(dev, eRFPath, RegAddr, 214 New_Value); 215 } else 216 _rtl92e_phy_rf_fw_write(dev, eRFPath, RegAddr, Data); 217 udelay(200); 218 219 } else { 220 if (BitMask != bMask12Bits) { 221 Original_Value = _rtl92e_phy_rf_read(dev, eRFPath, 222 RegAddr); 223 BitShift = _rtl92e_calculate_bit_shift(BitMask); 224 New_Value = (Original_Value & ~BitMask) | (Data << BitShift); 225 226 _rtl92e_phy_rf_write(dev, eRFPath, RegAddr, New_Value); 227 } else 228 _rtl92e_phy_rf_write(dev, eRFPath, RegAddr, Data); 229 } 230 } 231 232 u32 rtl92e_get_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath, 233 u32 RegAddr, u32 BitMask) 234 { 235 u32 Original_Value, Readback_Value, BitShift; 236 struct r8192_priv *priv = rtllib_priv(dev); 237 238 if (!rtl92e_is_legal_rf_path(dev, eRFPath)) 239 return 0; 240 if (priv->rtllib->rf_power_state != rf_on && !priv->being_init_adapter) 241 return 0; 242 mutex_lock(&priv->rf_mutex); 243 if (priv->rf_mode == RF_OP_By_FW) { 244 Original_Value = _rtl92e_phy_rf_fw_read(dev, eRFPath, RegAddr); 245 udelay(200); 246 } else { 247 Original_Value = _rtl92e_phy_rf_read(dev, eRFPath, RegAddr); 248 } 249 BitShift = _rtl92e_calculate_bit_shift(BitMask); 250 Readback_Value = (Original_Value & BitMask) >> BitShift; 251 mutex_unlock(&priv->rf_mutex); 252 return Readback_Value; 253 } 254 255 static u32 _rtl92e_phy_rf_fw_read(struct net_device *dev, 256 enum rf90_radio_path eRFPath, u32 Offset) 257 { 258 u32 Data = 0; 259 u8 time = 0; 260 261 Data |= ((Offset & 0xFF) << 12); 262 Data |= ((eRFPath & 0x3) << 20); 263 Data |= 0x80000000; 264 while (rtl92e_readl(dev, QPNR) & 0x80000000) { 265 if (time++ < 100) 266 udelay(10); 267 else 268 break; 269 } 270 rtl92e_writel(dev, QPNR, Data); 271 while (rtl92e_readl(dev, QPNR) & 0x80000000) { 272 if (time++ < 100) 273 udelay(10); 274 else 275 return 0; 276 } 277 return rtl92e_readl(dev, RF_DATA); 278 279 } 280 281 static void _rtl92e_phy_rf_fw_write(struct net_device *dev, 282 enum rf90_radio_path eRFPath, u32 Offset, 283 u32 Data) 284 { 285 u8 time = 0; 286 287 Data |= ((Offset & 0xFF) << 12); 288 Data |= ((eRFPath & 0x3) << 20); 289 Data |= 0x400000; 290 Data |= 0x80000000; 291 292 while (rtl92e_readl(dev, QPNR) & 0x80000000) { 293 if (time++ < 100) 294 udelay(10); 295 else 296 break; 297 } 298 rtl92e_writel(dev, QPNR, Data); 299 300 } 301 302 303 void rtl92e_config_mac(struct net_device *dev) 304 { 305 u32 dwArrayLen = 0, i = 0; 306 u32 *pdwArray = NULL; 307 struct r8192_priv *priv = rtllib_priv(dev); 308 309 if (priv->tx_pwr_data_read_from_eeprom) { 310 dwArrayLen = MACPHY_Array_PGLength; 311 pdwArray = Rtl819XMACPHY_Array_PG; 312 313 } else { 314 dwArrayLen = MACPHY_ArrayLength; 315 pdwArray = Rtl819XMACPHY_Array; 316 } 317 for (i = 0; i < dwArrayLen; i += 3) { 318 if (pdwArray[i] == 0x318) 319 pdwArray[i+2] = 0x00000800; 320 rtl92e_set_bb_reg(dev, pdwArray[i], pdwArray[i+1], 321 pdwArray[i+2]); 322 } 323 return; 324 325 } 326 327 static void _rtl92e_phy_config_bb(struct net_device *dev, u8 ConfigType) 328 { 329 int i; 330 u32 *Rtl819XPHY_REGArray_Table = NULL; 331 u32 *Rtl819XAGCTAB_Array_Table = NULL; 332 u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0; 333 struct r8192_priv *priv = rtllib_priv(dev); 334 335 AGCTAB_ArrayLen = AGCTAB_ArrayLength; 336 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array; 337 if (priv->rf_type == RF_2T4R) { 338 PHY_REGArrayLen = PHY_REGArrayLength; 339 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray; 340 } else if (priv->rf_type == RF_1T2R) { 341 PHY_REGArrayLen = PHY_REG_1T2RArrayLength; 342 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray; 343 } 344 345 if (ConfigType == BB_CONFIG_PHY_REG) { 346 for (i = 0; i < PHY_REGArrayLen; i += 2) { 347 rtl92e_set_bb_reg(dev, Rtl819XPHY_REGArray_Table[i], 348 bMaskDWord, 349 Rtl819XPHY_REGArray_Table[i+1]); 350 } 351 } else if (ConfigType == BB_CONFIG_AGC_TAB) { 352 for (i = 0; i < AGCTAB_ArrayLen; i += 2) { 353 rtl92e_set_bb_reg(dev, Rtl819XAGCTAB_Array_Table[i], 354 bMaskDWord, 355 Rtl819XAGCTAB_Array_Table[i+1]); 356 } 357 } 358 } 359 360 static void _rtl92e_init_bb_rf_reg_def(struct net_device *dev) 361 { 362 struct r8192_priv *priv = rtllib_priv(dev); 363 364 priv->phy_reg_def[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; 365 priv->phy_reg_def[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; 366 priv->phy_reg_def[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; 367 priv->phy_reg_def[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW; 368 369 priv->phy_reg_def[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; 370 priv->phy_reg_def[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB; 371 priv->phy_reg_def[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB; 372 priv->phy_reg_def[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB; 373 374 priv->phy_reg_def[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; 375 priv->phy_reg_def[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; 376 priv->phy_reg_def[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE; 377 priv->phy_reg_def[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE; 378 379 priv->phy_reg_def[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; 380 priv->phy_reg_def[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; 381 priv->phy_reg_def[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE; 382 priv->phy_reg_def[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE; 383 384 priv->phy_reg_def[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; 385 priv->phy_reg_def[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; 386 priv->phy_reg_def[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; 387 priv->phy_reg_def[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; 388 389 priv->phy_reg_def[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; 390 priv->phy_reg_def[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; 391 priv->phy_reg_def[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; 392 priv->phy_reg_def[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; 393 394 priv->phy_reg_def[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; 395 priv->phy_reg_def[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; 396 priv->phy_reg_def[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; 397 priv->phy_reg_def[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; 398 399 priv->phy_reg_def[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; 400 priv->phy_reg_def[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; 401 priv->phy_reg_def[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; 402 priv->phy_reg_def[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; 403 404 priv->phy_reg_def[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; 405 priv->phy_reg_def[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; 406 priv->phy_reg_def[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; 407 priv->phy_reg_def[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; 408 409 priv->phy_reg_def[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; 410 priv->phy_reg_def[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; 411 priv->phy_reg_def[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; 412 priv->phy_reg_def[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; 413 414 priv->phy_reg_def[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; 415 priv->phy_reg_def[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; 416 priv->phy_reg_def[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; 417 priv->phy_reg_def[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; 418 419 priv->phy_reg_def[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; 420 priv->phy_reg_def[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; 421 priv->phy_reg_def[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; 422 priv->phy_reg_def[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; 423 424 priv->phy_reg_def[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; 425 priv->phy_reg_def[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; 426 priv->phy_reg_def[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; 427 priv->phy_reg_def[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; 428 429 priv->phy_reg_def[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; 430 priv->phy_reg_def[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; 431 priv->phy_reg_def[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; 432 priv->phy_reg_def[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; 433 434 priv->phy_reg_def[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; 435 priv->phy_reg_def[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; 436 priv->phy_reg_def[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; 437 priv->phy_reg_def[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; 438 439 priv->phy_reg_def[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; 440 priv->phy_reg_def[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; 441 priv->phy_reg_def[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; 442 priv->phy_reg_def[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; 443 444 priv->phy_reg_def[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; 445 priv->phy_reg_def[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; 446 priv->phy_reg_def[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; 447 priv->phy_reg_def[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; 448 449 } 450 451 bool rtl92e_check_bb_and_rf(struct net_device *dev, enum hw90_block CheckBlock, 452 enum rf90_radio_path eRFPath) 453 { 454 bool ret = true; 455 u32 i, CheckTimes = 4, dwRegRead = 0; 456 u32 WriteAddr[4]; 457 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f}; 458 459 WriteAddr[HW90_BLOCK_MAC] = 0x100; 460 WriteAddr[HW90_BLOCK_PHY0] = 0x900; 461 WriteAddr[HW90_BLOCK_PHY1] = 0x800; 462 WriteAddr[HW90_BLOCK_RF] = 0x3; 463 464 if (CheckBlock == HW90_BLOCK_MAC) { 465 netdev_warn(dev, "%s(): No checks available for MAC block.\n", 466 __func__); 467 return ret; 468 } 469 470 for (i = 0; i < CheckTimes; i++) { 471 switch (CheckBlock) { 472 case HW90_BLOCK_PHY0: 473 case HW90_BLOCK_PHY1: 474 rtl92e_writel(dev, WriteAddr[CheckBlock], 475 WriteData[i]); 476 dwRegRead = rtl92e_readl(dev, WriteAddr[CheckBlock]); 477 break; 478 479 case HW90_BLOCK_RF: 480 WriteData[i] &= 0xfff; 481 rtl92e_set_rf_reg(dev, eRFPath, 482 WriteAddr[HW90_BLOCK_RF], 483 bMask12Bits, WriteData[i]); 484 mdelay(10); 485 dwRegRead = rtl92e_get_rf_reg(dev, eRFPath, 486 WriteAddr[HW90_BLOCK_RF], 487 bMaskDWord); 488 mdelay(10); 489 break; 490 491 default: 492 ret = false; 493 break; 494 } 495 496 497 if (dwRegRead != WriteData[i]) { 498 netdev_warn(dev, "%s(): Check failed.\n", __func__); 499 ret = false; 500 break; 501 } 502 } 503 504 return ret; 505 } 506 507 static bool _rtl92e_bb_config_para_file(struct net_device *dev) 508 { 509 struct r8192_priv *priv = rtllib_priv(dev); 510 bool rtStatus = true; 511 u8 bRegValue = 0, eCheckItem = 0; 512 u32 dwRegValue = 0; 513 514 bRegValue = rtl92e_readb(dev, BB_GLOBAL_RESET); 515 rtl92e_writeb(dev, BB_GLOBAL_RESET, (bRegValue|BB_GLOBAL_RESET_BIT)); 516 517 dwRegValue = rtl92e_readl(dev, CPU_GEN); 518 rtl92e_writel(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST))); 519 520 for (eCheckItem = (enum hw90_block)HW90_BLOCK_PHY0; 521 eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) { 522 rtStatus = rtl92e_check_bb_and_rf(dev, 523 (enum hw90_block)eCheckItem, 524 (enum rf90_radio_path)0); 525 if (!rtStatus) 526 return rtStatus; 527 } 528 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); 529 _rtl92e_phy_config_bb(dev, BB_CONFIG_PHY_REG); 530 531 dwRegValue = rtl92e_readl(dev, CPU_GEN); 532 rtl92e_writel(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST)); 533 534 _rtl92e_phy_config_bb(dev, BB_CONFIG_AGC_TAB); 535 536 if (priv->ic_cut > VERSION_8190_BD) { 537 if (priv->rf_type == RF_2T4R) 538 dwRegValue = priv->antenna_tx_pwr_diff[2] << 8 | 539 priv->antenna_tx_pwr_diff[1] << 4 | 540 priv->antenna_tx_pwr_diff[0]; 541 else 542 dwRegValue = 0x0; 543 rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage, 544 (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue); 545 546 547 dwRegValue = priv->crystal_cap; 548 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, 549 dwRegValue); 550 } 551 552 return rtStatus; 553 } 554 bool rtl92e_config_bb(struct net_device *dev) 555 { 556 _rtl92e_init_bb_rf_reg_def(dev); 557 return _rtl92e_bb_config_para_file(dev); 558 } 559 560 void rtl92e_get_tx_power(struct net_device *dev) 561 { 562 struct r8192_priv *priv = rtllib_priv(dev); 563 564 priv->mcs_tx_pwr_level_org_offset[0] = 565 rtl92e_readl(dev, rTxAGC_Rate18_06); 566 priv->mcs_tx_pwr_level_org_offset[1] = 567 rtl92e_readl(dev, rTxAGC_Rate54_24); 568 priv->mcs_tx_pwr_level_org_offset[2] = 569 rtl92e_readl(dev, rTxAGC_Mcs03_Mcs00); 570 priv->mcs_tx_pwr_level_org_offset[3] = 571 rtl92e_readl(dev, rTxAGC_Mcs07_Mcs04); 572 priv->mcs_tx_pwr_level_org_offset[4] = 573 rtl92e_readl(dev, rTxAGC_Mcs11_Mcs08); 574 priv->mcs_tx_pwr_level_org_offset[5] = 575 rtl92e_readl(dev, rTxAGC_Mcs15_Mcs12); 576 577 priv->def_initial_gain[0] = rtl92e_readb(dev, rOFDM0_XAAGCCore1); 578 priv->def_initial_gain[1] = rtl92e_readb(dev, rOFDM0_XBAGCCore1); 579 priv->def_initial_gain[2] = rtl92e_readb(dev, rOFDM0_XCAGCCore1); 580 priv->def_initial_gain[3] = rtl92e_readb(dev, rOFDM0_XDAGCCore1); 581 582 priv->framesync = rtl92e_readb(dev, rOFDM0_RxDetector3); 583 } 584 585 void rtl92e_set_tx_power(struct net_device *dev, u8 channel) 586 { 587 struct r8192_priv *priv = rtllib_priv(dev); 588 u8 powerlevel = 0, powerlevelOFDM24G = 0; 589 590 if (priv->epromtype == EEPROM_93C46) { 591 powerlevel = priv->tx_pwr_level_cck[channel - 1]; 592 powerlevelOFDM24G = priv->tx_pwr_level_ofdm_24g[channel - 1]; 593 } else if (priv->epromtype == EEPROM_93C56) { 594 if (priv->rf_type == RF_2T4R) { 595 priv->antenna_tx_pwr_diff[2] = 0; 596 priv->antenna_tx_pwr_diff[1] = 0; 597 priv->antenna_tx_pwr_diff[0] = 0; 598 599 rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage, 600 (bXBTxAGC | bXCTxAGC | bXDTxAGC), 0); 601 } 602 } 603 switch (priv->rf_chip) { 604 case RF_8225: 605 break; 606 case RF_8256: 607 rtl92e_set_cck_tx_power(dev, powerlevel); 608 rtl92e_set_ofdm_tx_power(dev, powerlevelOFDM24G); 609 break; 610 case RF_8258: 611 break; 612 default: 613 netdev_err(dev, "Invalid RF Chip ID.\n"); 614 break; 615 } 616 } 617 618 bool rtl92e_config_phy(struct net_device *dev) 619 { 620 struct r8192_priv *priv = rtllib_priv(dev); 621 bool rtStatus = true; 622 623 switch (priv->rf_chip) { 624 case RF_8225: 625 break; 626 case RF_8256: 627 rtStatus = rtl92e_config_rf(dev); 628 break; 629 630 case RF_8258: 631 break; 632 case RF_PSEUDO_11N: 633 break; 634 635 default: 636 netdev_err(dev, "Invalid RF Chip ID.\n"); 637 break; 638 } 639 return rtStatus; 640 } 641 642 u8 rtl92e_config_rf_path(struct net_device *dev, enum rf90_radio_path eRFPath) 643 { 644 645 int i; 646 647 switch (eRFPath) { 648 case RF90_PATH_A: 649 for (i = 0; i < RadioA_ArrayLength; i += 2) { 650 if (Rtl819XRadioA_Array[i] == 0xfe) { 651 msleep(100); 652 continue; 653 } 654 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioA_Array[i], 655 bMask12Bits, 656 Rtl819XRadioA_Array[i+1]); 657 658 } 659 break; 660 case RF90_PATH_B: 661 for (i = 0; i < RadioB_ArrayLength; i += 2) { 662 if (Rtl819XRadioB_Array[i] == 0xfe) { 663 msleep(100); 664 continue; 665 } 666 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioB_Array[i], 667 bMask12Bits, 668 Rtl819XRadioB_Array[i+1]); 669 670 } 671 break; 672 case RF90_PATH_C: 673 for (i = 0; i < RadioC_ArrayLength; i += 2) { 674 if (Rtl819XRadioC_Array[i] == 0xfe) { 675 msleep(100); 676 continue; 677 } 678 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioC_Array[i], 679 bMask12Bits, 680 Rtl819XRadioC_Array[i+1]); 681 682 } 683 break; 684 case RF90_PATH_D: 685 for (i = 0; i < RadioD_ArrayLength; i += 2) { 686 if (Rtl819XRadioD_Array[i] == 0xfe) { 687 msleep(100); 688 continue; 689 } 690 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioD_Array[i], 691 bMask12Bits, 692 Rtl819XRadioD_Array[i+1]); 693 694 } 695 break; 696 default: 697 break; 698 } 699 700 return 0; 701 702 } 703 704 static void _rtl92e_set_tx_power_level(struct net_device *dev, u8 channel) 705 { 706 struct r8192_priv *priv = rtllib_priv(dev); 707 u8 powerlevel = priv->tx_pwr_level_cck[channel - 1]; 708 u8 powerlevelOFDM24G = priv->tx_pwr_level_ofdm_24g[channel - 1]; 709 710 switch (priv->rf_chip) { 711 case RF_8225: 712 break; 713 714 case RF_8256: 715 rtl92e_set_cck_tx_power(dev, powerlevel); 716 rtl92e_set_ofdm_tx_power(dev, powerlevelOFDM24G); 717 break; 718 719 case RF_8258: 720 break; 721 default: 722 netdev_warn(dev, "%s(): Invalid RF Chip ID\n", __func__); 723 break; 724 } 725 } 726 727 static u8 _rtl92e_phy_set_sw_chnl_cmd_array(struct net_device *dev, 728 struct sw_chnl_cmd *CmdTable, 729 u32 CmdTableIdx, u32 CmdTableSz, 730 enum sw_chnl_cmd_id CmdID, 731 u32 Para1, u32 Para2, u32 msDelay) 732 { 733 struct sw_chnl_cmd *pCmd; 734 735 if (CmdTable == NULL) { 736 netdev_err(dev, "%s(): CmdTable cannot be NULL.\n", __func__); 737 return false; 738 } 739 if (CmdTableIdx >= CmdTableSz) { 740 netdev_err(dev, "%s(): Invalid index requested.\n", __func__); 741 return false; 742 } 743 744 pCmd = CmdTable + CmdTableIdx; 745 pCmd->CmdID = CmdID; 746 pCmd->Para1 = Para1; 747 pCmd->Para2 = Para2; 748 pCmd->msDelay = msDelay; 749 750 return true; 751 } 752 753 static u8 _rtl92e_phy_switch_channel_step(struct net_device *dev, u8 channel, 754 u8 *stage, u8 *step, u32 *delay) 755 { 756 struct r8192_priv *priv = rtllib_priv(dev); 757 struct rtllib_device *ieee = priv->rtllib; 758 u32 PreCommonCmdCnt; 759 u32 PostCommonCmdCnt; 760 u32 RfDependCmdCnt; 761 struct sw_chnl_cmd *CurrentCmd = NULL; 762 u8 eRFPath; 763 764 if (!rtllib_legal_channel(priv->rtllib, channel)) { 765 netdev_err(dev, "Invalid channel requested: %d\n", channel); 766 return true; 767 } 768 769 { 770 PreCommonCmdCnt = 0; 771 _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PreCommonCmd, 772 PreCommonCmdCnt++, 773 MAX_PRECMD_CNT, 774 CmdID_SetTxPowerLevel, 775 0, 0, 0); 776 _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PreCommonCmd, 777 PreCommonCmdCnt++, 778 MAX_PRECMD_CNT, CmdID_End, 779 0, 0, 0); 780 781 PostCommonCmdCnt = 0; 782 783 _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PostCommonCmd, 784 PostCommonCmdCnt++, 785 MAX_POSTCMD_CNT, CmdID_End, 786 0, 0, 0); 787 788 RfDependCmdCnt = 0; 789 switch (priv->rf_chip) { 790 case RF_8225: 791 if (!(channel >= 1 && channel <= 14)) { 792 netdev_err(dev, 793 "Invalid channel requested for 8225: %d\n", 794 channel); 795 return false; 796 } 797 _rtl92e_phy_set_sw_chnl_cmd_array(dev, 798 ieee->RfDependCmd, 799 RfDependCmdCnt++, 800 MAX_RFDEPENDCMD_CNT, 801 CmdID_RF_WriteReg, 802 rZebra1_Channel, 803 RF_CHANNEL_TABLE_ZEBRA[channel], 804 10); 805 _rtl92e_phy_set_sw_chnl_cmd_array(dev, 806 ieee->RfDependCmd, 807 RfDependCmdCnt++, 808 MAX_RFDEPENDCMD_CNT, 809 CmdID_End, 0, 0, 0); 810 break; 811 812 case RF_8256: 813 if (!(channel >= 1 && channel <= 14)) { 814 netdev_err(dev, 815 "Invalid channel requested for 8256: %d\n", 816 channel); 817 return false; 818 } 819 _rtl92e_phy_set_sw_chnl_cmd_array(dev, 820 ieee->RfDependCmd, 821 RfDependCmdCnt++, 822 MAX_RFDEPENDCMD_CNT, 823 CmdID_RF_WriteReg, 824 rZebra1_Channel, 825 channel, 10); 826 _rtl92e_phy_set_sw_chnl_cmd_array(dev, 827 ieee->RfDependCmd, 828 RfDependCmdCnt++, 829 MAX_RFDEPENDCMD_CNT, 830 CmdID_End, 0, 0, 0); 831 break; 832 833 case RF_8258: 834 break; 835 836 default: 837 netdev_warn(dev, "Unknown RF Chip ID\n"); 838 return false; 839 } 840 841 842 do { 843 switch (*stage) { 844 case 0: 845 CurrentCmd = &ieee->PreCommonCmd[*step]; 846 break; 847 case 1: 848 CurrentCmd = &ieee->RfDependCmd[*step]; 849 break; 850 case 2: 851 CurrentCmd = &ieee->PostCommonCmd[*step]; 852 break; 853 } 854 855 if (CurrentCmd && CurrentCmd->CmdID == CmdID_End) { 856 if ((*stage) == 2) 857 return true; 858 (*stage)++; 859 (*step) = 0; 860 continue; 861 } 862 863 if (!CurrentCmd) 864 continue; 865 switch (CurrentCmd->CmdID) { 866 case CmdID_SetTxPowerLevel: 867 if (priv->ic_cut > VERSION_8190_BD) 868 _rtl92e_set_tx_power_level(dev, 869 channel); 870 break; 871 case CmdID_WritePortUlong: 872 rtl92e_writel(dev, CurrentCmd->Para1, 873 CurrentCmd->Para2); 874 break; 875 case CmdID_WritePortUshort: 876 rtl92e_writew(dev, CurrentCmd->Para1, 877 CurrentCmd->Para2); 878 break; 879 case CmdID_WritePortUchar: 880 rtl92e_writeb(dev, CurrentCmd->Para1, 881 CurrentCmd->Para2); 882 break; 883 case CmdID_RF_WriteReg: 884 for (eRFPath = 0; eRFPath < 885 priv->num_total_rf_path; eRFPath++) 886 rtl92e_set_rf_reg(dev, 887 (enum rf90_radio_path)eRFPath, 888 CurrentCmd->Para1, bMask12Bits, 889 CurrentCmd->Para2<<7); 890 break; 891 default: 892 break; 893 } 894 895 break; 896 } while (true); 897 } /*for (Number of RF paths)*/ 898 899 (*delay) = CurrentCmd->msDelay; 900 (*step)++; 901 return false; 902 } 903 904 static void _rtl92e_phy_switch_channel(struct net_device *dev, u8 channel) 905 { 906 struct r8192_priv *priv = rtllib_priv(dev); 907 u32 delay = 0; 908 909 while (!_rtl92e_phy_switch_channel_step(dev, channel, 910 &priv->sw_chnl_stage, 911 &priv->sw_chnl_step, &delay)) { 912 if (delay > 0) 913 msleep(delay); 914 if (!priv->up) 915 break; 916 } 917 } 918 919 static void _rtl92e_phy_switch_channel_work_item(struct net_device *dev) 920 { 921 922 struct r8192_priv *priv = rtllib_priv(dev); 923 924 _rtl92e_phy_switch_channel(dev, priv->chan); 925 } 926 927 u8 rtl92e_set_channel(struct net_device *dev, u8 channel) 928 { 929 struct r8192_priv *priv = rtllib_priv(dev); 930 931 if (!priv->up) { 932 netdev_err(dev, "%s(): Driver is not initialized\n", __func__); 933 return false; 934 } 935 if (priv->sw_chnl_in_progress) 936 return false; 937 938 939 switch (priv->rtllib->mode) { 940 case WIRELESS_MODE_A: 941 case WIRELESS_MODE_N_5G: 942 if (channel <= 14) { 943 netdev_warn(dev, 944 "Channel %d not available in 802.11a.\n", 945 channel); 946 return false; 947 } 948 break; 949 case WIRELESS_MODE_B: 950 if (channel > 14) { 951 netdev_warn(dev, 952 "Channel %d not available in 802.11b.\n", 953 channel); 954 return false; 955 } 956 break; 957 case WIRELESS_MODE_G: 958 case WIRELESS_MODE_N_24G: 959 if (channel > 14) { 960 netdev_warn(dev, 961 "Channel %d not available in 802.11g.\n", 962 channel); 963 return false; 964 } 965 break; 966 } 967 968 priv->sw_chnl_in_progress = true; 969 if (channel == 0) 970 channel = 1; 971 972 priv->chan = channel; 973 974 priv->sw_chnl_stage = 0; 975 priv->sw_chnl_step = 0; 976 977 if (priv->up) 978 _rtl92e_phy_switch_channel_work_item(dev); 979 priv->sw_chnl_in_progress = false; 980 return true; 981 } 982 983 static void _rtl92e_cck_tx_power_track_bw_switch_tssi(struct net_device *dev) 984 { 985 struct r8192_priv *priv = rtllib_priv(dev); 986 987 switch (priv->current_chnl_bw) { 988 case HT_CHANNEL_WIDTH_20: 989 priv->cck_present_attn = 990 priv->cck_present_attn_20m_def + 991 priv->cck_present_attn_diff; 992 993 if (priv->cck_present_attn > 994 (CCK_TX_BB_GAIN_TABLE_LEN - 1)) 995 priv->cck_present_attn = 996 CCK_TX_BB_GAIN_TABLE_LEN - 1; 997 if (priv->cck_present_attn < 0) 998 priv->cck_present_attn = 0; 999 1000 if (priv->rtllib->current_network.channel == 14 && 1001 !priv->bcck_in_ch14) { 1002 priv->bcck_in_ch14 = true; 1003 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1004 } else if (priv->rtllib->current_network.channel != 1005 14 && priv->bcck_in_ch14) { 1006 priv->bcck_in_ch14 = false; 1007 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1008 } else { 1009 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1010 } 1011 break; 1012 1013 case HT_CHANNEL_WIDTH_20_40: 1014 priv->cck_present_attn = 1015 priv->cck_present_attn_40m_def + 1016 priv->cck_present_attn_diff; 1017 1018 if (priv->cck_present_attn > 1019 (CCK_TX_BB_GAIN_TABLE_LEN - 1)) 1020 priv->cck_present_attn = 1021 CCK_TX_BB_GAIN_TABLE_LEN - 1; 1022 if (priv->cck_present_attn < 0) 1023 priv->cck_present_attn = 0; 1024 1025 if (priv->rtllib->current_network.channel == 14 && 1026 !priv->bcck_in_ch14) { 1027 priv->bcck_in_ch14 = true; 1028 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1029 } else if (priv->rtllib->current_network.channel != 14 1030 && priv->bcck_in_ch14) { 1031 priv->bcck_in_ch14 = false; 1032 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1033 } else { 1034 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1035 } 1036 break; 1037 } 1038 } 1039 1040 static void _rtl92e_cck_tx_power_track_bw_switch_thermal(struct net_device *dev) 1041 { 1042 struct r8192_priv *priv = rtllib_priv(dev); 1043 1044 if (priv->rtllib->current_network.channel == 14 && 1045 !priv->bcck_in_ch14) 1046 priv->bcck_in_ch14 = true; 1047 else if (priv->rtllib->current_network.channel != 14 && 1048 priv->bcck_in_ch14) 1049 priv->bcck_in_ch14 = false; 1050 1051 switch (priv->current_chnl_bw) { 1052 case HT_CHANNEL_WIDTH_20: 1053 if (priv->rec_cck_20m_idx == 0) 1054 priv->rec_cck_20m_idx = 6; 1055 priv->cck_index = priv->rec_cck_20m_idx; 1056 break; 1057 1058 case HT_CHANNEL_WIDTH_20_40: 1059 priv->cck_index = priv->rec_cck_40m_idx; 1060 break; 1061 } 1062 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1063 } 1064 1065 static void _rtl92e_cck_tx_power_track_bw_switch(struct net_device *dev) 1066 { 1067 struct r8192_priv *priv = rtllib_priv(dev); 1068 1069 if (priv->ic_cut >= IC_VersionCut_D) 1070 _rtl92e_cck_tx_power_track_bw_switch_tssi(dev); 1071 else 1072 _rtl92e_cck_tx_power_track_bw_switch_thermal(dev); 1073 } 1074 1075 static void _rtl92e_set_bw_mode_work_item(struct net_device *dev) 1076 { 1077 1078 struct r8192_priv *priv = rtllib_priv(dev); 1079 u8 regBwOpMode; 1080 1081 if (priv->rf_chip == RF_PSEUDO_11N) { 1082 priv->set_bw_mode_in_progress = false; 1083 return; 1084 } 1085 if (!priv->up) { 1086 netdev_err(dev, "%s(): Driver is not initialized\n", __func__); 1087 return; 1088 } 1089 regBwOpMode = rtl92e_readb(dev, BW_OPMODE); 1090 1091 switch (priv->current_chnl_bw) { 1092 case HT_CHANNEL_WIDTH_20: 1093 regBwOpMode |= BW_OPMODE_20MHZ; 1094 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode); 1095 break; 1096 1097 case HT_CHANNEL_WIDTH_20_40: 1098 regBwOpMode &= ~BW_OPMODE_20MHZ; 1099 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode); 1100 break; 1101 1102 default: 1103 netdev_err(dev, "%s(): unknown Bandwidth: %#X\n", __func__, 1104 priv->current_chnl_bw); 1105 break; 1106 } 1107 1108 switch (priv->current_chnl_bw) { 1109 case HT_CHANNEL_WIDTH_20: 1110 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); 1111 rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); 1112 1113 if (!priv->btxpower_tracking) { 1114 rtl92e_writel(dev, rCCK0_TxFilter1, 0x1a1b0000); 1115 rtl92e_writel(dev, rCCK0_TxFilter2, 0x090e1317); 1116 rtl92e_writel(dev, rCCK0_DebugPort, 0x00000204); 1117 } else { 1118 _rtl92e_cck_tx_power_track_bw_switch(dev); 1119 } 1120 1121 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); 1122 1123 break; 1124 case HT_CHANNEL_WIDTH_20_40: 1125 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); 1126 rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); 1127 1128 if (!priv->btxpower_tracking) { 1129 rtl92e_writel(dev, rCCK0_TxFilter1, 0x35360000); 1130 rtl92e_writel(dev, rCCK0_TxFilter2, 0x121c252e); 1131 rtl92e_writel(dev, rCCK0_DebugPort, 0x00000409); 1132 } else { 1133 _rtl92e_cck_tx_power_track_bw_switch(dev); 1134 } 1135 1136 rtl92e_set_bb_reg(dev, rCCK0_System, bCCKSideBand, 1137 (priv->n_cur_40mhz_prime_sc>>1)); 1138 rtl92e_set_bb_reg(dev, rOFDM1_LSTF, 0xC00, 1139 priv->n_cur_40mhz_prime_sc); 1140 1141 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); 1142 break; 1143 default: 1144 netdev_err(dev, "%s(): unknown Bandwidth: %#X\n", __func__, 1145 priv->current_chnl_bw); 1146 break; 1147 1148 } 1149 1150 switch (priv->rf_chip) { 1151 case RF_8225: 1152 break; 1153 1154 case RF_8256: 1155 rtl92e_set_bandwidth(dev, priv->current_chnl_bw); 1156 break; 1157 1158 case RF_8258: 1159 break; 1160 1161 case RF_PSEUDO_11N: 1162 break; 1163 1164 default: 1165 netdev_info(dev, "%s(): Unknown RFChipID: %d\n", __func__, 1166 priv->rf_chip); 1167 break; 1168 } 1169 1170 atomic_dec(&(priv->rtllib->atm_swbw)); 1171 priv->set_bw_mode_in_progress = false; 1172 } 1173 1174 void rtl92e_set_bw_mode(struct net_device *dev, enum ht_channel_width bandwidth, 1175 enum ht_extchnl_offset Offset) 1176 { 1177 struct r8192_priv *priv = rtllib_priv(dev); 1178 1179 1180 if (priv->set_bw_mode_in_progress) 1181 return; 1182 1183 atomic_inc(&(priv->rtllib->atm_swbw)); 1184 priv->set_bw_mode_in_progress = true; 1185 1186 priv->current_chnl_bw = bandwidth; 1187 1188 if (Offset == HT_EXTCHNL_OFFSET_LOWER) 1189 priv->n_cur_40mhz_prime_sc = HAL_PRIME_CHNL_OFFSET_UPPER; 1190 else if (Offset == HT_EXTCHNL_OFFSET_UPPER) 1191 priv->n_cur_40mhz_prime_sc = HAL_PRIME_CHNL_OFFSET_LOWER; 1192 else 1193 priv->n_cur_40mhz_prime_sc = HAL_PRIME_CHNL_OFFSET_DONT_CARE; 1194 1195 _rtl92e_set_bw_mode_work_item(dev); 1196 1197 } 1198 1199 void rtl92e_init_gain(struct net_device *dev, u8 Operation) 1200 { 1201 #define SCAN_RX_INITIAL_GAIN 0x17 1202 #define POWER_DETECTION_TH 0x08 1203 struct r8192_priv *priv = rtllib_priv(dev); 1204 u32 BitMask; 1205 u8 initial_gain; 1206 1207 if (priv->up) { 1208 switch (Operation) { 1209 case IG_Backup: 1210 initial_gain = SCAN_RX_INITIAL_GAIN; 1211 BitMask = bMaskByte0; 1212 if (dm_digtable.dig_algorithm == 1213 DIG_ALGO_BY_FALSE_ALARM) 1214 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8); 1215 priv->initgain_backup.xaagccore1 = 1216 rtl92e_get_bb_reg(dev, rOFDM0_XAAGCCore1, 1217 BitMask); 1218 priv->initgain_backup.xbagccore1 = 1219 rtl92e_get_bb_reg(dev, rOFDM0_XBAGCCore1, 1220 BitMask); 1221 priv->initgain_backup.xcagccore1 = 1222 rtl92e_get_bb_reg(dev, rOFDM0_XCAGCCore1, 1223 BitMask); 1224 priv->initgain_backup.xdagccore1 = 1225 rtl92e_get_bb_reg(dev, rOFDM0_XDAGCCore1, 1226 BitMask); 1227 BitMask = bMaskByte2; 1228 priv->initgain_backup.cca = (u8)rtl92e_get_bb_reg(dev, 1229 rCCK0_CCA, BitMask); 1230 1231 rtl92e_writeb(dev, rOFDM0_XAAGCCore1, initial_gain); 1232 rtl92e_writeb(dev, rOFDM0_XBAGCCore1, initial_gain); 1233 rtl92e_writeb(dev, rOFDM0_XCAGCCore1, initial_gain); 1234 rtl92e_writeb(dev, rOFDM0_XDAGCCore1, initial_gain); 1235 rtl92e_writeb(dev, 0xa0a, POWER_DETECTION_TH); 1236 break; 1237 case IG_Restore: 1238 BitMask = 0x7f; 1239 if (dm_digtable.dig_algorithm == 1240 DIG_ALGO_BY_FALSE_ALARM) 1241 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8); 1242 1243 rtl92e_set_bb_reg(dev, rOFDM0_XAAGCCore1, BitMask, 1244 (u32)priv->initgain_backup.xaagccore1); 1245 rtl92e_set_bb_reg(dev, rOFDM0_XBAGCCore1, BitMask, 1246 (u32)priv->initgain_backup.xbagccore1); 1247 rtl92e_set_bb_reg(dev, rOFDM0_XCAGCCore1, BitMask, 1248 (u32)priv->initgain_backup.xcagccore1); 1249 rtl92e_set_bb_reg(dev, rOFDM0_XDAGCCore1, BitMask, 1250 (u32)priv->initgain_backup.xdagccore1); 1251 BitMask = bMaskByte2; 1252 rtl92e_set_bb_reg(dev, rCCK0_CCA, BitMask, 1253 (u32)priv->initgain_backup.cca); 1254 1255 rtl92e_set_tx_power(dev, 1256 priv->rtllib->current_network.channel); 1257 1258 if (dm_digtable.dig_algorithm == 1259 DIG_ALGO_BY_FALSE_ALARM) 1260 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x1); 1261 break; 1262 } 1263 } 1264 } 1265 1266 void rtl92e_set_rf_off(struct net_device *dev) 1267 { 1268 1269 rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); 1270 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0); 1271 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); 1272 rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0); 1273 rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0); 1274 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); 1275 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0); 1276 rtl92e_writeb(dev, ANAPAR_FOR_8192PCIE, 0x07); 1277 1278 } 1279 1280 static bool _rtl92e_set_rf_power_state(struct net_device *dev, 1281 enum rt_rf_power_state rf_power_state) 1282 { 1283 struct r8192_priv *priv = rtllib_priv(dev); 1284 struct rt_pwr_save_ctrl *psc = (struct rt_pwr_save_ctrl *) 1285 (&priv->rtllib->pwr_save_ctrl); 1286 bool bResult = true; 1287 u8 i = 0, QueueID = 0; 1288 struct rtl8192_tx_ring *ring = NULL; 1289 1290 if (priv->set_rf_pwr_state_in_progress) 1291 return false; 1292 priv->set_rf_pwr_state_in_progress = true; 1293 1294 switch (priv->rf_chip) { 1295 case RF_8256: 1296 switch (rf_power_state) { 1297 case rf_on: 1298 if ((priv->rtllib->rf_power_state == rf_off) && 1299 RT_IN_PS_LEVEL(psc, RT_RF_OFF_LEVL_HALT_NIC)) { 1300 bool rtstatus; 1301 u32 InitilizeCount = 3; 1302 1303 do { 1304 InitilizeCount--; 1305 rtstatus = rtl92e_enable_nic(dev); 1306 } while (!rtstatus && (InitilizeCount > 0)); 1307 1308 if (!rtstatus) { 1309 netdev_err(dev, 1310 "%s(): Failed to initialize Adapter.\n", 1311 __func__); 1312 priv->set_rf_pwr_state_in_progress = false; 1313 return false; 1314 } 1315 1316 RT_CLEAR_PS_LEVEL(psc, 1317 RT_RF_OFF_LEVL_HALT_NIC); 1318 } else { 1319 rtl92e_writeb(dev, ANAPAR, 0x37); 1320 mdelay(1); 1321 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 1322 0x4, 0x1); 1323 priv->hw_rf_off_action = 0; 1324 1325 rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE, 1326 BIT4, 0x1); 1327 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 1328 0x300, 0x3); 1329 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 1330 0x18, 0x3); 1331 rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable, 1332 0x3, 0x3); 1333 rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable, 1334 0x3, 0x3); 1335 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 1336 0x60, 0x3); 1337 1338 } 1339 1340 break; 1341 1342 case rf_sleep: 1343 if (priv->rtllib->rf_power_state == rf_off) 1344 break; 1345 1346 1347 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) { 1348 ring = &priv->tx_ring[QueueID]; 1349 1350 if (skb_queue_len(&ring->queue) == 0) { 1351 QueueID++; 1352 continue; 1353 } else { 1354 udelay(10); 1355 i++; 1356 } 1357 1358 if (i >= MAX_DOZE_WAITING_TIMES_9x) 1359 break; 1360 } 1361 rtl92e_set_rf_off(dev); 1362 break; 1363 1364 case rf_off: 1365 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) { 1366 ring = &priv->tx_ring[QueueID]; 1367 1368 if (skb_queue_len(&ring->queue) == 0) { 1369 QueueID++; 1370 continue; 1371 } else { 1372 udelay(10); 1373 i++; 1374 } 1375 1376 if (i >= MAX_DOZE_WAITING_TIMES_9x) 1377 break; 1378 } 1379 1380 if (psc->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && 1381 !RT_IN_PS_LEVEL(psc, RT_RF_OFF_LEVL_HALT_NIC)) { 1382 rtl92e_disable_nic(dev); 1383 RT_SET_PS_LEVEL(psc, RT_RF_OFF_LEVL_HALT_NIC); 1384 } else if (!(psc->RegRfPsLevel & 1385 RT_RF_OFF_LEVL_HALT_NIC)) { 1386 rtl92e_set_rf_off(dev); 1387 } 1388 1389 break; 1390 1391 default: 1392 bResult = false; 1393 netdev_warn(dev, 1394 "%s(): Unknown state requested: 0x%X.\n", 1395 __func__, rf_power_state); 1396 break; 1397 } 1398 1399 break; 1400 1401 default: 1402 netdev_warn(dev, "%s(): Unknown RF type\n", __func__); 1403 break; 1404 } 1405 1406 if (bResult) { 1407 priv->rtllib->rf_power_state = rf_power_state; 1408 1409 switch (priv->rf_chip) { 1410 case RF_8256: 1411 break; 1412 1413 default: 1414 netdev_warn(dev, "%s(): Unknown RF type\n", __func__); 1415 break; 1416 } 1417 } 1418 1419 priv->set_rf_pwr_state_in_progress = false; 1420 return bResult; 1421 } 1422 1423 bool rtl92e_set_rf_power_state(struct net_device *dev, 1424 enum rt_rf_power_state rf_power_state) 1425 { 1426 struct r8192_priv *priv = rtllib_priv(dev); 1427 1428 bool bResult = false; 1429 1430 if (rf_power_state == priv->rtllib->rf_power_state && 1431 priv->hw_rf_off_action == 0) { 1432 return bResult; 1433 } 1434 1435 bResult = _rtl92e_set_rf_power_state(dev, rf_power_state); 1436 return bResult; 1437 } 1438 1439 void rtl92e_scan_op_backup(struct net_device *dev, u8 Operation) 1440 { 1441 struct r8192_priv *priv = rtllib_priv(dev); 1442 1443 if (priv->up) { 1444 switch (Operation) { 1445 case SCAN_OPT_BACKUP: 1446 priv->rtllib->InitialGainHandler(dev, IG_Backup); 1447 break; 1448 1449 case SCAN_OPT_RESTORE: 1450 priv->rtllib->InitialGainHandler(dev, IG_Restore); 1451 break; 1452 } 1453 } 1454 } 1455