1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. 4 * 5 * Contact Information: wlanfae <wlanfae@realtek.com> 6 */ 7 #include <linux/bitops.h> 8 #include "rtl_core.h" 9 #include "r8192E_hw.h" 10 #include "r8192E_phyreg.h" 11 #include "r8190P_rtl8256.h" 12 #include "r8192E_phy.h" 13 #include "rtl_dm.h" 14 15 #include "r8192E_hwimg.h" 16 17 static u32 RF_CHANNEL_TABLE_ZEBRA[] = { 18 0, 19 0x085c, 20 0x08dc, 21 0x095c, 22 0x09dc, 23 0x0a5c, 24 0x0adc, 25 0x0b5c, 26 0x0bdc, 27 0x0c5c, 28 0x0cdc, 29 0x0d5c, 30 0x0ddc, 31 0x0e5c, 32 0x0f72, 33 }; 34 35 /*************************Define local function prototype**********************/ 36 37 static u32 _rtl92e_phy_rf_fw_read(struct net_device *dev, 38 enum rf90_radio_path eRFPath, u32 Offset); 39 static void _rtl92e_phy_rf_fw_write(struct net_device *dev, 40 enum rf90_radio_path eRFPath, u32 Offset, 41 u32 Data); 42 43 static u32 _rtl92e_calculate_bit_shift(u32 dwBitMask) 44 { 45 if (!dwBitMask) 46 return 32; 47 return ffs(dwBitMask) - 1; 48 } 49 50 u8 rtl92e_is_legal_rf_path(struct net_device *dev, u32 eRFPath) 51 { 52 u8 ret = 1; 53 struct r8192_priv *priv = rtllib_priv(dev); 54 55 if (priv->rf_type == RF_2T4R) 56 ret = 0; 57 else if (priv->rf_type == RF_1T2R) { 58 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) 59 ret = 1; 60 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) 61 ret = 0; 62 } 63 return ret; 64 } 65 66 void rtl92e_set_bb_reg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask, 67 u32 dwData) 68 { 69 70 u32 OriginalValue, BitShift, NewValue; 71 72 if (dwBitMask != bMaskDWord) { 73 OriginalValue = rtl92e_readl(dev, dwRegAddr); 74 BitShift = _rtl92e_calculate_bit_shift(dwBitMask); 75 NewValue = (OriginalValue & ~dwBitMask) | (dwData << BitShift); 76 rtl92e_writel(dev, dwRegAddr, NewValue); 77 } else 78 rtl92e_writel(dev, dwRegAddr, dwData); 79 } 80 81 u32 rtl92e_get_bb_reg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask) 82 { 83 u32 OriginalValue, BitShift; 84 85 OriginalValue = rtl92e_readl(dev, dwRegAddr); 86 BitShift = _rtl92e_calculate_bit_shift(dwBitMask); 87 88 return (OriginalValue & dwBitMask) >> BitShift; 89 } 90 91 static u32 _rtl92e_phy_rf_read(struct net_device *dev, 92 enum rf90_radio_path eRFPath, u32 Offset) 93 { 94 struct r8192_priv *priv = rtllib_priv(dev); 95 u32 ret = 0; 96 u32 NewOffset = 0; 97 struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath]; 98 99 Offset &= 0x3f; 100 101 if (priv->rf_chip == RF_8256) { 102 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); 103 if (Offset >= 31) { 104 priv->RfReg0Value[eRFPath] |= 0x140; 105 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, 106 bMaskDWord, 107 (priv->RfReg0Value[eRFPath]<<16)); 108 NewOffset = Offset - 30; 109 } else if (Offset >= 16) { 110 priv->RfReg0Value[eRFPath] |= 0x100; 111 priv->RfReg0Value[eRFPath] &= (~0x40); 112 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, 113 bMaskDWord, 114 (priv->RfReg0Value[eRFPath]<<16)); 115 116 NewOffset = Offset - 15; 117 } else 118 NewOffset = Offset; 119 } else { 120 NewOffset = Offset; 121 } 122 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, 123 NewOffset); 124 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); 125 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); 126 127 mdelay(1); 128 129 ret = rtl92e_get_bb_reg(dev, pPhyReg->rfLSSIReadBack, 130 bLSSIReadBackData); 131 132 if (priv->rf_chip == RF_8256) { 133 priv->RfReg0Value[eRFPath] &= 0xebf; 134 135 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, 136 (priv->RfReg0Value[eRFPath] << 16)); 137 138 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); 139 } 140 141 142 return ret; 143 144 } 145 146 static void _rtl92e_phy_rf_write(struct net_device *dev, 147 enum rf90_radio_path eRFPath, u32 Offset, 148 u32 Data) 149 { 150 struct r8192_priv *priv = rtllib_priv(dev); 151 u32 DataAndAddr = 0, NewOffset = 0; 152 struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath]; 153 154 Offset &= 0x3f; 155 if (priv->rf_chip == RF_8256) { 156 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); 157 158 if (Offset >= 31) { 159 priv->RfReg0Value[eRFPath] |= 0x140; 160 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, 161 bMaskDWord, 162 (priv->RfReg0Value[eRFPath] << 16)); 163 NewOffset = Offset - 30; 164 } else if (Offset >= 16) { 165 priv->RfReg0Value[eRFPath] |= 0x100; 166 priv->RfReg0Value[eRFPath] &= (~0x40); 167 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, 168 bMaskDWord, 169 (priv->RfReg0Value[eRFPath] << 16)); 170 NewOffset = Offset - 15; 171 } else 172 NewOffset = Offset; 173 } else { 174 NewOffset = Offset; 175 } 176 177 DataAndAddr = (NewOffset & 0x3f) | (Data << 16); 178 179 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); 180 181 if (Offset == 0x0) 182 priv->RfReg0Value[eRFPath] = Data; 183 184 if (priv->rf_chip == RF_8256) { 185 if (Offset != 0) { 186 priv->RfReg0Value[eRFPath] &= 0xebf; 187 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, 188 bMaskDWord, 189 (priv->RfReg0Value[eRFPath] << 16)); 190 } 191 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); 192 } 193 } 194 195 void rtl92e_set_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath, 196 u32 RegAddr, u32 BitMask, u32 Data) 197 { 198 struct r8192_priv *priv = rtllib_priv(dev); 199 u32 Original_Value, BitShift, New_Value; 200 201 if (!rtl92e_is_legal_rf_path(dev, eRFPath)) 202 return; 203 if (priv->rtllib->rf_power_state != rf_on && !priv->being_init_adapter) 204 return; 205 206 if (priv->Rf_Mode == RF_OP_By_FW) { 207 if (BitMask != bMask12Bits) { 208 Original_Value = _rtl92e_phy_rf_fw_read(dev, eRFPath, 209 RegAddr); 210 BitShift = _rtl92e_calculate_bit_shift(BitMask); 211 New_Value = (Original_Value & ~BitMask) | (Data << BitShift); 212 213 _rtl92e_phy_rf_fw_write(dev, eRFPath, RegAddr, 214 New_Value); 215 } else 216 _rtl92e_phy_rf_fw_write(dev, eRFPath, RegAddr, Data); 217 udelay(200); 218 219 } else { 220 if (BitMask != bMask12Bits) { 221 Original_Value = _rtl92e_phy_rf_read(dev, eRFPath, 222 RegAddr); 223 BitShift = _rtl92e_calculate_bit_shift(BitMask); 224 New_Value = (Original_Value & ~BitMask) | (Data << BitShift); 225 226 _rtl92e_phy_rf_write(dev, eRFPath, RegAddr, New_Value); 227 } else 228 _rtl92e_phy_rf_write(dev, eRFPath, RegAddr, Data); 229 } 230 } 231 232 u32 rtl92e_get_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath, 233 u32 RegAddr, u32 BitMask) 234 { 235 u32 Original_Value, Readback_Value, BitShift; 236 struct r8192_priv *priv = rtllib_priv(dev); 237 238 if (!rtl92e_is_legal_rf_path(dev, eRFPath)) 239 return 0; 240 if (priv->rtllib->rf_power_state != rf_on && !priv->being_init_adapter) 241 return 0; 242 mutex_lock(&priv->rf_mutex); 243 if (priv->Rf_Mode == RF_OP_By_FW) { 244 Original_Value = _rtl92e_phy_rf_fw_read(dev, eRFPath, RegAddr); 245 udelay(200); 246 } else { 247 Original_Value = _rtl92e_phy_rf_read(dev, eRFPath, RegAddr); 248 } 249 BitShift = _rtl92e_calculate_bit_shift(BitMask); 250 Readback_Value = (Original_Value & BitMask) >> BitShift; 251 mutex_unlock(&priv->rf_mutex); 252 return Readback_Value; 253 } 254 255 static u32 _rtl92e_phy_rf_fw_read(struct net_device *dev, 256 enum rf90_radio_path eRFPath, u32 Offset) 257 { 258 u32 Data = 0; 259 u8 time = 0; 260 261 Data |= ((Offset & 0xFF) << 12); 262 Data |= ((eRFPath & 0x3) << 20); 263 Data |= 0x80000000; 264 while (rtl92e_readl(dev, QPNR) & 0x80000000) { 265 if (time++ < 100) 266 udelay(10); 267 else 268 break; 269 } 270 rtl92e_writel(dev, QPNR, Data); 271 while (rtl92e_readl(dev, QPNR) & 0x80000000) { 272 if (time++ < 100) 273 udelay(10); 274 else 275 return 0; 276 } 277 return rtl92e_readl(dev, RF_DATA); 278 279 } 280 281 static void _rtl92e_phy_rf_fw_write(struct net_device *dev, 282 enum rf90_radio_path eRFPath, u32 Offset, 283 u32 Data) 284 { 285 u8 time = 0; 286 287 Data |= ((Offset & 0xFF) << 12); 288 Data |= ((eRFPath & 0x3) << 20); 289 Data |= 0x400000; 290 Data |= 0x80000000; 291 292 while (rtl92e_readl(dev, QPNR) & 0x80000000) { 293 if (time++ < 100) 294 udelay(10); 295 else 296 break; 297 } 298 rtl92e_writel(dev, QPNR, Data); 299 300 } 301 302 303 void rtl92e_config_mac(struct net_device *dev) 304 { 305 u32 dwArrayLen = 0, i = 0; 306 u32 *pdwArray = NULL; 307 struct r8192_priv *priv = rtllib_priv(dev); 308 309 if (priv->bTXPowerDataReadFromEEPORM) { 310 dwArrayLen = MACPHY_Array_PGLength; 311 pdwArray = Rtl819XMACPHY_Array_PG; 312 313 } else { 314 dwArrayLen = MACPHY_ArrayLength; 315 pdwArray = Rtl819XMACPHY_Array; 316 } 317 for (i = 0; i < dwArrayLen; i += 3) { 318 if (pdwArray[i] == 0x318) 319 pdwArray[i+2] = 0x00000800; 320 rtl92e_set_bb_reg(dev, pdwArray[i], pdwArray[i+1], 321 pdwArray[i+2]); 322 } 323 return; 324 325 } 326 327 static void _rtl92e_phy_config_bb(struct net_device *dev, u8 ConfigType) 328 { 329 int i; 330 u32 *Rtl819XPHY_REGArray_Table = NULL; 331 u32 *Rtl819XAGCTAB_Array_Table = NULL; 332 u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0; 333 struct r8192_priv *priv = rtllib_priv(dev); 334 335 AGCTAB_ArrayLen = AGCTAB_ArrayLength; 336 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array; 337 if (priv->rf_type == RF_2T4R) { 338 PHY_REGArrayLen = PHY_REGArrayLength; 339 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray; 340 } else if (priv->rf_type == RF_1T2R) { 341 PHY_REGArrayLen = PHY_REG_1T2RArrayLength; 342 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray; 343 } 344 345 if (ConfigType == BaseBand_Config_PHY_REG) { 346 for (i = 0; i < PHY_REGArrayLen; i += 2) { 347 rtl92e_set_bb_reg(dev, Rtl819XPHY_REGArray_Table[i], 348 bMaskDWord, 349 Rtl819XPHY_REGArray_Table[i+1]); 350 } 351 } else if (ConfigType == BaseBand_Config_AGC_TAB) { 352 for (i = 0; i < AGCTAB_ArrayLen; i += 2) { 353 rtl92e_set_bb_reg(dev, Rtl819XAGCTAB_Array_Table[i], 354 bMaskDWord, 355 Rtl819XAGCTAB_Array_Table[i+1]); 356 } 357 } 358 } 359 360 static void _rtl92e_init_bb_rf_reg_def(struct net_device *dev) 361 { 362 struct r8192_priv *priv = rtllib_priv(dev); 363 364 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; 365 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; 366 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; 367 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW; 368 369 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; 370 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB; 371 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB; 372 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB; 373 374 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; 375 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; 376 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE; 377 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE; 378 379 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; 380 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; 381 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE; 382 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE; 383 384 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; 385 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; 386 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; 387 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; 388 389 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; 390 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; 391 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; 392 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; 393 394 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; 395 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; 396 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; 397 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; 398 399 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; 400 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; 401 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; 402 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; 403 404 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; 405 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; 406 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; 407 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; 408 409 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; 410 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; 411 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; 412 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; 413 414 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; 415 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; 416 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; 417 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; 418 419 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; 420 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; 421 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; 422 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; 423 424 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; 425 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; 426 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; 427 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; 428 429 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; 430 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; 431 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; 432 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; 433 434 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; 435 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; 436 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; 437 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; 438 439 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; 440 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; 441 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; 442 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; 443 444 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; 445 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; 446 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; 447 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; 448 449 } 450 451 bool rtl92e_check_bb_and_rf(struct net_device *dev, enum hw90_block CheckBlock, 452 enum rf90_radio_path eRFPath) 453 { 454 bool ret = true; 455 u32 i, CheckTimes = 4, dwRegRead = 0; 456 u32 WriteAddr[4]; 457 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f}; 458 459 WriteAddr[HW90_BLOCK_MAC] = 0x100; 460 WriteAddr[HW90_BLOCK_PHY0] = 0x900; 461 WriteAddr[HW90_BLOCK_PHY1] = 0x800; 462 WriteAddr[HW90_BLOCK_RF] = 0x3; 463 464 if (CheckBlock == HW90_BLOCK_MAC) { 465 netdev_warn(dev, "%s(): No checks available for MAC block.\n", 466 __func__); 467 return ret; 468 } 469 470 for (i = 0; i < CheckTimes; i++) { 471 switch (CheckBlock) { 472 case HW90_BLOCK_PHY0: 473 case HW90_BLOCK_PHY1: 474 rtl92e_writel(dev, WriteAddr[CheckBlock], 475 WriteData[i]); 476 dwRegRead = rtl92e_readl(dev, WriteAddr[CheckBlock]); 477 break; 478 479 case HW90_BLOCK_RF: 480 WriteData[i] &= 0xfff; 481 rtl92e_set_rf_reg(dev, eRFPath, 482 WriteAddr[HW90_BLOCK_RF], 483 bMask12Bits, WriteData[i]); 484 mdelay(10); 485 dwRegRead = rtl92e_get_rf_reg(dev, eRFPath, 486 WriteAddr[HW90_BLOCK_RF], 487 bMaskDWord); 488 mdelay(10); 489 break; 490 491 default: 492 ret = false; 493 break; 494 } 495 496 497 if (dwRegRead != WriteData[i]) { 498 netdev_warn(dev, "%s(): Check failed.\n", __func__); 499 ret = false; 500 break; 501 } 502 } 503 504 return ret; 505 } 506 507 static bool _rtl92e_bb_config_para_file(struct net_device *dev) 508 { 509 struct r8192_priv *priv = rtllib_priv(dev); 510 bool rtStatus = true; 511 u8 bRegValue = 0, eCheckItem = 0; 512 u32 dwRegValue = 0; 513 514 bRegValue = rtl92e_readb(dev, BB_GLOBAL_RESET); 515 rtl92e_writeb(dev, BB_GLOBAL_RESET, (bRegValue|BB_GLOBAL_RESET_BIT)); 516 517 dwRegValue = rtl92e_readl(dev, CPU_GEN); 518 rtl92e_writel(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST))); 519 520 for (eCheckItem = (enum hw90_block)HW90_BLOCK_PHY0; 521 eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) { 522 rtStatus = rtl92e_check_bb_and_rf(dev, 523 (enum hw90_block)eCheckItem, 524 (enum rf90_radio_path)0); 525 if (!rtStatus) 526 return rtStatus; 527 } 528 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); 529 _rtl92e_phy_config_bb(dev, BaseBand_Config_PHY_REG); 530 531 dwRegValue = rtl92e_readl(dev, CPU_GEN); 532 rtl92e_writel(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST)); 533 534 _rtl92e_phy_config_bb(dev, BaseBand_Config_AGC_TAB); 535 536 if (priv->IC_Cut > VERSION_8190_BD) { 537 if (priv->rf_type == RF_2T4R) 538 dwRegValue = priv->AntennaTxPwDiff[2]<<8 | 539 priv->AntennaTxPwDiff[1]<<4 | 540 priv->AntennaTxPwDiff[0]; 541 else 542 dwRegValue = 0x0; 543 rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage, 544 (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue); 545 546 547 dwRegValue = priv->CrystalCap; 548 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, 549 dwRegValue); 550 } 551 552 return rtStatus; 553 } 554 bool rtl92e_config_bb(struct net_device *dev) 555 { 556 _rtl92e_init_bb_rf_reg_def(dev); 557 return _rtl92e_bb_config_para_file(dev); 558 } 559 560 void rtl92e_get_tx_power(struct net_device *dev) 561 { 562 struct r8192_priv *priv = rtllib_priv(dev); 563 564 priv->MCSTxPowerLevelOriginalOffset[0] = 565 rtl92e_readl(dev, rTxAGC_Rate18_06); 566 priv->MCSTxPowerLevelOriginalOffset[1] = 567 rtl92e_readl(dev, rTxAGC_Rate54_24); 568 priv->MCSTxPowerLevelOriginalOffset[2] = 569 rtl92e_readl(dev, rTxAGC_Mcs03_Mcs00); 570 priv->MCSTxPowerLevelOriginalOffset[3] = 571 rtl92e_readl(dev, rTxAGC_Mcs07_Mcs04); 572 priv->MCSTxPowerLevelOriginalOffset[4] = 573 rtl92e_readl(dev, rTxAGC_Mcs11_Mcs08); 574 priv->MCSTxPowerLevelOriginalOffset[5] = 575 rtl92e_readl(dev, rTxAGC_Mcs15_Mcs12); 576 577 priv->DefaultInitialGain[0] = rtl92e_readb(dev, rOFDM0_XAAGCCore1); 578 priv->DefaultInitialGain[1] = rtl92e_readb(dev, rOFDM0_XBAGCCore1); 579 priv->DefaultInitialGain[2] = rtl92e_readb(dev, rOFDM0_XCAGCCore1); 580 priv->DefaultInitialGain[3] = rtl92e_readb(dev, rOFDM0_XDAGCCore1); 581 582 priv->framesync = rtl92e_readb(dev, rOFDM0_RxDetector3); 583 priv->framesyncC34 = rtl92e_readl(dev, rOFDM0_RxDetector2); 584 priv->SifsTime = rtl92e_readw(dev, SIFS); 585 } 586 587 void rtl92e_set_tx_power(struct net_device *dev, u8 channel) 588 { 589 struct r8192_priv *priv = rtllib_priv(dev); 590 u8 powerlevel = 0, powerlevelOFDM24G = 0; 591 s8 ant_pwr_diff; 592 u32 u4RegValue; 593 594 if (priv->epromtype == EEPROM_93C46) { 595 powerlevel = priv->TxPowerLevelCCK[channel-1]; 596 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; 597 } else if (priv->epromtype == EEPROM_93C56) { 598 if (priv->rf_type == RF_1T2R) { 599 powerlevel = priv->TxPowerLevelCCK_C[channel-1]; 600 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1]; 601 } else if (priv->rf_type == RF_2T4R) { 602 powerlevel = priv->TxPowerLevelCCK_A[channel-1]; 603 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1]; 604 605 ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1] 606 - priv->TxPowerLevelOFDM24G_A[channel-1]; 607 608 priv->RF_C_TxPwDiff = ant_pwr_diff; 609 610 ant_pwr_diff &= 0xf; 611 612 priv->AntennaTxPwDiff[2] = 0; 613 priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff); 614 priv->AntennaTxPwDiff[0] = 0; 615 616 u4RegValue = priv->AntennaTxPwDiff[2]<<8 | 617 priv->AntennaTxPwDiff[1]<<4 | 618 priv->AntennaTxPwDiff[0]; 619 620 rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage, 621 (bXBTxAGC|bXCTxAGC|bXDTxAGC), 622 u4RegValue); 623 } 624 } 625 switch (priv->rf_chip) { 626 case RF_8225: 627 break; 628 case RF_8256: 629 rtl92e_set_cck_tx_power(dev, powerlevel); 630 rtl92e_set_ofdm_tx_power(dev, powerlevelOFDM24G); 631 break; 632 case RF_8258: 633 break; 634 default: 635 netdev_err(dev, "Invalid RF Chip ID.\n"); 636 break; 637 } 638 } 639 640 bool rtl92e_config_phy(struct net_device *dev) 641 { 642 struct r8192_priv *priv = rtllib_priv(dev); 643 bool rtStatus = true; 644 645 switch (priv->rf_chip) { 646 case RF_8225: 647 break; 648 case RF_8256: 649 rtStatus = rtl92e_config_rf(dev); 650 break; 651 652 case RF_8258: 653 break; 654 case RF_PSEUDO_11N: 655 break; 656 657 default: 658 netdev_err(dev, "Invalid RF Chip ID.\n"); 659 break; 660 } 661 return rtStatus; 662 } 663 664 u8 rtl92e_config_rf_path(struct net_device *dev, enum rf90_radio_path eRFPath) 665 { 666 667 int i; 668 669 switch (eRFPath) { 670 case RF90_PATH_A: 671 for (i = 0; i < RadioA_ArrayLength; i += 2) { 672 if (Rtl819XRadioA_Array[i] == 0xfe) { 673 msleep(100); 674 continue; 675 } 676 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioA_Array[i], 677 bMask12Bits, 678 Rtl819XRadioA_Array[i+1]); 679 680 } 681 break; 682 case RF90_PATH_B: 683 for (i = 0; i < RadioB_ArrayLength; i += 2) { 684 if (Rtl819XRadioB_Array[i] == 0xfe) { 685 msleep(100); 686 continue; 687 } 688 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioB_Array[i], 689 bMask12Bits, 690 Rtl819XRadioB_Array[i+1]); 691 692 } 693 break; 694 case RF90_PATH_C: 695 for (i = 0; i < RadioC_ArrayLength; i += 2) { 696 if (Rtl819XRadioC_Array[i] == 0xfe) { 697 msleep(100); 698 continue; 699 } 700 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioC_Array[i], 701 bMask12Bits, 702 Rtl819XRadioC_Array[i+1]); 703 704 } 705 break; 706 case RF90_PATH_D: 707 for (i = 0; i < RadioD_ArrayLength; i += 2) { 708 if (Rtl819XRadioD_Array[i] == 0xfe) { 709 msleep(100); 710 continue; 711 } 712 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioD_Array[i], 713 bMask12Bits, 714 Rtl819XRadioD_Array[i+1]); 715 716 } 717 break; 718 default: 719 break; 720 } 721 722 return 0; 723 724 } 725 726 static void _rtl92e_set_tx_power_level(struct net_device *dev, u8 channel) 727 { 728 struct r8192_priv *priv = rtllib_priv(dev); 729 u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; 730 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; 731 732 switch (priv->rf_chip) { 733 case RF_8225: 734 break; 735 736 case RF_8256: 737 rtl92e_set_cck_tx_power(dev, powerlevel); 738 rtl92e_set_ofdm_tx_power(dev, powerlevelOFDM24G); 739 break; 740 741 case RF_8258: 742 break; 743 default: 744 netdev_warn(dev, "%s(): Invalid RF Chip ID\n", __func__); 745 break; 746 } 747 } 748 749 static u8 _rtl92e_phy_set_sw_chnl_cmd_array(struct net_device *dev, 750 struct sw_chnl_cmd *CmdTable, 751 u32 CmdTableIdx, u32 CmdTableSz, 752 enum sw_chnl_cmd_id CmdID, 753 u32 Para1, u32 Para2, u32 msDelay) 754 { 755 struct sw_chnl_cmd *pCmd; 756 757 if (CmdTable == NULL) { 758 netdev_err(dev, "%s(): CmdTable cannot be NULL.\n", __func__); 759 return false; 760 } 761 if (CmdTableIdx >= CmdTableSz) { 762 netdev_err(dev, "%s(): Invalid index requested.\n", __func__); 763 return false; 764 } 765 766 pCmd = CmdTable + CmdTableIdx; 767 pCmd->CmdID = CmdID; 768 pCmd->Para1 = Para1; 769 pCmd->Para2 = Para2; 770 pCmd->msDelay = msDelay; 771 772 return true; 773 } 774 775 static u8 _rtl92e_phy_switch_channel_step(struct net_device *dev, u8 channel, 776 u8 *stage, u8 *step, u32 *delay) 777 { 778 struct r8192_priv *priv = rtllib_priv(dev); 779 struct rtllib_device *ieee = priv->rtllib; 780 u32 PreCommonCmdCnt; 781 u32 PostCommonCmdCnt; 782 u32 RfDependCmdCnt; 783 struct sw_chnl_cmd *CurrentCmd = NULL; 784 u8 eRFPath; 785 786 if (!rtllib_legal_channel(priv->rtllib, channel)) { 787 netdev_err(dev, "Invalid channel requested: %d\n", channel); 788 return true; 789 } 790 791 { 792 PreCommonCmdCnt = 0; 793 _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PreCommonCmd, 794 PreCommonCmdCnt++, 795 MAX_PRECMD_CNT, 796 CmdID_SetTxPowerLevel, 797 0, 0, 0); 798 _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PreCommonCmd, 799 PreCommonCmdCnt++, 800 MAX_PRECMD_CNT, CmdID_End, 801 0, 0, 0); 802 803 PostCommonCmdCnt = 0; 804 805 _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PostCommonCmd, 806 PostCommonCmdCnt++, 807 MAX_POSTCMD_CNT, CmdID_End, 808 0, 0, 0); 809 810 RfDependCmdCnt = 0; 811 switch (priv->rf_chip) { 812 case RF_8225: 813 if (!(channel >= 1 && channel <= 14)) { 814 netdev_err(dev, 815 "Invalid channel requested for 8225: %d\n", 816 channel); 817 return false; 818 } 819 _rtl92e_phy_set_sw_chnl_cmd_array(dev, 820 ieee->RfDependCmd, 821 RfDependCmdCnt++, 822 MAX_RFDEPENDCMD_CNT, 823 CmdID_RF_WriteReg, 824 rZebra1_Channel, 825 RF_CHANNEL_TABLE_ZEBRA[channel], 826 10); 827 _rtl92e_phy_set_sw_chnl_cmd_array(dev, 828 ieee->RfDependCmd, 829 RfDependCmdCnt++, 830 MAX_RFDEPENDCMD_CNT, 831 CmdID_End, 0, 0, 0); 832 break; 833 834 case RF_8256: 835 if (!(channel >= 1 && channel <= 14)) { 836 netdev_err(dev, 837 "Invalid channel requested for 8256: %d\n", 838 channel); 839 return false; 840 } 841 _rtl92e_phy_set_sw_chnl_cmd_array(dev, 842 ieee->RfDependCmd, 843 RfDependCmdCnt++, 844 MAX_RFDEPENDCMD_CNT, 845 CmdID_RF_WriteReg, 846 rZebra1_Channel, 847 channel, 10); 848 _rtl92e_phy_set_sw_chnl_cmd_array(dev, 849 ieee->RfDependCmd, 850 RfDependCmdCnt++, 851 MAX_RFDEPENDCMD_CNT, 852 CmdID_End, 0, 0, 0); 853 break; 854 855 case RF_8258: 856 break; 857 858 default: 859 netdev_warn(dev, "Unknown RF Chip ID\n"); 860 return false; 861 } 862 863 864 do { 865 switch (*stage) { 866 case 0: 867 CurrentCmd = &ieee->PreCommonCmd[*step]; 868 break; 869 case 1: 870 CurrentCmd = &ieee->RfDependCmd[*step]; 871 break; 872 case 2: 873 CurrentCmd = &ieee->PostCommonCmd[*step]; 874 break; 875 } 876 877 if (CurrentCmd && CurrentCmd->CmdID == CmdID_End) { 878 if ((*stage) == 2) 879 return true; 880 (*stage)++; 881 (*step) = 0; 882 continue; 883 } 884 885 if (!CurrentCmd) 886 continue; 887 switch (CurrentCmd->CmdID) { 888 case CmdID_SetTxPowerLevel: 889 if (priv->IC_Cut > VERSION_8190_BD) 890 _rtl92e_set_tx_power_level(dev, 891 channel); 892 break; 893 case CmdID_WritePortUlong: 894 rtl92e_writel(dev, CurrentCmd->Para1, 895 CurrentCmd->Para2); 896 break; 897 case CmdID_WritePortUshort: 898 rtl92e_writew(dev, CurrentCmd->Para1, 899 CurrentCmd->Para2); 900 break; 901 case CmdID_WritePortUchar: 902 rtl92e_writeb(dev, CurrentCmd->Para1, 903 CurrentCmd->Para2); 904 break; 905 case CmdID_RF_WriteReg: 906 for (eRFPath = 0; eRFPath < 907 priv->NumTotalRFPath; eRFPath++) 908 rtl92e_set_rf_reg(dev, 909 (enum rf90_radio_path)eRFPath, 910 CurrentCmd->Para1, bMask12Bits, 911 CurrentCmd->Para2<<7); 912 break; 913 default: 914 break; 915 } 916 917 break; 918 } while (true); 919 } /*for (Number of RF paths)*/ 920 921 (*delay) = CurrentCmd->msDelay; 922 (*step)++; 923 return false; 924 } 925 926 static void _rtl92e_phy_switch_channel(struct net_device *dev, u8 channel) 927 { 928 struct r8192_priv *priv = rtllib_priv(dev); 929 u32 delay = 0; 930 931 while (!_rtl92e_phy_switch_channel_step(dev, channel, 932 &priv->SwChnlStage, 933 &priv->SwChnlStep, &delay)) { 934 if (delay > 0) 935 msleep(delay); 936 if (!priv->up) 937 break; 938 } 939 } 940 941 static void _rtl92e_phy_switch_channel_work_item(struct net_device *dev) 942 { 943 944 struct r8192_priv *priv = rtllib_priv(dev); 945 946 _rtl92e_phy_switch_channel(dev, priv->chan); 947 } 948 949 u8 rtl92e_set_channel(struct net_device *dev, u8 channel) 950 { 951 struct r8192_priv *priv = rtllib_priv(dev); 952 953 if (!priv->up) { 954 netdev_err(dev, "%s(): Driver is not initialized\n", __func__); 955 return false; 956 } 957 if (priv->SwChnlInProgress) 958 return false; 959 960 961 switch (priv->rtllib->mode) { 962 case WIRELESS_MODE_A: 963 case WIRELESS_MODE_N_5G: 964 if (channel <= 14) { 965 netdev_warn(dev, 966 "Channel %d not available in 802.11a.\n", 967 channel); 968 return false; 969 } 970 break; 971 case WIRELESS_MODE_B: 972 if (channel > 14) { 973 netdev_warn(dev, 974 "Channel %d not available in 802.11b.\n", 975 channel); 976 return false; 977 } 978 break; 979 case WIRELESS_MODE_G: 980 case WIRELESS_MODE_N_24G: 981 if (channel > 14) { 982 netdev_warn(dev, 983 "Channel %d not available in 802.11g.\n", 984 channel); 985 return false; 986 } 987 break; 988 } 989 990 priv->SwChnlInProgress = true; 991 if (channel == 0) 992 channel = 1; 993 994 priv->chan = channel; 995 996 priv->SwChnlStage = 0; 997 priv->SwChnlStep = 0; 998 999 if (priv->up) 1000 _rtl92e_phy_switch_channel_work_item(dev); 1001 priv->SwChnlInProgress = false; 1002 return true; 1003 } 1004 1005 static void _rtl92e_cck_tx_power_track_bw_switch_tssi(struct net_device *dev) 1006 { 1007 struct r8192_priv *priv = rtllib_priv(dev); 1008 1009 switch (priv->CurrentChannelBW) { 1010 case HT_CHANNEL_WIDTH_20: 1011 priv->cck_present_attn = 1012 priv->CCKPresentAttentuation_20Mdefault + 1013 priv->CCKPresentAttentuation_difference; 1014 1015 if (priv->cck_present_attn > 1016 (CCKTxBBGainTableLength-1)) 1017 priv->cck_present_attn = 1018 CCKTxBBGainTableLength-1; 1019 if (priv->cck_present_attn < 0) 1020 priv->cck_present_attn = 0; 1021 1022 if (priv->rtllib->current_network.channel == 14 && 1023 !priv->bcck_in_ch14) { 1024 priv->bcck_in_ch14 = true; 1025 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1026 } else if (priv->rtllib->current_network.channel != 1027 14 && priv->bcck_in_ch14) { 1028 priv->bcck_in_ch14 = false; 1029 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1030 } else { 1031 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1032 } 1033 break; 1034 1035 case HT_CHANNEL_WIDTH_20_40: 1036 priv->cck_present_attn = 1037 priv->CCKPresentAttentuation_40Mdefault + 1038 priv->CCKPresentAttentuation_difference; 1039 1040 if (priv->cck_present_attn > 1041 (CCKTxBBGainTableLength - 1)) 1042 priv->cck_present_attn = 1043 CCKTxBBGainTableLength-1; 1044 if (priv->cck_present_attn < 0) 1045 priv->cck_present_attn = 0; 1046 1047 if (priv->rtllib->current_network.channel == 14 && 1048 !priv->bcck_in_ch14) { 1049 priv->bcck_in_ch14 = true; 1050 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1051 } else if (priv->rtllib->current_network.channel != 14 1052 && priv->bcck_in_ch14) { 1053 priv->bcck_in_ch14 = false; 1054 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1055 } else { 1056 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1057 } 1058 break; 1059 } 1060 } 1061 1062 static void _rtl92e_cck_tx_power_track_bw_switch_thermal(struct net_device *dev) 1063 { 1064 struct r8192_priv *priv = rtllib_priv(dev); 1065 1066 if (priv->rtllib->current_network.channel == 14 && 1067 !priv->bcck_in_ch14) 1068 priv->bcck_in_ch14 = true; 1069 else if (priv->rtllib->current_network.channel != 14 && 1070 priv->bcck_in_ch14) 1071 priv->bcck_in_ch14 = false; 1072 1073 switch (priv->CurrentChannelBW) { 1074 case HT_CHANNEL_WIDTH_20: 1075 if (priv->Record_CCK_20Mindex == 0) 1076 priv->Record_CCK_20Mindex = 6; 1077 priv->CCK_index = priv->Record_CCK_20Mindex; 1078 break; 1079 1080 case HT_CHANNEL_WIDTH_20_40: 1081 priv->CCK_index = priv->Record_CCK_40Mindex; 1082 break; 1083 } 1084 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1085 } 1086 1087 static void _rtl92e_cck_tx_power_track_bw_switch(struct net_device *dev) 1088 { 1089 struct r8192_priv *priv = rtllib_priv(dev); 1090 1091 if (priv->IC_Cut >= IC_VersionCut_D) 1092 _rtl92e_cck_tx_power_track_bw_switch_tssi(dev); 1093 else 1094 _rtl92e_cck_tx_power_track_bw_switch_thermal(dev); 1095 } 1096 1097 static void _rtl92e_set_bw_mode_work_item(struct net_device *dev) 1098 { 1099 1100 struct r8192_priv *priv = rtllib_priv(dev); 1101 u8 regBwOpMode; 1102 1103 if (priv->rf_chip == RF_PSEUDO_11N) { 1104 priv->SetBWModeInProgress = false; 1105 return; 1106 } 1107 if (!priv->up) { 1108 netdev_err(dev, "%s(): Driver is not initialized\n", __func__); 1109 return; 1110 } 1111 regBwOpMode = rtl92e_readb(dev, BW_OPMODE); 1112 1113 switch (priv->CurrentChannelBW) { 1114 case HT_CHANNEL_WIDTH_20: 1115 regBwOpMode |= BW_OPMODE_20MHZ; 1116 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode); 1117 break; 1118 1119 case HT_CHANNEL_WIDTH_20_40: 1120 regBwOpMode &= ~BW_OPMODE_20MHZ; 1121 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode); 1122 break; 1123 1124 default: 1125 netdev_err(dev, "%s(): unknown Bandwidth: %#X\n", __func__, 1126 priv->CurrentChannelBW); 1127 break; 1128 } 1129 1130 switch (priv->CurrentChannelBW) { 1131 case HT_CHANNEL_WIDTH_20: 1132 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); 1133 rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); 1134 1135 if (!priv->btxpower_tracking) { 1136 rtl92e_writel(dev, rCCK0_TxFilter1, 0x1a1b0000); 1137 rtl92e_writel(dev, rCCK0_TxFilter2, 0x090e1317); 1138 rtl92e_writel(dev, rCCK0_DebugPort, 0x00000204); 1139 } else { 1140 _rtl92e_cck_tx_power_track_bw_switch(dev); 1141 } 1142 1143 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); 1144 1145 break; 1146 case HT_CHANNEL_WIDTH_20_40: 1147 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); 1148 rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); 1149 1150 if (!priv->btxpower_tracking) { 1151 rtl92e_writel(dev, rCCK0_TxFilter1, 0x35360000); 1152 rtl92e_writel(dev, rCCK0_TxFilter2, 0x121c252e); 1153 rtl92e_writel(dev, rCCK0_DebugPort, 0x00000409); 1154 } else { 1155 _rtl92e_cck_tx_power_track_bw_switch(dev); 1156 } 1157 1158 rtl92e_set_bb_reg(dev, rCCK0_System, bCCKSideBand, 1159 (priv->nCur40MhzPrimeSC>>1)); 1160 rtl92e_set_bb_reg(dev, rOFDM1_LSTF, 0xC00, 1161 priv->nCur40MhzPrimeSC); 1162 1163 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); 1164 break; 1165 default: 1166 netdev_err(dev, "%s(): unknown Bandwidth: %#X\n", __func__, 1167 priv->CurrentChannelBW); 1168 break; 1169 1170 } 1171 1172 switch (priv->rf_chip) { 1173 case RF_8225: 1174 break; 1175 1176 case RF_8256: 1177 rtl92e_set_bandwidth(dev, priv->CurrentChannelBW); 1178 break; 1179 1180 case RF_8258: 1181 break; 1182 1183 case RF_PSEUDO_11N: 1184 break; 1185 1186 default: 1187 netdev_info(dev, "%s(): Unknown RFChipID: %d\n", __func__, 1188 priv->rf_chip); 1189 break; 1190 } 1191 1192 atomic_dec(&(priv->rtllib->atm_swbw)); 1193 priv->SetBWModeInProgress = false; 1194 } 1195 1196 void rtl92e_set_bw_mode(struct net_device *dev, enum ht_channel_width bandwidth, 1197 enum ht_extchnl_offset Offset) 1198 { 1199 struct r8192_priv *priv = rtllib_priv(dev); 1200 1201 1202 if (priv->SetBWModeInProgress) 1203 return; 1204 1205 atomic_inc(&(priv->rtllib->atm_swbw)); 1206 priv->SetBWModeInProgress = true; 1207 1208 priv->CurrentChannelBW = bandwidth; 1209 1210 if (Offset == HT_EXTCHNL_OFFSET_LOWER) 1211 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; 1212 else if (Offset == HT_EXTCHNL_OFFSET_UPPER) 1213 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; 1214 else 1215 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; 1216 1217 _rtl92e_set_bw_mode_work_item(dev); 1218 1219 } 1220 1221 void rtl92e_init_gain(struct net_device *dev, u8 Operation) 1222 { 1223 #define SCAN_RX_INITIAL_GAIN 0x17 1224 #define POWER_DETECTION_TH 0x08 1225 struct r8192_priv *priv = rtllib_priv(dev); 1226 u32 BitMask; 1227 u8 initial_gain; 1228 1229 if (priv->up) { 1230 switch (Operation) { 1231 case IG_Backup: 1232 initial_gain = SCAN_RX_INITIAL_GAIN; 1233 BitMask = bMaskByte0; 1234 if (dm_digtable.dig_algorithm == 1235 DIG_ALGO_BY_FALSE_ALARM) 1236 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8); 1237 priv->initgain_backup.xaagccore1 = 1238 rtl92e_get_bb_reg(dev, rOFDM0_XAAGCCore1, 1239 BitMask); 1240 priv->initgain_backup.xbagccore1 = 1241 rtl92e_get_bb_reg(dev, rOFDM0_XBAGCCore1, 1242 BitMask); 1243 priv->initgain_backup.xcagccore1 = 1244 rtl92e_get_bb_reg(dev, rOFDM0_XCAGCCore1, 1245 BitMask); 1246 priv->initgain_backup.xdagccore1 = 1247 rtl92e_get_bb_reg(dev, rOFDM0_XDAGCCore1, 1248 BitMask); 1249 BitMask = bMaskByte2; 1250 priv->initgain_backup.cca = (u8)rtl92e_get_bb_reg(dev, 1251 rCCK0_CCA, BitMask); 1252 1253 rtl92e_writeb(dev, rOFDM0_XAAGCCore1, initial_gain); 1254 rtl92e_writeb(dev, rOFDM0_XBAGCCore1, initial_gain); 1255 rtl92e_writeb(dev, rOFDM0_XCAGCCore1, initial_gain); 1256 rtl92e_writeb(dev, rOFDM0_XDAGCCore1, initial_gain); 1257 rtl92e_writeb(dev, 0xa0a, POWER_DETECTION_TH); 1258 break; 1259 case IG_Restore: 1260 BitMask = 0x7f; 1261 if (dm_digtable.dig_algorithm == 1262 DIG_ALGO_BY_FALSE_ALARM) 1263 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8); 1264 1265 rtl92e_set_bb_reg(dev, rOFDM0_XAAGCCore1, BitMask, 1266 (u32)priv->initgain_backup.xaagccore1); 1267 rtl92e_set_bb_reg(dev, rOFDM0_XBAGCCore1, BitMask, 1268 (u32)priv->initgain_backup.xbagccore1); 1269 rtl92e_set_bb_reg(dev, rOFDM0_XCAGCCore1, BitMask, 1270 (u32)priv->initgain_backup.xcagccore1); 1271 rtl92e_set_bb_reg(dev, rOFDM0_XDAGCCore1, BitMask, 1272 (u32)priv->initgain_backup.xdagccore1); 1273 BitMask = bMaskByte2; 1274 rtl92e_set_bb_reg(dev, rCCK0_CCA, BitMask, 1275 (u32)priv->initgain_backup.cca); 1276 1277 rtl92e_set_tx_power(dev, 1278 priv->rtllib->current_network.channel); 1279 1280 if (dm_digtable.dig_algorithm == 1281 DIG_ALGO_BY_FALSE_ALARM) 1282 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x1); 1283 break; 1284 } 1285 } 1286 } 1287 1288 void rtl92e_set_rf_off(struct net_device *dev) 1289 { 1290 1291 rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); 1292 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0); 1293 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); 1294 rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0); 1295 rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0); 1296 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); 1297 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0); 1298 rtl92e_writeb(dev, ANAPAR_FOR_8192PciE, 0x07); 1299 1300 } 1301 1302 static bool _rtl92e_set_rf_power_state(struct net_device *dev, 1303 enum rt_rf_power_state rf_power_state) 1304 { 1305 struct r8192_priv *priv = rtllib_priv(dev); 1306 struct rt_pwr_save_ctrl *psc = (struct rt_pwr_save_ctrl *) 1307 (&priv->rtllib->pwr_save_ctrl); 1308 bool bResult = true; 1309 u8 i = 0, QueueID = 0; 1310 struct rtl8192_tx_ring *ring = NULL; 1311 1312 if (priv->SetRFPowerStateInProgress) 1313 return false; 1314 priv->SetRFPowerStateInProgress = true; 1315 1316 switch (priv->rf_chip) { 1317 case RF_8256: 1318 switch (rf_power_state) { 1319 case rf_on: 1320 if ((priv->rtllib->rf_power_state == rf_off) && 1321 RT_IN_PS_LEVEL(psc, RT_RF_OFF_LEVL_HALT_NIC)) { 1322 bool rtstatus; 1323 u32 InitilizeCount = 3; 1324 1325 do { 1326 InitilizeCount--; 1327 rtstatus = rtl92e_enable_nic(dev); 1328 } while (!rtstatus && (InitilizeCount > 0)); 1329 1330 if (!rtstatus) { 1331 netdev_err(dev, 1332 "%s(): Failed to initialize Adapter.\n", 1333 __func__); 1334 priv->SetRFPowerStateInProgress = false; 1335 return false; 1336 } 1337 1338 RT_CLEAR_PS_LEVEL(psc, 1339 RT_RF_OFF_LEVL_HALT_NIC); 1340 } else { 1341 rtl92e_writeb(dev, ANAPAR, 0x37); 1342 mdelay(1); 1343 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 1344 0x4, 0x1); 1345 priv->hw_rf_off_action = 0; 1346 1347 rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE, 1348 BIT4, 0x1); 1349 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 1350 0x300, 0x3); 1351 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 1352 0x18, 0x3); 1353 rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable, 1354 0x3, 0x3); 1355 rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable, 1356 0x3, 0x3); 1357 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 1358 0x60, 0x3); 1359 1360 } 1361 1362 break; 1363 1364 case rf_sleep: 1365 if (priv->rtllib->rf_power_state == rf_off) 1366 break; 1367 1368 1369 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) { 1370 ring = &priv->tx_ring[QueueID]; 1371 1372 if (skb_queue_len(&ring->queue) == 0) { 1373 QueueID++; 1374 continue; 1375 } else { 1376 udelay(10); 1377 i++; 1378 } 1379 1380 if (i >= MAX_DOZE_WAITING_TIMES_9x) 1381 break; 1382 } 1383 rtl92e_set_rf_off(dev); 1384 break; 1385 1386 case rf_off: 1387 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) { 1388 ring = &priv->tx_ring[QueueID]; 1389 1390 if (skb_queue_len(&ring->queue) == 0) { 1391 QueueID++; 1392 continue; 1393 } else { 1394 udelay(10); 1395 i++; 1396 } 1397 1398 if (i >= MAX_DOZE_WAITING_TIMES_9x) 1399 break; 1400 } 1401 1402 if (psc->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && 1403 !RT_IN_PS_LEVEL(psc, RT_RF_OFF_LEVL_HALT_NIC)) { 1404 rtl92e_disable_nic(dev); 1405 RT_SET_PS_LEVEL(psc, RT_RF_OFF_LEVL_HALT_NIC); 1406 } else if (!(psc->RegRfPsLevel & 1407 RT_RF_OFF_LEVL_HALT_NIC)) { 1408 rtl92e_set_rf_off(dev); 1409 } 1410 1411 break; 1412 1413 default: 1414 bResult = false; 1415 netdev_warn(dev, 1416 "%s(): Unknown state requested: 0x%X.\n", 1417 __func__, rf_power_state); 1418 break; 1419 } 1420 1421 break; 1422 1423 default: 1424 netdev_warn(dev, "%s(): Unknown RF type\n", __func__); 1425 break; 1426 } 1427 1428 if (bResult) { 1429 priv->rtllib->rf_power_state = rf_power_state; 1430 1431 switch (priv->rf_chip) { 1432 case RF_8256: 1433 break; 1434 1435 default: 1436 netdev_warn(dev, "%s(): Unknown RF type\n", __func__); 1437 break; 1438 } 1439 } 1440 1441 priv->SetRFPowerStateInProgress = false; 1442 return bResult; 1443 } 1444 1445 bool rtl92e_set_rf_power_state(struct net_device *dev, 1446 enum rt_rf_power_state rf_power_state) 1447 { 1448 struct r8192_priv *priv = rtllib_priv(dev); 1449 1450 bool bResult = false; 1451 1452 if (rf_power_state == priv->rtllib->rf_power_state && 1453 priv->hw_rf_off_action == 0) { 1454 return bResult; 1455 } 1456 1457 bResult = _rtl92e_set_rf_power_state(dev, rf_power_state); 1458 return bResult; 1459 } 1460 1461 void rtl92e_scan_op_backup(struct net_device *dev, u8 Operation) 1462 { 1463 struct r8192_priv *priv = rtllib_priv(dev); 1464 1465 if (priv->up) { 1466 switch (Operation) { 1467 case SCAN_OPT_BACKUP: 1468 priv->rtllib->InitialGainHandler(dev, IG_Backup); 1469 break; 1470 1471 case SCAN_OPT_RESTORE: 1472 priv->rtllib->InitialGainHandler(dev, IG_Restore); 1473 break; 1474 } 1475 } 1476 } 1477