1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. 4 * All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * 17 * File: mac.h 18 * 19 * Purpose: MAC routines 20 * 21 * Author: Tevin Chen 22 * 23 * Date: May 21, 1996 24 * 25 * Revision History: 26 * 07-01-2003 Bryan YC Fan: Re-write codes to support VT3253 spec. 27 * 08-25-2003 Kyle Hsu: Porting MAC functions from sim53. 28 * 09-03-2003 Bryan YC Fan: Add MACvDisableProtectMD & MACvEnableProtectMD 29 */ 30 31 #ifndef __MAC_H__ 32 #define __MAC_H__ 33 34 #include "device.h" 35 36 #define REV_ID_VT3253_A0 0x00 37 #define REV_ID_VT3253_A1 0x01 38 #define REV_ID_VT3253_B0 0x08 39 #define REV_ID_VT3253_B1 0x09 40 41 /* Registers in the MAC */ 42 #define MAC_REG_BISTCMD 0x04 43 #define MAC_REG_BISTSR0 0x05 44 #define MAC_REG_BISTSR1 0x06 45 #define MAC_REG_BISTSR2 0x07 46 #define MAC_REG_I2MCSR 0x08 47 #define MAC_REG_I2MTGID 0x09 48 #define MAC_REG_I2MTGAD 0x0a 49 #define MAC_REG_I2MCFG 0x0b 50 #define MAC_REG_I2MDIPT 0x0c 51 #define MAC_REG_I2MDOPT 0x0e 52 #define MAC_REG_USBSUS 0x0f 53 54 #define MAC_REG_LOCALID 0x14 55 #define MAC_REG_TESTCFG 0x15 56 #define MAC_REG_JUMPER0 0x16 57 #define MAC_REG_JUMPER1 0x17 58 #define MAC_REG_TMCTL 0x18 59 #define MAC_REG_TMDATA0 0x1c 60 #define MAC_REG_TMDATA1 0x1d 61 #define MAC_REG_TMDATA2 0x1e 62 #define MAC_REG_TMDATA3 0x1f 63 64 /* MAC Parameter related */ 65 #define MAC_REG_LRT 0x20 66 #define MAC_REG_SRT 0x21 67 #define MAC_REG_SIFS 0x22 68 #define MAC_REG_DIFS 0x23 69 #define MAC_REG_EIFS 0x24 70 #define MAC_REG_SLOT 0x25 71 #define MAC_REG_BI 0x26 72 #define MAC_REG_CWMAXMIN0 0x28 73 #define MAC_REG_LINKOFFTOTM 0x2a 74 #define MAC_REG_SWTMOT 0x2b 75 #define MAC_REG_RTSOKCNT 0x2c 76 #define MAC_REG_RTSFAILCNT 0x2d 77 #define MAC_REG_ACKFAILCNT 0x2e 78 #define MAC_REG_FCSERRCNT 0x2f 79 80 /* TSF Related */ 81 #define MAC_REG_TSFCNTR 0x30 82 #define MAC_REG_NEXTTBTT 0x38 83 #define MAC_REG_TSFOFST 0x40 84 #define MAC_REG_TFTCTL 0x48 85 86 /* WMAC Control/Status Related */ 87 #define MAC_REG_ENCFG0 0x4c 88 #define MAC_REG_ENCFG1 0x4d 89 #define MAC_REG_ENCFG2 0x4e 90 91 #define MAC_REG_CFG 0x50 92 #define MAC_REG_TEST 0x52 93 #define MAC_REG_HOSTCR 0x54 94 #define MAC_REG_MACCR 0x55 95 #define MAC_REG_RCR 0x56 96 #define MAC_REG_TCR 0x57 97 #define MAC_REG_IMR 0x58 98 #define MAC_REG_ISR 0x5c 99 #define MAC_REG_ISR1 0x5d 100 101 /* Power Saving Related */ 102 #define MAC_REG_PSCFG 0x60 103 #define MAC_REG_PSCTL 0x61 104 #define MAC_REG_PSPWRSIG 0x62 105 #define MAC_REG_BBCR13 0x63 106 #define MAC_REG_AIDATIM 0x64 107 #define MAC_REG_PWBT 0x66 108 #define MAC_REG_WAKEOKTMR 0x68 109 #define MAC_REG_CALTMR 0x69 110 #define MAC_REG_SYNSPACCNT 0x6a 111 #define MAC_REG_WAKSYNOPT 0x6b 112 113 /* Baseband/IF Control Group */ 114 #define MAC_REG_BBREGCTL 0x6c 115 #define MAC_REG_CHANNEL 0x6d 116 #define MAC_REG_BBREGADR 0x6e 117 #define MAC_REG_BBREGDATA 0x6f 118 #define MAC_REG_IFREGCTL 0x70 119 #define MAC_REG_IFDATA 0x71 120 #define MAC_REG_ITRTMSET 0x74 121 #define MAC_REG_PAPEDELAY 0x77 122 #define MAC_REG_SOFTPWRCTL 0x78 123 #define MAC_REG_SOFTPWRCTL2 0x79 124 #define MAC_REG_GPIOCTL0 0x7a 125 #define MAC_REG_GPIOCTL1 0x7b 126 127 /* MiscFF PIO related */ 128 #define MAC_REG_MISCFFNDEX 0xbc 129 #define MAC_REG_MISCFFCTL 0xbe 130 #define MAC_REG_MISCFFDATA 0xc0 131 132 /* MAC Configuration Group */ 133 #define MAC_REG_PAR0 0xc4 134 #define MAC_REG_PAR4 0xc8 135 #define MAC_REG_BSSID0 0xcc 136 #define MAC_REG_BSSID4 0xd0 137 #define MAC_REG_MAR0 0xd4 138 #define MAC_REG_MAR4 0xd8 139 140 /* MAC RSPPKT INFO Group */ 141 #define MAC_REG_RSPINF_B_1 0xdC 142 #define MAC_REG_RSPINF_B_2 0xe0 143 #define MAC_REG_RSPINF_B_5 0xe4 144 #define MAC_REG_RSPINF_B_11 0xe8 145 #define MAC_REG_RSPINF_A_6 0xec 146 #define MAC_REG_RSPINF_A_9 0xee 147 #define MAC_REG_RSPINF_A_12 0xf0 148 #define MAC_REG_RSPINF_A_18 0xf2 149 #define MAC_REG_RSPINF_A_24 0xf4 150 #define MAC_REG_RSPINF_A_36 0xf6 151 #define MAC_REG_RSPINF_A_48 0xf8 152 #define MAC_REG_RSPINF_A_54 0xfa 153 #define MAC_REG_RSPINF_A_72 0xfc 154 155 /* Bits in the I2MCFG EEPROM register */ 156 #define I2MCFG_BOUNDCTL 0x80 157 #define I2MCFG_WAITCTL 0x20 158 #define I2MCFG_SCLOECTL 0x10 159 #define I2MCFG_WBUSYCTL 0x08 160 #define I2MCFG_NORETRY 0x04 161 #define I2MCFG_I2MLDSEQ 0x02 162 #define I2MCFG_I2CMFAST 0x01 163 164 /* Bits in the I2MCSR EEPROM register */ 165 #define I2MCSR_EEMW 0x80 166 #define I2MCSR_EEMR 0x40 167 #define I2MCSR_AUTOLD 0x08 168 #define I2MCSR_NACK 0x02 169 #define I2MCSR_DONE 0x01 170 171 /* Bits in the TMCTL register */ 172 #define TMCTL_TSUSP 0x04 173 #define TMCTL_TMD 0x02 174 #define TMCTL_TE 0x01 175 176 /* Bits in the TFTCTL register */ 177 #define TFTCTL_HWUTSF 0x80 178 #define TFTCTL_TBTTSYNC 0x40 179 #define TFTCTL_HWUTSFEN 0x20 180 #define TFTCTL_TSFCNTRRD 0x10 181 #define TFTCTL_TBTTSYNCEN 0x08 182 #define TFTCTL_TSFSYNCEN 0x04 183 #define TFTCTL_TSFCNTRST 0x02 184 #define TFTCTL_TSFCNTREN 0x01 185 186 /* Bits in the EnhanceCFG_0 register */ 187 #define EnCFG_BBType_a 0x00 188 #define EnCFG_BBType_b 0x01 189 #define EnCFG_BBType_g 0x02 190 #define EnCFG_BBType_MASK 0x03 191 #define EnCFG_ProtectMd 0x20 192 193 /* Bits in the EnhanceCFG_1 register */ 194 #define EnCFG_BcnSusInd 0x01 195 #define EnCFG_BcnSusClr 0x02 196 197 /* Bits in the EnhanceCFG_2 register */ 198 #define EnCFG_NXTBTTCFPSTR 0x01 199 #define EnCFG_BarkerPream 0x02 200 #define EnCFG_PktBurstMode 0x04 201 202 /* Bits in the CFG register */ 203 #define CFG_TKIPOPT 0x80 204 #define CFG_RXDMAOPT 0x40 205 #define CFG_TMOT_SW 0x20 206 #define CFG_TMOT_HWLONG 0x10 207 #define CFG_TMOT_HW 0x00 208 #define CFG_CFPENDOPT 0x08 209 #define CFG_BCNSUSEN 0x04 210 #define CFG_NOTXTIMEOUT 0x02 211 #define CFG_NOBUFOPT 0x01 212 213 /* Bits in the TEST register */ 214 #define TEST_LBEXT 0x80 215 #define TEST_LBINT 0x40 216 #define TEST_LBNONE 0x00 217 #define TEST_SOFTINT 0x20 218 #define TEST_CONTTX 0x10 219 #define TEST_TXPE 0x08 220 #define TEST_NAVDIS 0x04 221 #define TEST_NOCTS 0x02 222 #define TEST_NOACK 0x01 223 224 /* Bits in the HOSTCR register */ 225 #define HOSTCR_TXONST 0x80 226 #define HOSTCR_RXONST 0x40 227 #define HOSTCR_ADHOC 0x20 228 #define HOSTCR_AP 0x10 229 #define HOSTCR_TXON 0x08 230 #define HOSTCR_RXON 0x04 231 #define HOSTCR_MACEN 0x02 232 #define HOSTCR_SOFTRST 0x01 233 234 /* Bits in the MACCR register */ 235 #define MACCR_SYNCFLUSHOK 0x04 236 #define MACCR_SYNCFLUSH 0x02 237 #define MACCR_CLRNAV 0x01 238 239 /* Bits in the RCR register */ 240 #define RCR_SSID 0x80 241 #define RCR_RXALLTYPE 0x40 242 #define RCR_UNICAST 0x20 243 #define RCR_BROADCAST 0x10 244 #define RCR_MULTICAST 0x08 245 #define RCR_WPAERR 0x04 246 #define RCR_ERRCRC 0x02 247 #define RCR_BSSID 0x01 248 249 /* Bits in the TCR register */ 250 #define TCR_SYNCDCFOPT 0x02 251 #define TCR_AUTOBCNTX 0x01 252 253 /* ISR1 */ 254 #define ISR_GPIO3 0x40 255 #define ISR_RXNOBUF 0x08 256 #define ISR_MIBNEARFULL 0x04 257 #define ISR_SOFTINT 0x02 258 #define ISR_FETALERR 0x01 259 260 #define LEDSTS_STS 0x06 261 #define LEDSTS_TMLEN 0x78 262 #define LEDSTS_OFF 0x00 263 #define LEDSTS_ON 0x02 264 #define LEDSTS_SLOW 0x04 265 #define LEDSTS_INTER 0x06 266 267 /* ISR0 */ 268 #define ISR_WATCHDOG 0x80 269 #define ISR_SOFTTIMER 0x40 270 #define ISR_GPIO0 0x20 271 #define ISR_TBTT 0x10 272 #define ISR_RXDMA0 0x08 273 #define ISR_BNTX 0x04 274 #define ISR_ACTX 0x01 275 276 /* Bits in the PSCFG register */ 277 #define PSCFG_PHILIPMD 0x40 278 #define PSCFG_WAKECALEN 0x20 279 #define PSCFG_WAKETMREN 0x10 280 #define PSCFG_BBPSPROG 0x08 281 #define PSCFG_WAKESYN 0x04 282 #define PSCFG_SLEEPSYN 0x02 283 #define PSCFG_AUTOSLEEP 0x01 284 285 /* Bits in the PSCTL register */ 286 #define PSCTL_WAKEDONE 0x20 287 #define PSCTL_PS 0x10 288 #define PSCTL_GO2DOZE 0x08 289 #define PSCTL_LNBCN 0x04 290 #define PSCTL_ALBCN 0x02 291 #define PSCTL_PSEN 0x01 292 293 /* Bits in the PSPWSIG register */ 294 #define PSSIG_WPE3 0x80 295 #define PSSIG_WPE2 0x40 296 #define PSSIG_WPE1 0x20 297 #define PSSIG_WRADIOPE 0x10 298 #define PSSIG_SPE3 0x08 299 #define PSSIG_SPE2 0x04 300 #define PSSIG_SPE1 0x02 301 #define PSSIG_SRADIOPE 0x01 302 303 /* Bits in the BBREGCTL register */ 304 #define BBREGCTL_DONE 0x04 305 #define BBREGCTL_REGR 0x02 306 #define BBREGCTL_REGW 0x01 307 308 /* Bits in the IFREGCTL register */ 309 #define IFREGCTL_DONE 0x04 310 #define IFREGCTL_IFRF 0x02 311 #define IFREGCTL_REGW 0x01 312 313 /* Bits in the SOFTPWRCTL register */ 314 #define SOFTPWRCTL_RFLEOPT 0x08 315 #define SOFTPWRCTL_TXPEINV 0x02 316 #define SOFTPWRCTL_SWPECTI 0x01 317 #define SOFTPWRCTL_SWPAPE 0x20 318 #define SOFTPWRCTL_SWCALEN 0x10 319 #define SOFTPWRCTL_SWRADIO_PE 0x08 320 #define SOFTPWRCTL_SWPE2 0x04 321 #define SOFTPWRCTL_SWPE1 0x02 322 #define SOFTPWRCTL_SWPE3 0x01 323 324 /* Bits in the GPIOCTL1 register */ 325 #define GPIO3_MD 0x20 326 #define GPIO3_DATA 0x40 327 #define GPIO3_INTMD 0x80 328 329 /* Bits in the MISCFFCTL register */ 330 #define MISCFFCTL_WRITE 0x0001 331 332 /* Loopback mode */ 333 #define MAC_LB_EXT 0x02 334 #define MAC_LB_INTERNAL 0x01 335 #define MAC_LB_NONE 0x00 336 337 /* Ethernet address filter type */ 338 #define PKT_TYPE_NONE 0x00 /* turn off receiver */ 339 #define PKT_TYPE_ALL_MULTICAST 0x80 340 #define PKT_TYPE_PROMISCUOUS 0x40 341 #define PKT_TYPE_DIRECTED 0x20 /* obselete */ 342 #define PKT_TYPE_BROADCAST 0x10 343 #define PKT_TYPE_MULTICAST 0x08 344 #define PKT_TYPE_ERROR_WPA 0x04 345 #define PKT_TYPE_ERROR_CRC 0x02 346 #define PKT_TYPE_BSSID 0x01 347 348 #define Default_BI 0x200 349 350 /* MiscFIFO Offset */ 351 #define MISCFIFO_KEYETRY0 32 352 #define MISCFIFO_KEYENTRYSIZE 22 353 354 #define MAC_REVISION_A0 0x00 355 #define MAC_REVISION_A1 0x01 356 357 struct vnt_mac_set_key { 358 union { 359 struct { 360 u8 addr[ETH_ALEN]; 361 __le16 key_ctl; 362 } write __packed; 363 u32 swap[2]; 364 } u; 365 u8 key[WLAN_KEY_LEN_CCMP]; 366 } __packed; 367 368 void vnt_mac_set_filter(struct vnt_private *priv, u64 mc_filter); 369 void vnt_mac_shutdown(struct vnt_private *priv); 370 void vnt_mac_set_bb_type(struct vnt_private *priv, u8 type); 371 void vnt_mac_disable_keyentry(struct vnt_private *priv, u8 entry_idx); 372 void vnt_mac_set_keyentry(struct vnt_private *priv, u16 key_ctl, u32 entry_idx, 373 u32 key_idx, u8 *addr, u8 *key); 374 void vnt_mac_reg_bits_off(struct vnt_private *priv, u8 reg_ofs, u8 bits); 375 void vnt_mac_reg_bits_on(struct vnt_private *priv, u8 reg_ofs, u8 bits); 376 void vnt_mac_write_word(struct vnt_private *priv, u8 reg_ofs, u16 word); 377 void vnt_mac_set_bssid_addr(struct vnt_private *priv, u8 *addr); 378 void vnt_mac_enable_protect_mode(struct vnt_private *priv); 379 void vnt_mac_disable_protect_mode(struct vnt_private *priv); 380 void vnt_mac_enable_barker_preamble_mode(struct vnt_private *priv); 381 void vnt_mac_disable_barker_preamble_mode(struct vnt_private *priv); 382 void vnt_mac_set_beacon_interval(struct vnt_private *priv, u16 interval); 383 void vnt_mac_set_led(struct vnt_private *privpriv, u8 state, u8 led); 384 385 #endif /* __MAC_H__ */ 386