1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020 Linaro Limited 4 * 5 * Based on original driver: 6 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. 7 * 8 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/iio/adc/qcom-vadc-common.h> 13 #include <linux/iio/consumer.h> 14 #include <linux/interrupt.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_device.h> 18 #include <linux/platform_device.h> 19 #include <linux/regmap.h> 20 #include <linux/thermal.h> 21 #include <asm-generic/unaligned.h> 22 23 /* 24 * Thermal monitoring block consists of 8 (ADC_TM5_NUM_CHANNELS) channels. Each 25 * channel is programmed to use one of ADC channels for voltage comparison. 26 * Voltages are programmed using ADC codes, so we have to convert temp to 27 * voltage and then to ADC code value. 28 * 29 * Configuration of TM channels must match configuration of corresponding ADC 30 * channels. 31 */ 32 33 #define ADC5_MAX_CHANNEL 0xc0 34 #define ADC_TM5_NUM_CHANNELS 8 35 36 #define ADC_TM5_STATUS_LOW 0x0a 37 38 #define ADC_TM5_STATUS_HIGH 0x0b 39 40 #define ADC_TM5_NUM_BTM 0x0f 41 42 #define ADC_TM5_ADC_DIG_PARAM 0x42 43 44 #define ADC_TM5_FAST_AVG_CTL (ADC_TM5_ADC_DIG_PARAM + 1) 45 #define ADC_TM5_FAST_AVG_EN BIT(7) 46 47 #define ADC_TM5_MEAS_INTERVAL_CTL (ADC_TM5_ADC_DIG_PARAM + 2) 48 #define ADC_TM5_TIMER1 3 /* 3.9ms */ 49 50 #define ADC_TM5_MEAS_INTERVAL_CTL2 (ADC_TM5_ADC_DIG_PARAM + 3) 51 #define ADC_TM5_MEAS_INTERVAL_CTL2_MASK 0xf0 52 #define ADC_TM5_TIMER2 10 /* 1 second */ 53 #define ADC_TM5_MEAS_INTERVAL_CTL3_MASK 0xf 54 #define ADC_TM5_TIMER3 4 /* 4 second */ 55 56 #define ADC_TM_EN_CTL1 0x46 57 #define ADC_TM_EN BIT(7) 58 #define ADC_TM_CONV_REQ 0x47 59 #define ADC_TM_CONV_REQ_EN BIT(7) 60 61 #define ADC_TM5_M_CHAN_BASE 0x60 62 63 #define ADC_TM5_M_ADC_CH_SEL_CTL(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 0) 64 #define ADC_TM5_M_LOW_THR0(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 1) 65 #define ADC_TM5_M_LOW_THR1(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 2) 66 #define ADC_TM5_M_HIGH_THR0(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 3) 67 #define ADC_TM5_M_HIGH_THR1(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 4) 68 #define ADC_TM5_M_MEAS_INTERVAL_CTL(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 5) 69 #define ADC_TM5_M_CTL(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 6) 70 #define ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK 0xf 71 #define ADC_TM5_M_CTL_CAL_SEL_MASK 0x30 72 #define ADC_TM5_M_CTL_CAL_VAL 0x40 73 #define ADC_TM5_M_EN(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 7) 74 #define ADC_TM5_M_MEAS_EN BIT(7) 75 #define ADC_TM5_M_HIGH_THR_INT_EN BIT(1) 76 #define ADC_TM5_M_LOW_THR_INT_EN BIT(0) 77 78 #define ADC_TM_GEN2_STATUS1 0x08 79 #define ADC_TM_GEN2_STATUS_LOW_SET 0x09 80 #define ADC_TM_GEN2_STATUS_LOW_CLR 0x0a 81 #define ADC_TM_GEN2_STATUS_HIGH_SET 0x0b 82 #define ADC_TM_GEN2_STATUS_HIGH_CLR 0x0c 83 84 #define ADC_TM_GEN2_CFG_HS_SET 0x0d 85 #define ADC_TM_GEN2_CFG_HS_FLAG BIT(0) 86 #define ADC_TM_GEN2_CFG_HS_CLR 0x0e 87 88 #define ADC_TM_GEN2_SID 0x40 89 90 #define ADC_TM_GEN2_CH_CTL 0x41 91 #define ADC_TM_GEN2_TM_CH_SEL GENMASK(7, 5) 92 #define ADC_TM_GEN2_MEAS_INT_SEL GENMASK(3, 2) 93 94 #define ADC_TM_GEN2_ADC_DIG_PARAM 0x42 95 #define ADC_TM_GEN2_CTL_CAL_SEL GENMASK(5, 4) 96 #define ADC_TM_GEN2_CTL_DEC_RATIO_MASK GENMASK(3, 2) 97 98 #define ADC_TM_GEN2_FAST_AVG_CTL 0x43 99 #define ADC_TM_GEN2_FAST_AVG_EN BIT(7) 100 101 #define ADC_TM_GEN2_ADC_CH_SEL_CTL 0x44 102 103 #define ADC_TM_GEN2_DELAY_CTL 0x45 104 #define ADC_TM_GEN2_HW_SETTLE_DELAY GENMASK(3, 0) 105 106 #define ADC_TM_GEN2_EN_CTL1 0x46 107 #define ADC_TM_GEN2_EN BIT(7) 108 109 #define ADC_TM_GEN2_CONV_REQ 0x47 110 #define ADC_TM_GEN2_CONV_REQ_EN BIT(7) 111 112 #define ADC_TM_GEN2_LOW_THR0 0x49 113 #define ADC_TM_GEN2_LOW_THR1 0x4a 114 #define ADC_TM_GEN2_HIGH_THR0 0x4b 115 #define ADC_TM_GEN2_HIGH_THR1 0x4c 116 #define ADC_TM_GEN2_LOWER_MASK(n) ((n) & GENMASK(7, 0)) 117 #define ADC_TM_GEN2_UPPER_MASK(n) (((n) & GENMASK(15, 8)) >> 8) 118 119 #define ADC_TM_GEN2_MEAS_IRQ_EN 0x4d 120 #define ADC_TM_GEN2_MEAS_EN BIT(7) 121 #define ADC_TM5_GEN2_HIGH_THR_INT_EN BIT(1) 122 #define ADC_TM5_GEN2_LOW_THR_INT_EN BIT(0) 123 124 #define ADC_TM_GEN2_MEAS_INT_LSB 0x50 125 #define ADC_TM_GEN2_MEAS_INT_MSB 0x51 126 #define ADC_TM_GEN2_MEAS_INT_MODE 0x52 127 128 #define ADC_TM_GEN2_Mn_DATA0(n) ((n * 2) + 0xa0) 129 #define ADC_TM_GEN2_Mn_DATA1(n) ((n * 2) + 0xa1) 130 #define ADC_TM_GEN2_DATA_SHIFT 8 131 132 enum adc5_timer_select { 133 ADC5_TIMER_SEL_1 = 0, 134 ADC5_TIMER_SEL_2, 135 ADC5_TIMER_SEL_3, 136 ADC5_TIMER_SEL_NONE, 137 }; 138 139 enum adc5_gen { 140 ADC_TM5, 141 ADC_TM_HC, 142 ADC_TM5_GEN2, 143 ADC_TM5_MAX 144 }; 145 146 enum adc_tm5_cal_method { 147 ADC_TM5_NO_CAL = 0, 148 ADC_TM5_RATIOMETRIC_CAL, 149 ADC_TM5_ABSOLUTE_CAL 150 }; 151 152 enum adc_tm_gen2_time_select { 153 MEAS_INT_50MS = 0, 154 MEAS_INT_100MS, 155 MEAS_INT_1S, 156 MEAS_INT_SET, 157 MEAS_INT_NONE, 158 }; 159 160 struct adc_tm5_chip; 161 struct adc_tm5_channel; 162 163 struct adc_tm5_data { 164 const u32 full_scale_code_volt; 165 unsigned int *decimation; 166 unsigned int *hw_settle; 167 int (*disable_channel)(struct adc_tm5_channel *channel); 168 int (*configure)(struct adc_tm5_channel *channel, int low, int high); 169 irqreturn_t (*isr)(int irq, void *data); 170 int (*init)(struct adc_tm5_chip *chip); 171 char *irq_name; 172 int gen; 173 }; 174 175 /** 176 * struct adc_tm5_channel - ADC Thermal Monitoring channel data. 177 * @channel: channel number. 178 * @adc_channel: corresponding ADC channel number. 179 * @cal_method: calibration method. 180 * @prescale: channel scaling performed on the input signal. 181 * @hw_settle_time: the time between AMUX being configured and the 182 * start of conversion. 183 * @decimation: sampling rate supported for the channel. 184 * @avg_samples: ability to provide single result from the ADC 185 * that is an average of multiple measurements. 186 * @high_thr_en: channel upper voltage threshold enable state. 187 * @low_thr_en: channel lower voltage threshold enable state. 188 * @meas_en: recurring measurement enable state 189 * @iio: IIO channel instance used by this channel. 190 * @chip: ADC TM chip instance. 191 * @tzd: thermal zone device used by this channel. 192 */ 193 struct adc_tm5_channel { 194 unsigned int channel; 195 unsigned int adc_channel; 196 enum adc_tm5_cal_method cal_method; 197 unsigned int prescale; 198 unsigned int hw_settle_time; 199 unsigned int decimation; /* For Gen2 ADC_TM */ 200 unsigned int avg_samples; /* For Gen2 ADC_TM */ 201 bool high_thr_en; /* For Gen2 ADC_TM */ 202 bool low_thr_en; /* For Gen2 ADC_TM */ 203 bool meas_en; /* For Gen2 ADC_TM */ 204 struct iio_channel *iio; 205 struct adc_tm5_chip *chip; 206 struct thermal_zone_device *tzd; 207 }; 208 209 /** 210 * struct adc_tm5_chip - ADC Thermal Monitoring properties 211 * @regmap: SPMI ADC5 Thermal Monitoring peripheral register map field. 212 * @dev: SPMI ADC5 device. 213 * @data: software configuration data. 214 * @channels: array of ADC TM channel data. 215 * @nchannels: amount of channels defined/allocated 216 * @decimation: sampling rate supported for the channel. 217 * Applies to all channels, used only on Gen1 ADC_TM. 218 * @avg_samples: ability to provide single result from the ADC 219 * that is an average of multiple measurements. Applies to all 220 * channels, used only on Gen1 ADC_TM. 221 * @base: base address of TM registers. 222 * @adc_mutex_lock: ADC_TM mutex lock, used only on Gen2 ADC_TM. 223 * It is used to ensure only one ADC channel configuration 224 * is done at a time using the shared set of configuration 225 * registers. 226 */ 227 struct adc_tm5_chip { 228 struct regmap *regmap; 229 struct device *dev; 230 const struct adc_tm5_data *data; 231 struct adc_tm5_channel *channels; 232 unsigned int nchannels; 233 unsigned int decimation; 234 unsigned int avg_samples; 235 u16 base; 236 struct mutex adc_mutex_lock; 237 }; 238 239 static int adc_tm5_read(struct adc_tm5_chip *adc_tm, u16 offset, u8 *data, int len) 240 { 241 return regmap_bulk_read(adc_tm->regmap, adc_tm->base + offset, data, len); 242 } 243 244 static int adc_tm5_write(struct adc_tm5_chip *adc_tm, u16 offset, u8 *data, int len) 245 { 246 return regmap_bulk_write(adc_tm->regmap, adc_tm->base + offset, data, len); 247 } 248 249 static int adc_tm5_reg_update(struct adc_tm5_chip *adc_tm, u16 offset, u8 mask, u8 val) 250 { 251 return regmap_write_bits(adc_tm->regmap, adc_tm->base + offset, mask, val); 252 } 253 254 static irqreturn_t adc_tm5_isr(int irq, void *data) 255 { 256 struct adc_tm5_chip *chip = data; 257 u8 status_low, status_high, ctl; 258 int ret, i; 259 260 ret = adc_tm5_read(chip, ADC_TM5_STATUS_LOW, &status_low, sizeof(status_low)); 261 if (unlikely(ret)) { 262 dev_err(chip->dev, "read status low failed: %d\n", ret); 263 return IRQ_HANDLED; 264 } 265 266 ret = adc_tm5_read(chip, ADC_TM5_STATUS_HIGH, &status_high, sizeof(status_high)); 267 if (unlikely(ret)) { 268 dev_err(chip->dev, "read status high failed: %d\n", ret); 269 return IRQ_HANDLED; 270 } 271 272 for (i = 0; i < chip->nchannels; i++) { 273 bool upper_set = false, lower_set = false; 274 unsigned int ch = chip->channels[i].channel; 275 276 /* No TZD, we warned at the boot time */ 277 if (!chip->channels[i].tzd) 278 continue; 279 280 ret = adc_tm5_read(chip, ADC_TM5_M_EN(ch), &ctl, sizeof(ctl)); 281 if (unlikely(ret)) { 282 dev_err(chip->dev, "ctl read failed: %d, channel %d\n", ret, i); 283 continue; 284 } 285 286 if (!(ctl & ADC_TM5_M_MEAS_EN)) 287 continue; 288 289 lower_set = (status_low & BIT(ch)) && 290 (ctl & ADC_TM5_M_LOW_THR_INT_EN); 291 292 upper_set = (status_high & BIT(ch)) && 293 (ctl & ADC_TM5_M_HIGH_THR_INT_EN); 294 295 if (upper_set || lower_set) 296 thermal_zone_device_update(chip->channels[i].tzd, 297 THERMAL_EVENT_UNSPECIFIED); 298 } 299 300 return IRQ_HANDLED; 301 } 302 303 static irqreturn_t adc_tm5_gen2_isr(int irq, void *data) 304 { 305 struct adc_tm5_chip *chip = data; 306 u8 status_low, status_high; 307 int ret, i; 308 309 ret = adc_tm5_read(chip, ADC_TM_GEN2_STATUS_LOW_CLR, &status_low, sizeof(status_low)); 310 if (ret) { 311 dev_err(chip->dev, "read status_low failed: %d\n", ret); 312 return IRQ_HANDLED; 313 } 314 315 ret = adc_tm5_read(chip, ADC_TM_GEN2_STATUS_HIGH_CLR, &status_high, sizeof(status_high)); 316 if (ret) { 317 dev_err(chip->dev, "read status_high failed: %d\n", ret); 318 return IRQ_HANDLED; 319 } 320 321 ret = adc_tm5_write(chip, ADC_TM_GEN2_STATUS_LOW_CLR, &status_low, sizeof(status_low)); 322 if (ret < 0) { 323 dev_err(chip->dev, "clear status low failed with %d\n", ret); 324 return IRQ_HANDLED; 325 } 326 327 ret = adc_tm5_write(chip, ADC_TM_GEN2_STATUS_HIGH_CLR, &status_high, sizeof(status_high)); 328 if (ret < 0) { 329 dev_err(chip->dev, "clear status high failed with %d\n", ret); 330 return IRQ_HANDLED; 331 } 332 333 for (i = 0; i < chip->nchannels; i++) { 334 bool upper_set = false, lower_set = false; 335 unsigned int ch = chip->channels[i].channel; 336 337 /* No TZD, we warned at the boot time */ 338 if (!chip->channels[i].tzd) 339 continue; 340 341 if (!chip->channels[i].meas_en) 342 continue; 343 344 lower_set = (status_low & BIT(ch)) && 345 (chip->channels[i].low_thr_en); 346 347 upper_set = (status_high & BIT(ch)) && 348 (chip->channels[i].high_thr_en); 349 350 if (upper_set || lower_set) 351 thermal_zone_device_update(chip->channels[i].tzd, 352 THERMAL_EVENT_UNSPECIFIED); 353 } 354 355 return IRQ_HANDLED; 356 } 357 358 static int adc_tm5_get_temp(void *data, int *temp) 359 { 360 struct adc_tm5_channel *channel = data; 361 int ret; 362 363 if (!channel || !channel->iio) 364 return -EINVAL; 365 366 ret = iio_read_channel_processed(channel->iio, temp); 367 if (ret < 0) 368 return ret; 369 370 if (ret != IIO_VAL_INT) 371 return -EINVAL; 372 373 return 0; 374 } 375 376 static int adc_tm5_disable_channel(struct adc_tm5_channel *channel) 377 { 378 struct adc_tm5_chip *chip = channel->chip; 379 unsigned int reg = ADC_TM5_M_EN(channel->channel); 380 381 return adc_tm5_reg_update(chip, reg, 382 ADC_TM5_M_MEAS_EN | 383 ADC_TM5_M_HIGH_THR_INT_EN | 384 ADC_TM5_M_LOW_THR_INT_EN, 385 0); 386 } 387 388 #define ADC_TM_GEN2_POLL_DELAY_MIN_US 100 389 #define ADC_TM_GEN2_POLL_DELAY_MAX_US 110 390 #define ADC_TM_GEN2_POLL_RETRY_COUNT 3 391 392 static int32_t adc_tm5_gen2_conv_req(struct adc_tm5_chip *chip) 393 { 394 int ret; 395 u8 data; 396 unsigned int count; 397 398 data = ADC_TM_GEN2_EN; 399 ret = adc_tm5_write(chip, ADC_TM_GEN2_EN_CTL1, &data, 1); 400 if (ret < 0) { 401 dev_err(chip->dev, "adc-tm enable failed with %d\n", ret); 402 return ret; 403 } 404 405 data = ADC_TM_GEN2_CFG_HS_FLAG; 406 ret = adc_tm5_write(chip, ADC_TM_GEN2_CFG_HS_SET, &data, 1); 407 if (ret < 0) { 408 dev_err(chip->dev, "adc-tm handshake failed with %d\n", ret); 409 return ret; 410 } 411 412 data = ADC_TM_GEN2_CONV_REQ_EN; 413 ret = adc_tm5_write(chip, ADC_TM_GEN2_CONV_REQ, &data, 1); 414 if (ret < 0) { 415 dev_err(chip->dev, "adc-tm request conversion failed with %d\n", ret); 416 return ret; 417 } 418 419 /* 420 * SW sets a handshake bit and waits for PBS to clear it 421 * before the next conversion request can be queued. 422 */ 423 424 for (count = 0; count < ADC_TM_GEN2_POLL_RETRY_COUNT; count++) { 425 ret = adc_tm5_read(chip, ADC_TM_GEN2_CFG_HS_SET, &data, sizeof(data)); 426 if (ret < 0) { 427 dev_err(chip->dev, "adc-tm read failed with %d\n", ret); 428 return ret; 429 } 430 431 if (!(data & ADC_TM_GEN2_CFG_HS_FLAG)) 432 return ret; 433 usleep_range(ADC_TM_GEN2_POLL_DELAY_MIN_US, 434 ADC_TM_GEN2_POLL_DELAY_MAX_US); 435 } 436 437 dev_err(chip->dev, "adc-tm conversion request handshake timed out\n"); 438 439 return -ETIMEDOUT; 440 } 441 442 static int adc_tm5_gen2_disable_channel(struct adc_tm5_channel *channel) 443 { 444 struct adc_tm5_chip *chip = channel->chip; 445 int ret; 446 u8 val; 447 448 mutex_lock(&chip->adc_mutex_lock); 449 450 channel->meas_en = false; 451 channel->high_thr_en = false; 452 channel->low_thr_en = false; 453 454 ret = adc_tm5_read(chip, ADC_TM_GEN2_CH_CTL, &val, sizeof(val)); 455 if (ret < 0) { 456 dev_err(chip->dev, "adc-tm block read failed with %d\n", ret); 457 goto disable_fail; 458 } 459 460 val &= ~ADC_TM_GEN2_TM_CH_SEL; 461 val |= FIELD_PREP(ADC_TM_GEN2_TM_CH_SEL, channel->channel); 462 463 ret = adc_tm5_write(chip, ADC_TM_GEN2_CH_CTL, &val, 1); 464 if (ret < 0) { 465 dev_err(chip->dev, "adc-tm channel disable failed with %d\n", ret); 466 goto disable_fail; 467 } 468 469 val = 0; 470 ret = adc_tm5_write(chip, ADC_TM_GEN2_MEAS_IRQ_EN, &val, 1); 471 if (ret < 0) { 472 dev_err(chip->dev, "adc-tm interrupt disable failed with %d\n", ret); 473 goto disable_fail; 474 } 475 476 477 ret = adc_tm5_gen2_conv_req(channel->chip); 478 if (ret < 0) 479 dev_err(chip->dev, "adc-tm channel configure failed with %d\n", ret); 480 481 disable_fail: 482 mutex_unlock(&chip->adc_mutex_lock); 483 return ret; 484 } 485 486 static int adc_tm5_enable(struct adc_tm5_chip *chip) 487 { 488 int ret; 489 u8 data; 490 491 data = ADC_TM_EN; 492 ret = adc_tm5_write(chip, ADC_TM_EN_CTL1, &data, sizeof(data)); 493 if (ret < 0) { 494 dev_err(chip->dev, "adc-tm enable failed\n"); 495 return ret; 496 } 497 498 data = ADC_TM_CONV_REQ_EN; 499 ret = adc_tm5_write(chip, ADC_TM_CONV_REQ, &data, sizeof(data)); 500 if (ret < 0) { 501 dev_err(chip->dev, "adc-tm request conversion failed\n"); 502 return ret; 503 } 504 505 return 0; 506 } 507 508 static int adc_tm5_configure(struct adc_tm5_channel *channel, int low, int high) 509 { 510 struct adc_tm5_chip *chip = channel->chip; 511 u8 buf[8]; 512 u16 reg = ADC_TM5_M_ADC_CH_SEL_CTL(channel->channel); 513 int ret; 514 515 ret = adc_tm5_read(chip, reg, buf, sizeof(buf)); 516 if (ret) { 517 dev_err(chip->dev, "channel %d params read failed: %d\n", channel->channel, ret); 518 return ret; 519 } 520 521 buf[0] = channel->adc_channel; 522 523 /* High temperature corresponds to low voltage threshold */ 524 if (high != INT_MAX) { 525 u16 adc_code = qcom_adc_tm5_temp_volt_scale(channel->prescale, 526 chip->data->full_scale_code_volt, high); 527 528 put_unaligned_le16(adc_code, &buf[1]); 529 buf[7] |= ADC_TM5_M_LOW_THR_INT_EN; 530 } else { 531 buf[7] &= ~ADC_TM5_M_LOW_THR_INT_EN; 532 } 533 534 /* Low temperature corresponds to high voltage threshold */ 535 if (low != -INT_MAX) { 536 u16 adc_code = qcom_adc_tm5_temp_volt_scale(channel->prescale, 537 chip->data->full_scale_code_volt, low); 538 539 put_unaligned_le16(adc_code, &buf[3]); 540 buf[7] |= ADC_TM5_M_HIGH_THR_INT_EN; 541 } else { 542 buf[7] &= ~ADC_TM5_M_HIGH_THR_INT_EN; 543 } 544 545 buf[5] = ADC5_TIMER_SEL_2; 546 547 /* Set calibration select, hw_settle delay */ 548 buf[6] &= ~ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK; 549 buf[6] |= FIELD_PREP(ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK, channel->hw_settle_time); 550 buf[6] &= ~ADC_TM5_M_CTL_CAL_SEL_MASK; 551 buf[6] |= FIELD_PREP(ADC_TM5_M_CTL_CAL_SEL_MASK, channel->cal_method); 552 553 buf[7] |= ADC_TM5_M_MEAS_EN; 554 555 ret = adc_tm5_write(chip, reg, buf, sizeof(buf)); 556 if (ret) { 557 dev_err(chip->dev, "channel %d params write failed: %d\n", channel->channel, ret); 558 return ret; 559 } 560 561 return adc_tm5_enable(chip); 562 } 563 564 static int adc_tm5_gen2_configure(struct adc_tm5_channel *channel, int low, int high) 565 { 566 struct adc_tm5_chip *chip = channel->chip; 567 int ret; 568 u8 buf[14]; 569 u16 adc_code; 570 571 mutex_lock(&chip->adc_mutex_lock); 572 573 channel->meas_en = true; 574 575 ret = adc_tm5_read(chip, ADC_TM_GEN2_SID, buf, sizeof(buf)); 576 if (ret < 0) { 577 dev_err(chip->dev, "adc-tm block read failed with %d\n", ret); 578 goto config_fail; 579 } 580 581 /* Set SID from virtual channel number */ 582 buf[0] = channel->adc_channel >> 8; 583 584 /* Set TM channel number used and measurement interval */ 585 buf[1] &= ~ADC_TM_GEN2_TM_CH_SEL; 586 buf[1] |= FIELD_PREP(ADC_TM_GEN2_TM_CH_SEL, channel->channel); 587 buf[1] &= ~ADC_TM_GEN2_MEAS_INT_SEL; 588 buf[1] |= FIELD_PREP(ADC_TM_GEN2_MEAS_INT_SEL, MEAS_INT_1S); 589 590 buf[2] &= ~ADC_TM_GEN2_CTL_DEC_RATIO_MASK; 591 buf[2] |= FIELD_PREP(ADC_TM_GEN2_CTL_DEC_RATIO_MASK, channel->decimation); 592 buf[2] &= ~ADC_TM_GEN2_CTL_CAL_SEL; 593 buf[2] |= FIELD_PREP(ADC_TM_GEN2_CTL_CAL_SEL, channel->cal_method); 594 595 buf[3] = channel->avg_samples | ADC_TM_GEN2_FAST_AVG_EN; 596 597 buf[4] = channel->adc_channel & 0xff; 598 599 buf[5] = channel->hw_settle_time & ADC_TM_GEN2_HW_SETTLE_DELAY; 600 601 /* High temperature corresponds to low voltage threshold */ 602 if (high != INT_MAX) { 603 channel->low_thr_en = true; 604 adc_code = qcom_adc_tm5_gen2_temp_res_scale(high); 605 put_unaligned_le16(adc_code, &buf[9]); 606 } else { 607 channel->low_thr_en = false; 608 } 609 610 /* Low temperature corresponds to high voltage threshold */ 611 if (low != -INT_MAX) { 612 channel->high_thr_en = true; 613 adc_code = qcom_adc_tm5_gen2_temp_res_scale(low); 614 put_unaligned_le16(adc_code, &buf[11]); 615 } else { 616 channel->high_thr_en = false; 617 } 618 619 buf[13] = ADC_TM_GEN2_MEAS_EN; 620 if (channel->high_thr_en) 621 buf[13] |= ADC_TM5_GEN2_HIGH_THR_INT_EN; 622 if (channel->low_thr_en) 623 buf[13] |= ADC_TM5_GEN2_LOW_THR_INT_EN; 624 625 ret = adc_tm5_write(chip, ADC_TM_GEN2_SID, buf, sizeof(buf)); 626 if (ret) { 627 dev_err(chip->dev, "channel %d params write failed: %d\n", channel->channel, ret); 628 goto config_fail; 629 } 630 631 ret = adc_tm5_gen2_conv_req(channel->chip); 632 if (ret < 0) 633 dev_err(chip->dev, "adc-tm channel configure failed with %d\n", ret); 634 635 config_fail: 636 mutex_unlock(&chip->adc_mutex_lock); 637 return ret; 638 } 639 640 static int adc_tm5_set_trips(void *data, int low, int high) 641 { 642 struct adc_tm5_channel *channel = data; 643 struct adc_tm5_chip *chip; 644 int ret; 645 646 if (!channel) 647 return -EINVAL; 648 649 chip = channel->chip; 650 dev_dbg(chip->dev, "%d:low(mdegC):%d, high(mdegC):%d\n", 651 channel->channel, low, high); 652 653 if (high == INT_MAX && low <= -INT_MAX) 654 ret = chip->data->disable_channel(channel); 655 else 656 ret = chip->data->configure(channel, low, high); 657 658 return ret; 659 } 660 661 static struct thermal_zone_of_device_ops adc_tm5_thermal_ops = { 662 .get_temp = adc_tm5_get_temp, 663 .set_trips = adc_tm5_set_trips, 664 }; 665 666 static int adc_tm5_register_tzd(struct adc_tm5_chip *adc_tm) 667 { 668 unsigned int i; 669 struct thermal_zone_device *tzd; 670 671 for (i = 0; i < adc_tm->nchannels; i++) { 672 adc_tm->channels[i].chip = adc_tm; 673 674 tzd = devm_thermal_zone_of_sensor_register(adc_tm->dev, 675 adc_tm->channels[i].channel, 676 &adc_tm->channels[i], 677 &adc_tm5_thermal_ops); 678 if (IS_ERR(tzd)) { 679 if (PTR_ERR(tzd) == -ENODEV) { 680 dev_warn(adc_tm->dev, "thermal sensor on channel %d is not used\n", 681 adc_tm->channels[i].channel); 682 continue; 683 } 684 685 dev_err(adc_tm->dev, "Error registering TZ zone for channel %d: %ld\n", 686 adc_tm->channels[i].channel, PTR_ERR(tzd)); 687 return PTR_ERR(tzd); 688 } 689 adc_tm->channels[i].tzd = tzd; 690 } 691 692 return 0; 693 } 694 695 static int adc_tm_hc_init(struct adc_tm5_chip *chip) 696 { 697 unsigned int i; 698 u8 buf[2]; 699 int ret; 700 701 for (i = 0; i < chip->nchannels; i++) { 702 if (chip->channels[i].channel >= ADC_TM5_NUM_CHANNELS) { 703 dev_err(chip->dev, "Invalid channel %d\n", chip->channels[i].channel); 704 return -EINVAL; 705 } 706 } 707 708 buf[0] = chip->decimation; 709 buf[1] = chip->avg_samples | ADC_TM5_FAST_AVG_EN; 710 711 ret = adc_tm5_write(chip, ADC_TM5_ADC_DIG_PARAM, buf, sizeof(buf)); 712 if (ret) 713 dev_err(chip->dev, "block write failed: %d\n", ret); 714 715 return ret; 716 } 717 718 static int adc_tm5_init(struct adc_tm5_chip *chip) 719 { 720 u8 buf[4], channels_available; 721 int ret; 722 unsigned int i; 723 724 ret = adc_tm5_read(chip, ADC_TM5_NUM_BTM, 725 &channels_available, sizeof(channels_available)); 726 if (ret) { 727 dev_err(chip->dev, "read failed for BTM channels\n"); 728 return ret; 729 } 730 731 for (i = 0; i < chip->nchannels; i++) { 732 if (chip->channels[i].channel >= channels_available) { 733 dev_err(chip->dev, "Invalid channel %d\n", chip->channels[i].channel); 734 return -EINVAL; 735 } 736 } 737 738 buf[0] = chip->decimation; 739 buf[1] = chip->avg_samples | ADC_TM5_FAST_AVG_EN; 740 buf[2] = ADC_TM5_TIMER1; 741 buf[3] = FIELD_PREP(ADC_TM5_MEAS_INTERVAL_CTL2_MASK, ADC_TM5_TIMER2) | 742 FIELD_PREP(ADC_TM5_MEAS_INTERVAL_CTL3_MASK, ADC_TM5_TIMER3); 743 744 ret = adc_tm5_write(chip, ADC_TM5_ADC_DIG_PARAM, buf, sizeof(buf)); 745 if (ret) { 746 dev_err(chip->dev, "block write failed: %d\n", ret); 747 return ret; 748 } 749 750 return ret; 751 } 752 753 static int adc_tm5_gen2_init(struct adc_tm5_chip *chip) 754 { 755 u8 channels_available; 756 int ret; 757 unsigned int i; 758 759 ret = adc_tm5_read(chip, ADC_TM5_NUM_BTM, 760 &channels_available, sizeof(channels_available)); 761 if (ret) { 762 dev_err(chip->dev, "read failed for BTM channels\n"); 763 return ret; 764 } 765 766 for (i = 0; i < chip->nchannels; i++) { 767 if (chip->channels[i].channel >= channels_available) { 768 dev_err(chip->dev, "Invalid channel %d\n", chip->channels[i].channel); 769 return -EINVAL; 770 } 771 } 772 773 mutex_init(&chip->adc_mutex_lock); 774 775 return ret; 776 } 777 778 static int adc_tm5_get_dt_channel_data(struct adc_tm5_chip *adc_tm, 779 struct adc_tm5_channel *channel, 780 struct device_node *node) 781 { 782 const char *name = node->name; 783 u32 chan, value, adc_channel, varr[2]; 784 int ret; 785 struct device *dev = adc_tm->dev; 786 struct of_phandle_args args; 787 788 ret = of_property_read_u32(node, "reg", &chan); 789 if (ret) { 790 dev_err(dev, "%s: invalid channel number %d\n", name, ret); 791 return ret; 792 } 793 794 if (chan >= ADC_TM5_NUM_CHANNELS) { 795 dev_err(dev, "%s: channel number too big: %d\n", name, chan); 796 return -EINVAL; 797 } 798 799 channel->channel = chan; 800 801 /* 802 * We are tied to PMIC's ADC controller, which always use single 803 * argument for channel number. So don't bother parsing 804 * #io-channel-cells, just enforce cell_count = 1. 805 */ 806 ret = of_parse_phandle_with_fixed_args(node, "io-channels", 1, 0, &args); 807 if (ret < 0) { 808 dev_err(dev, "%s: error parsing ADC channel number %d: %d\n", name, chan, ret); 809 return ret; 810 } 811 of_node_put(args.np); 812 813 if (args.args_count != 1) { 814 dev_err(dev, "%s: invalid args count for ADC channel %d\n", name, chan); 815 return -EINVAL; 816 } 817 818 adc_channel = args.args[0]; 819 if (adc_tm->data->gen == ADC_TM5_GEN2) 820 adc_channel &= 0xff; 821 822 if (adc_channel >= ADC5_MAX_CHANNEL) { 823 dev_err(dev, "%s: invalid ADC channel number %d\n", name, chan); 824 return -EINVAL; 825 } 826 channel->adc_channel = args.args[0]; 827 828 channel->iio = devm_of_iio_channel_get_by_name(adc_tm->dev, node, NULL); 829 if (IS_ERR(channel->iio)) { 830 ret = PTR_ERR(channel->iio); 831 if (ret != -EPROBE_DEFER) 832 dev_err(dev, "%s: error getting channel: %d\n", name, ret); 833 return ret; 834 } 835 836 ret = of_property_read_u32_array(node, "qcom,pre-scaling", varr, 2); 837 if (!ret) { 838 ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]); 839 if (ret < 0) { 840 dev_err(dev, "%s: invalid pre-scaling <%d %d>\n", 841 name, varr[0], varr[1]); 842 return ret; 843 } 844 channel->prescale = ret; 845 } else { 846 /* 1:1 prescale is index 0 */ 847 channel->prescale = 0; 848 } 849 850 ret = of_property_read_u32(node, "qcom,hw-settle-time-us", &value); 851 if (!ret) { 852 ret = qcom_adc5_hw_settle_time_from_dt(value, adc_tm->data->hw_settle); 853 if (ret < 0) { 854 dev_err(dev, "%s invalid hw-settle-time-us %d us\n", 855 name, value); 856 return ret; 857 } 858 channel->hw_settle_time = ret; 859 } else { 860 channel->hw_settle_time = VADC_DEF_HW_SETTLE_TIME; 861 } 862 863 if (of_property_read_bool(node, "qcom,ratiometric")) 864 channel->cal_method = ADC_TM5_RATIOMETRIC_CAL; 865 else 866 channel->cal_method = ADC_TM5_ABSOLUTE_CAL; 867 868 if (adc_tm->data->gen == ADC_TM5_GEN2) { 869 ret = of_property_read_u32(node, "qcom,decimation", &value); 870 if (!ret) { 871 ret = qcom_adc5_decimation_from_dt(value, adc_tm->data->decimation); 872 if (ret < 0) { 873 dev_err(dev, "invalid decimation %d\n", value); 874 return ret; 875 } 876 channel->decimation = ret; 877 } else { 878 channel->decimation = ADC5_DECIMATION_DEFAULT; 879 } 880 881 ret = of_property_read_u32(node, "qcom,avg-samples", &value); 882 if (!ret) { 883 ret = qcom_adc5_avg_samples_from_dt(value); 884 if (ret < 0) { 885 dev_err(dev, "invalid avg-samples %d\n", value); 886 return ret; 887 } 888 channel->avg_samples = ret; 889 } else { 890 channel->avg_samples = VADC_DEF_AVG_SAMPLES; 891 } 892 } 893 894 return 0; 895 } 896 897 static const struct adc_tm5_data adc_tm5_data_pmic = { 898 .full_scale_code_volt = 0x70e4, 899 .decimation = (unsigned int []) { 250, 420, 840 }, 900 .hw_settle = (unsigned int []) { 15, 100, 200, 300, 400, 500, 600, 700, 901 1000, 2000, 4000, 8000, 16000, 32000, 902 64000, 128000 }, 903 .disable_channel = adc_tm5_disable_channel, 904 .configure = adc_tm5_configure, 905 .isr = adc_tm5_isr, 906 .init = adc_tm5_init, 907 .irq_name = "pm-adc-tm5", 908 .gen = ADC_TM5, 909 }; 910 911 static const struct adc_tm5_data adc_tm_hc_data_pmic = { 912 .full_scale_code_volt = 0x70e4, 913 .decimation = (unsigned int []) { 256, 512, 1024 }, 914 .hw_settle = (unsigned int []) { 0, 100, 200, 300, 400, 500, 600, 700, 915 1000, 2000, 4000, 6000, 8000, 10000 }, 916 .disable_channel = adc_tm5_disable_channel, 917 .configure = adc_tm5_configure, 918 .isr = adc_tm5_isr, 919 .init = adc_tm_hc_init, 920 .irq_name = "pm-adc-tm5", 921 .gen = ADC_TM_HC, 922 }; 923 924 static const struct adc_tm5_data adc_tm5_gen2_data_pmic = { 925 .full_scale_code_volt = 0x70e4, 926 .decimation = (unsigned int []) { 85, 340, 1360 }, 927 .hw_settle = (unsigned int []) { 15, 100, 200, 300, 400, 500, 600, 700, 928 1000, 2000, 4000, 8000, 16000, 32000, 929 64000, 128000 }, 930 .disable_channel = adc_tm5_gen2_disable_channel, 931 .configure = adc_tm5_gen2_configure, 932 .isr = adc_tm5_gen2_isr, 933 .init = adc_tm5_gen2_init, 934 .irq_name = "pm-adc-tm5-gen2", 935 .gen = ADC_TM5_GEN2, 936 }; 937 938 static int adc_tm5_get_dt_data(struct adc_tm5_chip *adc_tm, struct device_node *node) 939 { 940 struct adc_tm5_channel *channels; 941 struct device_node *child; 942 u32 value; 943 int ret; 944 struct device *dev = adc_tm->dev; 945 946 adc_tm->nchannels = of_get_available_child_count(node); 947 if (!adc_tm->nchannels) 948 return -EINVAL; 949 950 adc_tm->channels = devm_kcalloc(dev, adc_tm->nchannels, 951 sizeof(*adc_tm->channels), GFP_KERNEL); 952 if (!adc_tm->channels) 953 return -ENOMEM; 954 955 channels = adc_tm->channels; 956 957 adc_tm->data = of_device_get_match_data(dev); 958 if (!adc_tm->data) 959 adc_tm->data = &adc_tm5_data_pmic; 960 961 ret = of_property_read_u32(node, "qcom,decimation", &value); 962 if (!ret) { 963 ret = qcom_adc5_decimation_from_dt(value, adc_tm->data->decimation); 964 if (ret < 0) { 965 dev_err(dev, "invalid decimation %d\n", value); 966 return ret; 967 } 968 adc_tm->decimation = ret; 969 } else { 970 adc_tm->decimation = ADC5_DECIMATION_DEFAULT; 971 } 972 973 ret = of_property_read_u32(node, "qcom,avg-samples", &value); 974 if (!ret) { 975 ret = qcom_adc5_avg_samples_from_dt(value); 976 if (ret < 0) { 977 dev_err(dev, "invalid avg-samples %d\n", value); 978 return ret; 979 } 980 adc_tm->avg_samples = ret; 981 } else { 982 adc_tm->avg_samples = VADC_DEF_AVG_SAMPLES; 983 } 984 985 for_each_available_child_of_node(node, child) { 986 ret = adc_tm5_get_dt_channel_data(adc_tm, channels, child); 987 if (ret) { 988 of_node_put(child); 989 return ret; 990 } 991 992 channels++; 993 } 994 995 return 0; 996 } 997 998 static int adc_tm5_probe(struct platform_device *pdev) 999 { 1000 struct device_node *node = pdev->dev.of_node; 1001 struct device *dev = &pdev->dev; 1002 struct adc_tm5_chip *adc_tm; 1003 struct regmap *regmap; 1004 int ret, irq; 1005 u32 reg; 1006 1007 regmap = dev_get_regmap(dev->parent, NULL); 1008 if (!regmap) 1009 return -ENODEV; 1010 1011 ret = of_property_read_u32(node, "reg", ®); 1012 if (ret) 1013 return ret; 1014 1015 adc_tm = devm_kzalloc(&pdev->dev, sizeof(*adc_tm), GFP_KERNEL); 1016 if (!adc_tm) 1017 return -ENOMEM; 1018 1019 adc_tm->regmap = regmap; 1020 adc_tm->dev = dev; 1021 adc_tm->base = reg; 1022 1023 irq = platform_get_irq(pdev, 0); 1024 if (irq < 0) { 1025 dev_err(dev, "get_irq failed: %d\n", irq); 1026 return irq; 1027 } 1028 1029 ret = adc_tm5_get_dt_data(adc_tm, node); 1030 if (ret) { 1031 dev_err(dev, "get dt data failed: %d\n", ret); 1032 return ret; 1033 } 1034 1035 ret = adc_tm->data->init(adc_tm); 1036 if (ret) { 1037 dev_err(dev, "adc-tm init failed\n"); 1038 return ret; 1039 } 1040 1041 ret = adc_tm5_register_tzd(adc_tm); 1042 if (ret) { 1043 dev_err(dev, "tzd register failed\n"); 1044 return ret; 1045 } 1046 1047 return devm_request_threaded_irq(dev, irq, NULL, adc_tm->data->isr, 1048 IRQF_ONESHOT, adc_tm->data->irq_name, adc_tm); 1049 } 1050 1051 static const struct of_device_id adc_tm5_match_table[] = { 1052 { 1053 .compatible = "qcom,spmi-adc-tm5", 1054 .data = &adc_tm5_data_pmic, 1055 }, 1056 { 1057 .compatible = "qcom,spmi-adc-tm-hc", 1058 .data = &adc_tm_hc_data_pmic, 1059 }, 1060 { 1061 .compatible = "qcom,spmi-adc-tm5-gen2", 1062 .data = &adc_tm5_gen2_data_pmic, 1063 }, 1064 { } 1065 }; 1066 MODULE_DEVICE_TABLE(of, adc_tm5_match_table); 1067 1068 static struct platform_driver adc_tm5_driver = { 1069 .driver = { 1070 .name = "qcom-spmi-adc-tm5", 1071 .of_match_table = adc_tm5_match_table, 1072 }, 1073 .probe = adc_tm5_probe, 1074 }; 1075 module_platform_driver(adc_tm5_driver); 1076 1077 MODULE_DESCRIPTION("SPMI PMIC Thermal Monitor ADC driver"); 1078 MODULE_LICENSE("GPL v2"); 1079