1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Tegra30 SoC Thermal Sensor driver
4  *
5  * Based on downstream HWMON driver from NVIDIA.
6  * Copyright (C) 2011 NVIDIA Corporation
7  *
8  * Author: Dmitry Osipenko <digetx@gmail.com>
9  * Copyright (C) 2021 GRATE-DRIVER project
10  */
11 
12 #include <linux/bitfield.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/errno.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/iopoll.h>
19 #include <linux/math.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm.h>
24 #include <linux/reset.h>
25 #include <linux/slab.h>
26 #include <linux/thermal.h>
27 #include <linux/types.h>
28 
29 #include <soc/tegra/fuse.h>
30 
31 #include "../thermal_hwmon.h"
32 
33 #define TSENSOR_SENSOR0_CONFIG0				0x0
34 #define TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP		BIT(0)
35 #define TSENSOR_SENSOR0_CONFIG0_HW_FREQ_DIV_EN		BIT(1)
36 #define TSENSOR_SENSOR0_CONFIG0_THERMAL_RST_EN		BIT(2)
37 #define TSENSOR_SENSOR0_CONFIG0_DVFS_EN			BIT(3)
38 #define TSENSOR_SENSOR0_CONFIG0_INTR_OVERFLOW_EN	BIT(4)
39 #define TSENSOR_SENSOR0_CONFIG0_INTR_HW_FREQ_DIV_EN	BIT(5)
40 #define TSENSOR_SENSOR0_CONFIG0_INTR_THERMAL_RST_EN	BIT(6)
41 #define TSENSOR_SENSOR0_CONFIG0_M			GENMASK(23,  8)
42 #define TSENSOR_SENSOR0_CONFIG0_N			GENMASK(31, 24)
43 
44 #define TSENSOR_SENSOR0_CONFIG1				0x8
45 #define TSENSOR_SENSOR0_CONFIG1_TH1			GENMASK(15,  0)
46 #define TSENSOR_SENSOR0_CONFIG1_TH2			GENMASK(31, 16)
47 
48 #define TSENSOR_SENSOR0_CONFIG2				0xc
49 #define TSENSOR_SENSOR0_CONFIG2_TH3			GENMASK(15,  0)
50 
51 #define TSENSOR_SENSOR0_STATUS0				0x18
52 #define TSENSOR_SENSOR0_STATUS0_STATE			GENMASK(2, 0)
53 #define TSENSOR_SENSOR0_STATUS0_INTR			BIT(8)
54 #define TSENSOR_SENSOR0_STATUS0_CURRENT_VALID		BIT(9)
55 
56 #define TSENSOR_SENSOR0_TS_STATUS1			0x1c
57 #define TSENSOR_SENSOR0_TS_STATUS1_CURRENT_COUNT	GENMASK(31, 16)
58 
59 #define TEGRA30_FUSE_TEST_PROG_VER			0x28
60 
61 #define TEGRA30_FUSE_TSENSOR_CALIB			0x98
62 #define TEGRA30_FUSE_TSENSOR_CALIB_LOW			GENMASK(15,  0)
63 #define TEGRA30_FUSE_TSENSOR_CALIB_HIGH			GENMASK(31, 16)
64 
65 #define TEGRA30_FUSE_SPARE_BIT				0x144
66 
67 struct tegra_tsensor;
68 
69 struct tegra_tsensor_calibration_data {
70 	int a, b, m, n, p, r;
71 };
72 
73 struct tegra_tsensor_channel {
74 	void __iomem *regs;
75 	unsigned int id;
76 	struct tegra_tsensor *ts;
77 	struct thermal_zone_device *tzd;
78 };
79 
80 struct tegra_tsensor {
81 	void __iomem *regs;
82 	bool swap_channels;
83 	struct clk *clk;
84 	struct device *dev;
85 	struct reset_control *rst;
86 	struct tegra_tsensor_channel ch[2];
87 	struct tegra_tsensor_calibration_data calib;
88 };
89 
90 static int tegra_tsensor_hw_enable(const struct tegra_tsensor *ts)
91 {
92 	u32 val;
93 	int err;
94 
95 	err = reset_control_assert(ts->rst);
96 	if (err) {
97 		dev_err(ts->dev, "failed to assert hardware reset: %d\n", err);
98 		return err;
99 	}
100 
101 	err = clk_prepare_enable(ts->clk);
102 	if (err) {
103 		dev_err(ts->dev, "failed to enable clock: %d\n", err);
104 		return err;
105 	}
106 
107 	fsleep(1000);
108 
109 	err = reset_control_deassert(ts->rst);
110 	if (err) {
111 		dev_err(ts->dev, "failed to deassert hardware reset: %d\n", err);
112 		goto disable_clk;
113 	}
114 
115 	/*
116 	 * Sensors are enabled after reset by default, but not gauging
117 	 * until clock counter is programmed.
118 	 *
119 	 * M: number of reference clock pulses after which every
120 	 *    temperature / voltage measurement is made
121 	 *
122 	 * N: number of reference clock counts for which the counter runs
123 	 */
124 	val  = FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_M, 12500);
125 	val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_N, 255);
126 
127 	/* apply the same configuration to both channels */
128 	writel_relaxed(val, ts->regs + 0x40 + TSENSOR_SENSOR0_CONFIG0);
129 	writel_relaxed(val, ts->regs + 0x80 + TSENSOR_SENSOR0_CONFIG0);
130 
131 	return 0;
132 
133 disable_clk:
134 	clk_disable_unprepare(ts->clk);
135 
136 	return err;
137 }
138 
139 static int tegra_tsensor_hw_disable(const struct tegra_tsensor *ts)
140 {
141 	int err;
142 
143 	err = reset_control_assert(ts->rst);
144 	if (err) {
145 		dev_err(ts->dev, "failed to assert hardware reset: %d\n", err);
146 		return err;
147 	}
148 
149 	clk_disable_unprepare(ts->clk);
150 
151 	return 0;
152 }
153 
154 static void devm_tegra_tsensor_hw_disable(void *data)
155 {
156 	const struct tegra_tsensor *ts = data;
157 
158 	tegra_tsensor_hw_disable(ts);
159 }
160 
161 static int tegra_tsensor_get_temp(struct thermal_zone_device *tz, int *temp)
162 {
163 	const struct tegra_tsensor_channel *tsc = thermal_zone_device_priv(tz);
164 	const struct tegra_tsensor *ts = tsc->ts;
165 	int err, c1, c2, c3, c4, counter;
166 	u32 val;
167 
168 	/*
169 	 * Counter will be invalid if hardware is misprogrammed or not enough
170 	 * time passed since the time when sensor was enabled.
171 	 */
172 	err = readl_relaxed_poll_timeout(tsc->regs + TSENSOR_SENSOR0_STATUS0, val,
173 					 val & TSENSOR_SENSOR0_STATUS0_CURRENT_VALID,
174 					 21 * USEC_PER_MSEC,
175 					 21 * USEC_PER_MSEC * 50);
176 	if (err) {
177 		dev_err_once(ts->dev, "ch%u: counter invalid\n", tsc->id);
178 		return err;
179 	}
180 
181 	val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_TS_STATUS1);
182 	counter = FIELD_GET(TSENSOR_SENSOR0_TS_STATUS1_CURRENT_COUNT, val);
183 
184 	/*
185 	 * This shouldn't happen with a valid counter status, nevertheless
186 	 * lets verify the value since it's in a separate (from status)
187 	 * register.
188 	 */
189 	if (counter == 0xffff) {
190 		dev_err_once(ts->dev, "ch%u: counter overflow\n", tsc->id);
191 		return -EINVAL;
192 	}
193 
194 	/*
195 	 * temperature = a * counter + b
196 	 * temperature = m * (temperature ^ 2) + n * temperature + p
197 	 */
198 	c1 = DIV_ROUND_CLOSEST(ts->calib.a * counter + ts->calib.b, 1000000);
199 	c1 = c1 ?: 1;
200 	c2 = DIV_ROUND_CLOSEST(ts->calib.p, c1);
201 	c3 = c1 * ts->calib.m;
202 	c4 = ts->calib.n;
203 
204 	*temp = DIV_ROUND_CLOSEST(c1 * (c2 + c3 + c4), 1000);
205 
206 	return 0;
207 }
208 
209 static int tegra_tsensor_temp_to_counter(const struct tegra_tsensor *ts, int temp)
210 {
211 	int c1, c2;
212 
213 	c1 = DIV_ROUND_CLOSEST(ts->calib.p - temp * 1000, ts->calib.m);
214 	c2 = -ts->calib.r - int_sqrt(ts->calib.r * ts->calib.r - c1);
215 
216 	return DIV_ROUND_CLOSEST(c2 * 1000000 - ts->calib.b, ts->calib.a);
217 }
218 
219 static int tegra_tsensor_set_trips(struct thermal_zone_device *tz, int low, int high)
220 {
221 	const struct tegra_tsensor_channel *tsc = thermal_zone_device_priv(tz);
222 	const struct tegra_tsensor *ts = tsc->ts;
223 	u32 val;
224 
225 	/*
226 	 * TSENSOR doesn't trigger interrupt on the "low" temperature breach,
227 	 * hence bail out if high temperature is unspecified.
228 	 */
229 	if (high == INT_MAX)
230 		return 0;
231 
232 	val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG1);
233 	val &= ~TSENSOR_SENSOR0_CONFIG1_TH1;
234 
235 	high = tegra_tsensor_temp_to_counter(ts, high);
236 	val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG1_TH1, high);
237 	writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG1);
238 
239 	return 0;
240 }
241 
242 static const struct thermal_zone_device_ops ops = {
243 	.get_temp = tegra_tsensor_get_temp,
244 	.set_trips = tegra_tsensor_set_trips,
245 };
246 
247 static bool
248 tegra_tsensor_handle_channel_interrupt(const struct tegra_tsensor *ts,
249 				       unsigned int id)
250 {
251 	const struct tegra_tsensor_channel *tsc = &ts->ch[id];
252 	u32 val;
253 
254 	val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_STATUS0);
255 	writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_STATUS0);
256 
257 	if (FIELD_GET(TSENSOR_SENSOR0_STATUS0_STATE, val) == 5)
258 		dev_err_ratelimited(ts->dev, "ch%u: counter overflowed\n", id);
259 
260 	if (!FIELD_GET(TSENSOR_SENSOR0_STATUS0_INTR, val))
261 		return false;
262 
263 	thermal_zone_device_update(tsc->tzd, THERMAL_EVENT_UNSPECIFIED);
264 
265 	return true;
266 }
267 
268 static irqreturn_t tegra_tsensor_isr(int irq, void *data)
269 {
270 	const struct tegra_tsensor *ts = data;
271 	bool handled = false;
272 	unsigned int i;
273 
274 	for (i = 0; i < ARRAY_SIZE(ts->ch); i++)
275 		handled |= tegra_tsensor_handle_channel_interrupt(ts, i);
276 
277 	return handled ? IRQ_HANDLED : IRQ_NONE;
278 }
279 
280 static int tegra_tsensor_disable_hw_channel(const struct tegra_tsensor *ts,
281 					    unsigned int id)
282 {
283 	const struct tegra_tsensor_channel *tsc = &ts->ch[id];
284 	struct thermal_zone_device *tzd = tsc->tzd;
285 	u32 val;
286 	int err;
287 
288 	if (!tzd)
289 		goto stop_channel;
290 
291 	err = thermal_zone_device_disable(tzd);
292 	if (err) {
293 		dev_err(ts->dev, "ch%u: failed to disable zone: %d\n", id, err);
294 		return err;
295 	}
296 
297 stop_channel:
298 	/* stop channel gracefully */
299 	val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0);
300 	val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP, 1);
301 	writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0);
302 
303 	return 0;
304 }
305 
306 static void tegra_tsensor_get_hw_channel_trips(struct thermal_zone_device *tzd,
307 					       int *hot_trip, int *crit_trip)
308 {
309 	unsigned int i;
310 
311 	/*
312 	 * 90C is the maximal critical temperature of all Tegra30 SoC variants,
313 	 * use it for the default trip if unspecified in a device-tree.
314 	 */
315 	*hot_trip  = 85000;
316 	*crit_trip = 90000;
317 
318 	for (i = 0; i < thermal_zone_get_num_trips(tzd); i++) {
319 
320 		struct thermal_trip trip;
321 
322 		thermal_zone_get_trip(tzd, i, &trip);
323 
324 		if (trip.type == THERMAL_TRIP_HOT)
325 			*hot_trip = trip.temperature;
326 
327 		if (trip.type == THERMAL_TRIP_CRITICAL)
328 			*crit_trip = trip.temperature;
329 	}
330 
331 	/* clamp hardware trips to the calibration limits */
332 	*hot_trip = clamp(*hot_trip, 25000, 90000);
333 
334 	/*
335 	 * Kernel will perform a normal system shut down if it will
336 	 * see that critical temperature is breached, hence set the
337 	 * hardware limit by 5C higher in order to allow system to
338 	 * shut down gracefully before sending signal to the Power
339 	 * Management controller.
340 	 */
341 	*crit_trip = clamp(*crit_trip + 5000, 25000, 90000);
342 }
343 
344 static int tegra_tsensor_enable_hw_channel(const struct tegra_tsensor *ts,
345 					   unsigned int id)
346 {
347 	const struct tegra_tsensor_channel *tsc = &ts->ch[id];
348 	struct thermal_zone_device *tzd = tsc->tzd;
349 	int err, hot_trip = 0, crit_trip = 0;
350 	u32 val;
351 
352 	if (!tzd) {
353 		val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0);
354 		val &= ~TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP;
355 		writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0);
356 
357 		return 0;
358 	}
359 
360 	tegra_tsensor_get_hw_channel_trips(tzd, &hot_trip, &crit_trip);
361 
362 	dev_info_once(ts->dev, "ch%u: PMC emergency shutdown trip set to %dC\n",
363 		      id, DIV_ROUND_CLOSEST(crit_trip, 1000));
364 
365 	hot_trip  = tegra_tsensor_temp_to_counter(ts, hot_trip);
366 	crit_trip = tegra_tsensor_temp_to_counter(ts, crit_trip);
367 
368 	/* program LEVEL2 counter threshold */
369 	val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG1);
370 	val &= ~TSENSOR_SENSOR0_CONFIG1_TH2;
371 	val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG1_TH2, hot_trip);
372 	writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG1);
373 
374 	/* program LEVEL3 counter threshold */
375 	val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG2);
376 	val &= ~TSENSOR_SENSOR0_CONFIG2_TH3;
377 	val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG2_TH3, crit_trip);
378 	writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG2);
379 
380 	/*
381 	 * Enable sensor, emergency shutdown, interrupts for level 1/2/3
382 	 * breaches and counter overflow condition.
383 	 *
384 	 * Disable DIV2 throttle for now since we need to figure out how
385 	 * to integrate it properly with the thermal framework.
386 	 *
387 	 * Thermal levels supported by hardware:
388 	 *
389 	 *     Level 0 = cold
390 	 *     Level 1 = passive cooling (cpufreq DVFS)
391 	 *     Level 2 = passive cooling assisted by hardware (DIV2)
392 	 *     Level 3 = emergency shutdown assisted by hardware (PMC)
393 	 */
394 	val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0);
395 	val &= ~TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP;
396 	val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_DVFS_EN, 1);
397 	val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_HW_FREQ_DIV_EN, 0);
398 	val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_THERMAL_RST_EN, 1);
399 	val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_OVERFLOW_EN, 1);
400 	val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_HW_FREQ_DIV_EN, 1);
401 	val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_THERMAL_RST_EN, 1);
402 	writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0);
403 
404 	err = thermal_zone_device_enable(tzd);
405 	if (err) {
406 		dev_err(ts->dev, "ch%u: failed to enable zone: %d\n", id, err);
407 		return err;
408 	}
409 
410 	return 0;
411 }
412 
413 static bool tegra_tsensor_fuse_read_spare(unsigned int spare)
414 {
415 	u32 val = 0;
416 
417 	tegra_fuse_readl(TEGRA30_FUSE_SPARE_BIT + spare * 4, &val);
418 
419 	return !!val;
420 }
421 
422 static int tegra_tsensor_nvmem_setup(struct tegra_tsensor *ts)
423 {
424 	u32 i, ate_ver = 0, cal = 0, t1_25C = 0, t2_90C = 0;
425 	int err, c1_25C, c2_90C;
426 
427 	err = tegra_fuse_readl(TEGRA30_FUSE_TEST_PROG_VER, &ate_ver);
428 	if (err) {
429 		dev_err_probe(ts->dev, err, "failed to get ATE version\n");
430 		return err;
431 	}
432 
433 	if (ate_ver < 8) {
434 		dev_info(ts->dev, "unsupported ATE version: %u\n", ate_ver);
435 		return -ENODEV;
436 	}
437 
438 	/*
439 	 * We have two TSENSOR channels in a two different spots on SoC.
440 	 * Second channel provides more accurate data on older SoC versions,
441 	 * use it as a primary channel.
442 	 */
443 	if (ate_ver <= 21) {
444 		dev_info_once(ts->dev,
445 			      "older ATE version detected, channels remapped\n");
446 		ts->swap_channels = true;
447 	}
448 
449 	err = tegra_fuse_readl(TEGRA30_FUSE_TSENSOR_CALIB, &cal);
450 	if (err) {
451 		dev_err(ts->dev, "failed to get calibration data: %d\n", err);
452 		return err;
453 	}
454 
455 	/* get calibrated counter values for 25C/90C thresholds */
456 	c1_25C = FIELD_GET(TEGRA30_FUSE_TSENSOR_CALIB_LOW, cal);
457 	c2_90C = FIELD_GET(TEGRA30_FUSE_TSENSOR_CALIB_HIGH, cal);
458 
459 	/* and calibrated temperatures corresponding to the counter values */
460 	for (i = 0; i < 7; i++) {
461 		t1_25C |= tegra_tsensor_fuse_read_spare(14 + i) << i;
462 		t1_25C |= tegra_tsensor_fuse_read_spare(21 + i) << i;
463 
464 		t2_90C |= tegra_tsensor_fuse_read_spare(0 + i) << i;
465 		t2_90C |= tegra_tsensor_fuse_read_spare(7 + i) << i;
466 	}
467 
468 	if (c2_90C - c1_25C <= t2_90C - t1_25C) {
469 		dev_err(ts->dev, "invalid calibration data: %d %d %u %u\n",
470 			c2_90C, c1_25C, t2_90C, t1_25C);
471 		return -EINVAL;
472 	}
473 
474 	/* all calibration coefficients are premultiplied by 1000000 */
475 
476 	ts->calib.a = DIV_ROUND_CLOSEST((t2_90C - t1_25C) * 1000000,
477 					(c2_90C - c1_25C));
478 
479 	ts->calib.b = t1_25C * 1000000 - ts->calib.a * c1_25C;
480 
481 	if (tegra_sku_info.revision == TEGRA_REVISION_A01) {
482 		ts->calib.m =     -2775;
483 		ts->calib.n =   1338811;
484 		ts->calib.p =  -7300000;
485 	} else {
486 		ts->calib.m =     -3512;
487 		ts->calib.n =   1528943;
488 		ts->calib.p = -11100000;
489 	}
490 
491 	/* except the coefficient of a reduced quadratic equation */
492 	ts->calib.r = DIV_ROUND_CLOSEST(ts->calib.n, ts->calib.m * 2);
493 
494 	dev_info_once(ts->dev,
495 		      "calibration: %d %d %u %u ATE ver: %u SoC rev: %u\n",
496 		      c2_90C, c1_25C, t2_90C, t1_25C, ate_ver,
497 		      tegra_sku_info.revision);
498 
499 	return 0;
500 }
501 
502 static int tegra_tsensor_register_channel(struct tegra_tsensor *ts,
503 					  unsigned int id)
504 {
505 	struct tegra_tsensor_channel *tsc = &ts->ch[id];
506 	unsigned int hw_id = ts->swap_channels ? !id : id;
507 
508 	tsc->ts = ts;
509 	tsc->id = id;
510 	tsc->regs = ts->regs + 0x40 * (hw_id + 1);
511 
512 	tsc->tzd = devm_thermal_of_zone_register(ts->dev, id, tsc, &ops);
513 	if (IS_ERR(tsc->tzd)) {
514 		if (PTR_ERR(tsc->tzd) != -ENODEV)
515 			return dev_err_probe(ts->dev, PTR_ERR(tsc->tzd),
516 					     "failed to register thermal zone\n");
517 
518 		/*
519 		 * It's okay if sensor isn't assigned to any thermal zone
520 		 * in a device-tree.
521 		 */
522 		tsc->tzd = NULL;
523 		return 0;
524 	}
525 
526 	devm_thermal_add_hwmon_sysfs(ts->dev, tsc->tzd);
527 
528 	return 0;
529 }
530 
531 static int tegra_tsensor_probe(struct platform_device *pdev)
532 {
533 	struct tegra_tsensor *ts;
534 	unsigned int i;
535 	int err, irq;
536 
537 	ts = devm_kzalloc(&pdev->dev, sizeof(*ts), GFP_KERNEL);
538 	if (!ts)
539 		return -ENOMEM;
540 
541 	irq = platform_get_irq(pdev, 0);
542 	if (irq < 0)
543 		return irq;
544 
545 	ts->dev = &pdev->dev;
546 	platform_set_drvdata(pdev, ts);
547 
548 	ts->regs = devm_platform_ioremap_resource(pdev, 0);
549 	if (IS_ERR(ts->regs))
550 		return PTR_ERR(ts->regs);
551 
552 	ts->clk = devm_clk_get(&pdev->dev, NULL);
553 	if (IS_ERR(ts->clk))
554 		return dev_err_probe(&pdev->dev, PTR_ERR(ts->clk),
555 				     "failed to get clock\n");
556 
557 	ts->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
558 	if (IS_ERR(ts->rst))
559 		return dev_err_probe(&pdev->dev, PTR_ERR(ts->rst),
560 				     "failed to get reset control\n");
561 
562 	err = tegra_tsensor_nvmem_setup(ts);
563 	if (err)
564 		return err;
565 
566 	err = tegra_tsensor_hw_enable(ts);
567 	if (err)
568 		return err;
569 
570 	err = devm_add_action_or_reset(&pdev->dev,
571 				       devm_tegra_tsensor_hw_disable,
572 				       ts);
573 	if (err)
574 		return err;
575 
576 	for (i = 0; i < ARRAY_SIZE(ts->ch); i++) {
577 		err = tegra_tsensor_register_channel(ts, i);
578 		if (err)
579 			return err;
580 	}
581 
582 	/*
583 	 * Enable the channels before setting the interrupt so
584 	 * set_trips() can not be called while we are setting up the
585 	 * register TSENSOR_SENSOR0_CONFIG1. With this we close a
586 	 * potential race window where we are setting up the TH2 and
587 	 * the temperature hits TH1 resulting to an update of the
588 	 * TSENSOR_SENSOR0_CONFIG1 register in the ISR.
589 	 */
590 	for (i = 0; i < ARRAY_SIZE(ts->ch); i++) {
591 		err = tegra_tsensor_enable_hw_channel(ts, i);
592 		if (err)
593 			return err;
594 	}
595 
596 	err = devm_request_threaded_irq(&pdev->dev, irq, NULL,
597 					tegra_tsensor_isr, IRQF_ONESHOT,
598 					"tegra_tsensor", ts);
599 	if (err)
600 		return dev_err_probe(&pdev->dev, err,
601 				     "failed to request interrupt\n");
602 
603 	return 0;
604 }
605 
606 static int __maybe_unused tegra_tsensor_suspend(struct device *dev)
607 {
608 	struct tegra_tsensor *ts = dev_get_drvdata(dev);
609 	unsigned int i;
610 	int err;
611 
612 	for (i = 0; i < ARRAY_SIZE(ts->ch); i++) {
613 		err = tegra_tsensor_disable_hw_channel(ts, i);
614 		if (err)
615 			goto enable_channel;
616 	}
617 
618 	err = tegra_tsensor_hw_disable(ts);
619 	if (err)
620 		goto enable_channel;
621 
622 	return 0;
623 
624 enable_channel:
625 	while (i--)
626 		tegra_tsensor_enable_hw_channel(ts, i);
627 
628 	return err;
629 }
630 
631 static int __maybe_unused tegra_tsensor_resume(struct device *dev)
632 {
633 	struct tegra_tsensor *ts = dev_get_drvdata(dev);
634 	unsigned int i;
635 	int err;
636 
637 	err = tegra_tsensor_hw_enable(ts);
638 	if (err)
639 		return err;
640 
641 	for (i = 0; i < ARRAY_SIZE(ts->ch); i++) {
642 		err = tegra_tsensor_enable_hw_channel(ts, i);
643 		if (err)
644 			return err;
645 	}
646 
647 	return 0;
648 }
649 
650 static const struct dev_pm_ops tegra_tsensor_pm_ops = {
651 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_tsensor_suspend,
652 				      tegra_tsensor_resume)
653 };
654 
655 static const struct of_device_id tegra_tsensor_of_match[] = {
656 	{ .compatible = "nvidia,tegra30-tsensor", },
657 	{},
658 };
659 MODULE_DEVICE_TABLE(of, tegra_tsensor_of_match);
660 
661 static struct platform_driver tegra_tsensor_driver = {
662 	.probe = tegra_tsensor_probe,
663 	.driver = {
664 		.name = "tegra30-tsensor",
665 		.of_match_table = tegra_tsensor_of_match,
666 		.pm = &tegra_tsensor_pm_ops,
667 	},
668 };
669 module_platform_driver(tegra_tsensor_driver);
670 
671 MODULE_DESCRIPTION("NVIDIA Tegra30 Thermal Sensor driver");
672 MODULE_AUTHOR("Dmitry Osipenko <digetx@gmail.com>");
673 MODULE_LICENSE("GPL");
674