1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Thunderbolt driver - eeprom access 4 * 5 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com> 6 * Copyright (C) 2018, Intel Corporation 7 */ 8 9 #include <linux/crc32.h> 10 #include <linux/property.h> 11 #include <linux/slab.h> 12 #include "tb.h" 13 14 /** 15 * tb_eeprom_ctl_write() - write control word 16 */ 17 static int tb_eeprom_ctl_write(struct tb_switch *sw, struct tb_eeprom_ctl *ctl) 18 { 19 return tb_sw_write(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1); 20 } 21 22 /** 23 * tb_eeprom_ctl_write() - read control word 24 */ 25 static int tb_eeprom_ctl_read(struct tb_switch *sw, struct tb_eeprom_ctl *ctl) 26 { 27 return tb_sw_read(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1); 28 } 29 30 enum tb_eeprom_transfer { 31 TB_EEPROM_IN, 32 TB_EEPROM_OUT, 33 }; 34 35 /** 36 * tb_eeprom_active - enable rom access 37 * 38 * WARNING: Always disable access after usage. Otherwise the controller will 39 * fail to reprobe. 40 */ 41 static int tb_eeprom_active(struct tb_switch *sw, bool enable) 42 { 43 struct tb_eeprom_ctl ctl; 44 int res = tb_eeprom_ctl_read(sw, &ctl); 45 if (res) 46 return res; 47 if (enable) { 48 ctl.access_high = 1; 49 res = tb_eeprom_ctl_write(sw, &ctl); 50 if (res) 51 return res; 52 ctl.access_low = 0; 53 return tb_eeprom_ctl_write(sw, &ctl); 54 } else { 55 ctl.access_low = 1; 56 res = tb_eeprom_ctl_write(sw, &ctl); 57 if (res) 58 return res; 59 ctl.access_high = 0; 60 return tb_eeprom_ctl_write(sw, &ctl); 61 } 62 } 63 64 /** 65 * tb_eeprom_transfer - transfer one bit 66 * 67 * If TB_EEPROM_IN is passed, then the bit can be retrieved from ctl->data_in. 68 * If TB_EEPROM_OUT is passed, then ctl->data_out will be written. 69 */ 70 static int tb_eeprom_transfer(struct tb_switch *sw, struct tb_eeprom_ctl *ctl, 71 enum tb_eeprom_transfer direction) 72 { 73 int res; 74 if (direction == TB_EEPROM_OUT) { 75 res = tb_eeprom_ctl_write(sw, ctl); 76 if (res) 77 return res; 78 } 79 ctl->clock = 1; 80 res = tb_eeprom_ctl_write(sw, ctl); 81 if (res) 82 return res; 83 if (direction == TB_EEPROM_IN) { 84 res = tb_eeprom_ctl_read(sw, ctl); 85 if (res) 86 return res; 87 } 88 ctl->clock = 0; 89 return tb_eeprom_ctl_write(sw, ctl); 90 } 91 92 /** 93 * tb_eeprom_out - write one byte to the bus 94 */ 95 static int tb_eeprom_out(struct tb_switch *sw, u8 val) 96 { 97 struct tb_eeprom_ctl ctl; 98 int i; 99 int res = tb_eeprom_ctl_read(sw, &ctl); 100 if (res) 101 return res; 102 for (i = 0; i < 8; i++) { 103 ctl.data_out = val & 0x80; 104 res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_OUT); 105 if (res) 106 return res; 107 val <<= 1; 108 } 109 return 0; 110 } 111 112 /** 113 * tb_eeprom_in - read one byte from the bus 114 */ 115 static int tb_eeprom_in(struct tb_switch *sw, u8 *val) 116 { 117 struct tb_eeprom_ctl ctl; 118 int i; 119 int res = tb_eeprom_ctl_read(sw, &ctl); 120 if (res) 121 return res; 122 *val = 0; 123 for (i = 0; i < 8; i++) { 124 *val <<= 1; 125 res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_IN); 126 if (res) 127 return res; 128 *val |= ctl.data_in; 129 } 130 return 0; 131 } 132 133 /** 134 * tb_eeprom_get_drom_offset - get drom offset within eeprom 135 */ 136 static int tb_eeprom_get_drom_offset(struct tb_switch *sw, u16 *offset) 137 { 138 struct tb_cap_plug_events cap; 139 int res; 140 141 if (!sw->cap_plug_events) { 142 tb_sw_warn(sw, "no TB_CAP_PLUG_EVENTS, cannot read eeprom\n"); 143 return -ENODEV; 144 } 145 res = tb_sw_read(sw, &cap, TB_CFG_SWITCH, sw->cap_plug_events, 146 sizeof(cap) / 4); 147 if (res) 148 return res; 149 150 if (!cap.eeprom_ctl.present || cap.eeprom_ctl.not_present) { 151 tb_sw_warn(sw, "no NVM\n"); 152 return -ENODEV; 153 } 154 155 if (cap.drom_offset > 0xffff) { 156 tb_sw_warn(sw, "drom offset is larger than 0xffff: %#x\n", 157 cap.drom_offset); 158 return -ENXIO; 159 } 160 *offset = cap.drom_offset; 161 return 0; 162 } 163 164 /** 165 * tb_eeprom_read_n - read count bytes from offset into val 166 */ 167 static int tb_eeprom_read_n(struct tb_switch *sw, u16 offset, u8 *val, 168 size_t count) 169 { 170 u16 drom_offset; 171 int i, res; 172 173 res = tb_eeprom_get_drom_offset(sw, &drom_offset); 174 if (res) 175 return res; 176 177 offset += drom_offset; 178 179 res = tb_eeprom_active(sw, true); 180 if (res) 181 return res; 182 res = tb_eeprom_out(sw, 3); 183 if (res) 184 return res; 185 res = tb_eeprom_out(sw, offset >> 8); 186 if (res) 187 return res; 188 res = tb_eeprom_out(sw, offset); 189 if (res) 190 return res; 191 for (i = 0; i < count; i++) { 192 res = tb_eeprom_in(sw, val + i); 193 if (res) 194 return res; 195 } 196 return tb_eeprom_active(sw, false); 197 } 198 199 static u8 tb_crc8(u8 *data, int len) 200 { 201 int i, j; 202 u8 val = 0xff; 203 for (i = 0; i < len; i++) { 204 val ^= data[i]; 205 for (j = 0; j < 8; j++) 206 val = (val << 1) ^ ((val & 0x80) ? 7 : 0); 207 } 208 return val; 209 } 210 211 static u32 tb_crc32(void *data, size_t len) 212 { 213 return ~__crc32c_le(~0, data, len); 214 } 215 216 #define TB_DROM_DATA_START 13 217 struct tb_drom_header { 218 /* BYTE 0 */ 219 u8 uid_crc8; /* checksum for uid */ 220 /* BYTES 1-8 */ 221 u64 uid; 222 /* BYTES 9-12 */ 223 u32 data_crc32; /* checksum for data_len bytes starting at byte 13 */ 224 /* BYTE 13 */ 225 u8 device_rom_revision; /* should be <= 1 */ 226 u16 data_len:10; 227 u8 __unknown1:6; 228 /* BYTES 16-21 */ 229 u16 vendor_id; 230 u16 model_id; 231 u8 model_rev; 232 u8 eeprom_rev; 233 } __packed; 234 235 enum tb_drom_entry_type { 236 /* force unsigned to prevent "one-bit signed bitfield" warning */ 237 TB_DROM_ENTRY_GENERIC = 0U, 238 TB_DROM_ENTRY_PORT, 239 }; 240 241 struct tb_drom_entry_header { 242 u8 len; 243 u8 index:6; 244 bool port_disabled:1; /* only valid if type is TB_DROM_ENTRY_PORT */ 245 enum tb_drom_entry_type type:1; 246 } __packed; 247 248 struct tb_drom_entry_generic { 249 struct tb_drom_entry_header header; 250 u8 data[0]; 251 } __packed; 252 253 struct tb_drom_entry_port { 254 /* BYTES 0-1 */ 255 struct tb_drom_entry_header header; 256 /* BYTE 2 */ 257 u8 dual_link_port_rid:4; 258 u8 link_nr:1; 259 u8 unknown1:2; 260 bool has_dual_link_port:1; 261 262 /* BYTE 3 */ 263 u8 dual_link_port_nr:6; 264 u8 unknown2:2; 265 266 /* BYTES 4 - 5 TODO decode */ 267 u8 micro2:4; 268 u8 micro1:4; 269 u8 micro3; 270 271 /* BYTES 6-7, TODO: verify (find hardware that has these set) */ 272 u8 peer_port_rid:4; 273 u8 unknown3:3; 274 bool has_peer_port:1; 275 u8 peer_port_nr:6; 276 u8 unknown4:2; 277 } __packed; 278 279 280 /** 281 * tb_drom_read_uid_only - read uid directly from drom 282 * 283 * Does not use the cached copy in sw->drom. Used during resume to check switch 284 * identity. 285 */ 286 int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid) 287 { 288 u8 data[9]; 289 u8 crc; 290 int res; 291 292 /* read uid */ 293 res = tb_eeprom_read_n(sw, 0, data, 9); 294 if (res) 295 return res; 296 297 crc = tb_crc8(data + 1, 8); 298 if (crc != data[0]) { 299 tb_sw_warn(sw, "uid crc8 mismatch (expected: %#x, got: %#x)\n", 300 data[0], crc); 301 return -EIO; 302 } 303 304 *uid = *(u64 *)(data+1); 305 return 0; 306 } 307 308 static int tb_drom_parse_entry_generic(struct tb_switch *sw, 309 struct tb_drom_entry_header *header) 310 { 311 const struct tb_drom_entry_generic *entry = 312 (const struct tb_drom_entry_generic *)header; 313 314 switch (header->index) { 315 case 1: 316 /* Length includes 2 bytes header so remove it before copy */ 317 sw->vendor_name = kstrndup(entry->data, 318 header->len - sizeof(*header), GFP_KERNEL); 319 if (!sw->vendor_name) 320 return -ENOMEM; 321 break; 322 323 case 2: 324 sw->device_name = kstrndup(entry->data, 325 header->len - sizeof(*header), GFP_KERNEL); 326 if (!sw->device_name) 327 return -ENOMEM; 328 break; 329 } 330 331 return 0; 332 } 333 334 static int tb_drom_parse_entry_port(struct tb_switch *sw, 335 struct tb_drom_entry_header *header) 336 { 337 struct tb_port *port; 338 int res; 339 enum tb_port_type type; 340 341 /* 342 * Some DROMs list more ports than the controller actually has 343 * so we skip those but allow the parser to continue. 344 */ 345 if (header->index > sw->config.max_port_number) { 346 dev_info_once(&sw->dev, "ignoring unnecessary extra entries in DROM\n"); 347 return 0; 348 } 349 350 port = &sw->ports[header->index]; 351 port->disabled = header->port_disabled; 352 if (port->disabled) 353 return 0; 354 355 res = tb_port_read(port, &type, TB_CFG_PORT, 2, 1); 356 if (res) 357 return res; 358 type &= 0xffffff; 359 360 if (type == TB_TYPE_PORT) { 361 struct tb_drom_entry_port *entry = (void *) header; 362 if (header->len != sizeof(*entry)) { 363 tb_sw_warn(sw, 364 "port entry has size %#x (expected %#zx)\n", 365 header->len, sizeof(struct tb_drom_entry_port)); 366 return -EIO; 367 } 368 port->link_nr = entry->link_nr; 369 if (entry->has_dual_link_port) 370 port->dual_link_port = 371 &port->sw->ports[entry->dual_link_port_nr]; 372 } 373 return 0; 374 } 375 376 /** 377 * tb_drom_parse_entries - parse the linked list of drom entries 378 * 379 * Drom must have been copied to sw->drom. 380 */ 381 static int tb_drom_parse_entries(struct tb_switch *sw) 382 { 383 struct tb_drom_header *header = (void *) sw->drom; 384 u16 pos = sizeof(*header); 385 u16 drom_size = header->data_len + TB_DROM_DATA_START; 386 int res; 387 388 while (pos < drom_size) { 389 struct tb_drom_entry_header *entry = (void *) (sw->drom + pos); 390 if (pos + 1 == drom_size || pos + entry->len > drom_size 391 || !entry->len) { 392 tb_sw_warn(sw, "drom buffer overrun, aborting\n"); 393 return -EIO; 394 } 395 396 switch (entry->type) { 397 case TB_DROM_ENTRY_GENERIC: 398 res = tb_drom_parse_entry_generic(sw, entry); 399 break; 400 case TB_DROM_ENTRY_PORT: 401 res = tb_drom_parse_entry_port(sw, entry); 402 break; 403 } 404 if (res) 405 return res; 406 407 pos += entry->len; 408 } 409 return 0; 410 } 411 412 /** 413 * tb_drom_copy_efi - copy drom supplied by EFI to sw->drom if present 414 */ 415 static int tb_drom_copy_efi(struct tb_switch *sw, u16 *size) 416 { 417 struct device *dev = &sw->tb->nhi->pdev->dev; 418 int len, res; 419 420 len = device_property_count_u8(dev, "ThunderboltDROM"); 421 if (len < 0 || len < sizeof(struct tb_drom_header)) 422 return -EINVAL; 423 424 sw->drom = kmalloc(len, GFP_KERNEL); 425 if (!sw->drom) 426 return -ENOMEM; 427 428 res = device_property_read_u8_array(dev, "ThunderboltDROM", sw->drom, 429 len); 430 if (res) 431 goto err; 432 433 *size = ((struct tb_drom_header *)sw->drom)->data_len + 434 TB_DROM_DATA_START; 435 if (*size > len) 436 goto err; 437 438 return 0; 439 440 err: 441 kfree(sw->drom); 442 sw->drom = NULL; 443 return -EINVAL; 444 } 445 446 static int tb_drom_copy_nvm(struct tb_switch *sw, u16 *size) 447 { 448 u32 drom_offset; 449 int ret; 450 451 if (!sw->dma_port) 452 return -ENODEV; 453 454 ret = tb_sw_read(sw, &drom_offset, TB_CFG_SWITCH, 455 sw->cap_plug_events + 12, 1); 456 if (ret) 457 return ret; 458 459 if (!drom_offset) 460 return -ENODEV; 461 462 ret = dma_port_flash_read(sw->dma_port, drom_offset + 14, size, 463 sizeof(*size)); 464 if (ret) 465 return ret; 466 467 /* Size includes CRC8 + UID + CRC32 */ 468 *size += 1 + 8 + 4; 469 sw->drom = kzalloc(*size, GFP_KERNEL); 470 if (!sw->drom) 471 return -ENOMEM; 472 473 ret = dma_port_flash_read(sw->dma_port, drom_offset, sw->drom, *size); 474 if (ret) 475 goto err_free; 476 477 /* 478 * Read UID from the minimal DROM because the one in NVM is just 479 * a placeholder. 480 */ 481 tb_drom_read_uid_only(sw, &sw->uid); 482 return 0; 483 484 err_free: 485 kfree(sw->drom); 486 sw->drom = NULL; 487 return ret; 488 } 489 490 static int usb4_copy_host_drom(struct tb_switch *sw, u16 *size) 491 { 492 int ret; 493 494 ret = usb4_switch_drom_read(sw, 14, size, sizeof(*size)); 495 if (ret) 496 return ret; 497 498 /* Size includes CRC8 + UID + CRC32 */ 499 *size += 1 + 8 + 4; 500 sw->drom = kzalloc(*size, GFP_KERNEL); 501 if (!sw->drom) 502 return -ENOMEM; 503 504 ret = usb4_switch_drom_read(sw, 0, sw->drom, *size); 505 if (ret) { 506 kfree(sw->drom); 507 sw->drom = NULL; 508 } 509 510 return ret; 511 } 512 513 static int tb_drom_read_n(struct tb_switch *sw, u16 offset, u8 *val, 514 size_t count) 515 { 516 if (tb_switch_is_usb4(sw)) 517 return usb4_switch_drom_read(sw, offset, val, count); 518 return tb_eeprom_read_n(sw, offset, val, count); 519 } 520 521 /** 522 * tb_drom_read - copy drom to sw->drom and parse it 523 */ 524 int tb_drom_read(struct tb_switch *sw) 525 { 526 u16 size; 527 u32 crc; 528 struct tb_drom_header *header; 529 int res; 530 if (sw->drom) 531 return 0; 532 533 if (tb_route(sw) == 0) { 534 /* 535 * Apple's NHI EFI driver supplies a DROM for the root switch 536 * in a device property. Use it if available. 537 */ 538 if (tb_drom_copy_efi(sw, &size) == 0) 539 goto parse; 540 541 /* Non-Apple hardware has the DROM as part of NVM */ 542 if (tb_drom_copy_nvm(sw, &size) == 0) 543 goto parse; 544 545 /* 546 * USB4 hosts may support reading DROM through router 547 * operations. 548 */ 549 if (tb_switch_is_usb4(sw)) { 550 usb4_switch_read_uid(sw, &sw->uid); 551 if (!usb4_copy_host_drom(sw, &size)) 552 goto parse; 553 } else { 554 /* 555 * The root switch contains only a dummy drom 556 * (header only, no entries). Hardcode the 557 * configuration here. 558 */ 559 tb_drom_read_uid_only(sw, &sw->uid); 560 } 561 562 return 0; 563 } 564 565 res = tb_drom_read_n(sw, 14, (u8 *) &size, 2); 566 if (res) 567 return res; 568 size &= 0x3ff; 569 size += TB_DROM_DATA_START; 570 tb_sw_dbg(sw, "reading drom (length: %#x)\n", size); 571 if (size < sizeof(*header)) { 572 tb_sw_warn(sw, "drom too small, aborting\n"); 573 return -EIO; 574 } 575 576 sw->drom = kzalloc(size, GFP_KERNEL); 577 if (!sw->drom) 578 return -ENOMEM; 579 res = tb_drom_read_n(sw, 0, sw->drom, size); 580 if (res) 581 goto err; 582 583 parse: 584 header = (void *) sw->drom; 585 586 if (header->data_len + TB_DROM_DATA_START != size) { 587 tb_sw_warn(sw, "drom size mismatch, aborting\n"); 588 goto err; 589 } 590 591 crc = tb_crc8((u8 *) &header->uid, 8); 592 if (crc != header->uid_crc8) { 593 tb_sw_warn(sw, 594 "drom uid crc8 mismatch (expected: %#x, got: %#x), aborting\n", 595 header->uid_crc8, crc); 596 goto err; 597 } 598 if (!sw->uid) 599 sw->uid = header->uid; 600 sw->vendor = header->vendor_id; 601 sw->device = header->model_id; 602 603 crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len); 604 if (crc != header->data_crc32) { 605 tb_sw_warn(sw, 606 "drom data crc32 mismatch (expected: %#x, got: %#x), continuing\n", 607 header->data_crc32, crc); 608 } 609 610 if (header->device_rom_revision > 2) 611 tb_sw_warn(sw, "drom device_rom_revision %#x unknown\n", 612 header->device_rom_revision); 613 614 return tb_drom_parse_entries(sw); 615 err: 616 kfree(sw->drom); 617 sw->drom = NULL; 618 return -EIO; 619 620 } 621