1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Probe module for 8250/16550-type MCHP PCI serial ports. 4 * 5 * Based on drivers/tty/serial/8250/8250_pci.c, 6 * 7 * Copyright (C) 2022 Microchip Technology Inc., All Rights Reserved. 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bitops.h> 12 #include <linux/delay.h> 13 #include <linux/io.h> 14 #include <linux/iopoll.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/pci.h> 18 #include <linux/serial_core.h> 19 #include <linux/serial_reg.h> 20 #include <linux/serial_8250.h> 21 #include <linux/slab.h> 22 #include <linux/string.h> 23 #include <linux/units.h> 24 #include <linux/tty.h> 25 #include <linux/tty_flip.h> 26 #include <linux/8250_pci.h> 27 28 #include <asm/byteorder.h> 29 30 #include "8250.h" 31 #include "8250_pcilib.h" 32 33 #define PCI_DEVICE_ID_EFAR_PCI12000 0xa002 34 #define PCI_DEVICE_ID_EFAR_PCI11010 0xa012 35 #define PCI_DEVICE_ID_EFAR_PCI11101 0xa022 36 #define PCI_DEVICE_ID_EFAR_PCI11400 0xa032 37 #define PCI_DEVICE_ID_EFAR_PCI11414 0xa042 38 39 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p 0x0001 40 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012 0x0002 41 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013 0x0003 42 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023 0x0004 43 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123 0x0005 44 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01 0x0006 45 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02 0x0007 46 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03 0x0008 47 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12 0x0009 48 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13 0x000a 49 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23 0x000b 50 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0 0x000c 51 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1 0x000d 52 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2 0x000e 53 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3 0x000f 54 55 #define PCI_SUBDEVICE_ID_EFAR_PCI12000 PCI_DEVICE_ID_EFAR_PCI12000 56 #define PCI_SUBDEVICE_ID_EFAR_PCI11010 PCI_DEVICE_ID_EFAR_PCI11010 57 #define PCI_SUBDEVICE_ID_EFAR_PCI11101 PCI_DEVICE_ID_EFAR_PCI11101 58 #define PCI_SUBDEVICE_ID_EFAR_PCI11400 PCI_DEVICE_ID_EFAR_PCI11400 59 #define PCI_SUBDEVICE_ID_EFAR_PCI11414 PCI_DEVICE_ID_EFAR_PCI11414 60 61 #define UART_SYSTEM_ADDR_BASE 0x1000 62 #define UART_DEV_REV_REG (UART_SYSTEM_ADDR_BASE + 0x00) 63 #define UART_DEV_REV_MASK GENMASK(7, 0) 64 #define UART_SYSLOCK_REG (UART_SYSTEM_ADDR_BASE + 0xA0) 65 #define UART_SYSLOCK BIT(2) 66 #define SYSLOCK_SLEEP_TIMEOUT 100 67 #define SYSLOCK_RETRY_CNT 1000 68 69 #define UART_RX_BYTE_FIFO 0x00 70 #define UART_FIFO_CTL 0x02 71 72 #define UART_ACTV_REG 0x11 73 #define UART_BLOCK_SET_ACTIVE BIT(0) 74 75 #define UART_PCI_CTRL_REG 0x80 76 #define UART_PCI_CTRL_SET_MULTIPLE_MSI BIT(4) 77 #define UART_PCI_CTRL_D3_CLK_ENABLE BIT(0) 78 79 #define ADCL_CFG_REG 0x40 80 #define ADCL_CFG_POL_SEL BIT(2) 81 #define ADCL_CFG_PIN_SEL BIT(1) 82 #define ADCL_CFG_EN BIT(0) 83 84 #define UART_BIT_SAMPLE_CNT 16 85 #define BAUD_CLOCK_DIV_INT_MSK GENMASK(31, 8) 86 #define ADCL_CFG_RTS_DELAY_MASK GENMASK(11, 8) 87 #define UART_CLOCK_DEFAULT (62500 * HZ_PER_KHZ) 88 89 #define UART_WAKE_REG 0x8C 90 #define UART_WAKE_MASK_REG 0x90 91 #define UART_WAKE_N_PIN BIT(2) 92 #define UART_WAKE_NCTS BIT(1) 93 #define UART_WAKE_INT BIT(0) 94 #define UART_WAKE_SRCS \ 95 (UART_WAKE_N_PIN | UART_WAKE_NCTS | UART_WAKE_INT) 96 97 #define UART_BAUD_CLK_DIVISOR_REG 0x54 98 99 #define UART_RESET_REG 0x94 100 #define UART_RESET_D3_RESET_DISABLE BIT(16) 101 102 #define UART_BURST_STATUS_REG 0x9C 103 #define UART_RX_BURST_FIFO 0xA4 104 105 #define MAX_PORTS 4 106 #define PORT_OFFSET 0x100 107 #define RX_BUF_SIZE 512 108 #define UART_BYTE_SIZE 1 109 #define UART_BURST_SIZE 4 110 111 #define UART_BST_STAT_RX_COUNT_MASK 0x00FF 112 #define UART_BST_STAT_IIR_INT_PEND 0x100000 113 #define UART_LSR_OVERRUN_ERR_CLR 0x43 114 #define UART_BST_STAT_LSR_RX_MASK 0x9F000000 115 #define UART_BST_STAT_LSR_RX_ERR_MASK 0x9E000000 116 #define UART_BST_STAT_LSR_OVERRUN_ERR 0x2000000 117 #define UART_BST_STAT_LSR_PARITY_ERR 0x4000000 118 #define UART_BST_STAT_LSR_FRAME_ERR 0x8000000 119 120 struct pci1xxxx_8250 { 121 unsigned int nr; 122 u8 dev_rev; 123 u8 pad[3]; 124 void __iomem *membase; 125 int line[] __counted_by(nr); 126 }; 127 128 static const struct serial_rs485 pci1xxxx_rs485_supported = { 129 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | 130 SER_RS485_RTS_AFTER_SEND, 131 .delay_rts_after_send = 1, 132 /* Delay RTS before send is not supported */ 133 }; 134 135 static int pci1xxxx_set_sys_lock(struct pci1xxxx_8250 *port) 136 { 137 writel(UART_SYSLOCK, port->membase + UART_SYSLOCK_REG); 138 return readl(port->membase + UART_SYSLOCK_REG); 139 } 140 141 static int pci1xxxx_acquire_sys_lock(struct pci1xxxx_8250 *port) 142 { 143 u32 regval; 144 145 return readx_poll_timeout(pci1xxxx_set_sys_lock, port, regval, 146 (regval & UART_SYSLOCK), 147 SYSLOCK_SLEEP_TIMEOUT, 148 SYSLOCK_RETRY_CNT * SYSLOCK_SLEEP_TIMEOUT); 149 } 150 151 static void pci1xxxx_release_sys_lock(struct pci1xxxx_8250 *port) 152 { 153 writel(0x0, port->membase + UART_SYSLOCK_REG); 154 } 155 156 static const int logical_to_physical_port_idx[][MAX_PORTS] = { 157 {0, 1, 2, 3}, /* PCI12000, PCI11010, PCI11101, PCI11400, PCI11414 */ 158 {0, 1, 2, 3}, /* PCI4p */ 159 {0, 1, 2, -1}, /* PCI3p012 */ 160 {0, 1, 3, -1}, /* PCI3p013 */ 161 {0, 2, 3, -1}, /* PCI3p023 */ 162 {1, 2, 3, -1}, /* PCI3p123 */ 163 {0, 1, -1, -1}, /* PCI2p01 */ 164 {0, 2, -1, -1}, /* PCI2p02 */ 165 {0, 3, -1, -1}, /* PCI2p03 */ 166 {1, 2, -1, -1}, /* PCI2p12 */ 167 {1, 3, -1, -1}, /* PCI2p13 */ 168 {2, 3, -1, -1}, /* PCI2p23 */ 169 {0, -1, -1, -1}, /* PCI1p0 */ 170 {1, -1, -1, -1}, /* PCI1p1 */ 171 {2, -1, -1, -1}, /* PCI1p2 */ 172 {3, -1, -1, -1}, /* PCI1p3 */ 173 }; 174 175 static int pci1xxxx_get_num_ports(struct pci_dev *dev) 176 { 177 switch (dev->subsystem_device) { 178 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0: 179 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1: 180 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2: 181 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3: 182 case PCI_SUBDEVICE_ID_EFAR_PCI12000: 183 case PCI_SUBDEVICE_ID_EFAR_PCI11010: 184 case PCI_SUBDEVICE_ID_EFAR_PCI11101: 185 case PCI_SUBDEVICE_ID_EFAR_PCI11400: 186 default: 187 return 1; 188 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01: 189 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02: 190 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03: 191 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12: 192 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13: 193 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23: 194 return 2; 195 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012: 196 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123: 197 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013: 198 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023: 199 return 3; 200 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p: 201 case PCI_SUBDEVICE_ID_EFAR_PCI11414: 202 return 4; 203 } 204 } 205 206 static unsigned int pci1xxxx_get_divisor(struct uart_port *port, 207 unsigned int baud, unsigned int *frac) 208 { 209 unsigned int quot; 210 211 /* 212 * Calculate baud rate sampling period in nanoseconds. 213 * Fractional part x denotes x/255 parts of a nanosecond. 214 */ 215 quot = NSEC_PER_SEC / (baud * UART_BIT_SAMPLE_CNT); 216 *frac = (NSEC_PER_SEC - quot * baud * UART_BIT_SAMPLE_CNT) * 217 255 / UART_BIT_SAMPLE_CNT / baud; 218 219 return quot; 220 } 221 222 static void pci1xxxx_set_divisor(struct uart_port *port, unsigned int baud, 223 unsigned int quot, unsigned int frac) 224 { 225 writel(FIELD_PREP(BAUD_CLOCK_DIV_INT_MSK, quot) | frac, 226 port->membase + UART_BAUD_CLK_DIVISOR_REG); 227 } 228 229 static int pci1xxxx_rs485_config(struct uart_port *port, 230 struct ktermios *termios, 231 struct serial_rs485 *rs485) 232 { 233 u32 delay_in_baud_periods; 234 u32 baud_period_in_ns; 235 u32 mode_cfg = 0; 236 u32 clock_div; 237 238 /* 239 * pci1xxxx's uart hardware supports only RTS delay after 240 * Tx and in units of bit times to a maximum of 15 241 */ 242 if (rs485->flags & SER_RS485_ENABLED) { 243 mode_cfg = ADCL_CFG_EN | ADCL_CFG_PIN_SEL; 244 245 if (!(rs485->flags & SER_RS485_RTS_ON_SEND)) 246 mode_cfg |= ADCL_CFG_POL_SEL; 247 248 if (rs485->delay_rts_after_send) { 249 clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG); 250 baud_period_in_ns = 251 FIELD_GET(BAUD_CLOCK_DIV_INT_MSK, clock_div) * 252 UART_BIT_SAMPLE_CNT; 253 delay_in_baud_periods = 254 rs485->delay_rts_after_send * NSEC_PER_MSEC / 255 baud_period_in_ns; 256 delay_in_baud_periods = 257 min_t(u32, delay_in_baud_periods, 258 FIELD_MAX(ADCL_CFG_RTS_DELAY_MASK)); 259 mode_cfg |= FIELD_PREP(ADCL_CFG_RTS_DELAY_MASK, 260 delay_in_baud_periods); 261 rs485->delay_rts_after_send = 262 baud_period_in_ns * delay_in_baud_periods / 263 NSEC_PER_MSEC; 264 } 265 } 266 writel(mode_cfg, port->membase + ADCL_CFG_REG); 267 return 0; 268 } 269 270 static u32 pci1xxxx_read_burst_status(struct uart_port *port) 271 { 272 u32 status; 273 274 status = readl(port->membase + UART_BURST_STATUS_REG); 275 if (status & UART_BST_STAT_LSR_RX_ERR_MASK) { 276 if (status & UART_BST_STAT_LSR_OVERRUN_ERR) { 277 writeb(UART_LSR_OVERRUN_ERR_CLR, 278 port->membase + UART_FIFO_CTL); 279 port->icount.overrun++; 280 } 281 282 if (status & UART_BST_STAT_LSR_FRAME_ERR) 283 port->icount.frame++; 284 285 if (status & UART_BST_STAT_LSR_PARITY_ERR) 286 port->icount.parity++; 287 } 288 return status; 289 } 290 291 static void pci1xxxx_process_read_data(struct uart_port *port, 292 unsigned char *rx_buff, u32 *buff_index, 293 u32 *valid_byte_count) 294 { 295 u32 valid_burst_count = *valid_byte_count / UART_BURST_SIZE; 296 u32 *burst_buf; 297 298 /* 299 * Depending on the RX Trigger Level the number of bytes that can be 300 * stored in RX FIFO at a time varies. Each transaction reads data 301 * in DWORDs. If there are less than four remaining valid_byte_count 302 * to read, the data is received one byte at a time. 303 */ 304 while (valid_burst_count--) { 305 if (*buff_index >= (RX_BUF_SIZE - UART_BURST_SIZE)) 306 break; 307 burst_buf = (u32 *)&rx_buff[*buff_index]; 308 *burst_buf = readl(port->membase + UART_RX_BURST_FIFO); 309 *buff_index += UART_BURST_SIZE; 310 *valid_byte_count -= UART_BURST_SIZE; 311 } 312 313 while (*valid_byte_count) { 314 if (*buff_index >= RX_BUF_SIZE) 315 break; 316 rx_buff[*buff_index] = readb(port->membase + 317 UART_RX_BYTE_FIFO); 318 *buff_index += UART_BYTE_SIZE; 319 *valid_byte_count -= UART_BYTE_SIZE; 320 } 321 } 322 323 static void pci1xxxx_rx_burst(struct uart_port *port, u32 uart_status) 324 { 325 u32 valid_byte_count = uart_status & UART_BST_STAT_RX_COUNT_MASK; 326 struct tty_port *tty_port = &port->state->port; 327 unsigned char rx_buff[RX_BUF_SIZE]; 328 u32 buff_index = 0; 329 u32 copied_len; 330 331 if (valid_byte_count != 0 && 332 valid_byte_count < RX_BUF_SIZE) { 333 pci1xxxx_process_read_data(port, rx_buff, &buff_index, 334 &valid_byte_count); 335 336 copied_len = (u32)tty_insert_flip_string(tty_port, rx_buff, 337 buff_index); 338 339 if (copied_len != buff_index) 340 port->icount.overrun += buff_index - copied_len; 341 342 port->icount.rx += buff_index; 343 tty_flip_buffer_push(tty_port); 344 } 345 } 346 347 static int pci1xxxx_handle_irq(struct uart_port *port) 348 { 349 unsigned long flags; 350 u32 status; 351 352 status = pci1xxxx_read_burst_status(port); 353 354 if (status & UART_BST_STAT_IIR_INT_PEND) 355 return 0; 356 357 spin_lock_irqsave(&port->lock, flags); 358 359 if (status & UART_BST_STAT_LSR_RX_MASK) 360 pci1xxxx_rx_burst(port, status); 361 362 spin_unlock_irqrestore(&port->lock, flags); 363 364 return 1; 365 } 366 367 static bool pci1xxxx_port_suspend(int line) 368 { 369 struct uart_8250_port *up = serial8250_get_port(line); 370 struct uart_port *port = &up->port; 371 struct tty_port *tport = &port->state->port; 372 unsigned long flags; 373 bool ret = false; 374 u8 wakeup_mask; 375 376 mutex_lock(&tport->mutex); 377 if (port->suspended == 0 && port->dev) { 378 wakeup_mask = readb(up->port.membase + UART_WAKE_MASK_REG); 379 380 uart_port_lock_irqsave(port, &flags); 381 port->mctrl &= ~TIOCM_OUT2; 382 port->ops->set_mctrl(port, port->mctrl); 383 uart_port_unlock_irqrestore(port, flags); 384 385 ret = (wakeup_mask & UART_WAKE_SRCS) != UART_WAKE_SRCS; 386 } 387 388 writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG); 389 mutex_unlock(&tport->mutex); 390 391 return ret; 392 } 393 394 static void pci1xxxx_port_resume(int line) 395 { 396 struct uart_8250_port *up = serial8250_get_port(line); 397 struct uart_port *port = &up->port; 398 struct tty_port *tport = &port->state->port; 399 unsigned long flags; 400 401 mutex_lock(&tport->mutex); 402 writeb(UART_BLOCK_SET_ACTIVE, port->membase + UART_ACTV_REG); 403 writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG); 404 405 if (port->suspended == 0) { 406 uart_port_lock_irqsave(port, &flags); 407 port->mctrl |= TIOCM_OUT2; 408 port->ops->set_mctrl(port, port->mctrl); 409 uart_port_unlock_irqrestore(port, flags); 410 } 411 mutex_unlock(&tport->mutex); 412 } 413 414 static int pci1xxxx_suspend(struct device *dev) 415 { 416 struct pci1xxxx_8250 *priv = dev_get_drvdata(dev); 417 struct pci_dev *pcidev = to_pci_dev(dev); 418 bool wakeup = false; 419 unsigned int data; 420 void __iomem *p; 421 int i; 422 423 for (i = 0; i < priv->nr; i++) { 424 if (priv->line[i] >= 0) { 425 serial8250_suspend_port(priv->line[i]); 426 wakeup |= pci1xxxx_port_suspend(priv->line[i]); 427 } 428 } 429 430 p = pci_ioremap_bar(pcidev, 0); 431 if (!p) { 432 dev_err(dev, "remapping of bar 0 memory failed"); 433 return -ENOMEM; 434 } 435 436 data = readl(p + UART_RESET_REG); 437 writel(data | UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG); 438 439 if (wakeup) 440 writeb(UART_PCI_CTRL_D3_CLK_ENABLE, p + UART_PCI_CTRL_REG); 441 442 iounmap(p); 443 device_set_wakeup_enable(dev, true); 444 pci_wake_from_d3(pcidev, true); 445 446 return 0; 447 } 448 449 static int pci1xxxx_resume(struct device *dev) 450 { 451 struct pci1xxxx_8250 *priv = dev_get_drvdata(dev); 452 struct pci_dev *pcidev = to_pci_dev(dev); 453 unsigned int data; 454 void __iomem *p; 455 int i; 456 457 p = pci_ioremap_bar(pcidev, 0); 458 if (!p) { 459 dev_err(dev, "remapping of bar 0 memory failed"); 460 return -ENOMEM; 461 } 462 463 data = readl(p + UART_RESET_REG); 464 writel(data & ~UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG); 465 iounmap(p); 466 467 for (i = 0; i < priv->nr; i++) { 468 if (priv->line[i] >= 0) { 469 pci1xxxx_port_resume(priv->line[i]); 470 serial8250_resume_port(priv->line[i]); 471 } 472 } 473 474 return 0; 475 } 476 477 static int pci1xxxx_setup(struct pci_dev *pdev, 478 struct uart_8250_port *port, int port_idx, int rev) 479 { 480 int ret; 481 482 port->port.flags |= UPF_FIXED_TYPE | UPF_SKIP_TEST; 483 port->port.type = PORT_MCHP16550A; 484 port->port.set_termios = serial8250_do_set_termios; 485 port->port.get_divisor = pci1xxxx_get_divisor; 486 port->port.set_divisor = pci1xxxx_set_divisor; 487 port->port.rs485_config = pci1xxxx_rs485_config; 488 port->port.rs485_supported = pci1xxxx_rs485_supported; 489 490 /* From C0 rev Burst operation is supported */ 491 if (rev >= 0xC0) 492 port->port.handle_irq = pci1xxxx_handle_irq; 493 494 ret = serial8250_pci_setup_port(pdev, port, 0, PORT_OFFSET * port_idx, 0); 495 if (ret < 0) 496 return ret; 497 498 writeb(UART_BLOCK_SET_ACTIVE, port->port.membase + UART_ACTV_REG); 499 writeb(UART_WAKE_SRCS, port->port.membase + UART_WAKE_REG); 500 writeb(UART_WAKE_N_PIN, port->port.membase + UART_WAKE_MASK_REG); 501 502 return 0; 503 } 504 505 static unsigned int pci1xxxx_get_max_port(int subsys_dev) 506 { 507 unsigned int i = MAX_PORTS; 508 509 if (subsys_dev < ARRAY_SIZE(logical_to_physical_port_idx)) 510 while (i--) { 511 if (logical_to_physical_port_idx[subsys_dev][i] != -1) 512 return logical_to_physical_port_idx[subsys_dev][i] + 1; 513 } 514 515 if (subsys_dev == PCI_SUBDEVICE_ID_EFAR_PCI11414) 516 return 4; 517 518 return 1; 519 } 520 521 static int pci1xxxx_logical_to_physical_port_translate(int subsys_dev, int port) 522 { 523 if (subsys_dev < ARRAY_SIZE(logical_to_physical_port_idx)) 524 return logical_to_physical_port_idx[subsys_dev][port]; 525 526 return logical_to_physical_port_idx[0][port]; 527 } 528 529 static int pci1xxxx_get_device_revision(struct pci1xxxx_8250 *priv) 530 { 531 u32 regval; 532 int ret; 533 534 /* 535 * DEV REV is a system register, HW Syslock bit 536 * should be acquired before accessing the register 537 */ 538 ret = pci1xxxx_acquire_sys_lock(priv); 539 if (ret) 540 return ret; 541 542 regval = readl(priv->membase + UART_DEV_REV_REG); 543 priv->dev_rev = regval & UART_DEV_REV_MASK; 544 545 pci1xxxx_release_sys_lock(priv); 546 547 return 0; 548 } 549 550 static int pci1xxxx_serial_probe(struct pci_dev *pdev, 551 const struct pci_device_id *id) 552 { 553 struct device *dev = &pdev->dev; 554 struct pci1xxxx_8250 *priv; 555 struct uart_8250_port uart; 556 unsigned int max_vec_reqd; 557 unsigned int nr_ports, i; 558 int num_vectors; 559 int subsys_dev; 560 int port_idx; 561 int ret; 562 int rc; 563 564 rc = pcim_enable_device(pdev); 565 if (rc) 566 return rc; 567 568 nr_ports = pci1xxxx_get_num_ports(pdev); 569 570 priv = devm_kzalloc(dev, struct_size(priv, line, nr_ports), GFP_KERNEL); 571 if (!priv) 572 return -ENOMEM; 573 574 priv->membase = pci_ioremap_bar(pdev, 0); 575 if (!priv->membase) 576 return -ENOMEM; 577 578 ret = pci1xxxx_get_device_revision(priv); 579 if (ret) 580 return ret; 581 582 pci_set_master(pdev); 583 584 priv->nr = nr_ports; 585 586 subsys_dev = pdev->subsystem_device; 587 max_vec_reqd = pci1xxxx_get_max_port(subsys_dev); 588 589 num_vectors = pci_alloc_irq_vectors(pdev, 1, max_vec_reqd, PCI_IRQ_ALL_TYPES); 590 if (num_vectors < 0) { 591 pci_iounmap(pdev, priv->membase); 592 return num_vectors; 593 } 594 595 memset(&uart, 0, sizeof(uart)); 596 uart.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT; 597 uart.port.uartclk = UART_CLOCK_DEFAULT; 598 uart.port.dev = dev; 599 600 if (num_vectors == max_vec_reqd) 601 writeb(UART_PCI_CTRL_SET_MULTIPLE_MSI, priv->membase + UART_PCI_CTRL_REG); 602 603 for (i = 0; i < nr_ports; i++) { 604 priv->line[i] = -ENODEV; 605 606 port_idx = pci1xxxx_logical_to_physical_port_translate(subsys_dev, i); 607 608 if (num_vectors == max_vec_reqd) 609 uart.port.irq = pci_irq_vector(pdev, port_idx); 610 else 611 uart.port.irq = pci_irq_vector(pdev, 0); 612 613 rc = pci1xxxx_setup(pdev, &uart, port_idx, priv->dev_rev); 614 if (rc) { 615 dev_warn(dev, "Failed to setup port %u\n", i); 616 continue; 617 } 618 619 priv->line[i] = serial8250_register_8250_port(&uart); 620 if (priv->line[i] < 0) { 621 dev_warn(dev, 622 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 623 uart.port.iobase, uart.port.irq, uart.port.iotype, 624 priv->line[i]); 625 } 626 } 627 628 pci_set_drvdata(pdev, priv); 629 630 return 0; 631 } 632 633 static void pci1xxxx_serial_remove(struct pci_dev *dev) 634 { 635 struct pci1xxxx_8250 *priv = pci_get_drvdata(dev); 636 unsigned int i; 637 638 for (i = 0; i < priv->nr; i++) { 639 if (priv->line[i] >= 0) 640 serial8250_unregister_port(priv->line[i]); 641 } 642 643 pci_free_irq_vectors(dev); 644 pci_iounmap(dev, priv->membase); 645 } 646 647 static DEFINE_SIMPLE_DEV_PM_OPS(pci1xxxx_pm_ops, pci1xxxx_suspend, pci1xxxx_resume); 648 649 static const struct pci_device_id pci1xxxx_pci_tbl[] = { 650 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11010) }, 651 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11101) }, 652 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11400) }, 653 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11414) }, 654 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI12000) }, 655 {} 656 }; 657 MODULE_DEVICE_TABLE(pci, pci1xxxx_pci_tbl); 658 659 static struct pci_driver pci1xxxx_pci_driver = { 660 .name = "pci1xxxx serial", 661 .probe = pci1xxxx_serial_probe, 662 .remove = pci1xxxx_serial_remove, 663 .driver = { 664 .pm = pm_sleep_ptr(&pci1xxxx_pm_ops), 665 }, 666 .id_table = pci1xxxx_pci_tbl, 667 }; 668 module_pci_driver(pci1xxxx_pci_driver); 669 670 static_assert((ARRAY_SIZE(logical_to_physical_port_idx) == PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3 + 1)); 671 672 MODULE_IMPORT_NS(SERIAL_8250_PCI); 673 MODULE_DESCRIPTION("Microchip Technology Inc. PCIe to UART module"); 674 MODULE_AUTHOR("Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>"); 675 MODULE_AUTHOR("Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>"); 676 MODULE_LICENSE("GPL"); 677