1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for Atmel AT91 Serial ports 4 * Copyright (C) 2003 Rick Bronson 5 * 6 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. 7 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 8 * 9 * DMA support added by Chip Coldwell. 10 */ 11 #include <linux/tty.h> 12 #include <linux/ioport.h> 13 #include <linux/slab.h> 14 #include <linux/init.h> 15 #include <linux/serial.h> 16 #include <linux/clk.h> 17 #include <linux/console.h> 18 #include <linux/sysrq.h> 19 #include <linux/tty_flip.h> 20 #include <linux/platform_device.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/of_gpio.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/dmaengine.h> 26 #include <linux/atmel_pdc.h> 27 #include <linux/uaccess.h> 28 #include <linux/platform_data/atmel.h> 29 #include <linux/timer.h> 30 #include <linux/gpio.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/err.h> 33 #include <linux/irq.h> 34 #include <linux/suspend.h> 35 #include <linux/mm.h> 36 37 #include <asm/div64.h> 38 #include <asm/io.h> 39 #include <asm/ioctls.h> 40 41 #define PDC_BUFFER_SIZE 512 42 /* Revisit: We should calculate this based on the actual port settings */ 43 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ 44 45 /* The minium number of data FIFOs should be able to contain */ 46 #define ATMEL_MIN_FIFO_SIZE 8 47 /* 48 * These two offsets are substracted from the RX FIFO size to define the RTS 49 * high and low thresholds 50 */ 51 #define ATMEL_RTS_HIGH_OFFSET 16 52 #define ATMEL_RTS_LOW_OFFSET 20 53 54 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 55 #define SUPPORT_SYSRQ 56 #endif 57 58 #include <linux/serial_core.h> 59 60 #include "serial_mctrl_gpio.h" 61 #include "atmel_serial.h" 62 63 static void atmel_start_rx(struct uart_port *port); 64 static void atmel_stop_rx(struct uart_port *port); 65 66 #ifdef CONFIG_SERIAL_ATMEL_TTYAT 67 68 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we 69 * should coexist with the 8250 driver, such as if we have an external 16C550 70 * UART. */ 71 #define SERIAL_ATMEL_MAJOR 204 72 #define MINOR_START 154 73 #define ATMEL_DEVICENAME "ttyAT" 74 75 #else 76 77 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port 78 * name, but it is legally reserved for the 8250 driver. */ 79 #define SERIAL_ATMEL_MAJOR TTY_MAJOR 80 #define MINOR_START 64 81 #define ATMEL_DEVICENAME "ttyS" 82 83 #endif 84 85 #define ATMEL_ISR_PASS_LIMIT 256 86 87 struct atmel_dma_buffer { 88 unsigned char *buf; 89 dma_addr_t dma_addr; 90 unsigned int dma_size; 91 unsigned int ofs; 92 }; 93 94 struct atmel_uart_char { 95 u16 status; 96 u16 ch; 97 }; 98 99 /* 100 * Be careful, the real size of the ring buffer is 101 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer 102 * can contain up to 1024 characters in PIO mode and up to 4096 characters in 103 * DMA mode. 104 */ 105 #define ATMEL_SERIAL_RINGSIZE 1024 106 107 /* 108 * at91: 6 USARTs and one DBGU port (SAM9260) 109 * samx7: 3 USARTs and 5 UARTs 110 */ 111 #define ATMEL_MAX_UART 8 112 113 /* 114 * We wrap our port structure around the generic uart_port. 115 */ 116 struct atmel_uart_port { 117 struct uart_port uart; /* uart */ 118 struct clk *clk; /* uart clock */ 119 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ 120 u32 backup_imr; /* IMR saved during suspend */ 121 int break_active; /* break being received */ 122 123 bool use_dma_rx; /* enable DMA receiver */ 124 bool use_pdc_rx; /* enable PDC receiver */ 125 short pdc_rx_idx; /* current PDC RX buffer */ 126 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */ 127 128 bool use_dma_tx; /* enable DMA transmitter */ 129 bool use_pdc_tx; /* enable PDC transmitter */ 130 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */ 131 132 spinlock_t lock_tx; /* port lock */ 133 spinlock_t lock_rx; /* port lock */ 134 struct dma_chan *chan_tx; 135 struct dma_chan *chan_rx; 136 struct dma_async_tx_descriptor *desc_tx; 137 struct dma_async_tx_descriptor *desc_rx; 138 dma_cookie_t cookie_tx; 139 dma_cookie_t cookie_rx; 140 struct scatterlist sg_tx; 141 struct scatterlist sg_rx; 142 struct tasklet_struct tasklet_rx; 143 struct tasklet_struct tasklet_tx; 144 atomic_t tasklet_shutdown; 145 unsigned int irq_status_prev; 146 unsigned int tx_len; 147 148 struct circ_buf rx_ring; 149 150 struct mctrl_gpios *gpios; 151 u32 backup_mode; /* MR saved during iso7816 operations */ 152 u32 backup_brgr; /* BRGR saved during iso7816 operations */ 153 unsigned int tx_done_mask; 154 u32 fifo_size; 155 u32 rts_high; 156 u32 rts_low; 157 bool ms_irq_enabled; 158 u32 rtor; /* address of receiver timeout register if it exists */ 159 bool has_frac_baudrate; 160 bool has_hw_timer; 161 struct timer_list uart_timer; 162 163 bool tx_stopped; 164 bool suspended; 165 unsigned int pending; 166 unsigned int pending_status; 167 spinlock_t lock_suspended; 168 169 bool hd_start_rx; /* can start RX during half-duplex operation */ 170 171 /* ISO7816 */ 172 unsigned int fidi_min; 173 unsigned int fidi_max; 174 175 #ifdef CONFIG_PM 176 struct { 177 u32 cr; 178 u32 mr; 179 u32 imr; 180 u32 brgr; 181 u32 rtor; 182 u32 ttgr; 183 u32 fmr; 184 u32 fimr; 185 } cache; 186 #endif 187 188 int (*prepare_rx)(struct uart_port *port); 189 int (*prepare_tx)(struct uart_port *port); 190 void (*schedule_rx)(struct uart_port *port); 191 void (*schedule_tx)(struct uart_port *port); 192 void (*release_rx)(struct uart_port *port); 193 void (*release_tx)(struct uart_port *port); 194 }; 195 196 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; 197 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART); 198 199 #ifdef SUPPORT_SYSRQ 200 static struct console atmel_console; 201 #endif 202 203 #if defined(CONFIG_OF) 204 static const struct of_device_id atmel_serial_dt_ids[] = { 205 { .compatible = "atmel,at91rm9200-usart-serial" }, 206 { /* sentinel */ } 207 }; 208 #endif 209 210 static inline struct atmel_uart_port * 211 to_atmel_uart_port(struct uart_port *uart) 212 { 213 return container_of(uart, struct atmel_uart_port, uart); 214 } 215 216 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg) 217 { 218 return __raw_readl(port->membase + reg); 219 } 220 221 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value) 222 { 223 __raw_writel(value, port->membase + reg); 224 } 225 226 static inline u8 atmel_uart_read_char(struct uart_port *port) 227 { 228 return __raw_readb(port->membase + ATMEL_US_RHR); 229 } 230 231 static inline void atmel_uart_write_char(struct uart_port *port, u8 value) 232 { 233 __raw_writeb(value, port->membase + ATMEL_US_THR); 234 } 235 236 static inline int atmel_uart_is_half_duplex(struct uart_port *port) 237 { 238 return ((port->rs485.flags & SER_RS485_ENABLED) && 239 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) || 240 (port->iso7816.flags & SER_ISO7816_ENABLED); 241 } 242 243 #ifdef CONFIG_SERIAL_ATMEL_PDC 244 static bool atmel_use_pdc_rx(struct uart_port *port) 245 { 246 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 247 248 return atmel_port->use_pdc_rx; 249 } 250 251 static bool atmel_use_pdc_tx(struct uart_port *port) 252 { 253 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 254 255 return atmel_port->use_pdc_tx; 256 } 257 #else 258 static bool atmel_use_pdc_rx(struct uart_port *port) 259 { 260 return false; 261 } 262 263 static bool atmel_use_pdc_tx(struct uart_port *port) 264 { 265 return false; 266 } 267 #endif 268 269 static bool atmel_use_dma_tx(struct uart_port *port) 270 { 271 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 272 273 return atmel_port->use_dma_tx; 274 } 275 276 static bool atmel_use_dma_rx(struct uart_port *port) 277 { 278 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 279 280 return atmel_port->use_dma_rx; 281 } 282 283 static bool atmel_use_fifo(struct uart_port *port) 284 { 285 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 286 287 return atmel_port->fifo_size; 288 } 289 290 static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port, 291 struct tasklet_struct *t) 292 { 293 if (!atomic_read(&atmel_port->tasklet_shutdown)) 294 tasklet_schedule(t); 295 } 296 297 /* Enable or disable the rs485 support */ 298 static int atmel_config_rs485(struct uart_port *port, 299 struct serial_rs485 *rs485conf) 300 { 301 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 302 unsigned int mode; 303 304 /* Disable interrupts */ 305 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask); 306 307 mode = atmel_uart_readl(port, ATMEL_US_MR); 308 309 /* Resetting serial mode to RS232 (0x0) */ 310 mode &= ~ATMEL_US_USMODE; 311 312 port->rs485 = *rs485conf; 313 314 if (rs485conf->flags & SER_RS485_ENABLED) { 315 dev_dbg(port->dev, "Setting UART to RS485\n"); 316 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 317 atmel_uart_writel(port, ATMEL_US_TTGR, 318 rs485conf->delay_rts_after_send); 319 mode |= ATMEL_US_USMODE_RS485; 320 } else { 321 dev_dbg(port->dev, "Setting UART to RS232\n"); 322 if (atmel_use_pdc_tx(port)) 323 atmel_port->tx_done_mask = ATMEL_US_ENDTX | 324 ATMEL_US_TXBUFE; 325 else 326 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 327 } 328 atmel_uart_writel(port, ATMEL_US_MR, mode); 329 330 /* Enable interrupts */ 331 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask); 332 333 return 0; 334 } 335 336 static unsigned int atmel_calc_cd(struct uart_port *port, 337 struct serial_iso7816 *iso7816conf) 338 { 339 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 340 unsigned int cd; 341 u64 mck_rate; 342 343 mck_rate = (u64)clk_get_rate(atmel_port->clk); 344 do_div(mck_rate, iso7816conf->clk); 345 cd = mck_rate; 346 return cd; 347 } 348 349 static unsigned int atmel_calc_fidi(struct uart_port *port, 350 struct serial_iso7816 *iso7816conf) 351 { 352 u64 fidi = 0; 353 354 if (iso7816conf->sc_fi && iso7816conf->sc_di) { 355 fidi = (u64)iso7816conf->sc_fi; 356 do_div(fidi, iso7816conf->sc_di); 357 } 358 return (u32)fidi; 359 } 360 361 /* Enable or disable the iso7816 support */ 362 /* Called with interrupts disabled */ 363 static int atmel_config_iso7816(struct uart_port *port, 364 struct serial_iso7816 *iso7816conf) 365 { 366 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 367 unsigned int mode; 368 unsigned int cd, fidi; 369 int ret = 0; 370 371 /* Disable interrupts */ 372 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask); 373 374 mode = atmel_uart_readl(port, ATMEL_US_MR); 375 376 if (iso7816conf->flags & SER_ISO7816_ENABLED) { 377 mode &= ~ATMEL_US_USMODE; 378 379 if (iso7816conf->tg > 255) { 380 dev_err(port->dev, "ISO7816: Timeguard exceeding 255\n"); 381 memset(iso7816conf, 0, sizeof(struct serial_iso7816)); 382 ret = -EINVAL; 383 goto err_out; 384 } 385 386 if ((iso7816conf->flags & SER_ISO7816_T_PARAM) 387 == SER_ISO7816_T(0)) { 388 mode |= ATMEL_US_USMODE_ISO7816_T0 | ATMEL_US_DSNACK; 389 } else if ((iso7816conf->flags & SER_ISO7816_T_PARAM) 390 == SER_ISO7816_T(1)) { 391 mode |= ATMEL_US_USMODE_ISO7816_T1 | ATMEL_US_INACK; 392 } else { 393 dev_err(port->dev, "ISO7816: Type not supported\n"); 394 memset(iso7816conf, 0, sizeof(struct serial_iso7816)); 395 ret = -EINVAL; 396 goto err_out; 397 } 398 399 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_NBSTOP | ATMEL_US_PAR); 400 401 /* select mck clock, and output */ 402 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO; 403 /* set parity for normal/inverse mode + max iterations */ 404 mode |= ATMEL_US_PAR_EVEN | ATMEL_US_NBSTOP_1 | ATMEL_US_MAX_ITER(3); 405 406 cd = atmel_calc_cd(port, iso7816conf); 407 fidi = atmel_calc_fidi(port, iso7816conf); 408 if (fidi == 0) { 409 dev_warn(port->dev, "ISO7816 fidi = 0, Generator generates no signal\n"); 410 } else if (fidi < atmel_port->fidi_min 411 || fidi > atmel_port->fidi_max) { 412 dev_err(port->dev, "ISO7816 fidi = %u, value not supported\n", fidi); 413 memset(iso7816conf, 0, sizeof(struct serial_iso7816)); 414 ret = -EINVAL; 415 goto err_out; 416 } 417 418 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) { 419 /* port not yet in iso7816 mode: store configuration */ 420 atmel_port->backup_mode = atmel_uart_readl(port, ATMEL_US_MR); 421 atmel_port->backup_brgr = atmel_uart_readl(port, ATMEL_US_BRGR); 422 } 423 424 atmel_uart_writel(port, ATMEL_US_TTGR, iso7816conf->tg); 425 atmel_uart_writel(port, ATMEL_US_BRGR, cd); 426 atmel_uart_writel(port, ATMEL_US_FIDI, fidi); 427 428 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXEN); 429 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY | ATMEL_US_NACK | ATMEL_US_ITERATION; 430 } else { 431 dev_dbg(port->dev, "Setting UART back to RS232\n"); 432 /* back to last RS232 settings */ 433 mode = atmel_port->backup_mode; 434 memset(iso7816conf, 0, sizeof(struct serial_iso7816)); 435 atmel_uart_writel(port, ATMEL_US_TTGR, 0); 436 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->backup_brgr); 437 atmel_uart_writel(port, ATMEL_US_FIDI, 0x174); 438 439 if (atmel_use_pdc_tx(port)) 440 atmel_port->tx_done_mask = ATMEL_US_ENDTX | 441 ATMEL_US_TXBUFE; 442 else 443 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 444 } 445 446 port->iso7816 = *iso7816conf; 447 448 atmel_uart_writel(port, ATMEL_US_MR, mode); 449 450 err_out: 451 /* Enable interrupts */ 452 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask); 453 454 return ret; 455 } 456 457 /* 458 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. 459 */ 460 static u_int atmel_tx_empty(struct uart_port *port) 461 { 462 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 463 464 if (atmel_port->tx_stopped) 465 return TIOCSER_TEMT; 466 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ? 467 TIOCSER_TEMT : 468 0; 469 } 470 471 /* 472 * Set state of the modem control output lines 473 */ 474 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) 475 { 476 unsigned int control = 0; 477 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR); 478 unsigned int rts_paused, rts_ready; 479 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 480 481 /* override mode to RS485 if needed, otherwise keep the current mode */ 482 if (port->rs485.flags & SER_RS485_ENABLED) { 483 atmel_uart_writel(port, ATMEL_US_TTGR, 484 port->rs485.delay_rts_after_send); 485 mode &= ~ATMEL_US_USMODE; 486 mode |= ATMEL_US_USMODE_RS485; 487 } 488 489 /* set the RTS line state according to the mode */ 490 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) { 491 /* force RTS line to high level */ 492 rts_paused = ATMEL_US_RTSEN; 493 494 /* give the control of the RTS line back to the hardware */ 495 rts_ready = ATMEL_US_RTSDIS; 496 } else { 497 /* force RTS line to high level */ 498 rts_paused = ATMEL_US_RTSDIS; 499 500 /* force RTS line to low level */ 501 rts_ready = ATMEL_US_RTSEN; 502 } 503 504 if (mctrl & TIOCM_RTS) 505 control |= rts_ready; 506 else 507 control |= rts_paused; 508 509 if (mctrl & TIOCM_DTR) 510 control |= ATMEL_US_DTREN; 511 else 512 control |= ATMEL_US_DTRDIS; 513 514 atmel_uart_writel(port, ATMEL_US_CR, control); 515 516 mctrl_gpio_set(atmel_port->gpios, mctrl); 517 518 /* Local loopback mode? */ 519 mode &= ~ATMEL_US_CHMODE; 520 if (mctrl & TIOCM_LOOP) 521 mode |= ATMEL_US_CHMODE_LOC_LOOP; 522 else 523 mode |= ATMEL_US_CHMODE_NORMAL; 524 525 atmel_uart_writel(port, ATMEL_US_MR, mode); 526 } 527 528 /* 529 * Get state of the modem control input lines 530 */ 531 static u_int atmel_get_mctrl(struct uart_port *port) 532 { 533 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 534 unsigned int ret = 0, status; 535 536 status = atmel_uart_readl(port, ATMEL_US_CSR); 537 538 /* 539 * The control signals are active low. 540 */ 541 if (!(status & ATMEL_US_DCD)) 542 ret |= TIOCM_CD; 543 if (!(status & ATMEL_US_CTS)) 544 ret |= TIOCM_CTS; 545 if (!(status & ATMEL_US_DSR)) 546 ret |= TIOCM_DSR; 547 if (!(status & ATMEL_US_RI)) 548 ret |= TIOCM_RI; 549 550 return mctrl_gpio_get(atmel_port->gpios, &ret); 551 } 552 553 /* 554 * Stop transmitting. 555 */ 556 static void atmel_stop_tx(struct uart_port *port) 557 { 558 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 559 560 if (atmel_use_pdc_tx(port)) { 561 /* disable PDC transmit */ 562 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS); 563 } 564 565 /* 566 * Disable the transmitter. 567 * This is mandatory when DMA is used, otherwise the DMA buffer 568 * is fully transmitted. 569 */ 570 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS); 571 atmel_port->tx_stopped = true; 572 573 /* Disable interrupts */ 574 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask); 575 576 if (atmel_uart_is_half_duplex(port)) 577 atmel_start_rx(port); 578 579 } 580 581 /* 582 * Start transmitting. 583 */ 584 static void atmel_start_tx(struct uart_port *port) 585 { 586 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 587 588 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR) 589 & ATMEL_PDC_TXTEN)) 590 /* The transmitter is already running. Yes, we 591 really need this.*/ 592 return; 593 594 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port)) 595 if (atmel_uart_is_half_duplex(port)) 596 atmel_stop_rx(port); 597 598 if (atmel_use_pdc_tx(port)) 599 /* re-enable PDC transmit */ 600 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 601 602 /* Enable interrupts */ 603 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask); 604 605 /* re-enable the transmitter */ 606 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN); 607 atmel_port->tx_stopped = false; 608 } 609 610 /* 611 * start receiving - port is in process of being opened. 612 */ 613 static void atmel_start_rx(struct uart_port *port) 614 { 615 /* reset status and receiver */ 616 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 617 618 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN); 619 620 if (atmel_use_pdc_rx(port)) { 621 /* enable PDC controller */ 622 atmel_uart_writel(port, ATMEL_US_IER, 623 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 624 port->read_status_mask); 625 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); 626 } else { 627 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY); 628 } 629 } 630 631 /* 632 * Stop receiving - port is in process of being closed. 633 */ 634 static void atmel_stop_rx(struct uart_port *port) 635 { 636 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS); 637 638 if (atmel_use_pdc_rx(port)) { 639 /* disable PDC receive */ 640 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS); 641 atmel_uart_writel(port, ATMEL_US_IDR, 642 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | 643 port->read_status_mask); 644 } else { 645 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY); 646 } 647 } 648 649 /* 650 * Enable modem status interrupts 651 */ 652 static void atmel_enable_ms(struct uart_port *port) 653 { 654 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 655 uint32_t ier = 0; 656 657 /* 658 * Interrupt should not be enabled twice 659 */ 660 if (atmel_port->ms_irq_enabled) 661 return; 662 663 atmel_port->ms_irq_enabled = true; 664 665 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) 666 ier |= ATMEL_US_CTSIC; 667 668 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR)) 669 ier |= ATMEL_US_DSRIC; 670 671 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI)) 672 ier |= ATMEL_US_RIIC; 673 674 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD)) 675 ier |= ATMEL_US_DCDIC; 676 677 atmel_uart_writel(port, ATMEL_US_IER, ier); 678 679 mctrl_gpio_enable_ms(atmel_port->gpios); 680 } 681 682 /* 683 * Disable modem status interrupts 684 */ 685 static void atmel_disable_ms(struct uart_port *port) 686 { 687 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 688 uint32_t idr = 0; 689 690 /* 691 * Interrupt should not be disabled twice 692 */ 693 if (!atmel_port->ms_irq_enabled) 694 return; 695 696 atmel_port->ms_irq_enabled = false; 697 698 mctrl_gpio_disable_ms(atmel_port->gpios); 699 700 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) 701 idr |= ATMEL_US_CTSIC; 702 703 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR)) 704 idr |= ATMEL_US_DSRIC; 705 706 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI)) 707 idr |= ATMEL_US_RIIC; 708 709 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD)) 710 idr |= ATMEL_US_DCDIC; 711 712 atmel_uart_writel(port, ATMEL_US_IDR, idr); 713 } 714 715 /* 716 * Control the transmission of a break signal 717 */ 718 static void atmel_break_ctl(struct uart_port *port, int break_state) 719 { 720 if (break_state != 0) 721 /* start break */ 722 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK); 723 else 724 /* stop break */ 725 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK); 726 } 727 728 /* 729 * Stores the incoming character in the ring buffer 730 */ 731 static void 732 atmel_buffer_rx_char(struct uart_port *port, unsigned int status, 733 unsigned int ch) 734 { 735 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 736 struct circ_buf *ring = &atmel_port->rx_ring; 737 struct atmel_uart_char *c; 738 739 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE)) 740 /* Buffer overflow, ignore char */ 741 return; 742 743 c = &((struct atmel_uart_char *)ring->buf)[ring->head]; 744 c->status = status; 745 c->ch = ch; 746 747 /* Make sure the character is stored before we update head. */ 748 smp_wmb(); 749 750 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 751 } 752 753 /* 754 * Deal with parity, framing and overrun errors. 755 */ 756 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status) 757 { 758 /* clear error */ 759 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 760 761 if (status & ATMEL_US_RXBRK) { 762 /* ignore side-effect */ 763 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 764 port->icount.brk++; 765 } 766 if (status & ATMEL_US_PARE) 767 port->icount.parity++; 768 if (status & ATMEL_US_FRAME) 769 port->icount.frame++; 770 if (status & ATMEL_US_OVRE) 771 port->icount.overrun++; 772 } 773 774 /* 775 * Characters received (called from interrupt handler) 776 */ 777 static void atmel_rx_chars(struct uart_port *port) 778 { 779 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 780 unsigned int status, ch; 781 782 status = atmel_uart_readl(port, ATMEL_US_CSR); 783 while (status & ATMEL_US_RXRDY) { 784 ch = atmel_uart_read_char(port); 785 786 /* 787 * note that the error handling code is 788 * out of the main execution path 789 */ 790 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 791 | ATMEL_US_OVRE | ATMEL_US_RXBRK) 792 || atmel_port->break_active)) { 793 794 /* clear error */ 795 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 796 797 if (status & ATMEL_US_RXBRK 798 && !atmel_port->break_active) { 799 atmel_port->break_active = 1; 800 atmel_uart_writel(port, ATMEL_US_IER, 801 ATMEL_US_RXBRK); 802 } else { 803 /* 804 * This is either the end-of-break 805 * condition or we've received at 806 * least one character without RXBRK 807 * being set. In both cases, the next 808 * RXBRK will indicate start-of-break. 809 */ 810 atmel_uart_writel(port, ATMEL_US_IDR, 811 ATMEL_US_RXBRK); 812 status &= ~ATMEL_US_RXBRK; 813 atmel_port->break_active = 0; 814 } 815 } 816 817 atmel_buffer_rx_char(port, status, ch); 818 status = atmel_uart_readl(port, ATMEL_US_CSR); 819 } 820 821 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx); 822 } 823 824 /* 825 * Transmit characters (called from tasklet with TXRDY interrupt 826 * disabled) 827 */ 828 static void atmel_tx_chars(struct uart_port *port) 829 { 830 struct circ_buf *xmit = &port->state->xmit; 831 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 832 833 if (port->x_char && 834 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) { 835 atmel_uart_write_char(port, port->x_char); 836 port->icount.tx++; 837 port->x_char = 0; 838 } 839 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 840 return; 841 842 while (atmel_uart_readl(port, ATMEL_US_CSR) & 843 atmel_port->tx_done_mask) { 844 atmel_uart_write_char(port, xmit->buf[xmit->tail]); 845 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 846 port->icount.tx++; 847 if (uart_circ_empty(xmit)) 848 break; 849 } 850 851 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 852 uart_write_wakeup(port); 853 854 if (!uart_circ_empty(xmit)) 855 /* Enable interrupts */ 856 atmel_uart_writel(port, ATMEL_US_IER, 857 atmel_port->tx_done_mask); 858 } 859 860 static void atmel_complete_tx_dma(void *arg) 861 { 862 struct atmel_uart_port *atmel_port = arg; 863 struct uart_port *port = &atmel_port->uart; 864 struct circ_buf *xmit = &port->state->xmit; 865 struct dma_chan *chan = atmel_port->chan_tx; 866 unsigned long flags; 867 868 spin_lock_irqsave(&port->lock, flags); 869 870 if (chan) 871 dmaengine_terminate_all(chan); 872 xmit->tail += atmel_port->tx_len; 873 xmit->tail &= UART_XMIT_SIZE - 1; 874 875 port->icount.tx += atmel_port->tx_len; 876 877 spin_lock_irq(&atmel_port->lock_tx); 878 async_tx_ack(atmel_port->desc_tx); 879 atmel_port->cookie_tx = -EINVAL; 880 atmel_port->desc_tx = NULL; 881 spin_unlock_irq(&atmel_port->lock_tx); 882 883 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 884 uart_write_wakeup(port); 885 886 /* 887 * xmit is a circular buffer so, if we have just send data from 888 * xmit->tail to the end of xmit->buf, now we have to transmit the 889 * remaining data from the beginning of xmit->buf to xmit->head. 890 */ 891 if (!uart_circ_empty(xmit)) 892 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx); 893 else if (atmel_uart_is_half_duplex(port)) { 894 /* 895 * DMA done, re-enable TXEMPTY and signal that we can stop 896 * TX and start RX for RS485 897 */ 898 atmel_port->hd_start_rx = true; 899 atmel_uart_writel(port, ATMEL_US_IER, 900 atmel_port->tx_done_mask); 901 } 902 903 spin_unlock_irqrestore(&port->lock, flags); 904 } 905 906 static void atmel_release_tx_dma(struct uart_port *port) 907 { 908 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 909 struct dma_chan *chan = atmel_port->chan_tx; 910 911 if (chan) { 912 dmaengine_terminate_all(chan); 913 dma_release_channel(chan); 914 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1, 915 DMA_TO_DEVICE); 916 } 917 918 atmel_port->desc_tx = NULL; 919 atmel_port->chan_tx = NULL; 920 atmel_port->cookie_tx = -EINVAL; 921 } 922 923 /* 924 * Called from tasklet with TXRDY interrupt is disabled. 925 */ 926 static void atmel_tx_dma(struct uart_port *port) 927 { 928 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 929 struct circ_buf *xmit = &port->state->xmit; 930 struct dma_chan *chan = atmel_port->chan_tx; 931 struct dma_async_tx_descriptor *desc; 932 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx; 933 unsigned int tx_len, part1_len, part2_len, sg_len; 934 dma_addr_t phys_addr; 935 936 /* Make sure we have an idle channel */ 937 if (atmel_port->desc_tx != NULL) 938 return; 939 940 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 941 /* 942 * DMA is idle now. 943 * Port xmit buffer is already mapped, 944 * and it is one page... Just adjust 945 * offsets and lengths. Since it is a circular buffer, 946 * we have to transmit till the end, and then the rest. 947 * Take the port lock to get a 948 * consistent xmit buffer state. 949 */ 950 tx_len = CIRC_CNT_TO_END(xmit->head, 951 xmit->tail, 952 UART_XMIT_SIZE); 953 954 if (atmel_port->fifo_size) { 955 /* multi data mode */ 956 part1_len = (tx_len & ~0x3); /* DWORD access */ 957 part2_len = (tx_len & 0x3); /* BYTE access */ 958 } else { 959 /* single data (legacy) mode */ 960 part1_len = 0; 961 part2_len = tx_len; /* BYTE access only */ 962 } 963 964 sg_init_table(sgl, 2); 965 sg_len = 0; 966 phys_addr = sg_dma_address(sg_tx) + xmit->tail; 967 if (part1_len) { 968 sg = &sgl[sg_len++]; 969 sg_dma_address(sg) = phys_addr; 970 sg_dma_len(sg) = part1_len; 971 972 phys_addr += part1_len; 973 } 974 975 if (part2_len) { 976 sg = &sgl[sg_len++]; 977 sg_dma_address(sg) = phys_addr; 978 sg_dma_len(sg) = part2_len; 979 } 980 981 /* 982 * save tx_len so atmel_complete_tx_dma() will increase 983 * xmit->tail correctly 984 */ 985 atmel_port->tx_len = tx_len; 986 987 desc = dmaengine_prep_slave_sg(chan, 988 sgl, 989 sg_len, 990 DMA_MEM_TO_DEV, 991 DMA_PREP_INTERRUPT | 992 DMA_CTRL_ACK); 993 if (!desc) { 994 dev_err(port->dev, "Failed to send via dma!\n"); 995 return; 996 } 997 998 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE); 999 1000 atmel_port->desc_tx = desc; 1001 desc->callback = atmel_complete_tx_dma; 1002 desc->callback_param = atmel_port; 1003 atmel_port->cookie_tx = dmaengine_submit(desc); 1004 } 1005 1006 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1007 uart_write_wakeup(port); 1008 } 1009 1010 static int atmel_prepare_tx_dma(struct uart_port *port) 1011 { 1012 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1013 struct device *mfd_dev = port->dev->parent; 1014 dma_cap_mask_t mask; 1015 struct dma_slave_config config; 1016 int ret, nent; 1017 1018 dma_cap_zero(mask); 1019 dma_cap_set(DMA_SLAVE, mask); 1020 1021 atmel_port->chan_tx = dma_request_slave_channel(mfd_dev, "tx"); 1022 if (atmel_port->chan_tx == NULL) 1023 goto chan_err; 1024 dev_info(port->dev, "using %s for tx DMA transfers\n", 1025 dma_chan_name(atmel_port->chan_tx)); 1026 1027 spin_lock_init(&atmel_port->lock_tx); 1028 sg_init_table(&atmel_port->sg_tx, 1); 1029 /* UART circular tx buffer is an aligned page. */ 1030 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf)); 1031 sg_set_page(&atmel_port->sg_tx, 1032 virt_to_page(port->state->xmit.buf), 1033 UART_XMIT_SIZE, 1034 offset_in_page(port->state->xmit.buf)); 1035 nent = dma_map_sg(port->dev, 1036 &atmel_port->sg_tx, 1037 1, 1038 DMA_TO_DEVICE); 1039 1040 if (!nent) { 1041 dev_dbg(port->dev, "need to release resource of dma\n"); 1042 goto chan_err; 1043 } else { 1044 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__, 1045 sg_dma_len(&atmel_port->sg_tx), 1046 port->state->xmit.buf, 1047 &sg_dma_address(&atmel_port->sg_tx)); 1048 } 1049 1050 /* Configure the slave DMA */ 1051 memset(&config, 0, sizeof(config)); 1052 config.direction = DMA_MEM_TO_DEV; 1053 config.dst_addr_width = (atmel_port->fifo_size) ? 1054 DMA_SLAVE_BUSWIDTH_4_BYTES : 1055 DMA_SLAVE_BUSWIDTH_1_BYTE; 1056 config.dst_addr = port->mapbase + ATMEL_US_THR; 1057 config.dst_maxburst = 1; 1058 1059 ret = dmaengine_slave_config(atmel_port->chan_tx, 1060 &config); 1061 if (ret) { 1062 dev_err(port->dev, "DMA tx slave configuration failed\n"); 1063 goto chan_err; 1064 } 1065 1066 return 0; 1067 1068 chan_err: 1069 dev_err(port->dev, "TX channel not available, switch to pio\n"); 1070 atmel_port->use_dma_tx = 0; 1071 if (atmel_port->chan_tx) 1072 atmel_release_tx_dma(port); 1073 return -EINVAL; 1074 } 1075 1076 static void atmel_complete_rx_dma(void *arg) 1077 { 1078 struct uart_port *port = arg; 1079 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1080 1081 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx); 1082 } 1083 1084 static void atmel_release_rx_dma(struct uart_port *port) 1085 { 1086 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1087 struct dma_chan *chan = atmel_port->chan_rx; 1088 1089 if (chan) { 1090 dmaengine_terminate_all(chan); 1091 dma_release_channel(chan); 1092 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1, 1093 DMA_FROM_DEVICE); 1094 } 1095 1096 atmel_port->desc_rx = NULL; 1097 atmel_port->chan_rx = NULL; 1098 atmel_port->cookie_rx = -EINVAL; 1099 } 1100 1101 static void atmel_rx_from_dma(struct uart_port *port) 1102 { 1103 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1104 struct tty_port *tport = &port->state->port; 1105 struct circ_buf *ring = &atmel_port->rx_ring; 1106 struct dma_chan *chan = atmel_port->chan_rx; 1107 struct dma_tx_state state; 1108 enum dma_status dmastat; 1109 size_t count; 1110 1111 1112 /* Reset the UART timeout early so that we don't miss one */ 1113 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); 1114 dmastat = dmaengine_tx_status(chan, 1115 atmel_port->cookie_rx, 1116 &state); 1117 /* Restart a new tasklet if DMA status is error */ 1118 if (dmastat == DMA_ERROR) { 1119 dev_dbg(port->dev, "Get residue error, restart tasklet\n"); 1120 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT); 1121 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx); 1122 return; 1123 } 1124 1125 /* CPU claims ownership of RX DMA buffer */ 1126 dma_sync_sg_for_cpu(port->dev, 1127 &atmel_port->sg_rx, 1128 1, 1129 DMA_FROM_DEVICE); 1130 1131 /* 1132 * ring->head points to the end of data already written by the DMA. 1133 * ring->tail points to the beginning of data to be read by the 1134 * framework. 1135 * The current transfer size should not be larger than the dma buffer 1136 * length. 1137 */ 1138 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue; 1139 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx)); 1140 /* 1141 * At this point ring->head may point to the first byte right after the 1142 * last byte of the dma buffer: 1143 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx) 1144 * 1145 * However ring->tail must always points inside the dma buffer: 1146 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1 1147 * 1148 * Since we use a ring buffer, we have to handle the case 1149 * where head is lower than tail. In such a case, we first read from 1150 * tail to the end of the buffer then reset tail. 1151 */ 1152 if (ring->head < ring->tail) { 1153 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail; 1154 1155 tty_insert_flip_string(tport, ring->buf + ring->tail, count); 1156 ring->tail = 0; 1157 port->icount.rx += count; 1158 } 1159 1160 /* Finally we read data from tail to head */ 1161 if (ring->tail < ring->head) { 1162 count = ring->head - ring->tail; 1163 1164 tty_insert_flip_string(tport, ring->buf + ring->tail, count); 1165 /* Wrap ring->head if needed */ 1166 if (ring->head >= sg_dma_len(&atmel_port->sg_rx)) 1167 ring->head = 0; 1168 ring->tail = ring->head; 1169 port->icount.rx += count; 1170 } 1171 1172 /* USART retreives ownership of RX DMA buffer */ 1173 dma_sync_sg_for_device(port->dev, 1174 &atmel_port->sg_rx, 1175 1, 1176 DMA_FROM_DEVICE); 1177 1178 /* 1179 * Drop the lock here since it might end up calling 1180 * uart_start(), which takes the lock. 1181 */ 1182 spin_unlock(&port->lock); 1183 tty_flip_buffer_push(tport); 1184 spin_lock(&port->lock); 1185 1186 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT); 1187 } 1188 1189 static int atmel_prepare_rx_dma(struct uart_port *port) 1190 { 1191 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1192 struct device *mfd_dev = port->dev->parent; 1193 struct dma_async_tx_descriptor *desc; 1194 dma_cap_mask_t mask; 1195 struct dma_slave_config config; 1196 struct circ_buf *ring; 1197 int ret, nent; 1198 1199 ring = &atmel_port->rx_ring; 1200 1201 dma_cap_zero(mask); 1202 dma_cap_set(DMA_CYCLIC, mask); 1203 1204 atmel_port->chan_rx = dma_request_slave_channel(mfd_dev, "rx"); 1205 if (atmel_port->chan_rx == NULL) 1206 goto chan_err; 1207 dev_info(port->dev, "using %s for rx DMA transfers\n", 1208 dma_chan_name(atmel_port->chan_rx)); 1209 1210 spin_lock_init(&atmel_port->lock_rx); 1211 sg_init_table(&atmel_port->sg_rx, 1); 1212 /* UART circular rx buffer is an aligned page. */ 1213 BUG_ON(!PAGE_ALIGNED(ring->buf)); 1214 sg_set_page(&atmel_port->sg_rx, 1215 virt_to_page(ring->buf), 1216 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE, 1217 offset_in_page(ring->buf)); 1218 nent = dma_map_sg(port->dev, 1219 &atmel_port->sg_rx, 1220 1, 1221 DMA_FROM_DEVICE); 1222 1223 if (!nent) { 1224 dev_dbg(port->dev, "need to release resource of dma\n"); 1225 goto chan_err; 1226 } else { 1227 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__, 1228 sg_dma_len(&atmel_port->sg_rx), 1229 ring->buf, 1230 &sg_dma_address(&atmel_port->sg_rx)); 1231 } 1232 1233 /* Configure the slave DMA */ 1234 memset(&config, 0, sizeof(config)); 1235 config.direction = DMA_DEV_TO_MEM; 1236 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1237 config.src_addr = port->mapbase + ATMEL_US_RHR; 1238 config.src_maxburst = 1; 1239 1240 ret = dmaengine_slave_config(atmel_port->chan_rx, 1241 &config); 1242 if (ret) { 1243 dev_err(port->dev, "DMA rx slave configuration failed\n"); 1244 goto chan_err; 1245 } 1246 /* 1247 * Prepare a cyclic dma transfer, assign 2 descriptors, 1248 * each one is half ring buffer size 1249 */ 1250 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx, 1251 sg_dma_address(&atmel_port->sg_rx), 1252 sg_dma_len(&atmel_port->sg_rx), 1253 sg_dma_len(&atmel_port->sg_rx)/2, 1254 DMA_DEV_TO_MEM, 1255 DMA_PREP_INTERRUPT); 1256 if (!desc) { 1257 dev_err(port->dev, "Preparing DMA cyclic failed\n"); 1258 goto chan_err; 1259 } 1260 desc->callback = atmel_complete_rx_dma; 1261 desc->callback_param = port; 1262 atmel_port->desc_rx = desc; 1263 atmel_port->cookie_rx = dmaengine_submit(desc); 1264 1265 return 0; 1266 1267 chan_err: 1268 dev_err(port->dev, "RX channel not available, switch to pio\n"); 1269 atmel_port->use_dma_rx = 0; 1270 if (atmel_port->chan_rx) 1271 atmel_release_rx_dma(port); 1272 return -EINVAL; 1273 } 1274 1275 static void atmel_uart_timer_callback(struct timer_list *t) 1276 { 1277 struct atmel_uart_port *atmel_port = from_timer(atmel_port, t, 1278 uart_timer); 1279 struct uart_port *port = &atmel_port->uart; 1280 1281 if (!atomic_read(&atmel_port->tasklet_shutdown)) { 1282 tasklet_schedule(&atmel_port->tasklet_rx); 1283 mod_timer(&atmel_port->uart_timer, 1284 jiffies + uart_poll_timeout(port)); 1285 } 1286 } 1287 1288 /* 1289 * receive interrupt handler. 1290 */ 1291 static void 1292 atmel_handle_receive(struct uart_port *port, unsigned int pending) 1293 { 1294 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1295 1296 if (atmel_use_pdc_rx(port)) { 1297 /* 1298 * PDC receive. Just schedule the tasklet and let it 1299 * figure out the details. 1300 * 1301 * TODO: We're not handling error flags correctly at 1302 * the moment. 1303 */ 1304 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) { 1305 atmel_uart_writel(port, ATMEL_US_IDR, 1306 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)); 1307 atmel_tasklet_schedule(atmel_port, 1308 &atmel_port->tasklet_rx); 1309 } 1310 1311 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | 1312 ATMEL_US_FRAME | ATMEL_US_PARE)) 1313 atmel_pdc_rxerr(port, pending); 1314 } 1315 1316 if (atmel_use_dma_rx(port)) { 1317 if (pending & ATMEL_US_TIMEOUT) { 1318 atmel_uart_writel(port, ATMEL_US_IDR, 1319 ATMEL_US_TIMEOUT); 1320 atmel_tasklet_schedule(atmel_port, 1321 &atmel_port->tasklet_rx); 1322 } 1323 } 1324 1325 /* Interrupt receive */ 1326 if (pending & ATMEL_US_RXRDY) 1327 atmel_rx_chars(port); 1328 else if (pending & ATMEL_US_RXBRK) { 1329 /* 1330 * End of break detected. If it came along with a 1331 * character, atmel_rx_chars will handle it. 1332 */ 1333 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 1334 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK); 1335 atmel_port->break_active = 0; 1336 } 1337 } 1338 1339 /* 1340 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe) 1341 */ 1342 static void 1343 atmel_handle_transmit(struct uart_port *port, unsigned int pending) 1344 { 1345 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1346 1347 if (pending & atmel_port->tx_done_mask) { 1348 atmel_uart_writel(port, ATMEL_US_IDR, 1349 atmel_port->tx_done_mask); 1350 1351 /* Start RX if flag was set and FIFO is empty */ 1352 if (atmel_port->hd_start_rx) { 1353 if (!(atmel_uart_readl(port, ATMEL_US_CSR) 1354 & ATMEL_US_TXEMPTY)) 1355 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n"); 1356 1357 atmel_port->hd_start_rx = false; 1358 atmel_start_rx(port); 1359 } 1360 1361 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx); 1362 } 1363 } 1364 1365 /* 1366 * status flags interrupt handler. 1367 */ 1368 static void 1369 atmel_handle_status(struct uart_port *port, unsigned int pending, 1370 unsigned int status) 1371 { 1372 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1373 unsigned int status_change; 1374 1375 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC 1376 | ATMEL_US_CTSIC)) { 1377 status_change = status ^ atmel_port->irq_status_prev; 1378 atmel_port->irq_status_prev = status; 1379 1380 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR 1381 | ATMEL_US_DCD | ATMEL_US_CTS)) { 1382 /* TODO: All reads to CSR will clear these interrupts! */ 1383 if (status_change & ATMEL_US_RI) 1384 port->icount.rng++; 1385 if (status_change & ATMEL_US_DSR) 1386 port->icount.dsr++; 1387 if (status_change & ATMEL_US_DCD) 1388 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); 1389 if (status_change & ATMEL_US_CTS) 1390 uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); 1391 1392 wake_up_interruptible(&port->state->port.delta_msr_wait); 1393 } 1394 } 1395 1396 if (pending & (ATMEL_US_NACK | ATMEL_US_ITERATION)) 1397 dev_dbg(port->dev, "ISO7816 ERROR (0x%08x)\n", pending); 1398 } 1399 1400 /* 1401 * Interrupt handler 1402 */ 1403 static irqreturn_t atmel_interrupt(int irq, void *dev_id) 1404 { 1405 struct uart_port *port = dev_id; 1406 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1407 unsigned int status, pending, mask, pass_counter = 0; 1408 1409 spin_lock(&atmel_port->lock_suspended); 1410 1411 do { 1412 status = atmel_uart_readl(port, ATMEL_US_CSR); 1413 mask = atmel_uart_readl(port, ATMEL_US_IMR); 1414 pending = status & mask; 1415 if (!pending) 1416 break; 1417 1418 if (atmel_port->suspended) { 1419 atmel_port->pending |= pending; 1420 atmel_port->pending_status = status; 1421 atmel_uart_writel(port, ATMEL_US_IDR, mask); 1422 pm_system_wakeup(); 1423 break; 1424 } 1425 1426 atmel_handle_receive(port, pending); 1427 atmel_handle_status(port, pending, status); 1428 atmel_handle_transmit(port, pending); 1429 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT); 1430 1431 spin_unlock(&atmel_port->lock_suspended); 1432 1433 return pass_counter ? IRQ_HANDLED : IRQ_NONE; 1434 } 1435 1436 static void atmel_release_tx_pdc(struct uart_port *port) 1437 { 1438 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1439 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1440 1441 dma_unmap_single(port->dev, 1442 pdc->dma_addr, 1443 pdc->dma_size, 1444 DMA_TO_DEVICE); 1445 } 1446 1447 /* 1448 * Called from tasklet with ENDTX and TXBUFE interrupts disabled. 1449 */ 1450 static void atmel_tx_pdc(struct uart_port *port) 1451 { 1452 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1453 struct circ_buf *xmit = &port->state->xmit; 1454 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1455 int count; 1456 1457 /* nothing left to transmit? */ 1458 if (atmel_uart_readl(port, ATMEL_PDC_TCR)) 1459 return; 1460 1461 xmit->tail += pdc->ofs; 1462 xmit->tail &= UART_XMIT_SIZE - 1; 1463 1464 port->icount.tx += pdc->ofs; 1465 pdc->ofs = 0; 1466 1467 /* more to transmit - setup next transfer */ 1468 1469 /* disable PDC transmit */ 1470 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS); 1471 1472 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { 1473 dma_sync_single_for_device(port->dev, 1474 pdc->dma_addr, 1475 pdc->dma_size, 1476 DMA_TO_DEVICE); 1477 1478 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 1479 pdc->ofs = count; 1480 1481 atmel_uart_writel(port, ATMEL_PDC_TPR, 1482 pdc->dma_addr + xmit->tail); 1483 atmel_uart_writel(port, ATMEL_PDC_TCR, count); 1484 /* re-enable PDC transmit */ 1485 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 1486 /* Enable interrupts */ 1487 atmel_uart_writel(port, ATMEL_US_IER, 1488 atmel_port->tx_done_mask); 1489 } else { 1490 if (atmel_uart_is_half_duplex(port)) { 1491 /* DMA done, stop TX, start RX for RS485 */ 1492 atmel_start_rx(port); 1493 } 1494 } 1495 1496 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1497 uart_write_wakeup(port); 1498 } 1499 1500 static int atmel_prepare_tx_pdc(struct uart_port *port) 1501 { 1502 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1503 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; 1504 struct circ_buf *xmit = &port->state->xmit; 1505 1506 pdc->buf = xmit->buf; 1507 pdc->dma_addr = dma_map_single(port->dev, 1508 pdc->buf, 1509 UART_XMIT_SIZE, 1510 DMA_TO_DEVICE); 1511 pdc->dma_size = UART_XMIT_SIZE; 1512 pdc->ofs = 0; 1513 1514 return 0; 1515 } 1516 1517 static void atmel_rx_from_ring(struct uart_port *port) 1518 { 1519 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1520 struct circ_buf *ring = &atmel_port->rx_ring; 1521 unsigned int flg; 1522 unsigned int status; 1523 1524 while (ring->head != ring->tail) { 1525 struct atmel_uart_char c; 1526 1527 /* Make sure c is loaded after head. */ 1528 smp_rmb(); 1529 1530 c = ((struct atmel_uart_char *)ring->buf)[ring->tail]; 1531 1532 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1); 1533 1534 port->icount.rx++; 1535 status = c.status; 1536 flg = TTY_NORMAL; 1537 1538 /* 1539 * note that the error handling code is 1540 * out of the main execution path 1541 */ 1542 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME 1543 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) { 1544 if (status & ATMEL_US_RXBRK) { 1545 /* ignore side-effect */ 1546 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); 1547 1548 port->icount.brk++; 1549 if (uart_handle_break(port)) 1550 continue; 1551 } 1552 if (status & ATMEL_US_PARE) 1553 port->icount.parity++; 1554 if (status & ATMEL_US_FRAME) 1555 port->icount.frame++; 1556 if (status & ATMEL_US_OVRE) 1557 port->icount.overrun++; 1558 1559 status &= port->read_status_mask; 1560 1561 if (status & ATMEL_US_RXBRK) 1562 flg = TTY_BREAK; 1563 else if (status & ATMEL_US_PARE) 1564 flg = TTY_PARITY; 1565 else if (status & ATMEL_US_FRAME) 1566 flg = TTY_FRAME; 1567 } 1568 1569 1570 if (uart_handle_sysrq_char(port, c.ch)) 1571 continue; 1572 1573 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg); 1574 } 1575 1576 /* 1577 * Drop the lock here since it might end up calling 1578 * uart_start(), which takes the lock. 1579 */ 1580 spin_unlock(&port->lock); 1581 tty_flip_buffer_push(&port->state->port); 1582 spin_lock(&port->lock); 1583 } 1584 1585 static void atmel_release_rx_pdc(struct uart_port *port) 1586 { 1587 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1588 int i; 1589 1590 for (i = 0; i < 2; i++) { 1591 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1592 1593 dma_unmap_single(port->dev, 1594 pdc->dma_addr, 1595 pdc->dma_size, 1596 DMA_FROM_DEVICE); 1597 kfree(pdc->buf); 1598 } 1599 } 1600 1601 static void atmel_rx_from_pdc(struct uart_port *port) 1602 { 1603 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1604 struct tty_port *tport = &port->state->port; 1605 struct atmel_dma_buffer *pdc; 1606 int rx_idx = atmel_port->pdc_rx_idx; 1607 unsigned int head; 1608 unsigned int tail; 1609 unsigned int count; 1610 1611 do { 1612 /* Reset the UART timeout early so that we don't miss one */ 1613 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); 1614 1615 pdc = &atmel_port->pdc_rx[rx_idx]; 1616 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr; 1617 tail = pdc->ofs; 1618 1619 /* If the PDC has switched buffers, RPR won't contain 1620 * any address within the current buffer. Since head 1621 * is unsigned, we just need a one-way comparison to 1622 * find out. 1623 * 1624 * In this case, we just need to consume the entire 1625 * buffer and resubmit it for DMA. This will clear the 1626 * ENDRX bit as well, so that we can safely re-enable 1627 * all interrupts below. 1628 */ 1629 head = min(head, pdc->dma_size); 1630 1631 if (likely(head != tail)) { 1632 dma_sync_single_for_cpu(port->dev, pdc->dma_addr, 1633 pdc->dma_size, DMA_FROM_DEVICE); 1634 1635 /* 1636 * head will only wrap around when we recycle 1637 * the DMA buffer, and when that happens, we 1638 * explicitly set tail to 0. So head will 1639 * always be greater than tail. 1640 */ 1641 count = head - tail; 1642 1643 tty_insert_flip_string(tport, pdc->buf + pdc->ofs, 1644 count); 1645 1646 dma_sync_single_for_device(port->dev, pdc->dma_addr, 1647 pdc->dma_size, DMA_FROM_DEVICE); 1648 1649 port->icount.rx += count; 1650 pdc->ofs = head; 1651 } 1652 1653 /* 1654 * If the current buffer is full, we need to check if 1655 * the next one contains any additional data. 1656 */ 1657 if (head >= pdc->dma_size) { 1658 pdc->ofs = 0; 1659 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr); 1660 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size); 1661 1662 rx_idx = !rx_idx; 1663 atmel_port->pdc_rx_idx = rx_idx; 1664 } 1665 } while (head >= pdc->dma_size); 1666 1667 /* 1668 * Drop the lock here since it might end up calling 1669 * uart_start(), which takes the lock. 1670 */ 1671 spin_unlock(&port->lock); 1672 tty_flip_buffer_push(tport); 1673 spin_lock(&port->lock); 1674 1675 atmel_uart_writel(port, ATMEL_US_IER, 1676 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 1677 } 1678 1679 static int atmel_prepare_rx_pdc(struct uart_port *port) 1680 { 1681 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1682 int i; 1683 1684 for (i = 0; i < 2; i++) { 1685 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; 1686 1687 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL); 1688 if (pdc->buf == NULL) { 1689 if (i != 0) { 1690 dma_unmap_single(port->dev, 1691 atmel_port->pdc_rx[0].dma_addr, 1692 PDC_BUFFER_SIZE, 1693 DMA_FROM_DEVICE); 1694 kfree(atmel_port->pdc_rx[0].buf); 1695 } 1696 atmel_port->use_pdc_rx = 0; 1697 return -ENOMEM; 1698 } 1699 pdc->dma_addr = dma_map_single(port->dev, 1700 pdc->buf, 1701 PDC_BUFFER_SIZE, 1702 DMA_FROM_DEVICE); 1703 pdc->dma_size = PDC_BUFFER_SIZE; 1704 pdc->ofs = 0; 1705 } 1706 1707 atmel_port->pdc_rx_idx = 0; 1708 1709 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr); 1710 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE); 1711 1712 atmel_uart_writel(port, ATMEL_PDC_RNPR, 1713 atmel_port->pdc_rx[1].dma_addr); 1714 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE); 1715 1716 return 0; 1717 } 1718 1719 /* 1720 * tasklet handling tty stuff outside the interrupt handler. 1721 */ 1722 static void atmel_tasklet_rx_func(unsigned long data) 1723 { 1724 struct uart_port *port = (struct uart_port *)data; 1725 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1726 1727 /* The interrupt handler does not take the lock */ 1728 spin_lock(&port->lock); 1729 atmel_port->schedule_rx(port); 1730 spin_unlock(&port->lock); 1731 } 1732 1733 static void atmel_tasklet_tx_func(unsigned long data) 1734 { 1735 struct uart_port *port = (struct uart_port *)data; 1736 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1737 1738 /* The interrupt handler does not take the lock */ 1739 spin_lock(&port->lock); 1740 atmel_port->schedule_tx(port); 1741 spin_unlock(&port->lock); 1742 } 1743 1744 static void atmel_init_property(struct atmel_uart_port *atmel_port, 1745 struct platform_device *pdev) 1746 { 1747 struct device_node *np = pdev->dev.of_node; 1748 1749 /* DMA/PDC usage specification */ 1750 if (of_property_read_bool(np, "atmel,use-dma-rx")) { 1751 if (of_property_read_bool(np, "dmas")) { 1752 atmel_port->use_dma_rx = true; 1753 atmel_port->use_pdc_rx = false; 1754 } else { 1755 atmel_port->use_dma_rx = false; 1756 atmel_port->use_pdc_rx = true; 1757 } 1758 } else { 1759 atmel_port->use_dma_rx = false; 1760 atmel_port->use_pdc_rx = false; 1761 } 1762 1763 if (of_property_read_bool(np, "atmel,use-dma-tx")) { 1764 if (of_property_read_bool(np, "dmas")) { 1765 atmel_port->use_dma_tx = true; 1766 atmel_port->use_pdc_tx = false; 1767 } else { 1768 atmel_port->use_dma_tx = false; 1769 atmel_port->use_pdc_tx = true; 1770 } 1771 } else { 1772 atmel_port->use_dma_tx = false; 1773 atmel_port->use_pdc_tx = false; 1774 } 1775 } 1776 1777 static void atmel_set_ops(struct uart_port *port) 1778 { 1779 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1780 1781 if (atmel_use_dma_rx(port)) { 1782 atmel_port->prepare_rx = &atmel_prepare_rx_dma; 1783 atmel_port->schedule_rx = &atmel_rx_from_dma; 1784 atmel_port->release_rx = &atmel_release_rx_dma; 1785 } else if (atmel_use_pdc_rx(port)) { 1786 atmel_port->prepare_rx = &atmel_prepare_rx_pdc; 1787 atmel_port->schedule_rx = &atmel_rx_from_pdc; 1788 atmel_port->release_rx = &atmel_release_rx_pdc; 1789 } else { 1790 atmel_port->prepare_rx = NULL; 1791 atmel_port->schedule_rx = &atmel_rx_from_ring; 1792 atmel_port->release_rx = NULL; 1793 } 1794 1795 if (atmel_use_dma_tx(port)) { 1796 atmel_port->prepare_tx = &atmel_prepare_tx_dma; 1797 atmel_port->schedule_tx = &atmel_tx_dma; 1798 atmel_port->release_tx = &atmel_release_tx_dma; 1799 } else if (atmel_use_pdc_tx(port)) { 1800 atmel_port->prepare_tx = &atmel_prepare_tx_pdc; 1801 atmel_port->schedule_tx = &atmel_tx_pdc; 1802 atmel_port->release_tx = &atmel_release_tx_pdc; 1803 } else { 1804 atmel_port->prepare_tx = NULL; 1805 atmel_port->schedule_tx = &atmel_tx_chars; 1806 atmel_port->release_tx = NULL; 1807 } 1808 } 1809 1810 /* 1811 * Get ip name usart or uart 1812 */ 1813 static void atmel_get_ip_name(struct uart_port *port) 1814 { 1815 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1816 int name = atmel_uart_readl(port, ATMEL_US_NAME); 1817 u32 version; 1818 u32 usart, dbgu_uart, new_uart; 1819 /* ASCII decoding for IP version */ 1820 usart = 0x55534152; /* USAR(T) */ 1821 dbgu_uart = 0x44424755; /* DBGU */ 1822 new_uart = 0x55415254; /* UART */ 1823 1824 /* 1825 * Only USART devices from at91sam9260 SOC implement fractional 1826 * baudrate. It is available for all asynchronous modes, with the 1827 * following restriction: the sampling clock's duty cycle is not 1828 * constant. 1829 */ 1830 atmel_port->has_frac_baudrate = false; 1831 atmel_port->has_hw_timer = false; 1832 1833 if (name == new_uart) { 1834 dev_dbg(port->dev, "Uart with hw timer"); 1835 atmel_port->has_hw_timer = true; 1836 atmel_port->rtor = ATMEL_UA_RTOR; 1837 } else if (name == usart) { 1838 dev_dbg(port->dev, "Usart\n"); 1839 atmel_port->has_frac_baudrate = true; 1840 atmel_port->has_hw_timer = true; 1841 atmel_port->rtor = ATMEL_US_RTOR; 1842 version = atmel_uart_readl(port, ATMEL_US_VERSION); 1843 switch (version) { 1844 case 0x814: /* sama5d2 */ 1845 /* fall through */ 1846 case 0x701: /* sama5d4 */ 1847 atmel_port->fidi_min = 3; 1848 atmel_port->fidi_max = 65535; 1849 break; 1850 case 0x502: /* sam9x5, sama5d3 */ 1851 atmel_port->fidi_min = 3; 1852 atmel_port->fidi_max = 2047; 1853 break; 1854 default: 1855 atmel_port->fidi_min = 1; 1856 atmel_port->fidi_max = 2047; 1857 } 1858 } else if (name == dbgu_uart) { 1859 dev_dbg(port->dev, "Dbgu or uart without hw timer\n"); 1860 } else { 1861 /* fallback for older SoCs: use version field */ 1862 version = atmel_uart_readl(port, ATMEL_US_VERSION); 1863 switch (version) { 1864 case 0x302: 1865 case 0x10213: 1866 case 0x10302: 1867 dev_dbg(port->dev, "This version is usart\n"); 1868 atmel_port->has_frac_baudrate = true; 1869 atmel_port->has_hw_timer = true; 1870 atmel_port->rtor = ATMEL_US_RTOR; 1871 break; 1872 case 0x203: 1873 case 0x10202: 1874 dev_dbg(port->dev, "This version is uart\n"); 1875 break; 1876 default: 1877 dev_err(port->dev, "Not supported ip name nor version, set to uart\n"); 1878 } 1879 } 1880 } 1881 1882 /* 1883 * Perform initialization and enable port for reception 1884 */ 1885 static int atmel_startup(struct uart_port *port) 1886 { 1887 struct platform_device *pdev = to_platform_device(port->dev); 1888 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 1889 int retval; 1890 1891 /* 1892 * Ensure that no interrupts are enabled otherwise when 1893 * request_irq() is called we could get stuck trying to 1894 * handle an unexpected interrupt 1895 */ 1896 atmel_uart_writel(port, ATMEL_US_IDR, -1); 1897 atmel_port->ms_irq_enabled = false; 1898 1899 /* 1900 * Allocate the IRQ 1901 */ 1902 retval = request_irq(port->irq, atmel_interrupt, 1903 IRQF_SHARED | IRQF_COND_SUSPEND, 1904 dev_name(&pdev->dev), port); 1905 if (retval) { 1906 dev_err(port->dev, "atmel_startup - Can't get irq\n"); 1907 return retval; 1908 } 1909 1910 atomic_set(&atmel_port->tasklet_shutdown, 0); 1911 tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func, 1912 (unsigned long)port); 1913 tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func, 1914 (unsigned long)port); 1915 1916 /* 1917 * Initialize DMA (if necessary) 1918 */ 1919 atmel_init_property(atmel_port, pdev); 1920 atmel_set_ops(port); 1921 1922 if (atmel_port->prepare_rx) { 1923 retval = atmel_port->prepare_rx(port); 1924 if (retval < 0) 1925 atmel_set_ops(port); 1926 } 1927 1928 if (atmel_port->prepare_tx) { 1929 retval = atmel_port->prepare_tx(port); 1930 if (retval < 0) 1931 atmel_set_ops(port); 1932 } 1933 1934 /* 1935 * Enable FIFO when available 1936 */ 1937 if (atmel_port->fifo_size) { 1938 unsigned int txrdym = ATMEL_US_ONE_DATA; 1939 unsigned int rxrdym = ATMEL_US_ONE_DATA; 1940 unsigned int fmr; 1941 1942 atmel_uart_writel(port, ATMEL_US_CR, 1943 ATMEL_US_FIFOEN | 1944 ATMEL_US_RXFCLR | 1945 ATMEL_US_TXFLCLR); 1946 1947 if (atmel_use_dma_tx(port)) 1948 txrdym = ATMEL_US_FOUR_DATA; 1949 1950 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym); 1951 if (atmel_port->rts_high && 1952 atmel_port->rts_low) 1953 fmr |= ATMEL_US_FRTSC | 1954 ATMEL_US_RXFTHRES(atmel_port->rts_high) | 1955 ATMEL_US_RXFTHRES2(atmel_port->rts_low); 1956 1957 atmel_uart_writel(port, ATMEL_US_FMR, fmr); 1958 } 1959 1960 /* Save current CSR for comparison in atmel_tasklet_func() */ 1961 atmel_port->irq_status_prev = atmel_uart_readl(port, ATMEL_US_CSR); 1962 1963 /* 1964 * Finally, enable the serial port 1965 */ 1966 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 1967 /* enable xmit & rcvr */ 1968 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN); 1969 atmel_port->tx_stopped = false; 1970 1971 timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0); 1972 1973 if (atmel_use_pdc_rx(port)) { 1974 /* set UART timeout */ 1975 if (!atmel_port->has_hw_timer) { 1976 mod_timer(&atmel_port->uart_timer, 1977 jiffies + uart_poll_timeout(port)); 1978 /* set USART timeout */ 1979 } else { 1980 atmel_uart_writel(port, atmel_port->rtor, 1981 PDC_RX_TIMEOUT); 1982 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); 1983 1984 atmel_uart_writel(port, ATMEL_US_IER, 1985 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); 1986 } 1987 /* enable PDC controller */ 1988 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); 1989 } else if (atmel_use_dma_rx(port)) { 1990 /* set UART timeout */ 1991 if (!atmel_port->has_hw_timer) { 1992 mod_timer(&atmel_port->uart_timer, 1993 jiffies + uart_poll_timeout(port)); 1994 /* set USART timeout */ 1995 } else { 1996 atmel_uart_writel(port, atmel_port->rtor, 1997 PDC_RX_TIMEOUT); 1998 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); 1999 2000 atmel_uart_writel(port, ATMEL_US_IER, 2001 ATMEL_US_TIMEOUT); 2002 } 2003 } else { 2004 /* enable receive only */ 2005 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY); 2006 } 2007 2008 return 0; 2009 } 2010 2011 /* 2012 * Flush any TX data submitted for DMA. Called when the TX circular 2013 * buffer is reset. 2014 */ 2015 static void atmel_flush_buffer(struct uart_port *port) 2016 { 2017 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2018 2019 if (atmel_use_pdc_tx(port)) { 2020 atmel_uart_writel(port, ATMEL_PDC_TCR, 0); 2021 atmel_port->pdc_tx.ofs = 0; 2022 } 2023 /* 2024 * in uart_flush_buffer(), the xmit circular buffer has just 2025 * been cleared, so we have to reset tx_len accordingly. 2026 */ 2027 atmel_port->tx_len = 0; 2028 } 2029 2030 /* 2031 * Disable the port 2032 */ 2033 static void atmel_shutdown(struct uart_port *port) 2034 { 2035 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2036 2037 /* Disable modem control lines interrupts */ 2038 atmel_disable_ms(port); 2039 2040 /* Disable interrupts at device level */ 2041 atmel_uart_writel(port, ATMEL_US_IDR, -1); 2042 2043 /* Prevent spurious interrupts from scheduling the tasklet */ 2044 atomic_inc(&atmel_port->tasklet_shutdown); 2045 2046 /* 2047 * Prevent any tasklets being scheduled during 2048 * cleanup 2049 */ 2050 del_timer_sync(&atmel_port->uart_timer); 2051 2052 /* Make sure that no interrupt is on the fly */ 2053 synchronize_irq(port->irq); 2054 2055 /* 2056 * Clear out any scheduled tasklets before 2057 * we destroy the buffers 2058 */ 2059 tasklet_kill(&atmel_port->tasklet_rx); 2060 tasklet_kill(&atmel_port->tasklet_tx); 2061 2062 /* 2063 * Ensure everything is stopped and 2064 * disable port and break condition. 2065 */ 2066 atmel_stop_rx(port); 2067 atmel_stop_tx(port); 2068 2069 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); 2070 2071 /* 2072 * Shut-down the DMA. 2073 */ 2074 if (atmel_port->release_rx) 2075 atmel_port->release_rx(port); 2076 if (atmel_port->release_tx) 2077 atmel_port->release_tx(port); 2078 2079 /* 2080 * Reset ring buffer pointers 2081 */ 2082 atmel_port->rx_ring.head = 0; 2083 atmel_port->rx_ring.tail = 0; 2084 2085 /* 2086 * Free the interrupts 2087 */ 2088 free_irq(port->irq, port); 2089 2090 atmel_flush_buffer(port); 2091 } 2092 2093 /* 2094 * Power / Clock management. 2095 */ 2096 static void atmel_serial_pm(struct uart_port *port, unsigned int state, 2097 unsigned int oldstate) 2098 { 2099 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2100 2101 switch (state) { 2102 case 0: 2103 /* 2104 * Enable the peripheral clock for this serial port. 2105 * This is called on uart_open() or a resume event. 2106 */ 2107 clk_prepare_enable(atmel_port->clk); 2108 2109 /* re-enable interrupts if we disabled some on suspend */ 2110 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr); 2111 break; 2112 case 3: 2113 /* Back up the interrupt mask and disable all interrupts */ 2114 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR); 2115 atmel_uart_writel(port, ATMEL_US_IDR, -1); 2116 2117 /* 2118 * Disable the peripheral clock for this serial port. 2119 * This is called on uart_close() or a suspend event. 2120 */ 2121 clk_disable_unprepare(atmel_port->clk); 2122 break; 2123 default: 2124 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state); 2125 } 2126 } 2127 2128 /* 2129 * Change the port parameters 2130 */ 2131 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, 2132 struct ktermios *old) 2133 { 2134 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2135 unsigned long flags; 2136 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0; 2137 2138 /* save the current mode register */ 2139 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR); 2140 2141 /* reset the mode, clock divisor, parity, stop bits and data size */ 2142 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP | 2143 ATMEL_US_PAR | ATMEL_US_USMODE); 2144 2145 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 2146 2147 /* byte size */ 2148 switch (termios->c_cflag & CSIZE) { 2149 case CS5: 2150 mode |= ATMEL_US_CHRL_5; 2151 break; 2152 case CS6: 2153 mode |= ATMEL_US_CHRL_6; 2154 break; 2155 case CS7: 2156 mode |= ATMEL_US_CHRL_7; 2157 break; 2158 default: 2159 mode |= ATMEL_US_CHRL_8; 2160 break; 2161 } 2162 2163 /* stop bits */ 2164 if (termios->c_cflag & CSTOPB) 2165 mode |= ATMEL_US_NBSTOP_2; 2166 2167 /* parity */ 2168 if (termios->c_cflag & PARENB) { 2169 /* Mark or Space parity */ 2170 if (termios->c_cflag & CMSPAR) { 2171 if (termios->c_cflag & PARODD) 2172 mode |= ATMEL_US_PAR_MARK; 2173 else 2174 mode |= ATMEL_US_PAR_SPACE; 2175 } else if (termios->c_cflag & PARODD) 2176 mode |= ATMEL_US_PAR_ODD; 2177 else 2178 mode |= ATMEL_US_PAR_EVEN; 2179 } else 2180 mode |= ATMEL_US_PAR_NONE; 2181 2182 spin_lock_irqsave(&port->lock, flags); 2183 2184 port->read_status_mask = ATMEL_US_OVRE; 2185 if (termios->c_iflag & INPCK) 2186 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 2187 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2188 port->read_status_mask |= ATMEL_US_RXBRK; 2189 2190 if (atmel_use_pdc_rx(port)) 2191 /* need to enable error interrupts */ 2192 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask); 2193 2194 /* 2195 * Characters to ignore 2196 */ 2197 port->ignore_status_mask = 0; 2198 if (termios->c_iflag & IGNPAR) 2199 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); 2200 if (termios->c_iflag & IGNBRK) { 2201 port->ignore_status_mask |= ATMEL_US_RXBRK; 2202 /* 2203 * If we're ignoring parity and break indicators, 2204 * ignore overruns too (for real raw support). 2205 */ 2206 if (termios->c_iflag & IGNPAR) 2207 port->ignore_status_mask |= ATMEL_US_OVRE; 2208 } 2209 /* TODO: Ignore all characters if CREAD is set.*/ 2210 2211 /* update the per-port timeout */ 2212 uart_update_timeout(port, termios->c_cflag, baud); 2213 2214 /* 2215 * save/disable interrupts. The tty layer will ensure that the 2216 * transmitter is empty if requested by the caller, so there's 2217 * no need to wait for it here. 2218 */ 2219 imr = atmel_uart_readl(port, ATMEL_US_IMR); 2220 atmel_uart_writel(port, ATMEL_US_IDR, -1); 2221 2222 /* disable receiver and transmitter */ 2223 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS); 2224 atmel_port->tx_stopped = true; 2225 2226 /* mode */ 2227 if (port->rs485.flags & SER_RS485_ENABLED) { 2228 atmel_uart_writel(port, ATMEL_US_TTGR, 2229 port->rs485.delay_rts_after_send); 2230 mode |= ATMEL_US_USMODE_RS485; 2231 } else if (port->iso7816.flags & SER_ISO7816_ENABLED) { 2232 atmel_uart_writel(port, ATMEL_US_TTGR, port->iso7816.tg); 2233 /* select mck clock, and output */ 2234 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO; 2235 /* set max iterations */ 2236 mode |= ATMEL_US_MAX_ITER(3); 2237 if ((port->iso7816.flags & SER_ISO7816_T_PARAM) 2238 == SER_ISO7816_T(0)) 2239 mode |= ATMEL_US_USMODE_ISO7816_T0; 2240 else 2241 mode |= ATMEL_US_USMODE_ISO7816_T1; 2242 } else if (termios->c_cflag & CRTSCTS) { 2243 /* RS232 with hardware handshake (RTS/CTS) */ 2244 if (atmel_use_fifo(port) && 2245 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) { 2246 /* 2247 * with ATMEL_US_USMODE_HWHS set, the controller will 2248 * be able to drive the RTS pin high/low when the RX 2249 * FIFO is above RXFTHRES/below RXFTHRES2. 2250 * It will also disable the transmitter when the CTS 2251 * pin is high. 2252 * This mode is not activated if CTS pin is a GPIO 2253 * because in this case, the transmitter is always 2254 * disabled (there must be an internal pull-up 2255 * responsible for this behaviour). 2256 * If the RTS pin is a GPIO, the controller won't be 2257 * able to drive it according to the FIFO thresholds, 2258 * but it will be handled by the driver. 2259 */ 2260 mode |= ATMEL_US_USMODE_HWHS; 2261 } else { 2262 /* 2263 * For platforms without FIFO, the flow control is 2264 * handled by the driver. 2265 */ 2266 mode |= ATMEL_US_USMODE_NORMAL; 2267 } 2268 } else { 2269 /* RS232 without hadware handshake */ 2270 mode |= ATMEL_US_USMODE_NORMAL; 2271 } 2272 2273 /* 2274 * Set the baud rate: 2275 * Fractional baudrate allows to setup output frequency more 2276 * accurately. This feature is enabled only when using normal mode. 2277 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8)) 2278 * Currently, OVER is always set to 0 so we get 2279 * baudrate = selected clock / (16 * (CD + FP / 8)) 2280 * then 2281 * 8 CD + FP = selected clock / (2 * baudrate) 2282 */ 2283 if (atmel_port->has_frac_baudrate) { 2284 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2); 2285 cd = div >> 3; 2286 fp = div & ATMEL_US_FP_MASK; 2287 } else { 2288 cd = uart_get_divisor(port, baud); 2289 } 2290 2291 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */ 2292 cd /= 8; 2293 mode |= ATMEL_US_USCLKS_MCK_DIV8; 2294 } 2295 quot = cd | fp << ATMEL_US_FP_OFFSET; 2296 2297 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) 2298 atmel_uart_writel(port, ATMEL_US_BRGR, quot); 2299 2300 /* set the mode, clock divisor, parity, stop bits and data size */ 2301 atmel_uart_writel(port, ATMEL_US_MR, mode); 2302 2303 /* 2304 * when switching the mode, set the RTS line state according to the 2305 * new mode, otherwise keep the former state 2306 */ 2307 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) { 2308 unsigned int rts_state; 2309 2310 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) { 2311 /* let the hardware control the RTS line */ 2312 rts_state = ATMEL_US_RTSDIS; 2313 } else { 2314 /* force RTS line to low level */ 2315 rts_state = ATMEL_US_RTSEN; 2316 } 2317 2318 atmel_uart_writel(port, ATMEL_US_CR, rts_state); 2319 } 2320 2321 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 2322 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN); 2323 atmel_port->tx_stopped = false; 2324 2325 /* restore interrupts */ 2326 atmel_uart_writel(port, ATMEL_US_IER, imr); 2327 2328 /* CTS flow-control and modem-status interrupts */ 2329 if (UART_ENABLE_MS(port, termios->c_cflag)) 2330 atmel_enable_ms(port); 2331 else 2332 atmel_disable_ms(port); 2333 2334 spin_unlock_irqrestore(&port->lock, flags); 2335 } 2336 2337 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios) 2338 { 2339 if (termios->c_line == N_PPS) { 2340 port->flags |= UPF_HARDPPS_CD; 2341 spin_lock_irq(&port->lock); 2342 atmel_enable_ms(port); 2343 spin_unlock_irq(&port->lock); 2344 } else { 2345 port->flags &= ~UPF_HARDPPS_CD; 2346 if (!UART_ENABLE_MS(port, termios->c_cflag)) { 2347 spin_lock_irq(&port->lock); 2348 atmel_disable_ms(port); 2349 spin_unlock_irq(&port->lock); 2350 } 2351 } 2352 } 2353 2354 /* 2355 * Return string describing the specified port 2356 */ 2357 static const char *atmel_type(struct uart_port *port) 2358 { 2359 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; 2360 } 2361 2362 /* 2363 * Release the memory region(s) being used by 'port'. 2364 */ 2365 static void atmel_release_port(struct uart_port *port) 2366 { 2367 struct platform_device *mpdev = to_platform_device(port->dev->parent); 2368 int size = resource_size(mpdev->resource); 2369 2370 release_mem_region(port->mapbase, size); 2371 2372 if (port->flags & UPF_IOREMAP) { 2373 iounmap(port->membase); 2374 port->membase = NULL; 2375 } 2376 } 2377 2378 /* 2379 * Request the memory region(s) being used by 'port'. 2380 */ 2381 static int atmel_request_port(struct uart_port *port) 2382 { 2383 struct platform_device *mpdev = to_platform_device(port->dev->parent); 2384 int size = resource_size(mpdev->resource); 2385 2386 if (!request_mem_region(port->mapbase, size, "atmel_serial")) 2387 return -EBUSY; 2388 2389 if (port->flags & UPF_IOREMAP) { 2390 port->membase = ioremap(port->mapbase, size); 2391 if (port->membase == NULL) { 2392 release_mem_region(port->mapbase, size); 2393 return -ENOMEM; 2394 } 2395 } 2396 2397 return 0; 2398 } 2399 2400 /* 2401 * Configure/autoconfigure the port. 2402 */ 2403 static void atmel_config_port(struct uart_port *port, int flags) 2404 { 2405 if (flags & UART_CONFIG_TYPE) { 2406 port->type = PORT_ATMEL; 2407 atmel_request_port(port); 2408 } 2409 } 2410 2411 /* 2412 * Verify the new serial_struct (for TIOCSSERIAL). 2413 */ 2414 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) 2415 { 2416 int ret = 0; 2417 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) 2418 ret = -EINVAL; 2419 if (port->irq != ser->irq) 2420 ret = -EINVAL; 2421 if (ser->io_type != SERIAL_IO_MEM) 2422 ret = -EINVAL; 2423 if (port->uartclk / 16 != ser->baud_base) 2424 ret = -EINVAL; 2425 if (port->mapbase != (unsigned long)ser->iomem_base) 2426 ret = -EINVAL; 2427 if (port->iobase != ser->port) 2428 ret = -EINVAL; 2429 if (ser->hub6 != 0) 2430 ret = -EINVAL; 2431 return ret; 2432 } 2433 2434 #ifdef CONFIG_CONSOLE_POLL 2435 static int atmel_poll_get_char(struct uart_port *port) 2436 { 2437 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY)) 2438 cpu_relax(); 2439 2440 return atmel_uart_read_char(port); 2441 } 2442 2443 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch) 2444 { 2445 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) 2446 cpu_relax(); 2447 2448 atmel_uart_write_char(port, ch); 2449 } 2450 #endif 2451 2452 static const struct uart_ops atmel_pops = { 2453 .tx_empty = atmel_tx_empty, 2454 .set_mctrl = atmel_set_mctrl, 2455 .get_mctrl = atmel_get_mctrl, 2456 .stop_tx = atmel_stop_tx, 2457 .start_tx = atmel_start_tx, 2458 .stop_rx = atmel_stop_rx, 2459 .enable_ms = atmel_enable_ms, 2460 .break_ctl = atmel_break_ctl, 2461 .startup = atmel_startup, 2462 .shutdown = atmel_shutdown, 2463 .flush_buffer = atmel_flush_buffer, 2464 .set_termios = atmel_set_termios, 2465 .set_ldisc = atmel_set_ldisc, 2466 .type = atmel_type, 2467 .release_port = atmel_release_port, 2468 .request_port = atmel_request_port, 2469 .config_port = atmel_config_port, 2470 .verify_port = atmel_verify_port, 2471 .pm = atmel_serial_pm, 2472 #ifdef CONFIG_CONSOLE_POLL 2473 .poll_get_char = atmel_poll_get_char, 2474 .poll_put_char = atmel_poll_put_char, 2475 #endif 2476 }; 2477 2478 /* 2479 * Configure the port from the platform device resource info. 2480 */ 2481 static int atmel_init_port(struct atmel_uart_port *atmel_port, 2482 struct platform_device *pdev) 2483 { 2484 int ret; 2485 struct uart_port *port = &atmel_port->uart; 2486 struct platform_device *mpdev = to_platform_device(pdev->dev.parent); 2487 2488 atmel_init_property(atmel_port, pdev); 2489 atmel_set_ops(port); 2490 2491 uart_get_rs485_mode(&mpdev->dev, &port->rs485); 2492 2493 port->iotype = UPIO_MEM; 2494 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP; 2495 port->ops = &atmel_pops; 2496 port->fifosize = 1; 2497 port->dev = &pdev->dev; 2498 port->mapbase = mpdev->resource[0].start; 2499 port->irq = mpdev->resource[1].start; 2500 port->rs485_config = atmel_config_rs485; 2501 port->iso7816_config = atmel_config_iso7816; 2502 port->membase = NULL; 2503 2504 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring)); 2505 2506 /* for console, the clock could already be configured */ 2507 if (!atmel_port->clk) { 2508 atmel_port->clk = clk_get(&mpdev->dev, "usart"); 2509 if (IS_ERR(atmel_port->clk)) { 2510 ret = PTR_ERR(atmel_port->clk); 2511 atmel_port->clk = NULL; 2512 return ret; 2513 } 2514 ret = clk_prepare_enable(atmel_port->clk); 2515 if (ret) { 2516 clk_put(atmel_port->clk); 2517 atmel_port->clk = NULL; 2518 return ret; 2519 } 2520 port->uartclk = clk_get_rate(atmel_port->clk); 2521 clk_disable_unprepare(atmel_port->clk); 2522 /* only enable clock when USART is in use */ 2523 } 2524 2525 /* 2526 * Use TXEMPTY for interrupt when rs485 or ISO7816 else TXRDY or 2527 * ENDTX|TXBUFE 2528 */ 2529 if (port->rs485.flags & SER_RS485_ENABLED || 2530 port->iso7816.flags & SER_ISO7816_ENABLED) 2531 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; 2532 else if (atmel_use_pdc_tx(port)) { 2533 port->fifosize = PDC_BUFFER_SIZE; 2534 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE; 2535 } else { 2536 atmel_port->tx_done_mask = ATMEL_US_TXRDY; 2537 } 2538 2539 return 0; 2540 } 2541 2542 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE 2543 static void atmel_console_putchar(struct uart_port *port, int ch) 2544 { 2545 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) 2546 cpu_relax(); 2547 atmel_uart_write_char(port, ch); 2548 } 2549 2550 /* 2551 * Interrupts are disabled on entering 2552 */ 2553 static void atmel_console_write(struct console *co, const char *s, u_int count) 2554 { 2555 struct uart_port *port = &atmel_ports[co->index].uart; 2556 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2557 unsigned int status, imr; 2558 unsigned int pdc_tx; 2559 2560 /* 2561 * First, save IMR and then disable interrupts 2562 */ 2563 imr = atmel_uart_readl(port, ATMEL_US_IMR); 2564 atmel_uart_writel(port, ATMEL_US_IDR, 2565 ATMEL_US_RXRDY | atmel_port->tx_done_mask); 2566 2567 /* Store PDC transmit status and disable it */ 2568 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN; 2569 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS); 2570 2571 /* Make sure that tx path is actually able to send characters */ 2572 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN); 2573 atmel_port->tx_stopped = false; 2574 2575 uart_console_write(port, s, count, atmel_console_putchar); 2576 2577 /* 2578 * Finally, wait for transmitter to become empty 2579 * and restore IMR 2580 */ 2581 do { 2582 status = atmel_uart_readl(port, ATMEL_US_CSR); 2583 } while (!(status & ATMEL_US_TXRDY)); 2584 2585 /* Restore PDC transmit status */ 2586 if (pdc_tx) 2587 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); 2588 2589 /* set interrupts back the way they were */ 2590 atmel_uart_writel(port, ATMEL_US_IER, imr); 2591 } 2592 2593 /* 2594 * If the port was already initialised (eg, by a boot loader), 2595 * try to determine the current setup. 2596 */ 2597 static void __init atmel_console_get_options(struct uart_port *port, int *baud, 2598 int *parity, int *bits) 2599 { 2600 unsigned int mr, quot; 2601 2602 /* 2603 * If the baud rate generator isn't running, the port wasn't 2604 * initialized by the boot loader. 2605 */ 2606 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD; 2607 if (!quot) 2608 return; 2609 2610 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL; 2611 if (mr == ATMEL_US_CHRL_8) 2612 *bits = 8; 2613 else 2614 *bits = 7; 2615 2616 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR; 2617 if (mr == ATMEL_US_PAR_EVEN) 2618 *parity = 'e'; 2619 else if (mr == ATMEL_US_PAR_ODD) 2620 *parity = 'o'; 2621 2622 /* 2623 * The serial core only rounds down when matching this to a 2624 * supported baud rate. Make sure we don't end up slightly 2625 * lower than one of those, as it would make us fall through 2626 * to a much lower baud rate than we really want. 2627 */ 2628 *baud = port->uartclk / (16 * (quot - 1)); 2629 } 2630 2631 static int __init atmel_console_setup(struct console *co, char *options) 2632 { 2633 int ret; 2634 struct uart_port *port = &atmel_ports[co->index].uart; 2635 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2636 int baud = 115200; 2637 int bits = 8; 2638 int parity = 'n'; 2639 int flow = 'n'; 2640 2641 if (port->membase == NULL) { 2642 /* Port not initialized yet - delay setup */ 2643 return -ENODEV; 2644 } 2645 2646 ret = clk_prepare_enable(atmel_ports[co->index].clk); 2647 if (ret) 2648 return ret; 2649 2650 atmel_uart_writel(port, ATMEL_US_IDR, -1); 2651 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); 2652 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN); 2653 atmel_port->tx_stopped = false; 2654 2655 if (options) 2656 uart_parse_options(options, &baud, &parity, &bits, &flow); 2657 else 2658 atmel_console_get_options(port, &baud, &parity, &bits); 2659 2660 return uart_set_options(port, co, baud, parity, bits, flow); 2661 } 2662 2663 static struct uart_driver atmel_uart; 2664 2665 static struct console atmel_console = { 2666 .name = ATMEL_DEVICENAME, 2667 .write = atmel_console_write, 2668 .device = uart_console_device, 2669 .setup = atmel_console_setup, 2670 .flags = CON_PRINTBUFFER, 2671 .index = -1, 2672 .data = &atmel_uart, 2673 }; 2674 2675 #define ATMEL_CONSOLE_DEVICE (&atmel_console) 2676 2677 static inline bool atmel_is_console_port(struct uart_port *port) 2678 { 2679 return port->cons && port->cons->index == port->line; 2680 } 2681 2682 #else 2683 #define ATMEL_CONSOLE_DEVICE NULL 2684 2685 static inline bool atmel_is_console_port(struct uart_port *port) 2686 { 2687 return false; 2688 } 2689 #endif 2690 2691 static struct uart_driver atmel_uart = { 2692 .owner = THIS_MODULE, 2693 .driver_name = "atmel_serial", 2694 .dev_name = ATMEL_DEVICENAME, 2695 .major = SERIAL_ATMEL_MAJOR, 2696 .minor = MINOR_START, 2697 .nr = ATMEL_MAX_UART, 2698 .cons = ATMEL_CONSOLE_DEVICE, 2699 }; 2700 2701 #ifdef CONFIG_PM 2702 static bool atmel_serial_clk_will_stop(void) 2703 { 2704 #ifdef CONFIG_ARCH_AT91 2705 return at91_suspend_entering_slow_clock(); 2706 #else 2707 return false; 2708 #endif 2709 } 2710 2711 static int atmel_serial_suspend(struct platform_device *pdev, 2712 pm_message_t state) 2713 { 2714 struct uart_port *port = platform_get_drvdata(pdev); 2715 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2716 2717 if (atmel_is_console_port(port) && console_suspend_enabled) { 2718 /* Drain the TX shifter */ 2719 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & 2720 ATMEL_US_TXEMPTY)) 2721 cpu_relax(); 2722 } 2723 2724 if (atmel_is_console_port(port) && !console_suspend_enabled) { 2725 /* Cache register values as we won't get a full shutdown/startup 2726 * cycle 2727 */ 2728 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR); 2729 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR); 2730 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR); 2731 atmel_port->cache.rtor = atmel_uart_readl(port, 2732 atmel_port->rtor); 2733 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR); 2734 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR); 2735 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR); 2736 } 2737 2738 /* we can not wake up if we're running on slow clock */ 2739 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev); 2740 if (atmel_serial_clk_will_stop()) { 2741 unsigned long flags; 2742 2743 spin_lock_irqsave(&atmel_port->lock_suspended, flags); 2744 atmel_port->suspended = true; 2745 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags); 2746 device_set_wakeup_enable(&pdev->dev, 0); 2747 } 2748 2749 uart_suspend_port(&atmel_uart, port); 2750 2751 return 0; 2752 } 2753 2754 static int atmel_serial_resume(struct platform_device *pdev) 2755 { 2756 struct uart_port *port = platform_get_drvdata(pdev); 2757 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2758 unsigned long flags; 2759 2760 if (atmel_is_console_port(port) && !console_suspend_enabled) { 2761 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr); 2762 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr); 2763 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr); 2764 atmel_uart_writel(port, atmel_port->rtor, 2765 atmel_port->cache.rtor); 2766 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr); 2767 2768 if (atmel_port->fifo_size) { 2769 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN | 2770 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR); 2771 atmel_uart_writel(port, ATMEL_US_FMR, 2772 atmel_port->cache.fmr); 2773 atmel_uart_writel(port, ATMEL_US_FIER, 2774 atmel_port->cache.fimr); 2775 } 2776 atmel_start_rx(port); 2777 } 2778 2779 spin_lock_irqsave(&atmel_port->lock_suspended, flags); 2780 if (atmel_port->pending) { 2781 atmel_handle_receive(port, atmel_port->pending); 2782 atmel_handle_status(port, atmel_port->pending, 2783 atmel_port->pending_status); 2784 atmel_handle_transmit(port, atmel_port->pending); 2785 atmel_port->pending = 0; 2786 } 2787 atmel_port->suspended = false; 2788 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags); 2789 2790 uart_resume_port(&atmel_uart, port); 2791 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup); 2792 2793 return 0; 2794 } 2795 #else 2796 #define atmel_serial_suspend NULL 2797 #define atmel_serial_resume NULL 2798 #endif 2799 2800 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port, 2801 struct platform_device *pdev) 2802 { 2803 atmel_port->fifo_size = 0; 2804 atmel_port->rts_low = 0; 2805 atmel_port->rts_high = 0; 2806 2807 if (of_property_read_u32(pdev->dev.of_node, 2808 "atmel,fifo-size", 2809 &atmel_port->fifo_size)) 2810 return; 2811 2812 if (!atmel_port->fifo_size) 2813 return; 2814 2815 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) { 2816 atmel_port->fifo_size = 0; 2817 dev_err(&pdev->dev, "Invalid FIFO size\n"); 2818 return; 2819 } 2820 2821 /* 2822 * 0 <= rts_low <= rts_high <= fifo_size 2823 * Once their CTS line asserted by the remote peer, some x86 UARTs tend 2824 * to flush their internal TX FIFO, commonly up to 16 data, before 2825 * actually stopping to send new data. So we try to set the RTS High 2826 * Threshold to a reasonably high value respecting this 16 data 2827 * empirical rule when possible. 2828 */ 2829 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1, 2830 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET); 2831 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2, 2832 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET); 2833 2834 dev_info(&pdev->dev, "Using FIFO (%u data)\n", 2835 atmel_port->fifo_size); 2836 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n", 2837 atmel_port->rts_high); 2838 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n", 2839 atmel_port->rts_low); 2840 } 2841 2842 static int atmel_serial_probe(struct platform_device *pdev) 2843 { 2844 struct atmel_uart_port *atmel_port; 2845 struct device_node *np = pdev->dev.parent->of_node; 2846 void *data; 2847 int ret; 2848 bool rs485_enabled; 2849 2850 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1)); 2851 2852 /* 2853 * In device tree there is no node with "atmel,at91rm9200-usart-serial" 2854 * as compatible string. This driver is probed by at91-usart mfd driver 2855 * which is just a wrapper over the atmel_serial driver and 2856 * spi-at91-usart driver. All attributes needed by this driver are 2857 * found in of_node of parent. 2858 */ 2859 pdev->dev.of_node = np; 2860 2861 ret = of_alias_get_id(np, "serial"); 2862 if (ret < 0) 2863 /* port id not found in platform data nor device-tree aliases: 2864 * auto-enumerate it */ 2865 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART); 2866 2867 if (ret >= ATMEL_MAX_UART) { 2868 ret = -ENODEV; 2869 goto err; 2870 } 2871 2872 if (test_and_set_bit(ret, atmel_ports_in_use)) { 2873 /* port already in use */ 2874 ret = -EBUSY; 2875 goto err; 2876 } 2877 2878 atmel_port = &atmel_ports[ret]; 2879 atmel_port->backup_imr = 0; 2880 atmel_port->uart.line = ret; 2881 atmel_serial_probe_fifos(atmel_port, pdev); 2882 2883 atomic_set(&atmel_port->tasklet_shutdown, 0); 2884 spin_lock_init(&atmel_port->lock_suspended); 2885 2886 ret = atmel_init_port(atmel_port, pdev); 2887 if (ret) 2888 goto err_clear_bit; 2889 2890 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0); 2891 if (IS_ERR(atmel_port->gpios)) { 2892 ret = PTR_ERR(atmel_port->gpios); 2893 goto err_clear_bit; 2894 } 2895 2896 if (!atmel_use_pdc_rx(&atmel_port->uart)) { 2897 ret = -ENOMEM; 2898 data = kmalloc_array(ATMEL_SERIAL_RINGSIZE, 2899 sizeof(struct atmel_uart_char), 2900 GFP_KERNEL); 2901 if (!data) 2902 goto err_alloc_ring; 2903 atmel_port->rx_ring.buf = data; 2904 } 2905 2906 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED; 2907 2908 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart); 2909 if (ret) 2910 goto err_add_port; 2911 2912 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE 2913 if (atmel_is_console_port(&atmel_port->uart) 2914 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) { 2915 /* 2916 * The serial core enabled the clock for us, so undo 2917 * the clk_prepare_enable() in atmel_console_setup() 2918 */ 2919 clk_disable_unprepare(atmel_port->clk); 2920 } 2921 #endif 2922 2923 device_init_wakeup(&pdev->dev, 1); 2924 platform_set_drvdata(pdev, atmel_port); 2925 2926 /* 2927 * The peripheral clock has been disabled by atmel_init_port(): 2928 * enable it before accessing I/O registers 2929 */ 2930 clk_prepare_enable(atmel_port->clk); 2931 2932 if (rs485_enabled) { 2933 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR, 2934 ATMEL_US_USMODE_NORMAL); 2935 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR, 2936 ATMEL_US_RTSEN); 2937 } 2938 2939 /* 2940 * Get port name of usart or uart 2941 */ 2942 atmel_get_ip_name(&atmel_port->uart); 2943 2944 /* 2945 * The peripheral clock can now safely be disabled till the port 2946 * is used 2947 */ 2948 clk_disable_unprepare(atmel_port->clk); 2949 2950 return 0; 2951 2952 err_add_port: 2953 kfree(atmel_port->rx_ring.buf); 2954 atmel_port->rx_ring.buf = NULL; 2955 err_alloc_ring: 2956 if (!atmel_is_console_port(&atmel_port->uart)) { 2957 clk_put(atmel_port->clk); 2958 atmel_port->clk = NULL; 2959 } 2960 err_clear_bit: 2961 clear_bit(atmel_port->uart.line, atmel_ports_in_use); 2962 err: 2963 return ret; 2964 } 2965 2966 /* 2967 * Even if the driver is not modular, it makes sense to be able to 2968 * unbind a device: there can be many bound devices, and there are 2969 * situations where dynamic binding and unbinding can be useful. 2970 * 2971 * For example, a connected device can require a specific firmware update 2972 * protocol that needs bitbanging on IO lines, but use the regular serial 2973 * port in the normal case. 2974 */ 2975 static int atmel_serial_remove(struct platform_device *pdev) 2976 { 2977 struct uart_port *port = platform_get_drvdata(pdev); 2978 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); 2979 int ret = 0; 2980 2981 tasklet_kill(&atmel_port->tasklet_rx); 2982 tasklet_kill(&atmel_port->tasklet_tx); 2983 2984 device_init_wakeup(&pdev->dev, 0); 2985 2986 ret = uart_remove_one_port(&atmel_uart, port); 2987 2988 kfree(atmel_port->rx_ring.buf); 2989 2990 /* "port" is allocated statically, so we shouldn't free it */ 2991 2992 clear_bit(port->line, atmel_ports_in_use); 2993 2994 clk_put(atmel_port->clk); 2995 atmel_port->clk = NULL; 2996 pdev->dev.of_node = NULL; 2997 2998 return ret; 2999 } 3000 3001 static struct platform_driver atmel_serial_driver = { 3002 .probe = atmel_serial_probe, 3003 .remove = atmel_serial_remove, 3004 .suspend = atmel_serial_suspend, 3005 .resume = atmel_serial_resume, 3006 .driver = { 3007 .name = "atmel_usart_serial", 3008 .of_match_table = of_match_ptr(atmel_serial_dt_ids), 3009 }, 3010 }; 3011 3012 static int __init atmel_serial_init(void) 3013 { 3014 int ret; 3015 3016 ret = uart_register_driver(&atmel_uart); 3017 if (ret) 3018 return ret; 3019 3020 ret = platform_driver_register(&atmel_serial_driver); 3021 if (ret) 3022 uart_unregister_driver(&atmel_uart); 3023 3024 return ret; 3025 } 3026 device_initcall(atmel_serial_init); 3027