1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Freescale LINFlexD UART serial port driver 4 * 5 * Copyright 2012-2016 Freescale Semiconductor, Inc. 6 * Copyright 2017-2019 NXP 7 */ 8 9 #include <linux/console.h> 10 #include <linux/io.h> 11 #include <linux/irq.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/serial_core.h> 16 #include <linux/slab.h> 17 #include <linux/tty_flip.h> 18 #include <linux/delay.h> 19 20 /* All registers are 32-bit width */ 21 22 #define LINCR1 0x0000 /* LIN control register */ 23 #define LINIER 0x0004 /* LIN interrupt enable register */ 24 #define LINSR 0x0008 /* LIN status register */ 25 #define LINESR 0x000C /* LIN error status register */ 26 #define UARTCR 0x0010 /* UART mode control register */ 27 #define UARTSR 0x0014 /* UART mode status register */ 28 #define LINTCSR 0x0018 /* LIN timeout control status register */ 29 #define LINOCR 0x001C /* LIN output compare register */ 30 #define LINTOCR 0x0020 /* LIN timeout control register */ 31 #define LINFBRR 0x0024 /* LIN fractional baud rate register */ 32 #define LINIBRR 0x0028 /* LIN integer baud rate register */ 33 #define LINCFR 0x002C /* LIN checksum field register */ 34 #define LINCR2 0x0030 /* LIN control register 2 */ 35 #define BIDR 0x0034 /* Buffer identifier register */ 36 #define BDRL 0x0038 /* Buffer data register least significant */ 37 #define BDRM 0x003C /* Buffer data register most significant */ 38 #define IFER 0x0040 /* Identifier filter enable register */ 39 #define IFMI 0x0044 /* Identifier filter match index */ 40 #define IFMR 0x0048 /* Identifier filter mode register */ 41 #define GCR 0x004C /* Global control register */ 42 #define UARTPTO 0x0050 /* UART preset timeout register */ 43 #define UARTCTO 0x0054 /* UART current timeout register */ 44 45 /* 46 * Register field definitions 47 */ 48 49 #define LINFLEXD_LINCR1_INIT BIT(0) 50 #define LINFLEXD_LINCR1_MME BIT(4) 51 #define LINFLEXD_LINCR1_BF BIT(7) 52 53 #define LINFLEXD_LINSR_LINS_INITMODE BIT(12) 54 #define LINFLEXD_LINSR_LINS_MASK (0xF << 12) 55 56 #define LINFLEXD_LINIER_SZIE BIT(15) 57 #define LINFLEXD_LINIER_OCIE BIT(14) 58 #define LINFLEXD_LINIER_BEIE BIT(13) 59 #define LINFLEXD_LINIER_CEIE BIT(12) 60 #define LINFLEXD_LINIER_HEIE BIT(11) 61 #define LINFLEXD_LINIER_FEIE BIT(8) 62 #define LINFLEXD_LINIER_BOIE BIT(7) 63 #define LINFLEXD_LINIER_LSIE BIT(6) 64 #define LINFLEXD_LINIER_WUIE BIT(5) 65 #define LINFLEXD_LINIER_DBFIE BIT(4) 66 #define LINFLEXD_LINIER_DBEIETOIE BIT(3) 67 #define LINFLEXD_LINIER_DRIE BIT(2) 68 #define LINFLEXD_LINIER_DTIE BIT(1) 69 #define LINFLEXD_LINIER_HRIE BIT(0) 70 71 #define LINFLEXD_UARTCR_OSR_MASK (0xF << 24) 72 #define LINFLEXD_UARTCR_OSR(uartcr) (((uartcr) \ 73 & LINFLEXD_UARTCR_OSR_MASK) >> 24) 74 75 #define LINFLEXD_UARTCR_ROSE BIT(23) 76 77 #define LINFLEXD_UARTCR_RFBM BIT(9) 78 #define LINFLEXD_UARTCR_TFBM BIT(8) 79 #define LINFLEXD_UARTCR_WL1 BIT(7) 80 #define LINFLEXD_UARTCR_PC1 BIT(6) 81 82 #define LINFLEXD_UARTCR_RXEN BIT(5) 83 #define LINFLEXD_UARTCR_TXEN BIT(4) 84 #define LINFLEXD_UARTCR_PC0 BIT(3) 85 86 #define LINFLEXD_UARTCR_PCE BIT(2) 87 #define LINFLEXD_UARTCR_WL0 BIT(1) 88 #define LINFLEXD_UARTCR_UART BIT(0) 89 90 #define LINFLEXD_UARTSR_SZF BIT(15) 91 #define LINFLEXD_UARTSR_OCF BIT(14) 92 #define LINFLEXD_UARTSR_PE3 BIT(13) 93 #define LINFLEXD_UARTSR_PE2 BIT(12) 94 #define LINFLEXD_UARTSR_PE1 BIT(11) 95 #define LINFLEXD_UARTSR_PE0 BIT(10) 96 #define LINFLEXD_UARTSR_RMB BIT(9) 97 #define LINFLEXD_UARTSR_FEF BIT(8) 98 #define LINFLEXD_UARTSR_BOF BIT(7) 99 #define LINFLEXD_UARTSR_RPS BIT(6) 100 #define LINFLEXD_UARTSR_WUF BIT(5) 101 #define LINFLEXD_UARTSR_4 BIT(4) 102 103 #define LINFLEXD_UARTSR_TO BIT(3) 104 105 #define LINFLEXD_UARTSR_DRFRFE BIT(2) 106 #define LINFLEXD_UARTSR_DTFTFF BIT(1) 107 #define LINFLEXD_UARTSR_NF BIT(0) 108 #define LINFLEXD_UARTSR_PE (LINFLEXD_UARTSR_PE0 |\ 109 LINFLEXD_UARTSR_PE1 |\ 110 LINFLEXD_UARTSR_PE2 |\ 111 LINFLEXD_UARTSR_PE3) 112 113 #define LINFLEX_LDIV_MULTIPLIER (16) 114 115 #define DRIVER_NAME "fsl-linflexuart" 116 #define DEV_NAME "ttyLF" 117 #define UART_NR 4 118 119 #define EARLYCON_BUFFER_INITIAL_CAP 8 120 121 #define PREINIT_DELAY 2000 /* us */ 122 123 static const struct of_device_id linflex_dt_ids[] = { 124 { 125 .compatible = "fsl,s32v234-linflexuart", 126 }, 127 { /* sentinel */ } 128 }; 129 MODULE_DEVICE_TABLE(of, linflex_dt_ids); 130 131 #ifdef CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE 132 static struct uart_port *earlycon_port; 133 static bool linflex_earlycon_same_instance; 134 static DEFINE_SPINLOCK(init_lock); 135 static bool during_init; 136 137 static struct { 138 char *content; 139 unsigned int len, cap; 140 } earlycon_buf; 141 #endif 142 143 static void linflex_stop_tx(struct uart_port *port) 144 { 145 unsigned long ier; 146 147 ier = readl(port->membase + LINIER); 148 ier &= ~(LINFLEXD_LINIER_DTIE); 149 writel(ier, port->membase + LINIER); 150 } 151 152 static void linflex_stop_rx(struct uart_port *port) 153 { 154 unsigned long ier; 155 156 ier = readl(port->membase + LINIER); 157 writel(ier & ~LINFLEXD_LINIER_DRIE, port->membase + LINIER); 158 } 159 160 static inline void linflex_transmit_buffer(struct uart_port *sport) 161 { 162 struct circ_buf *xmit = &sport->state->xmit; 163 unsigned char c; 164 unsigned long status; 165 166 while (!uart_circ_empty(xmit)) { 167 c = xmit->buf[xmit->tail]; 168 writeb(c, sport->membase + BDRL); 169 170 /* Waiting for data transmission completed. */ 171 while (((status = readl(sport->membase + UARTSR)) & 172 LINFLEXD_UARTSR_DTFTFF) != 173 LINFLEXD_UARTSR_DTFTFF) 174 ; 175 176 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 177 sport->icount.tx++; 178 179 writel(status | LINFLEXD_UARTSR_DTFTFF, 180 sport->membase + UARTSR); 181 } 182 183 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 184 uart_write_wakeup(sport); 185 186 if (uart_circ_empty(xmit)) 187 linflex_stop_tx(sport); 188 } 189 190 static void linflex_start_tx(struct uart_port *port) 191 { 192 unsigned long ier; 193 194 linflex_transmit_buffer(port); 195 ier = readl(port->membase + LINIER); 196 writel(ier | LINFLEXD_LINIER_DTIE, port->membase + LINIER); 197 } 198 199 static irqreturn_t linflex_txint(int irq, void *dev_id) 200 { 201 struct uart_port *sport = dev_id; 202 struct circ_buf *xmit = &sport->state->xmit; 203 unsigned long flags; 204 unsigned long status; 205 206 spin_lock_irqsave(&sport->lock, flags); 207 208 if (sport->x_char) { 209 writeb(sport->x_char, sport->membase + BDRL); 210 211 /* waiting for data transmission completed */ 212 while (((status = readl(sport->membase + UARTSR)) & 213 LINFLEXD_UARTSR_DTFTFF) != LINFLEXD_UARTSR_DTFTFF) 214 ; 215 216 writel(status | LINFLEXD_UARTSR_DTFTFF, 217 sport->membase + UARTSR); 218 219 goto out; 220 } 221 222 if (uart_circ_empty(xmit) || uart_tx_stopped(sport)) { 223 linflex_stop_tx(sport); 224 goto out; 225 } 226 227 linflex_transmit_buffer(sport); 228 229 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 230 uart_write_wakeup(sport); 231 232 out: 233 spin_unlock_irqrestore(&sport->lock, flags); 234 return IRQ_HANDLED; 235 } 236 237 static irqreturn_t linflex_rxint(int irq, void *dev_id) 238 { 239 struct uart_port *sport = dev_id; 240 unsigned int flg; 241 struct tty_port *port = &sport->state->port; 242 unsigned long flags, status; 243 unsigned char rx; 244 bool brk; 245 246 spin_lock_irqsave(&sport->lock, flags); 247 248 status = readl(sport->membase + UARTSR); 249 while (status & LINFLEXD_UARTSR_RMB) { 250 rx = readb(sport->membase + BDRM); 251 brk = false; 252 flg = TTY_NORMAL; 253 sport->icount.rx++; 254 255 if (status & (LINFLEXD_UARTSR_BOF | LINFLEXD_UARTSR_SZF | 256 LINFLEXD_UARTSR_FEF | LINFLEXD_UARTSR_PE)) { 257 if (status & LINFLEXD_UARTSR_SZF) 258 status |= LINFLEXD_UARTSR_SZF; 259 if (status & LINFLEXD_UARTSR_BOF) 260 status |= LINFLEXD_UARTSR_BOF; 261 if (status & LINFLEXD_UARTSR_FEF) { 262 if (!rx) 263 brk = true; 264 status |= LINFLEXD_UARTSR_FEF; 265 } 266 if (status & LINFLEXD_UARTSR_PE) 267 status |= LINFLEXD_UARTSR_PE; 268 } 269 270 writel(status | LINFLEXD_UARTSR_RMB | LINFLEXD_UARTSR_DRFRFE, 271 sport->membase + UARTSR); 272 status = readl(sport->membase + UARTSR); 273 274 if (brk) { 275 uart_handle_break(sport); 276 } else { 277 if (uart_handle_sysrq_char(sport, (unsigned char)rx)) 278 continue; 279 tty_insert_flip_char(port, rx, flg); 280 } 281 } 282 283 spin_unlock_irqrestore(&sport->lock, flags); 284 285 tty_flip_buffer_push(port); 286 287 return IRQ_HANDLED; 288 } 289 290 static irqreturn_t linflex_int(int irq, void *dev_id) 291 { 292 struct uart_port *sport = dev_id; 293 unsigned long status; 294 295 status = readl(sport->membase + UARTSR); 296 297 if (status & LINFLEXD_UARTSR_DRFRFE) 298 linflex_rxint(irq, dev_id); 299 if (status & LINFLEXD_UARTSR_DTFTFF) 300 linflex_txint(irq, dev_id); 301 302 return IRQ_HANDLED; 303 } 304 305 /* return TIOCSER_TEMT when transmitter is not busy */ 306 static unsigned int linflex_tx_empty(struct uart_port *port) 307 { 308 unsigned long status; 309 310 status = readl(port->membase + UARTSR) & LINFLEXD_UARTSR_DTFTFF; 311 312 return status ? TIOCSER_TEMT : 0; 313 } 314 315 static unsigned int linflex_get_mctrl(struct uart_port *port) 316 { 317 return 0; 318 } 319 320 static void linflex_set_mctrl(struct uart_port *port, unsigned int mctrl) 321 { 322 } 323 324 static void linflex_break_ctl(struct uart_port *port, int break_state) 325 { 326 } 327 328 static void linflex_setup_watermark(struct uart_port *sport) 329 { 330 unsigned long cr, ier, cr1; 331 332 /* Disable transmission/reception */ 333 ier = readl(sport->membase + LINIER); 334 ier &= ~(LINFLEXD_LINIER_DRIE | LINFLEXD_LINIER_DTIE); 335 writel(ier, sport->membase + LINIER); 336 337 cr = readl(sport->membase + UARTCR); 338 cr &= ~(LINFLEXD_UARTCR_RXEN | LINFLEXD_UARTCR_TXEN); 339 writel(cr, sport->membase + UARTCR); 340 341 /* Enter initialization mode by setting INIT bit */ 342 343 /* set the Linflex in master mode and activate by-pass filter */ 344 cr1 = LINFLEXD_LINCR1_BF | LINFLEXD_LINCR1_MME 345 | LINFLEXD_LINCR1_INIT; 346 writel(cr1, sport->membase + LINCR1); 347 348 /* wait for init mode entry */ 349 while ((readl(sport->membase + LINSR) 350 & LINFLEXD_LINSR_LINS_MASK) 351 != LINFLEXD_LINSR_LINS_INITMODE) 352 ; 353 354 /* 355 * UART = 0x1; - Linflex working in UART mode 356 * TXEN = 0x1; - Enable transmission of data now 357 * RXEn = 0x1; - Receiver enabled 358 * WL0 = 0x1; - 8 bit data 359 * PCE = 0x0; - No parity 360 */ 361 362 /* set UART bit to allow writing other bits */ 363 writel(LINFLEXD_UARTCR_UART, sport->membase + UARTCR); 364 365 cr = (LINFLEXD_UARTCR_RXEN | LINFLEXD_UARTCR_TXEN | 366 LINFLEXD_UARTCR_WL0 | LINFLEXD_UARTCR_UART); 367 368 writel(cr, sport->membase + UARTCR); 369 370 cr1 &= ~(LINFLEXD_LINCR1_INIT); 371 372 writel(cr1, sport->membase + LINCR1); 373 374 ier = readl(sport->membase + LINIER); 375 ier |= LINFLEXD_LINIER_DRIE; 376 ier |= LINFLEXD_LINIER_DTIE; 377 378 writel(ier, sport->membase + LINIER); 379 } 380 381 static int linflex_startup(struct uart_port *port) 382 { 383 int ret = 0; 384 unsigned long flags; 385 386 spin_lock_irqsave(&port->lock, flags); 387 388 linflex_setup_watermark(port); 389 390 spin_unlock_irqrestore(&port->lock, flags); 391 392 ret = devm_request_irq(port->dev, port->irq, linflex_int, 0, 393 DRIVER_NAME, port); 394 395 return ret; 396 } 397 398 static void linflex_shutdown(struct uart_port *port) 399 { 400 unsigned long ier; 401 unsigned long flags; 402 403 spin_lock_irqsave(&port->lock, flags); 404 405 /* disable interrupts */ 406 ier = readl(port->membase + LINIER); 407 ier &= ~(LINFLEXD_LINIER_DRIE | LINFLEXD_LINIER_DTIE); 408 writel(ier, port->membase + LINIER); 409 410 spin_unlock_irqrestore(&port->lock, flags); 411 412 devm_free_irq(port->dev, port->irq, port); 413 } 414 415 static void 416 linflex_set_termios(struct uart_port *port, struct ktermios *termios, 417 struct ktermios *old) 418 { 419 unsigned long flags; 420 unsigned long cr, old_cr, cr1; 421 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 422 423 cr = readl(port->membase + UARTCR); 424 old_cr = cr; 425 426 /* Enter initialization mode by setting INIT bit */ 427 cr1 = readl(port->membase + LINCR1); 428 cr1 |= LINFLEXD_LINCR1_INIT; 429 writel(cr1, port->membase + LINCR1); 430 431 /* wait for init mode entry */ 432 while ((readl(port->membase + LINSR) 433 & LINFLEXD_LINSR_LINS_MASK) 434 != LINFLEXD_LINSR_LINS_INITMODE) 435 ; 436 437 /* 438 * only support CS8 and CS7, and for CS7 must enable PE. 439 * supported mode: 440 * - (7,e/o,1) 441 * - (8,n,1) 442 * - (8,e/o,1) 443 */ 444 /* enter the UART into configuration mode */ 445 446 while ((termios->c_cflag & CSIZE) != CS8 && 447 (termios->c_cflag & CSIZE) != CS7) { 448 termios->c_cflag &= ~CSIZE; 449 termios->c_cflag |= old_csize; 450 old_csize = CS8; 451 } 452 453 if ((termios->c_cflag & CSIZE) == CS7) { 454 /* Word length: WL1WL0:00 */ 455 cr = old_cr & ~LINFLEXD_UARTCR_WL1 & ~LINFLEXD_UARTCR_WL0; 456 } 457 458 if ((termios->c_cflag & CSIZE) == CS8) { 459 /* Word length: WL1WL0:01 */ 460 cr = (old_cr | LINFLEXD_UARTCR_WL0) & ~LINFLEXD_UARTCR_WL1; 461 } 462 463 if (termios->c_cflag & CMSPAR) { 464 if ((termios->c_cflag & CSIZE) != CS8) { 465 termios->c_cflag &= ~CSIZE; 466 termios->c_cflag |= CS8; 467 } 468 /* has a space/sticky bit */ 469 cr |= LINFLEXD_UARTCR_WL0; 470 } 471 472 if (termios->c_cflag & CSTOPB) 473 termios->c_cflag &= ~CSTOPB; 474 475 /* parity must be enabled when CS7 to match 8-bits format */ 476 if ((termios->c_cflag & CSIZE) == CS7) 477 termios->c_cflag |= PARENB; 478 479 if ((termios->c_cflag & PARENB)) { 480 cr |= LINFLEXD_UARTCR_PCE; 481 if (termios->c_cflag & PARODD) 482 cr = (cr | LINFLEXD_UARTCR_PC0) & 483 (~LINFLEXD_UARTCR_PC1); 484 else 485 cr = cr & (~LINFLEXD_UARTCR_PC1 & 486 ~LINFLEXD_UARTCR_PC0); 487 } else { 488 cr &= ~LINFLEXD_UARTCR_PCE; 489 } 490 491 spin_lock_irqsave(&port->lock, flags); 492 493 port->read_status_mask = 0; 494 495 if (termios->c_iflag & INPCK) 496 port->read_status_mask |= (LINFLEXD_UARTSR_FEF | 497 LINFLEXD_UARTSR_PE0 | 498 LINFLEXD_UARTSR_PE1 | 499 LINFLEXD_UARTSR_PE2 | 500 LINFLEXD_UARTSR_PE3); 501 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 502 port->read_status_mask |= LINFLEXD_UARTSR_FEF; 503 504 /* characters to ignore */ 505 port->ignore_status_mask = 0; 506 if (termios->c_iflag & IGNPAR) 507 port->ignore_status_mask |= LINFLEXD_UARTSR_PE; 508 if (termios->c_iflag & IGNBRK) { 509 port->ignore_status_mask |= LINFLEXD_UARTSR_PE; 510 /* 511 * if we're ignoring parity and break indicators, 512 * ignore overruns too (for real raw support). 513 */ 514 if (termios->c_iflag & IGNPAR) 515 port->ignore_status_mask |= LINFLEXD_UARTSR_BOF; 516 } 517 518 writel(cr, port->membase + UARTCR); 519 520 cr1 &= ~(LINFLEXD_LINCR1_INIT); 521 522 writel(cr1, port->membase + LINCR1); 523 524 spin_unlock_irqrestore(&port->lock, flags); 525 } 526 527 static const char *linflex_type(struct uart_port *port) 528 { 529 return "FSL_LINFLEX"; 530 } 531 532 static void linflex_release_port(struct uart_port *port) 533 { 534 /* nothing to do */ 535 } 536 537 static int linflex_request_port(struct uart_port *port) 538 { 539 return 0; 540 } 541 542 /* configure/auto-configure the port */ 543 static void linflex_config_port(struct uart_port *port, int flags) 544 { 545 if (flags & UART_CONFIG_TYPE) 546 port->type = PORT_LINFLEXUART; 547 } 548 549 static const struct uart_ops linflex_pops = { 550 .tx_empty = linflex_tx_empty, 551 .set_mctrl = linflex_set_mctrl, 552 .get_mctrl = linflex_get_mctrl, 553 .stop_tx = linflex_stop_tx, 554 .start_tx = linflex_start_tx, 555 .stop_rx = linflex_stop_rx, 556 .break_ctl = linflex_break_ctl, 557 .startup = linflex_startup, 558 .shutdown = linflex_shutdown, 559 .set_termios = linflex_set_termios, 560 .type = linflex_type, 561 .request_port = linflex_request_port, 562 .release_port = linflex_release_port, 563 .config_port = linflex_config_port, 564 }; 565 566 static struct uart_port *linflex_ports[UART_NR]; 567 568 #ifdef CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE 569 static void linflex_console_putchar(struct uart_port *port, int ch) 570 { 571 unsigned long cr; 572 573 cr = readl(port->membase + UARTCR); 574 575 writeb(ch, port->membase + BDRL); 576 577 if (!(cr & LINFLEXD_UARTCR_TFBM)) 578 while ((readl(port->membase + UARTSR) & 579 LINFLEXD_UARTSR_DTFTFF) 580 != LINFLEXD_UARTSR_DTFTFF) 581 ; 582 else 583 while (readl(port->membase + UARTSR) & 584 LINFLEXD_UARTSR_DTFTFF) 585 ; 586 587 if (!(cr & LINFLEXD_UARTCR_TFBM)) { 588 writel((readl(port->membase + UARTSR) | 589 LINFLEXD_UARTSR_DTFTFF), 590 port->membase + UARTSR); 591 } 592 } 593 594 static void linflex_earlycon_putchar(struct uart_port *port, int ch) 595 { 596 unsigned long flags; 597 char *ret; 598 599 if (!linflex_earlycon_same_instance) { 600 linflex_console_putchar(port, ch); 601 return; 602 } 603 604 spin_lock_irqsave(&init_lock, flags); 605 if (!during_init) 606 goto outside_init; 607 608 if (earlycon_buf.len >= 1 << CONFIG_LOG_BUF_SHIFT) 609 goto init_release; 610 611 if (!earlycon_buf.cap) { 612 earlycon_buf.content = kmalloc(EARLYCON_BUFFER_INITIAL_CAP, 613 GFP_ATOMIC); 614 earlycon_buf.cap = earlycon_buf.content ? 615 EARLYCON_BUFFER_INITIAL_CAP : 0; 616 } else if (earlycon_buf.len == earlycon_buf.cap) { 617 ret = krealloc(earlycon_buf.content, earlycon_buf.cap << 1, 618 GFP_ATOMIC); 619 if (ret) { 620 earlycon_buf.content = ret; 621 earlycon_buf.cap <<= 1; 622 } 623 } 624 625 if (earlycon_buf.len < earlycon_buf.cap) 626 earlycon_buf.content[earlycon_buf.len++] = ch; 627 628 goto init_release; 629 630 outside_init: 631 linflex_console_putchar(port, ch); 632 init_release: 633 spin_unlock_irqrestore(&init_lock, flags); 634 } 635 636 static void linflex_string_write(struct uart_port *sport, const char *s, 637 unsigned int count) 638 { 639 unsigned long cr, ier = 0; 640 641 ier = readl(sport->membase + LINIER); 642 linflex_stop_tx(sport); 643 644 cr = readl(sport->membase + UARTCR); 645 cr |= (LINFLEXD_UARTCR_TXEN); 646 writel(cr, sport->membase + UARTCR); 647 648 uart_console_write(sport, s, count, linflex_console_putchar); 649 650 writel(ier, sport->membase + LINIER); 651 } 652 653 static void 654 linflex_console_write(struct console *co, const char *s, unsigned int count) 655 { 656 struct uart_port *sport = linflex_ports[co->index]; 657 unsigned long flags; 658 int locked = 1; 659 660 if (sport->sysrq) 661 locked = 0; 662 else if (oops_in_progress) 663 locked = spin_trylock_irqsave(&sport->lock, flags); 664 else 665 spin_lock_irqsave(&sport->lock, flags); 666 667 linflex_string_write(sport, s, count); 668 669 if (locked) 670 spin_unlock_irqrestore(&sport->lock, flags); 671 } 672 673 /* 674 * if the port was already initialised (eg, by a boot loader), 675 * try to determine the current setup. 676 */ 677 static void __init 678 linflex_console_get_options(struct uart_port *sport, int *parity, int *bits) 679 { 680 unsigned long cr; 681 682 cr = readl(sport->membase + UARTCR); 683 cr &= LINFLEXD_UARTCR_RXEN | LINFLEXD_UARTCR_TXEN; 684 685 if (!cr) 686 return; 687 688 /* ok, the port was enabled */ 689 690 *parity = 'n'; 691 if (cr & LINFLEXD_UARTCR_PCE) { 692 if (cr & LINFLEXD_UARTCR_PC0) 693 *parity = 'o'; 694 else 695 *parity = 'e'; 696 } 697 698 if ((cr & LINFLEXD_UARTCR_WL0) && ((cr & LINFLEXD_UARTCR_WL1) == 0)) { 699 if (cr & LINFLEXD_UARTCR_PCE) 700 *bits = 9; 701 else 702 *bits = 8; 703 } 704 } 705 706 static int __init linflex_console_setup(struct console *co, char *options) 707 { 708 struct uart_port *sport; 709 int baud = 115200; 710 int bits = 8; 711 int parity = 'n'; 712 int flow = 'n'; 713 int ret; 714 int i; 715 unsigned long flags; 716 /* 717 * check whether an invalid uart number has been specified, and 718 * if so, search for the first available port that does have 719 * console support. 720 */ 721 if (co->index == -1 || co->index >= ARRAY_SIZE(linflex_ports)) 722 co->index = 0; 723 724 sport = linflex_ports[co->index]; 725 if (!sport) 726 return -ENODEV; 727 728 if (options) 729 uart_parse_options(options, &baud, &parity, &bits, &flow); 730 else 731 linflex_console_get_options(sport, &parity, &bits); 732 733 if (earlycon_port && sport->mapbase == earlycon_port->mapbase) { 734 linflex_earlycon_same_instance = true; 735 736 spin_lock_irqsave(&init_lock, flags); 737 during_init = true; 738 spin_unlock_irqrestore(&init_lock, flags); 739 740 /* Workaround for character loss or output of many invalid 741 * characters, when INIT mode is entered shortly after a 742 * character has just been printed. 743 */ 744 udelay(PREINIT_DELAY); 745 } 746 747 linflex_setup_watermark(sport); 748 749 ret = uart_set_options(sport, co, baud, parity, bits, flow); 750 751 if (!linflex_earlycon_same_instance) 752 goto done; 753 754 spin_lock_irqsave(&init_lock, flags); 755 756 /* Emptying buffer */ 757 if (earlycon_buf.len) { 758 for (i = 0; i < earlycon_buf.len; i++) 759 linflex_console_putchar(earlycon_port, 760 earlycon_buf.content[i]); 761 762 kfree(earlycon_buf.content); 763 earlycon_buf.len = 0; 764 } 765 766 during_init = false; 767 spin_unlock_irqrestore(&init_lock, flags); 768 769 done: 770 return ret; 771 } 772 773 static struct uart_driver linflex_reg; 774 static struct console linflex_console = { 775 .name = DEV_NAME, 776 .write = linflex_console_write, 777 .device = uart_console_device, 778 .setup = linflex_console_setup, 779 .flags = CON_PRINTBUFFER, 780 .index = -1, 781 .data = &linflex_reg, 782 }; 783 784 static void linflex_earlycon_write(struct console *con, const char *s, 785 unsigned int n) 786 { 787 struct earlycon_device *dev = con->data; 788 789 uart_console_write(&dev->port, s, n, linflex_earlycon_putchar); 790 } 791 792 static int __init linflex_early_console_setup(struct earlycon_device *device, 793 const char *options) 794 { 795 if (!device->port.membase) 796 return -ENODEV; 797 798 device->con->write = linflex_earlycon_write; 799 earlycon_port = &device->port; 800 801 return 0; 802 } 803 804 OF_EARLYCON_DECLARE(linflex, "fsl,s32v234-linflexuart", 805 linflex_early_console_setup); 806 807 #define LINFLEX_CONSOLE (&linflex_console) 808 #else 809 #define LINFLEX_CONSOLE NULL 810 #endif 811 812 static struct uart_driver linflex_reg = { 813 .owner = THIS_MODULE, 814 .driver_name = DRIVER_NAME, 815 .dev_name = DEV_NAME, 816 .nr = ARRAY_SIZE(linflex_ports), 817 .cons = LINFLEX_CONSOLE, 818 }; 819 820 static int linflex_probe(struct platform_device *pdev) 821 { 822 struct device_node *np = pdev->dev.of_node; 823 struct uart_port *sport; 824 struct resource *res; 825 int ret; 826 827 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 828 if (!sport) 829 return -ENOMEM; 830 831 ret = of_alias_get_id(np, "serial"); 832 if (ret < 0) { 833 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 834 return ret; 835 } 836 if (ret >= UART_NR) { 837 dev_err(&pdev->dev, "driver limited to %d serial ports\n", 838 UART_NR); 839 return -ENOMEM; 840 } 841 842 sport->line = ret; 843 844 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 845 if (!res) 846 return -ENODEV; 847 848 sport->mapbase = res->start; 849 sport->membase = devm_ioremap_resource(&pdev->dev, res); 850 if (IS_ERR(sport->membase)) 851 return PTR_ERR(sport->membase); 852 853 sport->dev = &pdev->dev; 854 sport->type = PORT_LINFLEXUART; 855 sport->iotype = UPIO_MEM; 856 sport->irq = platform_get_irq(pdev, 0); 857 sport->ops = &linflex_pops; 858 sport->flags = UPF_BOOT_AUTOCONF; 859 sport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE); 860 861 linflex_ports[sport->line] = sport; 862 863 platform_set_drvdata(pdev, sport); 864 865 ret = uart_add_one_port(&linflex_reg, sport); 866 if (ret) 867 return ret; 868 869 return 0; 870 } 871 872 static int linflex_remove(struct platform_device *pdev) 873 { 874 struct uart_port *sport = platform_get_drvdata(pdev); 875 876 uart_remove_one_port(&linflex_reg, sport); 877 878 return 0; 879 } 880 881 #ifdef CONFIG_PM_SLEEP 882 static int linflex_suspend(struct device *dev) 883 { 884 struct uart_port *sport = dev_get_drvdata(dev); 885 886 uart_suspend_port(&linflex_reg, sport); 887 888 return 0; 889 } 890 891 static int linflex_resume(struct device *dev) 892 { 893 struct uart_port *sport = dev_get_drvdata(dev); 894 895 uart_resume_port(&linflex_reg, sport); 896 897 return 0; 898 } 899 #endif 900 901 static SIMPLE_DEV_PM_OPS(linflex_pm_ops, linflex_suspend, linflex_resume); 902 903 static struct platform_driver linflex_driver = { 904 .probe = linflex_probe, 905 .remove = linflex_remove, 906 .driver = { 907 .name = DRIVER_NAME, 908 .of_match_table = linflex_dt_ids, 909 .pm = &linflex_pm_ops, 910 }, 911 }; 912 913 static int __init linflex_serial_init(void) 914 { 915 int ret; 916 917 ret = uart_register_driver(&linflex_reg); 918 if (ret) 919 return ret; 920 921 ret = platform_driver_register(&linflex_driver); 922 if (ret) 923 uart_unregister_driver(&linflex_reg); 924 925 return ret; 926 } 927 928 static void __exit linflex_serial_exit(void) 929 { 930 platform_driver_unregister(&linflex_driver); 931 uart_unregister_driver(&linflex_reg); 932 } 933 934 module_init(linflex_serial_init); 935 module_exit(linflex_serial_exit); 936 937 MODULE_DESCRIPTION("Freescale LINFlexD serial port driver"); 938 MODULE_LICENSE("GPL v2"); 939