1 // SPDX-License-Identifier: GPL-2.0+ 2 /************************************************************************ 3 * Copyright 2003 Digi International (www.digi.com) 4 * 5 * Copyright (C) 2004 IBM Corporation. All rights reserved. 6 * 7 * Contact Information: 8 * Scott H Kilau <Scott_Kilau@digi.com> 9 * Wendy Xiong <wendyx@us.ibm.com> 10 * 11 ***********************************************************************/ 12 #include <linux/delay.h> /* For udelay */ 13 #include <linux/serial_reg.h> /* For the various UART offsets */ 14 #include <linux/tty.h> 15 #include <linux/pci.h> 16 #include <asm/io.h> 17 18 #include "jsm.h" /* Driver main header file */ 19 20 static u32 jsm_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }; 21 22 /* 23 * This function allows calls to ensure that all outstanding 24 * PCI writes have been completed, by doing a PCI read against 25 * a non-destructive, read-only location on the Neo card. 26 * 27 * In this case, we are reading the DVID (Read-only Device Identification) 28 * value of the Neo card. 29 */ 30 static inline void neo_pci_posting_flush(struct jsm_board *bd) 31 { 32 readb(bd->re_map_membase + 0x8D); 33 } 34 35 static void neo_set_cts_flow_control(struct jsm_channel *ch) 36 { 37 u8 ier, efr; 38 ier = readb(&ch->ch_neo_uart->ier); 39 efr = readb(&ch->ch_neo_uart->efr); 40 41 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n"); 42 43 /* Turn on auto CTS flow control */ 44 ier |= (UART_17158_IER_CTSDSR); 45 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR); 46 47 /* Turn off auto Xon flow control */ 48 efr &= ~(UART_17158_EFR_IXON); 49 50 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 51 writeb(0, &ch->ch_neo_uart->efr); 52 53 /* Turn on UART enhanced bits */ 54 writeb(efr, &ch->ch_neo_uart->efr); 55 56 /* Turn on table D, with 8 char hi/low watermarks */ 57 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); 58 59 /* Feed the UART our trigger levels */ 60 writeb(8, &ch->ch_neo_uart->tfifo); 61 ch->ch_t_tlevel = 8; 62 63 writeb(ier, &ch->ch_neo_uart->ier); 64 } 65 66 static void neo_set_rts_flow_control(struct jsm_channel *ch) 67 { 68 u8 ier, efr; 69 ier = readb(&ch->ch_neo_uart->ier); 70 efr = readb(&ch->ch_neo_uart->efr); 71 72 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n"); 73 74 /* Turn on auto RTS flow control */ 75 ier |= (UART_17158_IER_RTSDTR); 76 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR); 77 78 /* Turn off auto Xoff flow control */ 79 ier &= ~(UART_17158_IER_XOFF); 80 efr &= ~(UART_17158_EFR_IXOFF); 81 82 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 83 writeb(0, &ch->ch_neo_uart->efr); 84 85 /* Turn on UART enhanced bits */ 86 writeb(efr, &ch->ch_neo_uart->efr); 87 88 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); 89 ch->ch_r_watermark = 4; 90 91 writeb(56, &ch->ch_neo_uart->rfifo); 92 ch->ch_r_tlevel = 56; 93 94 writeb(ier, &ch->ch_neo_uart->ier); 95 96 /* 97 * From the Neo UART spec sheet: 98 * The auto RTS/DTR function must be started by asserting 99 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after 100 * it is enabled. 101 */ 102 ch->ch_mostat |= (UART_MCR_RTS); 103 } 104 105 106 static void neo_set_ixon_flow_control(struct jsm_channel *ch) 107 { 108 u8 ier, efr; 109 ier = readb(&ch->ch_neo_uart->ier); 110 efr = readb(&ch->ch_neo_uart->efr); 111 112 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n"); 113 114 /* Turn off auto CTS flow control */ 115 ier &= ~(UART_17158_IER_CTSDSR); 116 efr &= ~(UART_17158_EFR_CTSDSR); 117 118 /* Turn on auto Xon flow control */ 119 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON); 120 121 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 122 writeb(0, &ch->ch_neo_uart->efr); 123 124 /* Turn on UART enhanced bits */ 125 writeb(efr, &ch->ch_neo_uart->efr); 126 127 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 128 ch->ch_r_watermark = 4; 129 130 writeb(32, &ch->ch_neo_uart->rfifo); 131 ch->ch_r_tlevel = 32; 132 133 /* Tell UART what start/stop chars it should be looking for */ 134 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 135 writeb(0, &ch->ch_neo_uart->xonchar2); 136 137 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 138 writeb(0, &ch->ch_neo_uart->xoffchar2); 139 140 writeb(ier, &ch->ch_neo_uart->ier); 141 } 142 143 static void neo_set_ixoff_flow_control(struct jsm_channel *ch) 144 { 145 u8 ier, efr; 146 ier = readb(&ch->ch_neo_uart->ier); 147 efr = readb(&ch->ch_neo_uart->efr); 148 149 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n"); 150 151 /* Turn off auto RTS flow control */ 152 ier &= ~(UART_17158_IER_RTSDTR); 153 efr &= ~(UART_17158_EFR_RTSDTR); 154 155 /* Turn on auto Xoff flow control */ 156 ier |= (UART_17158_IER_XOFF); 157 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF); 158 159 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 160 writeb(0, &ch->ch_neo_uart->efr); 161 162 /* Turn on UART enhanced bits */ 163 writeb(efr, &ch->ch_neo_uart->efr); 164 165 /* Turn on table D, with 8 char hi/low watermarks */ 166 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 167 168 writeb(8, &ch->ch_neo_uart->tfifo); 169 ch->ch_t_tlevel = 8; 170 171 /* Tell UART what start/stop chars it should be looking for */ 172 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 173 writeb(0, &ch->ch_neo_uart->xonchar2); 174 175 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 176 writeb(0, &ch->ch_neo_uart->xoffchar2); 177 178 writeb(ier, &ch->ch_neo_uart->ier); 179 } 180 181 static void neo_set_no_input_flow_control(struct jsm_channel *ch) 182 { 183 u8 ier, efr; 184 ier = readb(&ch->ch_neo_uart->ier); 185 efr = readb(&ch->ch_neo_uart->efr); 186 187 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n"); 188 189 /* Turn off auto RTS flow control */ 190 ier &= ~(UART_17158_IER_RTSDTR); 191 efr &= ~(UART_17158_EFR_RTSDTR); 192 193 /* Turn off auto Xoff flow control */ 194 ier &= ~(UART_17158_IER_XOFF); 195 if (ch->ch_c_iflag & IXON) 196 efr &= ~(UART_17158_EFR_IXOFF); 197 else 198 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF); 199 200 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 201 writeb(0, &ch->ch_neo_uart->efr); 202 203 /* Turn on UART enhanced bits */ 204 writeb(efr, &ch->ch_neo_uart->efr); 205 206 /* Turn on table D, with 8 char hi/low watermarks */ 207 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 208 209 ch->ch_r_watermark = 0; 210 211 writeb(16, &ch->ch_neo_uart->tfifo); 212 ch->ch_t_tlevel = 16; 213 214 writeb(16, &ch->ch_neo_uart->rfifo); 215 ch->ch_r_tlevel = 16; 216 217 writeb(ier, &ch->ch_neo_uart->ier); 218 } 219 220 static void neo_set_no_output_flow_control(struct jsm_channel *ch) 221 { 222 u8 ier, efr; 223 ier = readb(&ch->ch_neo_uart->ier); 224 efr = readb(&ch->ch_neo_uart->efr); 225 226 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n"); 227 228 /* Turn off auto CTS flow control */ 229 ier &= ~(UART_17158_IER_CTSDSR); 230 efr &= ~(UART_17158_EFR_CTSDSR); 231 232 /* Turn off auto Xon flow control */ 233 if (ch->ch_c_iflag & IXOFF) 234 efr &= ~(UART_17158_EFR_IXON); 235 else 236 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON); 237 238 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 239 writeb(0, &ch->ch_neo_uart->efr); 240 241 /* Turn on UART enhanced bits */ 242 writeb(efr, &ch->ch_neo_uart->efr); 243 244 /* Turn on table D, with 8 char hi/low watermarks */ 245 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 246 247 ch->ch_r_watermark = 0; 248 249 writeb(16, &ch->ch_neo_uart->tfifo); 250 ch->ch_t_tlevel = 16; 251 252 writeb(16, &ch->ch_neo_uart->rfifo); 253 ch->ch_r_tlevel = 16; 254 255 writeb(ier, &ch->ch_neo_uart->ier); 256 } 257 258 static inline void neo_set_new_start_stop_chars(struct jsm_channel *ch) 259 { 260 261 /* if hardware flow control is set, then skip this whole thing */ 262 if (ch->ch_c_cflag & CRTSCTS) 263 return; 264 265 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "start\n"); 266 267 /* Tell UART what start/stop chars it should be looking for */ 268 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 269 writeb(0, &ch->ch_neo_uart->xonchar2); 270 271 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 272 writeb(0, &ch->ch_neo_uart->xoffchar2); 273 } 274 275 static void neo_copy_data_from_uart_to_queue(struct jsm_channel *ch) 276 { 277 int qleft = 0; 278 u8 linestatus = 0; 279 u8 error_mask = 0; 280 int n = 0; 281 int total = 0; 282 u16 head; 283 u16 tail; 284 285 if (!ch) 286 return; 287 288 /* cache head and tail of queue */ 289 head = ch->ch_r_head & RQUEUEMASK; 290 tail = ch->ch_r_tail & RQUEUEMASK; 291 292 /* Get our cached LSR */ 293 linestatus = ch->ch_cached_lsr; 294 ch->ch_cached_lsr = 0; 295 296 /* Store how much space we have left in the queue */ 297 if ((qleft = tail - head - 1) < 0) 298 qleft += RQUEUEMASK + 1; 299 300 /* 301 * If the UART is not in FIFO mode, force the FIFO copy to 302 * NOT be run, by setting total to 0. 303 * 304 * On the other hand, if the UART IS in FIFO mode, then ask 305 * the UART to give us an approximation of data it has RX'ed. 306 */ 307 if (!(ch->ch_flags & CH_FIFO_ENABLED)) 308 total = 0; 309 else { 310 total = readb(&ch->ch_neo_uart->rfifo); 311 312 /* 313 * EXAR chip bug - RX FIFO COUNT - Fudge factor. 314 * 315 * This resolves a problem/bug with the Exar chip that sometimes 316 * returns a bogus value in the rfifo register. 317 * The count can be any where from 0-3 bytes "off". 318 * Bizarre, but true. 319 */ 320 total -= 3; 321 } 322 323 /* 324 * Finally, bound the copy to make sure we don't overflow 325 * our own queue... 326 * The byte by byte copy loop below this loop this will 327 * deal with the queue overflow possibility. 328 */ 329 total = min(total, qleft); 330 331 while (total > 0) { 332 /* 333 * Grab the linestatus register, we need to check 334 * to see if there are any errors in the FIFO. 335 */ 336 linestatus = readb(&ch->ch_neo_uart->lsr); 337 338 /* 339 * Break out if there is a FIFO error somewhere. 340 * This will allow us to go byte by byte down below, 341 * finding the exact location of the error. 342 */ 343 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR) 344 break; 345 346 /* Make sure we don't go over the end of our queue */ 347 n = min(((u32) total), (RQUEUESIZE - (u32) head)); 348 349 /* 350 * Cut down n even further if needed, this is to fix 351 * a problem with memcpy_fromio() with the Neo on the 352 * IBM pSeries platform. 353 * 15 bytes max appears to be the magic number. 354 */ 355 n = min((u32) n, (u32) 12); 356 357 /* 358 * Since we are grabbing the linestatus register, which 359 * will reset some bits after our read, we need to ensure 360 * we don't miss our TX FIFO emptys. 361 */ 362 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) 363 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 364 365 linestatus = 0; 366 367 /* Copy data from uart to the queue */ 368 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n); 369 /* 370 * Since RX_FIFO_DATA_ERROR was 0, we are guaranteed 371 * that all the data currently in the FIFO is free of 372 * breaks and parity/frame/orun errors. 373 */ 374 memset(ch->ch_equeue + head, 0, n); 375 376 /* Add to and flip head if needed */ 377 head = (head + n) & RQUEUEMASK; 378 total -= n; 379 qleft -= n; 380 ch->ch_rxcount += n; 381 } 382 383 /* 384 * Create a mask to determine whether we should 385 * insert the character (if any) into our queue. 386 */ 387 if (ch->ch_c_iflag & IGNBRK) 388 error_mask |= UART_LSR_BI; 389 390 /* 391 * Now cleanup any leftover bytes still in the UART. 392 * Also deal with any possible queue overflow here as well. 393 */ 394 while (1) { 395 396 /* 397 * Its possible we have a linestatus from the loop above 398 * this, so we "OR" on any extra bits. 399 */ 400 linestatus |= readb(&ch->ch_neo_uart->lsr); 401 402 /* 403 * If the chip tells us there is no more data pending to 404 * be read, we can then leave. 405 * But before we do, cache the linestatus, just in case. 406 */ 407 if (!(linestatus & UART_LSR_DR)) { 408 ch->ch_cached_lsr = linestatus; 409 break; 410 } 411 412 /* No need to store this bit */ 413 linestatus &= ~UART_LSR_DR; 414 415 /* 416 * Since we are grabbing the linestatus register, which 417 * will reset some bits after our read, we need to ensure 418 * we don't miss our TX FIFO emptys. 419 */ 420 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) { 421 linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR); 422 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 423 } 424 425 /* 426 * Discard character if we are ignoring the error mask. 427 */ 428 if (linestatus & error_mask) { 429 u8 discard; 430 linestatus = 0; 431 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1); 432 continue; 433 } 434 435 /* 436 * If our queue is full, we have no choice but to drop some data. 437 * The assumption is that HWFLOW or SWFLOW should have stopped 438 * things way way before we got to this point. 439 * 440 * I decided that I wanted to ditch the oldest data first, 441 * I hope thats okay with everyone? Yes? Good. 442 */ 443 while (qleft < 1) { 444 jsm_dbg(READ, &ch->ch_bd->pci_dev, 445 "Queue full, dropping DATA:%x LSR:%x\n", 446 ch->ch_rqueue[tail], ch->ch_equeue[tail]); 447 448 ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK; 449 ch->ch_err_overrun++; 450 qleft++; 451 } 452 453 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1); 454 ch->ch_equeue[head] = (u8) linestatus; 455 456 jsm_dbg(READ, &ch->ch_bd->pci_dev, "DATA/LSR pair: %x %x\n", 457 ch->ch_rqueue[head], ch->ch_equeue[head]); 458 459 /* Ditch any remaining linestatus value. */ 460 linestatus = 0; 461 462 /* Add to and flip head if needed */ 463 head = (head + 1) & RQUEUEMASK; 464 465 qleft--; 466 ch->ch_rxcount++; 467 } 468 469 /* 470 * Write new final heads to channel structure. 471 */ 472 ch->ch_r_head = head & RQUEUEMASK; 473 ch->ch_e_head = head & EQUEUEMASK; 474 jsm_input(ch); 475 } 476 477 static void neo_copy_data_from_queue_to_uart(struct jsm_channel *ch) 478 { 479 u16 head; 480 u16 tail; 481 int n; 482 int s; 483 int qlen; 484 u32 len_written = 0; 485 struct circ_buf *circ; 486 487 if (!ch) 488 return; 489 490 circ = &ch->uart_port.state->xmit; 491 492 /* No data to write to the UART */ 493 if (uart_circ_empty(circ)) 494 return; 495 496 /* If port is "stopped", don't send any data to the UART */ 497 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING)) 498 return; 499 /* 500 * If FIFOs are disabled. Send data directly to txrx register 501 */ 502 if (!(ch->ch_flags & CH_FIFO_ENABLED)) { 503 u8 lsrbits = readb(&ch->ch_neo_uart->lsr); 504 505 ch->ch_cached_lsr |= lsrbits; 506 if (ch->ch_cached_lsr & UART_LSR_THRE) { 507 ch->ch_cached_lsr &= ~(UART_LSR_THRE); 508 509 writeb(circ->buf[circ->tail], &ch->ch_neo_uart->txrx); 510 jsm_dbg(WRITE, &ch->ch_bd->pci_dev, 511 "Tx data: %x\n", circ->buf[circ->tail]); 512 circ->tail = (circ->tail + 1) & (UART_XMIT_SIZE - 1); 513 ch->ch_txcount++; 514 } 515 return; 516 } 517 518 /* 519 * We have to do it this way, because of the EXAR TXFIFO count bug. 520 */ 521 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) 522 return; 523 524 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel; 525 526 /* cache head and tail of queue */ 527 head = circ->head & (UART_XMIT_SIZE - 1); 528 tail = circ->tail & (UART_XMIT_SIZE - 1); 529 qlen = uart_circ_chars_pending(circ); 530 531 /* Find minimum of the FIFO space, versus queue length */ 532 n = min(n, qlen); 533 534 while (n > 0) { 535 536 s = ((head >= tail) ? head : UART_XMIT_SIZE) - tail; 537 s = min(s, n); 538 539 if (s <= 0) 540 break; 541 542 memcpy_toio(&ch->ch_neo_uart->txrxburst, circ->buf + tail, s); 543 /* Add and flip queue if needed */ 544 tail = (tail + s) & (UART_XMIT_SIZE - 1); 545 n -= s; 546 ch->ch_txcount += s; 547 len_written += s; 548 } 549 550 /* Update the final tail */ 551 circ->tail = tail & (UART_XMIT_SIZE - 1); 552 553 if (len_written >= ch->ch_t_tlevel) 554 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 555 556 if (uart_circ_empty(circ)) 557 uart_write_wakeup(&ch->uart_port); 558 } 559 560 static void neo_parse_modem(struct jsm_channel *ch, u8 signals) 561 { 562 u8 msignals = signals; 563 564 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev, 565 "neo_parse_modem: port: %d msignals: %x\n", 566 ch->ch_portnum, msignals); 567 568 /* Scrub off lower bits. They signify delta's, which I don't care about */ 569 /* Keep DDCD and DDSR though */ 570 msignals &= 0xf8; 571 572 if (msignals & UART_MSR_DDCD) 573 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD); 574 if (msignals & UART_MSR_DDSR) 575 uart_handle_cts_change(&ch->uart_port, msignals & UART_MSR_CTS); 576 if (msignals & UART_MSR_DCD) 577 ch->ch_mistat |= UART_MSR_DCD; 578 else 579 ch->ch_mistat &= ~UART_MSR_DCD; 580 581 if (msignals & UART_MSR_DSR) 582 ch->ch_mistat |= UART_MSR_DSR; 583 else 584 ch->ch_mistat &= ~UART_MSR_DSR; 585 586 if (msignals & UART_MSR_RI) 587 ch->ch_mistat |= UART_MSR_RI; 588 else 589 ch->ch_mistat &= ~UART_MSR_RI; 590 591 if (msignals & UART_MSR_CTS) 592 ch->ch_mistat |= UART_MSR_CTS; 593 else 594 ch->ch_mistat &= ~UART_MSR_CTS; 595 596 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev, 597 "Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n", 598 ch->ch_portnum, 599 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR), 600 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS), 601 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS), 602 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR), 603 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI), 604 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD)); 605 } 606 607 /* Make the UART raise any of the output signals we want up */ 608 static void neo_assert_modem_signals(struct jsm_channel *ch) 609 { 610 if (!ch) 611 return; 612 613 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr); 614 615 /* flush write operation */ 616 neo_pci_posting_flush(ch->ch_bd); 617 } 618 619 /* 620 * Flush the WRITE FIFO on the Neo. 621 * 622 * NOTE: Channel lock MUST be held before calling this function! 623 */ 624 static void neo_flush_uart_write(struct jsm_channel *ch) 625 { 626 u8 tmp = 0; 627 int i = 0; 628 629 if (!ch) 630 return; 631 632 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr); 633 634 for (i = 0; i < 10; i++) { 635 636 /* Check to see if the UART feels it completely flushed the FIFO. */ 637 tmp = readb(&ch->ch_neo_uart->isr_fcr); 638 if (tmp & UART_FCR_CLEAR_XMIT) { 639 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, 640 "Still flushing TX UART... i: %d\n", i); 641 udelay(10); 642 } 643 else 644 break; 645 } 646 647 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 648 } 649 650 651 /* 652 * Flush the READ FIFO on the Neo. 653 * 654 * NOTE: Channel lock MUST be held before calling this function! 655 */ 656 static void neo_flush_uart_read(struct jsm_channel *ch) 657 { 658 u8 tmp = 0; 659 int i = 0; 660 661 if (!ch) 662 return; 663 664 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr); 665 666 for (i = 0; i < 10; i++) { 667 668 /* Check to see if the UART feels it completely flushed the FIFO. */ 669 tmp = readb(&ch->ch_neo_uart->isr_fcr); 670 if (tmp & 2) { 671 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, 672 "Still flushing RX UART... i: %d\n", i); 673 udelay(10); 674 } 675 else 676 break; 677 } 678 } 679 680 /* 681 * No locks are assumed to be held when calling this function. 682 */ 683 static void neo_clear_break(struct jsm_channel *ch) 684 { 685 unsigned long lock_flags; 686 687 spin_lock_irqsave(&ch->ch_lock, lock_flags); 688 689 /* Turn break off, and unset some variables */ 690 if (ch->ch_flags & CH_BREAK_SENDING) { 691 u8 temp = readb(&ch->ch_neo_uart->lcr); 692 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr); 693 694 ch->ch_flags &= ~(CH_BREAK_SENDING); 695 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, 696 "clear break Finishing UART_LCR_SBC! finished: %lx\n", 697 jiffies); 698 699 /* flush write operation */ 700 neo_pci_posting_flush(ch->ch_bd); 701 } 702 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 703 } 704 705 /* 706 * Parse the ISR register. 707 */ 708 static void neo_parse_isr(struct jsm_board *brd, u32 port) 709 { 710 struct jsm_channel *ch; 711 u8 isr; 712 u8 cause; 713 unsigned long lock_flags; 714 715 if (!brd) 716 return; 717 718 if (port >= brd->maxports) 719 return; 720 721 ch = brd->channels[port]; 722 if (!ch) 723 return; 724 725 /* Here we try to figure out what caused the interrupt to happen */ 726 while (1) { 727 728 isr = readb(&ch->ch_neo_uart->isr_fcr); 729 730 /* Bail if no pending interrupt */ 731 if (isr & UART_IIR_NO_INT) 732 break; 733 734 /* 735 * Yank off the upper 2 bits, which just show that the FIFO's are enabled. 736 */ 737 isr &= ~(UART_17158_IIR_FIFO_ENABLED); 738 739 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d isr: %x\n", 740 __FILE__, __LINE__, isr); 741 742 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) { 743 /* Read data from uart -> queue */ 744 neo_copy_data_from_uart_to_queue(ch); 745 746 /* Call our tty layer to enforce queue flow control if needed. */ 747 spin_lock_irqsave(&ch->ch_lock, lock_flags); 748 jsm_check_queue_flow_control(ch); 749 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 750 } 751 752 if (isr & UART_IIR_THRI) { 753 /* Transfer data (if any) from Write Queue -> UART. */ 754 spin_lock_irqsave(&ch->ch_lock, lock_flags); 755 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 756 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 757 neo_copy_data_from_queue_to_uart(ch); 758 } 759 760 if (isr & UART_17158_IIR_XONXOFF) { 761 cause = readb(&ch->ch_neo_uart->xoffchar1); 762 763 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 764 "Port %d. Got ISR_XONXOFF: cause:%x\n", 765 port, cause); 766 767 /* 768 * Since the UART detected either an XON or 769 * XOFF match, we need to figure out which 770 * one it was, so we can suspend or resume data flow. 771 */ 772 spin_lock_irqsave(&ch->ch_lock, lock_flags); 773 if (cause == UART_17158_XON_DETECT) { 774 /* Is output stopped right now, if so, resume it */ 775 if (brd->channels[port]->ch_flags & CH_STOP) { 776 ch->ch_flags &= ~(CH_STOP); 777 } 778 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 779 "Port %d. XON detected in incoming data\n", 780 port); 781 } 782 else if (cause == UART_17158_XOFF_DETECT) { 783 if (!(brd->channels[port]->ch_flags & CH_STOP)) { 784 ch->ch_flags |= CH_STOP; 785 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 786 "Setting CH_STOP\n"); 787 } 788 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 789 "Port: %d. XOFF detected in incoming data\n", 790 port); 791 } 792 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 793 } 794 795 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) { 796 /* 797 * If we get here, this means the hardware is doing auto flow control. 798 * Check to see whether RTS/DTR or CTS/DSR caused this interrupt. 799 */ 800 cause = readb(&ch->ch_neo_uart->mcr); 801 802 /* Which pin is doing auto flow? RTS or DTR? */ 803 spin_lock_irqsave(&ch->ch_lock, lock_flags); 804 if ((cause & 0x4) == 0) { 805 if (cause & UART_MCR_RTS) 806 ch->ch_mostat |= UART_MCR_RTS; 807 else 808 ch->ch_mostat &= ~(UART_MCR_RTS); 809 } else { 810 if (cause & UART_MCR_DTR) 811 ch->ch_mostat |= UART_MCR_DTR; 812 else 813 ch->ch_mostat &= ~(UART_MCR_DTR); 814 } 815 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 816 } 817 818 /* Parse any modem signal changes */ 819 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 820 "MOD_STAT: sending to parse_modem_sigs\n"); 821 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr)); 822 } 823 } 824 825 static inline void neo_parse_lsr(struct jsm_board *brd, u32 port) 826 { 827 struct jsm_channel *ch; 828 int linestatus; 829 unsigned long lock_flags; 830 831 if (!brd) 832 return; 833 834 if (port >= brd->maxports) 835 return; 836 837 ch = brd->channels[port]; 838 if (!ch) 839 return; 840 841 linestatus = readb(&ch->ch_neo_uart->lsr); 842 843 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d port: %d linestatus: %x\n", 844 __FILE__, __LINE__, port, linestatus); 845 846 ch->ch_cached_lsr |= linestatus; 847 848 if (ch->ch_cached_lsr & UART_LSR_DR) { 849 /* Read data from uart -> queue */ 850 neo_copy_data_from_uart_to_queue(ch); 851 spin_lock_irqsave(&ch->ch_lock, lock_flags); 852 jsm_check_queue_flow_control(ch); 853 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 854 } 855 856 /* 857 * This is a special flag. It indicates that at least 1 858 * RX error (parity, framing, or break) has happened. 859 * Mark this in our struct, which will tell me that I have 860 *to do the special RX+LSR read for this FIFO load. 861 */ 862 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR) 863 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 864 "%s:%d Port: %d Got an RX error, need to parse LSR\n", 865 __FILE__, __LINE__, port); 866 867 /* 868 * The next 3 tests should *NOT* happen, as the above test 869 * should encapsulate all 3... At least, thats what Exar says. 870 */ 871 872 if (linestatus & UART_LSR_PE) { 873 ch->ch_err_parity++; 874 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. PAR ERR!\n", 875 __FILE__, __LINE__, port); 876 } 877 878 if (linestatus & UART_LSR_FE) { 879 ch->ch_err_frame++; 880 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. FRM ERR!\n", 881 __FILE__, __LINE__, port); 882 } 883 884 if (linestatus & UART_LSR_BI) { 885 ch->ch_err_break++; 886 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 887 "%s:%d Port: %d. BRK INTR!\n", 888 __FILE__, __LINE__, port); 889 } 890 891 if (linestatus & UART_LSR_OE) { 892 /* 893 * Rx Oruns. Exar says that an orun will NOT corrupt 894 * the FIFO. It will just replace the holding register 895 * with this new data byte. So basically just ignore this. 896 * Probably we should eventually have an orun stat in our driver... 897 */ 898 ch->ch_err_overrun++; 899 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 900 "%s:%d Port: %d. Rx Overrun!\n", 901 __FILE__, __LINE__, port); 902 } 903 904 if (linestatus & UART_LSR_THRE) { 905 spin_lock_irqsave(&ch->ch_lock, lock_flags); 906 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 907 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 908 909 /* Transfer data (if any) from Write Queue -> UART. */ 910 neo_copy_data_from_queue_to_uart(ch); 911 } 912 else if (linestatus & UART_17158_TX_AND_FIFO_CLR) { 913 spin_lock_irqsave(&ch->ch_lock, lock_flags); 914 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 915 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 916 917 /* Transfer data (if any) from Write Queue -> UART. */ 918 neo_copy_data_from_queue_to_uart(ch); 919 } 920 } 921 922 /* 923 * neo_param() 924 * Send any/all changes to the line to the UART. 925 */ 926 static void neo_param(struct jsm_channel *ch) 927 { 928 u8 lcr = 0; 929 u8 uart_lcr, ier; 930 u32 baud; 931 int quot; 932 struct jsm_board *bd; 933 934 bd = ch->ch_bd; 935 if (!bd) 936 return; 937 938 /* 939 * If baud rate is zero, flush queues, and set mval to drop DTR. 940 */ 941 if ((ch->ch_c_cflag & (CBAUD)) == 0) { 942 ch->ch_r_head = ch->ch_r_tail = 0; 943 ch->ch_e_head = ch->ch_e_tail = 0; 944 945 neo_flush_uart_write(ch); 946 neo_flush_uart_read(ch); 947 948 ch->ch_flags |= (CH_BAUD0); 949 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR); 950 neo_assert_modem_signals(ch); 951 return; 952 953 } else { 954 int i; 955 unsigned int cflag; 956 static struct { 957 unsigned int rate; 958 unsigned int cflag; 959 } baud_rates[] = { 960 { 921600, B921600 }, 961 { 460800, B460800 }, 962 { 230400, B230400 }, 963 { 115200, B115200 }, 964 { 57600, B57600 }, 965 { 38400, B38400 }, 966 { 19200, B19200 }, 967 { 9600, B9600 }, 968 { 4800, B4800 }, 969 { 2400, B2400 }, 970 { 1200, B1200 }, 971 { 600, B600 }, 972 { 300, B300 }, 973 { 200, B200 }, 974 { 150, B150 }, 975 { 134, B134 }, 976 { 110, B110 }, 977 { 75, B75 }, 978 { 50, B50 }, 979 }; 980 981 cflag = C_BAUD(ch->uart_port.state->port.tty); 982 baud = 9600; 983 for (i = 0; i < ARRAY_SIZE(baud_rates); i++) { 984 if (baud_rates[i].cflag == cflag) { 985 baud = baud_rates[i].rate; 986 break; 987 } 988 } 989 990 if (ch->ch_flags & CH_BAUD0) 991 ch->ch_flags &= ~(CH_BAUD0); 992 } 993 994 if (ch->ch_c_cflag & PARENB) 995 lcr |= UART_LCR_PARITY; 996 997 if (!(ch->ch_c_cflag & PARODD)) 998 lcr |= UART_LCR_EPAR; 999 1000 /* 1001 * Not all platforms support mark/space parity, 1002 * so this will hide behind an ifdef. 1003 */ 1004 #ifdef CMSPAR 1005 if (ch->ch_c_cflag & CMSPAR) 1006 lcr |= UART_LCR_SPAR; 1007 #endif 1008 1009 if (ch->ch_c_cflag & CSTOPB) 1010 lcr |= UART_LCR_STOP; 1011 1012 switch (ch->ch_c_cflag & CSIZE) { 1013 case CS5: 1014 lcr |= UART_LCR_WLEN5; 1015 break; 1016 case CS6: 1017 lcr |= UART_LCR_WLEN6; 1018 break; 1019 case CS7: 1020 lcr |= UART_LCR_WLEN7; 1021 break; 1022 case CS8: 1023 default: 1024 lcr |= UART_LCR_WLEN8; 1025 break; 1026 } 1027 1028 ier = readb(&ch->ch_neo_uart->ier); 1029 uart_lcr = readb(&ch->ch_neo_uart->lcr); 1030 1031 quot = ch->ch_bd->bd_dividend / baud; 1032 1033 if (quot != 0) { 1034 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr); 1035 writeb((quot & 0xff), &ch->ch_neo_uart->txrx); 1036 writeb((quot >> 8), &ch->ch_neo_uart->ier); 1037 writeb(lcr, &ch->ch_neo_uart->lcr); 1038 } 1039 1040 if (uart_lcr != lcr) 1041 writeb(lcr, &ch->ch_neo_uart->lcr); 1042 1043 if (ch->ch_c_cflag & CREAD) 1044 ier |= (UART_IER_RDI | UART_IER_RLSI); 1045 1046 ier |= (UART_IER_THRI | UART_IER_MSI); 1047 1048 writeb(ier, &ch->ch_neo_uart->ier); 1049 1050 /* Set new start/stop chars */ 1051 neo_set_new_start_stop_chars(ch); 1052 1053 if (ch->ch_c_cflag & CRTSCTS) 1054 neo_set_cts_flow_control(ch); 1055 else if (ch->ch_c_iflag & IXON) { 1056 /* If start/stop is set to disable, then we should disable flow control */ 1057 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR)) 1058 neo_set_no_output_flow_control(ch); 1059 else 1060 neo_set_ixon_flow_control(ch); 1061 } 1062 else 1063 neo_set_no_output_flow_control(ch); 1064 1065 if (ch->ch_c_cflag & CRTSCTS) 1066 neo_set_rts_flow_control(ch); 1067 else if (ch->ch_c_iflag & IXOFF) { 1068 /* If start/stop is set to disable, then we should disable flow control */ 1069 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR)) 1070 neo_set_no_input_flow_control(ch); 1071 else 1072 neo_set_ixoff_flow_control(ch); 1073 } 1074 else 1075 neo_set_no_input_flow_control(ch); 1076 /* 1077 * Adjust the RX FIFO Trigger level if baud is less than 9600. 1078 * Not exactly elegant, but this is needed because of the Exar chip's 1079 * delay on firing off the RX FIFO interrupt on slower baud rates. 1080 */ 1081 if (baud < 9600) { 1082 writeb(1, &ch->ch_neo_uart->rfifo); 1083 ch->ch_r_tlevel = 1; 1084 } 1085 1086 neo_assert_modem_signals(ch); 1087 1088 /* Get current status of the modem signals now */ 1089 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr)); 1090 return; 1091 } 1092 1093 /* 1094 * jsm_neo_intr() 1095 * 1096 * Neo specific interrupt handler. 1097 */ 1098 static irqreturn_t neo_intr(int irq, void *voidbrd) 1099 { 1100 struct jsm_board *brd = voidbrd; 1101 struct jsm_channel *ch; 1102 int port = 0; 1103 int type = 0; 1104 int current_port; 1105 u32 tmp; 1106 u32 uart_poll; 1107 unsigned long lock_flags; 1108 unsigned long lock_flags2; 1109 int outofloop_count = 0; 1110 1111 /* Lock out the slow poller from running on this board. */ 1112 spin_lock_irqsave(&brd->bd_intr_lock, lock_flags); 1113 1114 /* 1115 * Read in "extended" IRQ information from the 32bit Neo register. 1116 * Bits 0-7: What port triggered the interrupt. 1117 * Bits 8-31: Each 3bits indicate what type of interrupt occurred. 1118 */ 1119 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET); 1120 1121 jsm_dbg(INTR, &brd->pci_dev, "%s:%d uart_poll: %x\n", 1122 __FILE__, __LINE__, uart_poll); 1123 1124 if (!uart_poll) { 1125 jsm_dbg(INTR, &brd->pci_dev, 1126 "Kernel interrupted to me, but no pending interrupts...\n"); 1127 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags); 1128 return IRQ_NONE; 1129 } 1130 1131 /* At this point, we have at least SOMETHING to service, dig further... */ 1132 1133 current_port = 0; 1134 1135 /* Loop on each port */ 1136 while (((uart_poll & 0xff) != 0) && (outofloop_count < 0xff)){ 1137 1138 tmp = uart_poll; 1139 outofloop_count++; 1140 1141 /* Check current port to see if it has interrupt pending */ 1142 if ((tmp & jsm_offset_table[current_port]) != 0) { 1143 port = current_port; 1144 type = tmp >> (8 + (port * 3)); 1145 type &= 0x7; 1146 } else { 1147 current_port++; 1148 continue; 1149 } 1150 1151 jsm_dbg(INTR, &brd->pci_dev, "%s:%d port: %x type: %x\n", 1152 __FILE__, __LINE__, port, type); 1153 1154 /* Remove this port + type from uart_poll */ 1155 uart_poll &= ~(jsm_offset_table[port]); 1156 1157 if (!type) { 1158 /* If no type, just ignore it, and move onto next port */ 1159 jsm_dbg(INTR, &brd->pci_dev, 1160 "Interrupt with no type! port: %d\n", port); 1161 continue; 1162 } 1163 1164 /* Switch on type of interrupt we have */ 1165 switch (type) { 1166 1167 case UART_17158_RXRDY_TIMEOUT: 1168 /* 1169 * RXRDY Time-out is cleared by reading data in the 1170 * RX FIFO until it falls below the trigger level. 1171 */ 1172 1173 /* Verify the port is in range. */ 1174 if (port >= brd->nasync) 1175 continue; 1176 1177 ch = brd->channels[port]; 1178 neo_copy_data_from_uart_to_queue(ch); 1179 1180 /* Call our tty layer to enforce queue flow control if needed. */ 1181 spin_lock_irqsave(&ch->ch_lock, lock_flags2); 1182 jsm_check_queue_flow_control(ch); 1183 spin_unlock_irqrestore(&ch->ch_lock, lock_flags2); 1184 1185 continue; 1186 1187 case UART_17158_RX_LINE_STATUS: 1188 /* 1189 * RXRDY and RX LINE Status (logic OR of LSR[4:1]) 1190 */ 1191 neo_parse_lsr(brd, port); 1192 continue; 1193 1194 case UART_17158_TXRDY: 1195 /* 1196 * TXRDY interrupt clears after reading ISR register for the UART channel. 1197 */ 1198 1199 /* 1200 * Yes, this is odd... 1201 * Why would I check EVERY possibility of type of 1202 * interrupt, when we know its TXRDY??? 1203 * Becuz for some reason, even tho we got triggered for TXRDY, 1204 * it seems to be occasionally wrong. Instead of TX, which 1205 * it should be, I was getting things like RXDY too. Weird. 1206 */ 1207 neo_parse_isr(brd, port); 1208 continue; 1209 1210 case UART_17158_MSR: 1211 /* 1212 * MSR or flow control was seen. 1213 */ 1214 neo_parse_isr(brd, port); 1215 continue; 1216 1217 default: 1218 /* 1219 * The UART triggered us with a bogus interrupt type. 1220 * It appears the Exar chip, when REALLY bogged down, will throw 1221 * these once and awhile. 1222 * Its harmless, just ignore it and move on. 1223 */ 1224 jsm_dbg(INTR, &brd->pci_dev, 1225 "%s:%d Unknown Interrupt type: %x\n", 1226 __FILE__, __LINE__, type); 1227 continue; 1228 } 1229 } 1230 1231 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags); 1232 1233 jsm_dbg(INTR, &brd->pci_dev, "finish\n"); 1234 return IRQ_HANDLED; 1235 } 1236 1237 /* 1238 * Neo specific way of turning off the receiver. 1239 * Used as a way to enforce queue flow control when in 1240 * hardware flow control mode. 1241 */ 1242 static void neo_disable_receiver(struct jsm_channel *ch) 1243 { 1244 u8 tmp = readb(&ch->ch_neo_uart->ier); 1245 tmp &= ~(UART_IER_RDI); 1246 writeb(tmp, &ch->ch_neo_uart->ier); 1247 1248 /* flush write operation */ 1249 neo_pci_posting_flush(ch->ch_bd); 1250 } 1251 1252 1253 /* 1254 * Neo specific way of turning on the receiver. 1255 * Used as a way to un-enforce queue flow control when in 1256 * hardware flow control mode. 1257 */ 1258 static void neo_enable_receiver(struct jsm_channel *ch) 1259 { 1260 u8 tmp = readb(&ch->ch_neo_uart->ier); 1261 tmp |= (UART_IER_RDI); 1262 writeb(tmp, &ch->ch_neo_uart->ier); 1263 1264 /* flush write operation */ 1265 neo_pci_posting_flush(ch->ch_bd); 1266 } 1267 1268 static void neo_send_start_character(struct jsm_channel *ch) 1269 { 1270 if (!ch) 1271 return; 1272 1273 if (ch->ch_startc != __DISABLED_CHAR) { 1274 ch->ch_xon_sends++; 1275 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx); 1276 1277 /* flush write operation */ 1278 neo_pci_posting_flush(ch->ch_bd); 1279 } 1280 } 1281 1282 static void neo_send_stop_character(struct jsm_channel *ch) 1283 { 1284 if (!ch) 1285 return; 1286 1287 if (ch->ch_stopc != __DISABLED_CHAR) { 1288 ch->ch_xoff_sends++; 1289 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx); 1290 1291 /* flush write operation */ 1292 neo_pci_posting_flush(ch->ch_bd); 1293 } 1294 } 1295 1296 /* 1297 * neo_uart_init 1298 */ 1299 static void neo_uart_init(struct jsm_channel *ch) 1300 { 1301 writeb(0, &ch->ch_neo_uart->ier); 1302 writeb(0, &ch->ch_neo_uart->efr); 1303 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr); 1304 1305 /* Clear out UART and FIFO */ 1306 readb(&ch->ch_neo_uart->txrx); 1307 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr); 1308 readb(&ch->ch_neo_uart->lsr); 1309 readb(&ch->ch_neo_uart->msr); 1310 1311 ch->ch_flags |= CH_FIFO_ENABLED; 1312 1313 /* Assert any signals we want up */ 1314 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr); 1315 } 1316 1317 /* 1318 * Make the UART completely turn off. 1319 */ 1320 static void neo_uart_off(struct jsm_channel *ch) 1321 { 1322 /* Turn off UART enhanced bits */ 1323 writeb(0, &ch->ch_neo_uart->efr); 1324 1325 /* Stop all interrupts from occurring. */ 1326 writeb(0, &ch->ch_neo_uart->ier); 1327 } 1328 1329 static u32 neo_get_uart_bytes_left(struct jsm_channel *ch) 1330 { 1331 u8 left = 0; 1332 u8 lsr = readb(&ch->ch_neo_uart->lsr); 1333 1334 /* We must cache the LSR as some of the bits get reset once read... */ 1335 ch->ch_cached_lsr |= lsr; 1336 1337 /* Determine whether the Transmitter is empty or not */ 1338 if (!(lsr & UART_LSR_TEMT)) 1339 left = 1; 1340 else { 1341 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 1342 left = 0; 1343 } 1344 1345 return left; 1346 } 1347 1348 /* Channel lock MUST be held by the calling function! */ 1349 static void neo_send_break(struct jsm_channel *ch) 1350 { 1351 /* 1352 * Set the time we should stop sending the break. 1353 * If we are already sending a break, toss away the existing 1354 * time to stop, and use this new value instead. 1355 */ 1356 1357 /* Tell the UART to start sending the break */ 1358 if (!(ch->ch_flags & CH_BREAK_SENDING)) { 1359 u8 temp = readb(&ch->ch_neo_uart->lcr); 1360 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr); 1361 ch->ch_flags |= (CH_BREAK_SENDING); 1362 1363 /* flush write operation */ 1364 neo_pci_posting_flush(ch->ch_bd); 1365 } 1366 } 1367 1368 /* 1369 * neo_send_immediate_char. 1370 * 1371 * Sends a specific character as soon as possible to the UART, 1372 * jumping over any bytes that might be in the write queue. 1373 * 1374 * The channel lock MUST be held by the calling function. 1375 */ 1376 static void neo_send_immediate_char(struct jsm_channel *ch, unsigned char c) 1377 { 1378 if (!ch) 1379 return; 1380 1381 writeb(c, &ch->ch_neo_uart->txrx); 1382 1383 /* flush write operation */ 1384 neo_pci_posting_flush(ch->ch_bd); 1385 } 1386 1387 struct board_ops jsm_neo_ops = { 1388 .intr = neo_intr, 1389 .uart_init = neo_uart_init, 1390 .uart_off = neo_uart_off, 1391 .param = neo_param, 1392 .assert_modem_signals = neo_assert_modem_signals, 1393 .flush_uart_write = neo_flush_uart_write, 1394 .flush_uart_read = neo_flush_uart_read, 1395 .disable_receiver = neo_disable_receiver, 1396 .enable_receiver = neo_enable_receiver, 1397 .send_break = neo_send_break, 1398 .clear_break = neo_clear_break, 1399 .send_start_character = neo_send_start_character, 1400 .send_stop_character = neo_send_stop_character, 1401 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart, 1402 .get_uart_bytes_left = neo_get_uart_bytes_left, 1403 .send_immediate_char = neo_send_immediate_char 1404 }; 1405