1e3b3d0f5SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0
2ff7693d0SCarlo Caione /*
3ff7693d0SCarlo Caione * Based on meson_uart.c, by AMLOGIC, INC.
4ff7693d0SCarlo Caione *
5ff7693d0SCarlo Caione * Copyright (C) 2014 Carlo Caione <carlo@caione.org>
6ff7693d0SCarlo Caione */
7ff7693d0SCarlo Caione
8ff7693d0SCarlo Caione #include <linux/clk.h>
9ff7693d0SCarlo Caione #include <linux/console.h>
10ff7693d0SCarlo Caione #include <linux/delay.h>
11ff7693d0SCarlo Caione #include <linux/init.h>
12ff7693d0SCarlo Caione #include <linux/io.h>
138412ba1dSJulien Masson #include <linux/iopoll.h>
14ff7693d0SCarlo Caione #include <linux/module.h>
15ff7693d0SCarlo Caione #include <linux/kernel.h>
16ff7693d0SCarlo Caione #include <linux/of.h>
17ff7693d0SCarlo Caione #include <linux/platform_device.h>
18ff7693d0SCarlo Caione #include <linux/serial.h>
19ff7693d0SCarlo Caione #include <linux/serial_core.h>
20ff7693d0SCarlo Caione #include <linux/tty.h>
21ff7693d0SCarlo Caione #include <linux/tty_flip.h>
22ff7693d0SCarlo Caione
23ff7693d0SCarlo Caione /* Register offsets */
24ff7693d0SCarlo Caione #define AML_UART_WFIFO 0x00
25ff7693d0SCarlo Caione #define AML_UART_RFIFO 0x04
26ff7693d0SCarlo Caione #define AML_UART_CONTROL 0x08
27ff7693d0SCarlo Caione #define AML_UART_STATUS 0x0c
28ff7693d0SCarlo Caione #define AML_UART_MISC 0x10
29ff7693d0SCarlo Caione #define AML_UART_REG5 0x14
30ff7693d0SCarlo Caione
31ff7693d0SCarlo Caione /* AML_UART_CONTROL bits */
32ff7693d0SCarlo Caione #define AML_UART_TX_EN BIT(12)
33ff7693d0SCarlo Caione #define AML_UART_RX_EN BIT(13)
3444137e40SMartin Blumenstingl #define AML_UART_TWO_WIRE_EN BIT(15)
35f859722aSMartin Blumenstingl #define AML_UART_STOP_BIT_LEN_MASK (0x03 << 16)
36f859722aSMartin Blumenstingl #define AML_UART_STOP_BIT_1SB (0x00 << 16)
37f859722aSMartin Blumenstingl #define AML_UART_STOP_BIT_2SB (0x01 << 16)
3844137e40SMartin Blumenstingl #define AML_UART_PARITY_TYPE BIT(18)
3944137e40SMartin Blumenstingl #define AML_UART_PARITY_EN BIT(19)
40ff7693d0SCarlo Caione #define AML_UART_TX_RST BIT(22)
41ff7693d0SCarlo Caione #define AML_UART_RX_RST BIT(23)
4244137e40SMartin Blumenstingl #define AML_UART_CLEAR_ERR BIT(24)
43ff7693d0SCarlo Caione #define AML_UART_RX_INT_EN BIT(27)
44ff7693d0SCarlo Caione #define AML_UART_TX_INT_EN BIT(28)
45ff7693d0SCarlo Caione #define AML_UART_DATA_LEN_MASK (0x03 << 20)
46ff7693d0SCarlo Caione #define AML_UART_DATA_LEN_8BIT (0x00 << 20)
47ff7693d0SCarlo Caione #define AML_UART_DATA_LEN_7BIT (0x01 << 20)
48ff7693d0SCarlo Caione #define AML_UART_DATA_LEN_6BIT (0x02 << 20)
49ff7693d0SCarlo Caione #define AML_UART_DATA_LEN_5BIT (0x03 << 20)
50ff7693d0SCarlo Caione
51ff7693d0SCarlo Caione /* AML_UART_STATUS bits */
52ff7693d0SCarlo Caione #define AML_UART_PARITY_ERR BIT(16)
53ff7693d0SCarlo Caione #define AML_UART_FRAME_ERR BIT(17)
54ff7693d0SCarlo Caione #define AML_UART_TX_FIFO_WERR BIT(18)
55ff7693d0SCarlo Caione #define AML_UART_RX_EMPTY BIT(20)
56ff7693d0SCarlo Caione #define AML_UART_TX_FULL BIT(21)
57ff7693d0SCarlo Caione #define AML_UART_TX_EMPTY BIT(22)
5888679739SBen Dooks #define AML_UART_XMIT_BUSY BIT(25)
59ff7693d0SCarlo Caione #define AML_UART_ERR (AML_UART_PARITY_ERR | \
60ff7693d0SCarlo Caione AML_UART_FRAME_ERR | \
61ff7693d0SCarlo Caione AML_UART_TX_FIFO_WERR)
62ff7693d0SCarlo Caione
63ff7693d0SCarlo Caione /* AML_UART_MISC bits */
64ff7693d0SCarlo Caione #define AML_UART_XMIT_IRQ(c) (((c) & 0xff) << 8)
65ff7693d0SCarlo Caione #define AML_UART_RECV_IRQ(c) ((c) & 0xff)
66ff7693d0SCarlo Caione
67ff7693d0SCarlo Caione /* AML_UART_REG5 bits */
6816b3ac90SGreg Kroah-Hartman #define AML_UART_BAUD_MASK 0x7fffff
69ff7693d0SCarlo Caione #define AML_UART_BAUD_USE BIT(23)
7016b3ac90SGreg Kroah-Hartman #define AML_UART_BAUD_XTAL BIT(24)
7100a7fa83SYu Tu #define AML_UART_BAUD_XTAL_DIV2 BIT(27)
72ff7693d0SCarlo Caione
73a26988e8SLoys Ollivier #define AML_UART_PORT_NUM 12
74a26988e8SLoys Ollivier #define AML_UART_PORT_OFFSET 6
75ff7693d0SCarlo Caione
768412ba1dSJulien Masson #define AML_UART_POLL_USEC 5
778412ba1dSJulien Masson #define AML_UART_TIMEOUT_USEC 10000
78ff7693d0SCarlo Caione
7917be181bSDmitry Rokosov static struct uart_driver meson_uart_driver_ttyAML;
8017be181bSDmitry Rokosov static struct uart_driver meson_uart_driver_ttyS;
81ff7693d0SCarlo Caione
82ff7693d0SCarlo Caione static struct uart_port *meson_ports[AML_UART_PORT_NUM];
83ff7693d0SCarlo Caione
8400a7fa83SYu Tu struct meson_uart_data {
85e71aab9dSDmitry Rokosov struct uart_driver *uart_driver;
8600a7fa83SYu Tu bool has_xtal_div2;
8700a7fa83SYu Tu };
8800a7fa83SYu Tu
meson_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)89ff7693d0SCarlo Caione static void meson_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
90ff7693d0SCarlo Caione {
91ff7693d0SCarlo Caione }
92ff7693d0SCarlo Caione
meson_uart_get_mctrl(struct uart_port * port)93ff7693d0SCarlo Caione static unsigned int meson_uart_get_mctrl(struct uart_port *port)
94ff7693d0SCarlo Caione {
95ff7693d0SCarlo Caione return TIOCM_CTS;
96ff7693d0SCarlo Caione }
97ff7693d0SCarlo Caione
meson_uart_tx_empty(struct uart_port * port)98ff7693d0SCarlo Caione static unsigned int meson_uart_tx_empty(struct uart_port *port)
99ff7693d0SCarlo Caione {
100ff7693d0SCarlo Caione u32 val;
101ff7693d0SCarlo Caione
102ff7693d0SCarlo Caione val = readl(port->membase + AML_UART_STATUS);
10388679739SBen Dooks val &= (AML_UART_TX_EMPTY | AML_UART_XMIT_BUSY);
10488679739SBen Dooks return (val == AML_UART_TX_EMPTY) ? TIOCSER_TEMT : 0;
105ff7693d0SCarlo Caione }
106ff7693d0SCarlo Caione
meson_uart_stop_tx(struct uart_port * port)107ff7693d0SCarlo Caione static void meson_uart_stop_tx(struct uart_port *port)
108ff7693d0SCarlo Caione {
109ff7693d0SCarlo Caione u32 val;
110ff7693d0SCarlo Caione
111ff7693d0SCarlo Caione val = readl(port->membase + AML_UART_CONTROL);
112855ddcabSBen Dooks val &= ~AML_UART_TX_INT_EN;
113ff7693d0SCarlo Caione writel(val, port->membase + AML_UART_CONTROL);
114ff7693d0SCarlo Caione }
115ff7693d0SCarlo Caione
meson_uart_stop_rx(struct uart_port * port)116ff7693d0SCarlo Caione static void meson_uart_stop_rx(struct uart_port *port)
117ff7693d0SCarlo Caione {
118ff7693d0SCarlo Caione u32 val;
119ff7693d0SCarlo Caione
120ff7693d0SCarlo Caione val = readl(port->membase + AML_UART_CONTROL);
121ff7693d0SCarlo Caione val &= ~AML_UART_RX_EN;
122ff7693d0SCarlo Caione writel(val, port->membase + AML_UART_CONTROL);
123ff7693d0SCarlo Caione }
124ff7693d0SCarlo Caione
meson_uart_shutdown(struct uart_port * port)125ff7693d0SCarlo Caione static void meson_uart_shutdown(struct uart_port *port)
126ff7693d0SCarlo Caione {
127ff7693d0SCarlo Caione unsigned long flags;
128ff7693d0SCarlo Caione u32 val;
129ff7693d0SCarlo Caione
130ff7693d0SCarlo Caione free_irq(port->irq, port);
131ff7693d0SCarlo Caione
132042d7848SThomas Gleixner uart_port_lock_irqsave(port, &flags);
133ff7693d0SCarlo Caione
134ff7693d0SCarlo Caione val = readl(port->membase + AML_UART_CONTROL);
135855ddcabSBen Dooks val &= ~AML_UART_RX_EN;
136ff7693d0SCarlo Caione val &= ~(AML_UART_RX_INT_EN | AML_UART_TX_INT_EN);
137ff7693d0SCarlo Caione writel(val, port->membase + AML_UART_CONTROL);
138ff7693d0SCarlo Caione
139042d7848SThomas Gleixner uart_port_unlock_irqrestore(port, flags);
140ff7693d0SCarlo Caione }
141ff7693d0SCarlo Caione
meson_uart_start_tx(struct uart_port * port)142ff7693d0SCarlo Caione static void meson_uart_start_tx(struct uart_port *port)
143ff7693d0SCarlo Caione {
144*1788cf6aSJiri Slaby (SUSE) struct tty_port *tport = &port->state->port;
145*1788cf6aSJiri Slaby (SUSE) unsigned char ch;
146f1dd05c8SBen Dooks u32 val;
147ff7693d0SCarlo Caione
148ff7693d0SCarlo Caione if (uart_tx_stopped(port)) {
149ff7693d0SCarlo Caione meson_uart_stop_tx(port);
150ff7693d0SCarlo Caione return;
151ff7693d0SCarlo Caione }
152ff7693d0SCarlo Caione
153ff7693d0SCarlo Caione while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) {
154ff7693d0SCarlo Caione if (port->x_char) {
155ff7693d0SCarlo Caione writel(port->x_char, port->membase + AML_UART_WFIFO);
156ff7693d0SCarlo Caione port->icount.tx++;
157ff7693d0SCarlo Caione port->x_char = 0;
158ff7693d0SCarlo Caione continue;
159ff7693d0SCarlo Caione }
160ff7693d0SCarlo Caione
161*1788cf6aSJiri Slaby (SUSE) if (!uart_fifo_get(port, &ch))
162ff7693d0SCarlo Caione break;
163ff7693d0SCarlo Caione
164ff7693d0SCarlo Caione writel(ch, port->membase + AML_UART_WFIFO);
165ff7693d0SCarlo Caione }
166ff7693d0SCarlo Caione
167*1788cf6aSJiri Slaby (SUSE) if (!kfifo_is_empty(&tport->xmit_fifo)) {
168f1dd05c8SBen Dooks val = readl(port->membase + AML_UART_CONTROL);
169f1dd05c8SBen Dooks val |= AML_UART_TX_INT_EN;
170f1dd05c8SBen Dooks writel(val, port->membase + AML_UART_CONTROL);
171f1dd05c8SBen Dooks }
172f1dd05c8SBen Dooks
173*1788cf6aSJiri Slaby (SUSE) if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
174ff7693d0SCarlo Caione uart_write_wakeup(port);
175ff7693d0SCarlo Caione }
176ff7693d0SCarlo Caione
meson_receive_chars(struct uart_port * port)177ff7693d0SCarlo Caione static void meson_receive_chars(struct uart_port *port)
178ff7693d0SCarlo Caione {
179ff7693d0SCarlo Caione struct tty_port *tport = &port->state->port;
180ff7693d0SCarlo Caione char flag;
181b86ac225SYixun Lan u32 ostatus, status, ch, mode;
182ff7693d0SCarlo Caione
183ff7693d0SCarlo Caione do {
184ff7693d0SCarlo Caione flag = TTY_NORMAL;
185ff7693d0SCarlo Caione port->icount.rx++;
186b86ac225SYixun Lan ostatus = status = readl(port->membase + AML_UART_STATUS);
187ff7693d0SCarlo Caione
188ff7693d0SCarlo Caione if (status & AML_UART_ERR) {
189ff7693d0SCarlo Caione if (status & AML_UART_TX_FIFO_WERR)
190ff7693d0SCarlo Caione port->icount.overrun++;
191ff7693d0SCarlo Caione else if (status & AML_UART_FRAME_ERR)
192ff7693d0SCarlo Caione port->icount.frame++;
193ff7693d0SCarlo Caione else if (status & AML_UART_PARITY_ERR)
194ff7693d0SCarlo Caione port->icount.frame++;
195ff7693d0SCarlo Caione
196ff7693d0SCarlo Caione mode = readl(port->membase + AML_UART_CONTROL);
197ff7693d0SCarlo Caione mode |= AML_UART_CLEAR_ERR;
198ff7693d0SCarlo Caione writel(mode, port->membase + AML_UART_CONTROL);
199ff7693d0SCarlo Caione
200ff7693d0SCarlo Caione /* It doesn't clear to 0 automatically */
201ff7693d0SCarlo Caione mode &= ~AML_UART_CLEAR_ERR;
202ff7693d0SCarlo Caione writel(mode, port->membase + AML_UART_CONTROL);
203ff7693d0SCarlo Caione
204ff7693d0SCarlo Caione status &= port->read_status_mask;
205ff7693d0SCarlo Caione if (status & AML_UART_FRAME_ERR)
206ff7693d0SCarlo Caione flag = TTY_FRAME;
207ff7693d0SCarlo Caione else if (status & AML_UART_PARITY_ERR)
208ff7693d0SCarlo Caione flag = TTY_PARITY;
209ff7693d0SCarlo Caione }
210ff7693d0SCarlo Caione
211ff7693d0SCarlo Caione ch = readl(port->membase + AML_UART_RFIFO);
212ff7693d0SCarlo Caione ch &= 0xff;
213ff7693d0SCarlo Caione
214b86ac225SYixun Lan if ((ostatus & AML_UART_FRAME_ERR) && (ch == 0)) {
215b86ac225SYixun Lan port->icount.brk++;
216b86ac225SYixun Lan flag = TTY_BREAK;
217b86ac225SYixun Lan if (uart_handle_break(port))
218b86ac225SYixun Lan continue;
219b86ac225SYixun Lan }
220b86ac225SYixun Lan
221fb793b95SSebastian Andrzej Siewior if (uart_prepare_sysrq_char(port, ch))
222b86ac225SYixun Lan continue;
223b86ac225SYixun Lan
224ff7693d0SCarlo Caione if ((status & port->ignore_status_mask) == 0)
225ff7693d0SCarlo Caione tty_insert_flip_char(tport, ch, flag);
226ff7693d0SCarlo Caione
227ff7693d0SCarlo Caione if (status & AML_UART_TX_FIFO_WERR)
228ff7693d0SCarlo Caione tty_insert_flip_char(tport, 0, TTY_OVERRUN);
229ff7693d0SCarlo Caione
230ff7693d0SCarlo Caione } while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY));
231ff7693d0SCarlo Caione
232ff7693d0SCarlo Caione tty_flip_buffer_push(tport);
233ff7693d0SCarlo Caione }
234ff7693d0SCarlo Caione
meson_uart_interrupt(int irq,void * dev_id)235ff7693d0SCarlo Caione static irqreturn_t meson_uart_interrupt(int irq, void *dev_id)
236ff7693d0SCarlo Caione {
237ff7693d0SCarlo Caione struct uart_port *port = (struct uart_port *)dev_id;
238ff7693d0SCarlo Caione
239042d7848SThomas Gleixner uart_port_lock(port);
240ff7693d0SCarlo Caione
241ff7693d0SCarlo Caione if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY))
242ff7693d0SCarlo Caione meson_receive_chars(port);
243ff7693d0SCarlo Caione
24439469654SBen Dooks if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) {
24539469654SBen Dooks if (readl(port->membase + AML_UART_CONTROL) & AML_UART_TX_INT_EN)
246ff7693d0SCarlo Caione meson_uart_start_tx(port);
24739469654SBen Dooks }
248ff7693d0SCarlo Caione
249fb793b95SSebastian Andrzej Siewior uart_unlock_and_check_sysrq(port);
250ff7693d0SCarlo Caione
251ff7693d0SCarlo Caione return IRQ_HANDLED;
252ff7693d0SCarlo Caione }
253ff7693d0SCarlo Caione
meson_uart_type(struct uart_port * port)254ff7693d0SCarlo Caione static const char *meson_uart_type(struct uart_port *port)
255ff7693d0SCarlo Caione {
256ff7693d0SCarlo Caione return (port->type == PORT_MESON) ? "meson_uart" : NULL;
257ff7693d0SCarlo Caione }
258ff7693d0SCarlo Caione
259589f892aSJohn Ogness /*
260589f892aSJohn Ogness * This function is called only from probe() using a temporary io mapping
261589f892aSJohn Ogness * in order to perform a reset before setting up the device. Since the
262589f892aSJohn Ogness * temporarily mapped region was successfully requested, there can be no
263589f892aSJohn Ogness * console on this port at this time. Hence it is not necessary for this
264589f892aSJohn Ogness * function to acquire the port->lock. (Since there is no console on this
265589f892aSJohn Ogness * port at this time, the port->lock is not initialized yet.)
266589f892aSJohn Ogness */
meson_uart_reset(struct uart_port * port)26700661dd8SBen Dooks static void meson_uart_reset(struct uart_port *port)
268ff7693d0SCarlo Caione {
269ff7693d0SCarlo Caione u32 val;
270ff7693d0SCarlo Caione
271ff7693d0SCarlo Caione val = readl(port->membase + AML_UART_CONTROL);
272c0f0b8c5SMartin Blumenstingl val |= (AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLEAR_ERR);
273ff7693d0SCarlo Caione writel(val, port->membase + AML_UART_CONTROL);
274ff7693d0SCarlo Caione
275c0f0b8c5SMartin Blumenstingl val &= ~(AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLEAR_ERR);
276ff7693d0SCarlo Caione writel(val, port->membase + AML_UART_CONTROL);
27700661dd8SBen Dooks }
27800661dd8SBen Dooks
meson_uart_startup(struct uart_port * port)27900661dd8SBen Dooks static int meson_uart_startup(struct uart_port *port)
28000661dd8SBen Dooks {
281589f892aSJohn Ogness unsigned long flags;
28200661dd8SBen Dooks u32 val;
28300661dd8SBen Dooks int ret = 0;
28400661dd8SBen Dooks
285042d7848SThomas Gleixner uart_port_lock_irqsave(port, &flags);
286589f892aSJohn Ogness
28700661dd8SBen Dooks val = readl(port->membase + AML_UART_CONTROL);
288c0f0b8c5SMartin Blumenstingl val |= AML_UART_CLEAR_ERR;
28900661dd8SBen Dooks writel(val, port->membase + AML_UART_CONTROL);
290c0f0b8c5SMartin Blumenstingl val &= ~AML_UART_CLEAR_ERR;
29100661dd8SBen Dooks writel(val, port->membase + AML_UART_CONTROL);
292ff7693d0SCarlo Caione
293ff7693d0SCarlo Caione val |= (AML_UART_RX_EN | AML_UART_TX_EN);
294ff7693d0SCarlo Caione writel(val, port->membase + AML_UART_CONTROL);
295ff7693d0SCarlo Caione
296ff7693d0SCarlo Caione val |= (AML_UART_RX_INT_EN | AML_UART_TX_INT_EN);
297ff7693d0SCarlo Caione writel(val, port->membase + AML_UART_CONTROL);
298ff7693d0SCarlo Caione
299ff7693d0SCarlo Caione val = (AML_UART_RECV_IRQ(1) | AML_UART_XMIT_IRQ(port->fifosize / 2));
300ff7693d0SCarlo Caione writel(val, port->membase + AML_UART_MISC);
301ff7693d0SCarlo Caione
302042d7848SThomas Gleixner uart_port_unlock_irqrestore(port, flags);
303589f892aSJohn Ogness
304ff7693d0SCarlo Caione ret = request_irq(port->irq, meson_uart_interrupt, 0,
3058b7a6b2bSHeiner Kallweit port->name, port);
306ff7693d0SCarlo Caione
307ff7693d0SCarlo Caione return ret;
308ff7693d0SCarlo Caione }
309ff7693d0SCarlo Caione
meson_uart_change_speed(struct uart_port * port,unsigned long baud)310ff7693d0SCarlo Caione static void meson_uart_change_speed(struct uart_port *port, unsigned long baud)
311ff7693d0SCarlo Caione {
31200a7fa83SYu Tu const struct meson_uart_data *private_data = port->private_data;
31300a7fa83SYu Tu u32 val = 0;
314ff7693d0SCarlo Caione
315f1f5c140SBen Dooks while (!meson_uart_tx_empty(port))
316ff7693d0SCarlo Caione cpu_relax();
317ff7693d0SCarlo Caione
31816b3ac90SGreg Kroah-Hartman if (port->uartclk == 24000000) {
31900a7fa83SYu Tu unsigned int xtal_div = 3;
32000a7fa83SYu Tu
32100a7fa83SYu Tu if (private_data && private_data->has_xtal_div2) {
32200a7fa83SYu Tu xtal_div = 2;
32300a7fa83SYu Tu val |= AML_UART_BAUD_XTAL_DIV2;
32400a7fa83SYu Tu }
32500a7fa83SYu Tu val |= DIV_ROUND_CLOSEST(port->uartclk / xtal_div, baud) - 1;
32616b3ac90SGreg Kroah-Hartman val |= AML_UART_BAUD_XTAL;
32716b3ac90SGreg Kroah-Hartman } else {
328368ab68bSYu Tu val = DIV_ROUND_CLOSEST(port->uartclk / 4, baud) - 1;
32916b3ac90SGreg Kroah-Hartman }
330ff7693d0SCarlo Caione val |= AML_UART_BAUD_USE;
331ff7693d0SCarlo Caione writel(val, port->membase + AML_UART_REG5);
332ff7693d0SCarlo Caione }
333ff7693d0SCarlo Caione
meson_uart_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)334ff7693d0SCarlo Caione static void meson_uart_set_termios(struct uart_port *port,
335ff7693d0SCarlo Caione struct ktermios *termios,
336bec5b814SIlpo Järvinen const struct ktermios *old)
337ff7693d0SCarlo Caione {
338ff7693d0SCarlo Caione unsigned int cflags, iflags, baud;
339ff7693d0SCarlo Caione unsigned long flags;
340ff7693d0SCarlo Caione u32 val;
341ff7693d0SCarlo Caione
342042d7848SThomas Gleixner uart_port_lock_irqsave(port, &flags);
343ff7693d0SCarlo Caione
344ff7693d0SCarlo Caione cflags = termios->c_cflag;
345ff7693d0SCarlo Caione iflags = termios->c_iflag;
346ff7693d0SCarlo Caione
347ff7693d0SCarlo Caione val = readl(port->membase + AML_UART_CONTROL);
348ff7693d0SCarlo Caione
349ff7693d0SCarlo Caione val &= ~AML_UART_DATA_LEN_MASK;
350ff7693d0SCarlo Caione switch (cflags & CSIZE) {
351ff7693d0SCarlo Caione case CS8:
352ff7693d0SCarlo Caione val |= AML_UART_DATA_LEN_8BIT;
353ff7693d0SCarlo Caione break;
354ff7693d0SCarlo Caione case CS7:
355ff7693d0SCarlo Caione val |= AML_UART_DATA_LEN_7BIT;
356ff7693d0SCarlo Caione break;
357ff7693d0SCarlo Caione case CS6:
358ff7693d0SCarlo Caione val |= AML_UART_DATA_LEN_6BIT;
359ff7693d0SCarlo Caione break;
360ff7693d0SCarlo Caione case CS5:
361ff7693d0SCarlo Caione val |= AML_UART_DATA_LEN_5BIT;
362ff7693d0SCarlo Caione break;
363ff7693d0SCarlo Caione }
364ff7693d0SCarlo Caione
365ff7693d0SCarlo Caione if (cflags & PARENB)
366ff7693d0SCarlo Caione val |= AML_UART_PARITY_EN;
367ff7693d0SCarlo Caione else
368ff7693d0SCarlo Caione val &= ~AML_UART_PARITY_EN;
369ff7693d0SCarlo Caione
370ff7693d0SCarlo Caione if (cflags & PARODD)
371ff7693d0SCarlo Caione val |= AML_UART_PARITY_TYPE;
372ff7693d0SCarlo Caione else
373ff7693d0SCarlo Caione val &= ~AML_UART_PARITY_TYPE;
374ff7693d0SCarlo Caione
375f859722aSMartin Blumenstingl val &= ~AML_UART_STOP_BIT_LEN_MASK;
376ff7693d0SCarlo Caione if (cflags & CSTOPB)
377f859722aSMartin Blumenstingl val |= AML_UART_STOP_BIT_2SB;
378ff7693d0SCarlo Caione else
379f859722aSMartin Blumenstingl val |= AML_UART_STOP_BIT_1SB;
380ff7693d0SCarlo Caione
3812a1d728fSPavel Krasavin if (cflags & CRTSCTS) {
3822a1d728fSPavel Krasavin if (port->flags & UPF_HARD_FLOW)
383ff7693d0SCarlo Caione val &= ~AML_UART_TWO_WIRE_EN;
384ff7693d0SCarlo Caione else
3852a1d728fSPavel Krasavin termios->c_cflag &= ~CRTSCTS;
3862a1d728fSPavel Krasavin } else {
387ff7693d0SCarlo Caione val |= AML_UART_TWO_WIRE_EN;
3882a1d728fSPavel Krasavin }
389ff7693d0SCarlo Caione
390ff7693d0SCarlo Caione writel(val, port->membase + AML_UART_CONTROL);
391ff7693d0SCarlo Caione
3929b11f19eSThomas Rohloff baud = uart_get_baud_rate(port, termios, old, 50, 4000000);
393ff7693d0SCarlo Caione meson_uart_change_speed(port, baud);
394ff7693d0SCarlo Caione
395ff7693d0SCarlo Caione port->read_status_mask = AML_UART_TX_FIFO_WERR;
396ff7693d0SCarlo Caione if (iflags & INPCK)
397ff7693d0SCarlo Caione port->read_status_mask |= AML_UART_PARITY_ERR |
398ff7693d0SCarlo Caione AML_UART_FRAME_ERR;
399ff7693d0SCarlo Caione
400ff7693d0SCarlo Caione port->ignore_status_mask = 0;
401ff7693d0SCarlo Caione if (iflags & IGNPAR)
402ff7693d0SCarlo Caione port->ignore_status_mask |= AML_UART_PARITY_ERR |
403ff7693d0SCarlo Caione AML_UART_FRAME_ERR;
404ff7693d0SCarlo Caione
405ff7693d0SCarlo Caione uart_update_timeout(port, termios->c_cflag, baud);
406042d7848SThomas Gleixner uart_port_unlock_irqrestore(port, flags);
407ff7693d0SCarlo Caione }
408ff7693d0SCarlo Caione
meson_uart_verify_port(struct uart_port * port,struct serial_struct * ser)409ff7693d0SCarlo Caione static int meson_uart_verify_port(struct uart_port *port,
410ff7693d0SCarlo Caione struct serial_struct *ser)
411ff7693d0SCarlo Caione {
412ff7693d0SCarlo Caione int ret = 0;
413ff7693d0SCarlo Caione
414ff7693d0SCarlo Caione if (port->type != PORT_MESON)
415ff7693d0SCarlo Caione ret = -EINVAL;
416ff7693d0SCarlo Caione if (port->irq != ser->irq)
417ff7693d0SCarlo Caione ret = -EINVAL;
418ff7693d0SCarlo Caione if (ser->baud_base < 9600)
419ff7693d0SCarlo Caione ret = -EINVAL;
420ff7693d0SCarlo Caione return ret;
421ff7693d0SCarlo Caione }
422ff7693d0SCarlo Caione
meson_uart_release_port(struct uart_port * port)423ff7693d0SCarlo Caione static void meson_uart_release_port(struct uart_port *port)
424ff7693d0SCarlo Caione {
42516b3ac90SGreg Kroah-Hartman devm_iounmap(port->dev, port->membase);
42616b3ac90SGreg Kroah-Hartman port->membase = NULL;
42716b3ac90SGreg Kroah-Hartman devm_release_mem_region(port->dev, port->mapbase, port->mapsize);
428ff7693d0SCarlo Caione }
429ff7693d0SCarlo Caione
meson_uart_request_port(struct uart_port * port)430ff7693d0SCarlo Caione static int meson_uart_request_port(struct uart_port *port)
431ff7693d0SCarlo Caione {
43216b3ac90SGreg Kroah-Hartman if (!devm_request_mem_region(port->dev, port->mapbase, port->mapsize,
43316b3ac90SGreg Kroah-Hartman dev_name(port->dev))) {
43416b3ac90SGreg Kroah-Hartman dev_err(port->dev, "Memory region busy\n");
43516b3ac90SGreg Kroah-Hartman return -EBUSY;
43616b3ac90SGreg Kroah-Hartman }
43744023b8eSYu Tu
43816b3ac90SGreg Kroah-Hartman port->membase = devm_ioremap(port->dev, port->mapbase,
43916b3ac90SGreg Kroah-Hartman port->mapsize);
44016b3ac90SGreg Kroah-Hartman if (!port->membase)
44116b3ac90SGreg Kroah-Hartman return -ENOMEM;
44244023b8eSYu Tu
443ff7693d0SCarlo Caione return 0;
444ff7693d0SCarlo Caione }
445ff7693d0SCarlo Caione
meson_uart_config_port(struct uart_port * port,int flags)446ff7693d0SCarlo Caione static void meson_uart_config_port(struct uart_port *port, int flags)
447ff7693d0SCarlo Caione {
448ff7693d0SCarlo Caione if (flags & UART_CONFIG_TYPE) {
449ff7693d0SCarlo Caione port->type = PORT_MESON;
450ff7693d0SCarlo Caione meson_uart_request_port(port);
451ff7693d0SCarlo Caione }
452ff7693d0SCarlo Caione }
453ff7693d0SCarlo Caione
4548412ba1dSJulien Masson #ifdef CONFIG_CONSOLE_POLL
4558412ba1dSJulien Masson /*
4568412ba1dSJulien Masson * Console polling routines for writing and reading from the uart while
4578412ba1dSJulien Masson * in an interrupt or debug context (i.e. kgdb).
4588412ba1dSJulien Masson */
4598412ba1dSJulien Masson
meson_uart_poll_get_char(struct uart_port * port)4608412ba1dSJulien Masson static int meson_uart_poll_get_char(struct uart_port *port)
4618412ba1dSJulien Masson {
4628412ba1dSJulien Masson u32 c;
4638412ba1dSJulien Masson unsigned long flags;
4648412ba1dSJulien Masson
465042d7848SThomas Gleixner uart_port_lock_irqsave(port, &flags);
4668412ba1dSJulien Masson
4678412ba1dSJulien Masson if (readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)
4688412ba1dSJulien Masson c = NO_POLL_CHAR;
4698412ba1dSJulien Masson else
4708412ba1dSJulien Masson c = readl(port->membase + AML_UART_RFIFO);
4718412ba1dSJulien Masson
472042d7848SThomas Gleixner uart_port_unlock_irqrestore(port, flags);
4738412ba1dSJulien Masson
4748412ba1dSJulien Masson return c;
4758412ba1dSJulien Masson }
4768412ba1dSJulien Masson
meson_uart_poll_put_char(struct uart_port * port,unsigned char c)4778412ba1dSJulien Masson static void meson_uart_poll_put_char(struct uart_port *port, unsigned char c)
4788412ba1dSJulien Masson {
4798412ba1dSJulien Masson unsigned long flags;
4808412ba1dSJulien Masson u32 reg;
4818412ba1dSJulien Masson int ret;
4828412ba1dSJulien Masson
483042d7848SThomas Gleixner uart_port_lock_irqsave(port, &flags);
4848412ba1dSJulien Masson
4858412ba1dSJulien Masson /* Wait until FIFO is empty or timeout */
4868412ba1dSJulien Masson ret = readl_poll_timeout_atomic(port->membase + AML_UART_STATUS, reg,
4878412ba1dSJulien Masson reg & AML_UART_TX_EMPTY,
4888412ba1dSJulien Masson AML_UART_POLL_USEC,
4898412ba1dSJulien Masson AML_UART_TIMEOUT_USEC);
4908412ba1dSJulien Masson if (ret == -ETIMEDOUT) {
4918412ba1dSJulien Masson dev_err(port->dev, "Timeout waiting for UART TX EMPTY\n");
4928412ba1dSJulien Masson goto out;
4938412ba1dSJulien Masson }
4948412ba1dSJulien Masson
4958412ba1dSJulien Masson /* Write the character */
4968412ba1dSJulien Masson writel(c, port->membase + AML_UART_WFIFO);
4978412ba1dSJulien Masson
4988412ba1dSJulien Masson /* Wait until FIFO is empty or timeout */
4998412ba1dSJulien Masson ret = readl_poll_timeout_atomic(port->membase + AML_UART_STATUS, reg,
5008412ba1dSJulien Masson reg & AML_UART_TX_EMPTY,
5018412ba1dSJulien Masson AML_UART_POLL_USEC,
5028412ba1dSJulien Masson AML_UART_TIMEOUT_USEC);
5038412ba1dSJulien Masson if (ret == -ETIMEDOUT)
5048412ba1dSJulien Masson dev_err(port->dev, "Timeout waiting for UART TX EMPTY\n");
5058412ba1dSJulien Masson
5068412ba1dSJulien Masson out:
507042d7848SThomas Gleixner uart_port_unlock_irqrestore(port, flags);
5088412ba1dSJulien Masson }
5098412ba1dSJulien Masson
5108412ba1dSJulien Masson #endif /* CONFIG_CONSOLE_POLL */
5118412ba1dSJulien Masson
512921469f7SJulia Lawall static const struct uart_ops meson_uart_ops = {
513ff7693d0SCarlo Caione .set_mctrl = meson_uart_set_mctrl,
514ff7693d0SCarlo Caione .get_mctrl = meson_uart_get_mctrl,
515ff7693d0SCarlo Caione .tx_empty = meson_uart_tx_empty,
516ff7693d0SCarlo Caione .start_tx = meson_uart_start_tx,
517ff7693d0SCarlo Caione .stop_tx = meson_uart_stop_tx,
518ff7693d0SCarlo Caione .stop_rx = meson_uart_stop_rx,
519ff7693d0SCarlo Caione .startup = meson_uart_startup,
520ff7693d0SCarlo Caione .shutdown = meson_uart_shutdown,
521ff7693d0SCarlo Caione .set_termios = meson_uart_set_termios,
522ff7693d0SCarlo Caione .type = meson_uart_type,
523ff7693d0SCarlo Caione .config_port = meson_uart_config_port,
524ff7693d0SCarlo Caione .request_port = meson_uart_request_port,
525ff7693d0SCarlo Caione .release_port = meson_uart_release_port,
526ff7693d0SCarlo Caione .verify_port = meson_uart_verify_port,
5278412ba1dSJulien Masson #ifdef CONFIG_CONSOLE_POLL
5288412ba1dSJulien Masson .poll_get_char = meson_uart_poll_get_char,
5298412ba1dSJulien Masson .poll_put_char = meson_uart_poll_put_char,
5308412ba1dSJulien Masson #endif
531ff7693d0SCarlo Caione };
532ff7693d0SCarlo Caione
533ff7693d0SCarlo Caione #ifdef CONFIG_SERIAL_MESON_CONSOLE
meson_uart_enable_tx_engine(struct uart_port * port)5345fa4accfSArnd Bergmann static void meson_uart_enable_tx_engine(struct uart_port *port)
5355fa4accfSArnd Bergmann {
5365fa4accfSArnd Bergmann u32 val;
5375fa4accfSArnd Bergmann
5385fa4accfSArnd Bergmann val = readl(port->membase + AML_UART_CONTROL);
5395fa4accfSArnd Bergmann val |= AML_UART_TX_EN;
5405fa4accfSArnd Bergmann writel(val, port->membase + AML_UART_CONTROL);
5415fa4accfSArnd Bergmann }
542ff7693d0SCarlo Caione
meson_console_putchar(struct uart_port * port,unsigned char ch)5433f8bab17SJiri Slaby static void meson_console_putchar(struct uart_port *port, unsigned char ch)
544ff7693d0SCarlo Caione {
545ff7693d0SCarlo Caione if (!port->membase)
546ff7693d0SCarlo Caione return;
547ff7693d0SCarlo Caione
548ff7693d0SCarlo Caione while (readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)
549ff7693d0SCarlo Caione cpu_relax();
550ff7693d0SCarlo Caione writel(ch, port->membase + AML_UART_WFIFO);
551ff7693d0SCarlo Caione }
552ff7693d0SCarlo Caione
meson_serial_port_write(struct uart_port * port,const char * s,u_int count)553736d5538SAndreas Färber static void meson_serial_port_write(struct uart_port *port, const char *s,
554ff7693d0SCarlo Caione u_int count)
555ff7693d0SCarlo Caione {
556ff7693d0SCarlo Caione unsigned long flags;
557fb793b95SSebastian Andrzej Siewior int locked = 1;
5582561f068SBen Dooks u32 val, tmp;
559ff7693d0SCarlo Caione
560fb793b95SSebastian Andrzej Siewior if (oops_in_progress)
561fb793b95SSebastian Andrzej Siewior locked = uart_port_trylock_irqsave(port, &flags);
562fb793b95SSebastian Andrzej Siewior else
563fb793b95SSebastian Andrzej Siewior uart_port_lock_irqsave(port, &flags);
564ff7693d0SCarlo Caione
56541788f05SBen Dooks val = readl(port->membase + AML_UART_CONTROL);
5662561f068SBen Dooks tmp = val & ~(AML_UART_TX_INT_EN | AML_UART_RX_INT_EN);
5672561f068SBen Dooks writel(tmp, port->membase + AML_UART_CONTROL);
56841788f05SBen Dooks
569ff7693d0SCarlo Caione uart_console_write(port, s, count, meson_console_putchar);
5702561f068SBen Dooks writel(val, port->membase + AML_UART_CONTROL);
571ff7693d0SCarlo Caione
572ff7693d0SCarlo Caione if (locked)
573fb793b95SSebastian Andrzej Siewior uart_port_unlock_irqrestore(port, flags);
574ff7693d0SCarlo Caione }
575ff7693d0SCarlo Caione
meson_serial_console_write(struct console * co,const char * s,u_int count)576736d5538SAndreas Färber static void meson_serial_console_write(struct console *co, const char *s,
577736d5538SAndreas Färber u_int count)
578736d5538SAndreas Färber {
579736d5538SAndreas Färber struct uart_port *port;
580736d5538SAndreas Färber
581736d5538SAndreas Färber port = meson_ports[co->index];
582736d5538SAndreas Färber if (!port)
583736d5538SAndreas Färber return;
584736d5538SAndreas Färber
585736d5538SAndreas Färber meson_serial_port_write(port, s, count);
586736d5538SAndreas Färber }
587736d5538SAndreas Färber
meson_serial_console_setup(struct console * co,char * options)588ff7693d0SCarlo Caione static int meson_serial_console_setup(struct console *co, char *options)
589ff7693d0SCarlo Caione {
590ff7693d0SCarlo Caione struct uart_port *port;
591ff7693d0SCarlo Caione int baud = 115200;
592ff7693d0SCarlo Caione int bits = 8;
593ff7693d0SCarlo Caione int parity = 'n';
594ff7693d0SCarlo Caione int flow = 'n';
595ff7693d0SCarlo Caione
596ff7693d0SCarlo Caione if (co->index < 0 || co->index >= AML_UART_PORT_NUM)
597ff7693d0SCarlo Caione return -EINVAL;
598ff7693d0SCarlo Caione
599ff7693d0SCarlo Caione port = meson_ports[co->index];
600ff7693d0SCarlo Caione if (!port || !port->membase)
601ff7693d0SCarlo Caione return -ENODEV;
602ff7693d0SCarlo Caione
603ba50f1dfSHeiner Kallweit meson_uart_enable_tx_engine(port);
604ba50f1dfSHeiner Kallweit
605ff7693d0SCarlo Caione if (options)
606ff7693d0SCarlo Caione uart_parse_options(options, &baud, &parity, &bits, &flow);
607ff7693d0SCarlo Caione
608ff7693d0SCarlo Caione return uart_set_options(port, co, baud, parity, bits, flow);
609ff7693d0SCarlo Caione }
610ff7693d0SCarlo Caione
61117be181bSDmitry Rokosov #define MESON_SERIAL_CONSOLE(_devname) \
61217be181bSDmitry Rokosov static struct console meson_serial_console_##_devname = { \
613e71aab9dSDmitry Rokosov .name = __stringify(_devname), \
614e71aab9dSDmitry Rokosov .write = meson_serial_console_write, \
615e71aab9dSDmitry Rokosov .device = uart_console_device, \
616e71aab9dSDmitry Rokosov .setup = meson_serial_console_setup, \
617e71aab9dSDmitry Rokosov .flags = CON_PRINTBUFFER, \
618e71aab9dSDmitry Rokosov .index = -1, \
61917be181bSDmitry Rokosov .data = &meson_uart_driver_##_devname, \
620e71aab9dSDmitry Rokosov }
621e71aab9dSDmitry Rokosov
62217be181bSDmitry Rokosov MESON_SERIAL_CONSOLE(ttyAML);
62317be181bSDmitry Rokosov MESON_SERIAL_CONSOLE(ttyS);
624ff7693d0SCarlo Caione
meson_serial_early_console_write(struct console * co,const char * s,u_int count)625736d5538SAndreas Färber static void meson_serial_early_console_write(struct console *co,
626736d5538SAndreas Färber const char *s,
627736d5538SAndreas Färber u_int count)
628736d5538SAndreas Färber {
629736d5538SAndreas Färber struct earlycon_device *dev = co->data;
630736d5538SAndreas Färber
631736d5538SAndreas Färber meson_serial_port_write(&dev->port, s, count);
632736d5538SAndreas Färber }
633736d5538SAndreas Färber
634736d5538SAndreas Färber static int __init
meson_serial_early_console_setup(struct earlycon_device * device,const char * opt)635736d5538SAndreas Färber meson_serial_early_console_setup(struct earlycon_device *device, const char *opt)
636736d5538SAndreas Färber {
637736d5538SAndreas Färber if (!device->port.membase)
638736d5538SAndreas Färber return -ENODEV;
639736d5538SAndreas Färber
640ba50f1dfSHeiner Kallweit meson_uart_enable_tx_engine(&device->port);
641736d5538SAndreas Färber device->con->write = meson_serial_early_console_write;
642736d5538SAndreas Färber return 0;
643736d5538SAndreas Färber }
644ad234e2bSYu Tu
6453047b5b5SLucas Tanure OF_EARLYCON_DECLARE(meson, "amlogic,meson-ao-uart", meson_serial_early_console_setup);
6463047b5b5SLucas Tanure OF_EARLYCON_DECLARE(meson, "amlogic,meson-s4-uart", meson_serial_early_console_setup);
647736d5538SAndreas Färber
64817be181bSDmitry Rokosov #define MESON_SERIAL_CONSOLE_PTR(_devname) (&meson_serial_console_##_devname)
649ff7693d0SCarlo Caione #else
650e71aab9dSDmitry Rokosov #define MESON_SERIAL_CONSOLE_PTR(_devname) (NULL)
651ff7693d0SCarlo Caione #endif
652ff7693d0SCarlo Caione
65317be181bSDmitry Rokosov #define MESON_UART_DRIVER(_devname) \
65417be181bSDmitry Rokosov static struct uart_driver meson_uart_driver_##_devname = { \
655e71aab9dSDmitry Rokosov .owner = THIS_MODULE, \
656e71aab9dSDmitry Rokosov .driver_name = "meson_uart", \
657e71aab9dSDmitry Rokosov .dev_name = __stringify(_devname), \
658e71aab9dSDmitry Rokosov .nr = AML_UART_PORT_NUM, \
659e71aab9dSDmitry Rokosov .cons = MESON_SERIAL_CONSOLE_PTR(_devname), \
660e71aab9dSDmitry Rokosov }
661e71aab9dSDmitry Rokosov
66217be181bSDmitry Rokosov MESON_UART_DRIVER(ttyAML);
66317be181bSDmitry Rokosov MESON_UART_DRIVER(ttyS);
664ff7693d0SCarlo Caione
meson_uart_probe_clocks(struct platform_device * pdev,struct uart_port * port)66516b3ac90SGreg Kroah-Hartman static int meson_uart_probe_clocks(struct platform_device *pdev,
66616b3ac90SGreg Kroah-Hartman struct uart_port *port)
66716b3ac90SGreg Kroah-Hartman {
66816b3ac90SGreg Kroah-Hartman struct clk *clk_xtal = NULL;
66916b3ac90SGreg Kroah-Hartman struct clk *clk_pclk = NULL;
67016b3ac90SGreg Kroah-Hartman struct clk *clk_baud = NULL;
67116b3ac90SGreg Kroah-Hartman
6724f1b576dSChristophe JAILLET clk_pclk = devm_clk_get_enabled(&pdev->dev, "pclk");
67316b3ac90SGreg Kroah-Hartman if (IS_ERR(clk_pclk))
67416b3ac90SGreg Kroah-Hartman return PTR_ERR(clk_pclk);
67516b3ac90SGreg Kroah-Hartman
6764f1b576dSChristophe JAILLET clk_xtal = devm_clk_get_enabled(&pdev->dev, "xtal");
67744023b8eSYu Tu if (IS_ERR(clk_xtal))
67816b3ac90SGreg Kroah-Hartman return PTR_ERR(clk_xtal);
67944023b8eSYu Tu
6804f1b576dSChristophe JAILLET clk_baud = devm_clk_get_enabled(&pdev->dev, "baud");
68116b3ac90SGreg Kroah-Hartman if (IS_ERR(clk_baud))
68216b3ac90SGreg Kroah-Hartman return PTR_ERR(clk_baud);
68344023b8eSYu Tu
68416b3ac90SGreg Kroah-Hartman port->uartclk = clk_get_rate(clk_baud);
6859f60e0e7SHelmut Klein
6869f60e0e7SHelmut Klein return 0;
6879f60e0e7SHelmut Klein }
6889f60e0e7SHelmut Klein
meson_uart_current(const struct meson_uart_data * pd)689e71aab9dSDmitry Rokosov static struct uart_driver *meson_uart_current(const struct meson_uart_data *pd)
690e71aab9dSDmitry Rokosov {
691e71aab9dSDmitry Rokosov return (pd && pd->uart_driver) ?
69217be181bSDmitry Rokosov pd->uart_driver : &meson_uart_driver_ttyAML;
693e71aab9dSDmitry Rokosov }
694e71aab9dSDmitry Rokosov
meson_uart_probe(struct platform_device * pdev)695ff7693d0SCarlo Caione static int meson_uart_probe(struct platform_device *pdev)
696ff7693d0SCarlo Caione {
697e71aab9dSDmitry Rokosov const struct meson_uart_data *priv_data;
698e71aab9dSDmitry Rokosov struct uart_driver *uart_driver;
6995b680619SLad Prabhakar struct resource *res_mem;
700ff7693d0SCarlo Caione struct uart_port *port;
70127d44e05SNeil Armstrong u32 fifosize = 64; /* Default is 64, 128 for EE UART_0 */
702ff7693d0SCarlo Caione int ret = 0;
7035b680619SLad Prabhakar int irq;
7042a1d728fSPavel Krasavin bool has_rtscts;
705ff7693d0SCarlo Caione
706ff7693d0SCarlo Caione if (pdev->dev.of_node)
707ff7693d0SCarlo Caione pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
708ff7693d0SCarlo Caione
709a26988e8SLoys Ollivier if (pdev->id < 0) {
710021212f5SColin Ian King int id;
711021212f5SColin Ian King
712a26988e8SLoys Ollivier for (id = AML_UART_PORT_OFFSET; id < AML_UART_PORT_NUM; id++) {
713a26988e8SLoys Ollivier if (!meson_ports[id]) {
714a26988e8SLoys Ollivier pdev->id = id;
715a26988e8SLoys Ollivier break;
716a26988e8SLoys Ollivier }
717a26988e8SLoys Ollivier }
718a26988e8SLoys Ollivier }
719a26988e8SLoys Ollivier
720ff7693d0SCarlo Caione if (pdev->id < 0 || pdev->id >= AML_UART_PORT_NUM)
721ff7693d0SCarlo Caione return -EINVAL;
722ff7693d0SCarlo Caione
723ff7693d0SCarlo Caione res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
724ff7693d0SCarlo Caione if (!res_mem)
725ff7693d0SCarlo Caione return -ENODEV;
726ff7693d0SCarlo Caione
7275b680619SLad Prabhakar irq = platform_get_irq(pdev, 0);
7285b680619SLad Prabhakar if (irq < 0)
7295b680619SLad Prabhakar return irq;
730ff7693d0SCarlo Caione
73127d44e05SNeil Armstrong of_property_read_u32(pdev->dev.of_node, "fifo-size", &fifosize);
7322a1d728fSPavel Krasavin has_rtscts = of_property_read_bool(pdev->dev.of_node, "uart-has-rtscts");
73327d44e05SNeil Armstrong
734ff7693d0SCarlo Caione if (meson_ports[pdev->id]) {
735b6092f36SDmitry Rokosov return dev_err_probe(&pdev->dev, -EBUSY,
736b6092f36SDmitry Rokosov "port %d already allocated\n", pdev->id);
737ff7693d0SCarlo Caione }
738ff7693d0SCarlo Caione
739ff7693d0SCarlo Caione port = devm_kzalloc(&pdev->dev, sizeof(struct uart_port), GFP_KERNEL);
740ff7693d0SCarlo Caione if (!port)
741ff7693d0SCarlo Caione return -ENOMEM;
742ff7693d0SCarlo Caione
74316b3ac90SGreg Kroah-Hartman ret = meson_uart_probe_clocks(pdev, port);
74416b3ac90SGreg Kroah-Hartman if (ret)
74516b3ac90SGreg Kroah-Hartman return ret;
7469f60e0e7SHelmut Klein
747e71aab9dSDmitry Rokosov priv_data = device_get_match_data(&pdev->dev);
748e71aab9dSDmitry Rokosov
749e71aab9dSDmitry Rokosov uart_driver = meson_uart_current(priv_data);
750e71aab9dSDmitry Rokosov
751e71aab9dSDmitry Rokosov if (!uart_driver->state) {
752e71aab9dSDmitry Rokosov ret = uart_register_driver(uart_driver);
753bcb5645fSDmitry Rokosov if (ret)
754bcb5645fSDmitry Rokosov return dev_err_probe(&pdev->dev, ret,
755bcb5645fSDmitry Rokosov "can't register uart driver\n");
756bcb5645fSDmitry Rokosov }
757bcb5645fSDmitry Rokosov
758ff7693d0SCarlo Caione port->iotype = UPIO_MEM;
759ff7693d0SCarlo Caione port->mapbase = res_mem->start;
760ff3b9cadSHeiner Kallweit port->mapsize = resource_size(res_mem);
7615b680619SLad Prabhakar port->irq = irq;
7621b1ecaa6SHeiner Kallweit port->flags = UPF_BOOT_AUTOCONF | UPF_LOW_LATENCY;
7632a1d728fSPavel Krasavin if (has_rtscts)
7642a1d728fSPavel Krasavin port->flags |= UPF_HARD_FLOW;
765dca3ac8dSDmitry Safonov port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MESON_CONSOLE);
766ff7693d0SCarlo Caione port->dev = &pdev->dev;
767ff7693d0SCarlo Caione port->line = pdev->id;
768ff7693d0SCarlo Caione port->type = PORT_MESON;
769ff7693d0SCarlo Caione port->x_char = 0;
770ff7693d0SCarlo Caione port->ops = &meson_uart_ops;
77127d44e05SNeil Armstrong port->fifosize = fifosize;
772e71aab9dSDmitry Rokosov port->private_data = (void *)priv_data;
773ff7693d0SCarlo Caione
774ff7693d0SCarlo Caione meson_ports[pdev->id] = port;
775ff7693d0SCarlo Caione platform_set_drvdata(pdev, port);
776ff7693d0SCarlo Caione
77700661dd8SBen Dooks /* reset port before registering (and possibly registering console) */
77816b3ac90SGreg Kroah-Hartman if (meson_uart_request_port(port) >= 0) {
77900661dd8SBen Dooks meson_uart_reset(port);
78016b3ac90SGreg Kroah-Hartman meson_uart_release_port(port);
78116b3ac90SGreg Kroah-Hartman }
78200661dd8SBen Dooks
783e71aab9dSDmitry Rokosov ret = uart_add_one_port(uart_driver, port);
784ff7693d0SCarlo Caione if (ret)
785ff7693d0SCarlo Caione meson_ports[pdev->id] = NULL;
786ff7693d0SCarlo Caione
787ff7693d0SCarlo Caione return ret;
788ff7693d0SCarlo Caione }
789ff7693d0SCarlo Caione
meson_uart_remove(struct platform_device * pdev)790c4a5b262SUwe Kleine-König static void meson_uart_remove(struct platform_device *pdev)
791ff7693d0SCarlo Caione {
792e71aab9dSDmitry Rokosov struct uart_driver *uart_driver;
793ff7693d0SCarlo Caione struct uart_port *port;
794ff7693d0SCarlo Caione
795ff7693d0SCarlo Caione port = platform_get_drvdata(pdev);
796e71aab9dSDmitry Rokosov uart_driver = meson_uart_current(port->private_data);
797e71aab9dSDmitry Rokosov uart_remove_one_port(uart_driver, port);
798ff7693d0SCarlo Caione meson_ports[pdev->id] = NULL;
799ff7693d0SCarlo Caione
800bcb5645fSDmitry Rokosov for (int id = 0; id < AML_UART_PORT_NUM; id++)
801bcb5645fSDmitry Rokosov if (meson_ports[id])
802c4a5b262SUwe Kleine-König return;
803bcb5645fSDmitry Rokosov
804bcb5645fSDmitry Rokosov /* No more available uart ports, unregister uart driver */
805e71aab9dSDmitry Rokosov uart_unregister_driver(uart_driver);
806ff7693d0SCarlo Caione }
807ff7693d0SCarlo Caione
808804e6d69SMartin Blumenstingl static struct meson_uart_data meson_g12a_uart_data = {
8099b92cc5eSYu Tu .has_xtal_div2 = true,
8109b92cc5eSYu Tu };
8119b92cc5eSYu Tu
8125651f657SDmitry Rokosov static struct meson_uart_data meson_a1_uart_data = {
81317be181bSDmitry Rokosov .uart_driver = &meson_uart_driver_ttyS,
8145651f657SDmitry Rokosov .has_xtal_div2 = false,
8155651f657SDmitry Rokosov };
8165651f657SDmitry Rokosov
817bd86980bSDmitry Rokosov static struct meson_uart_data meson_s4_uart_data = {
81817be181bSDmitry Rokosov .uart_driver = &meson_uart_driver_ttyS,
819bd86980bSDmitry Rokosov .has_xtal_div2 = true,
820bd86980bSDmitry Rokosov };
821bd86980bSDmitry Rokosov
822ff7693d0SCarlo Caione static const struct of_device_id meson_uart_dt_match[] = {
82316b3ac90SGreg Kroah-Hartman { .compatible = "amlogic,meson6-uart" },
82416b3ac90SGreg Kroah-Hartman { .compatible = "amlogic,meson8-uart" },
82516b3ac90SGreg Kroah-Hartman { .compatible = "amlogic,meson8b-uart" },
82616b3ac90SGreg Kroah-Hartman { .compatible = "amlogic,meson-gx-uart" },
8279b92cc5eSYu Tu {
828804e6d69SMartin Blumenstingl .compatible = "amlogic,meson-g12a-uart",
829804e6d69SMartin Blumenstingl .data = (void *)&meson_g12a_uart_data,
830804e6d69SMartin Blumenstingl },
831804e6d69SMartin Blumenstingl {
8329b92cc5eSYu Tu .compatible = "amlogic,meson-s4-uart",
833bd86980bSDmitry Rokosov .data = (void *)&meson_s4_uart_data,
8349b92cc5eSYu Tu },
8355651f657SDmitry Rokosov {
8365651f657SDmitry Rokosov .compatible = "amlogic,meson-a1-uart",
8375651f657SDmitry Rokosov .data = (void *)&meson_a1_uart_data,
8385651f657SDmitry Rokosov },
839ff7693d0SCarlo Caione { /* sentinel */ },
840ff7693d0SCarlo Caione };
841ff7693d0SCarlo Caione MODULE_DEVICE_TABLE(of, meson_uart_dt_match);
842ff7693d0SCarlo Caione
843ff7693d0SCarlo Caione static struct platform_driver meson_uart_platform_driver = {
844ff7693d0SCarlo Caione .probe = meson_uart_probe,
845c4a5b262SUwe Kleine-König .remove_new = meson_uart_remove,
846ff7693d0SCarlo Caione .driver = {
847ff7693d0SCarlo Caione .name = "meson_uart",
848ff7693d0SCarlo Caione .of_match_table = meson_uart_dt_match,
849ff7693d0SCarlo Caione },
850ff7693d0SCarlo Caione };
851ff7693d0SCarlo Caione
852bcb5645fSDmitry Rokosov module_platform_driver(meson_uart_platform_driver);
853ff7693d0SCarlo Caione
854ff7693d0SCarlo Caione MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
855ff7693d0SCarlo Caione MODULE_DESCRIPTION("Amlogic Meson serial port driver");
856ff7693d0SCarlo Caione MODULE_LICENSE("GPL v2");
857