1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 4 */ 5 #include <linux/kernel.h> 6 #include <linux/serial.h> 7 #include <linux/serial_reg.h> 8 #include <linux/slab.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 #include <linux/console.h> 12 #include <linux/serial_core.h> 13 #include <linux/tty.h> 14 #include <linux/tty_flip.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/dmi.h> 18 #include <linux/nmi.h> 19 #include <linux/delay.h> 20 #include <linux/of.h> 21 22 #include <linux/debugfs.h> 23 #include <linux/dmaengine.h> 24 #include <linux/pch_dma.h> 25 26 enum { 27 PCH_UART_HANDLED_RX_INT_SHIFT, 28 PCH_UART_HANDLED_TX_INT_SHIFT, 29 PCH_UART_HANDLED_RX_ERR_INT_SHIFT, 30 PCH_UART_HANDLED_RX_TRG_INT_SHIFT, 31 PCH_UART_HANDLED_MS_INT_SHIFT, 32 PCH_UART_HANDLED_LS_INT_SHIFT, 33 }; 34 35 #define PCH_UART_DRIVER_DEVICE "ttyPCH" 36 37 /* Set the max number of UART port 38 * Intel EG20T PCH: 4 port 39 * LAPIS Semiconductor ML7213 IOH: 3 port 40 * LAPIS Semiconductor ML7223 IOH: 2 port 41 */ 42 #define PCH_UART_NR 4 43 44 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1)) 45 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1)) 46 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\ 47 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1)) 48 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\ 49 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1)) 50 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1)) 51 52 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1)) 53 54 #define PCH_UART_RBR 0x00 55 #define PCH_UART_THR 0x00 56 57 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\ 58 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI) 59 #define PCH_UART_IER_ERBFI 0x00000001 60 #define PCH_UART_IER_ETBEI 0x00000002 61 #define PCH_UART_IER_ELSI 0x00000004 62 #define PCH_UART_IER_EDSSI 0x00000008 63 64 #define PCH_UART_IIR_IP 0x00000001 65 #define PCH_UART_IIR_IID 0x00000006 66 #define PCH_UART_IIR_MSI 0x00000000 67 #define PCH_UART_IIR_TRI 0x00000002 68 #define PCH_UART_IIR_RRI 0x00000004 69 #define PCH_UART_IIR_REI 0x00000006 70 #define PCH_UART_IIR_TOI 0x00000008 71 #define PCH_UART_IIR_FIFO256 0x00000020 72 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256 73 #define PCH_UART_IIR_FE 0x000000C0 74 75 #define PCH_UART_FCR_FIFOE 0x00000001 76 #define PCH_UART_FCR_RFR 0x00000002 77 #define PCH_UART_FCR_TFR 0x00000004 78 #define PCH_UART_FCR_DMS 0x00000008 79 #define PCH_UART_FCR_FIFO256 0x00000020 80 #define PCH_UART_FCR_RFTL 0x000000C0 81 82 #define PCH_UART_FCR_RFTL1 0x00000000 83 #define PCH_UART_FCR_RFTL64 0x00000040 84 #define PCH_UART_FCR_RFTL128 0x00000080 85 #define PCH_UART_FCR_RFTL224 0x000000C0 86 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64 87 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128 88 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224 89 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64 90 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128 91 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224 92 #define PCH_UART_FCR_RFTL_SHIFT 6 93 94 #define PCH_UART_LCR_WLS 0x00000003 95 #define PCH_UART_LCR_STB 0x00000004 96 #define PCH_UART_LCR_PEN 0x00000008 97 #define PCH_UART_LCR_EPS 0x00000010 98 #define PCH_UART_LCR_SP 0x00000020 99 #define PCH_UART_LCR_SB 0x00000040 100 #define PCH_UART_LCR_DLAB 0x00000080 101 #define PCH_UART_LCR_NP 0x00000000 102 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN 103 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS) 104 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP) 105 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\ 106 PCH_UART_LCR_SP) 107 108 #define PCH_UART_LCR_5BIT 0x00000000 109 #define PCH_UART_LCR_6BIT 0x00000001 110 #define PCH_UART_LCR_7BIT 0x00000002 111 #define PCH_UART_LCR_8BIT 0x00000003 112 113 #define PCH_UART_MCR_DTR 0x00000001 114 #define PCH_UART_MCR_RTS 0x00000002 115 #define PCH_UART_MCR_OUT 0x0000000C 116 #define PCH_UART_MCR_LOOP 0x00000010 117 #define PCH_UART_MCR_AFE 0x00000020 118 119 #define PCH_UART_LSR_DR 0x00000001 120 #define PCH_UART_LSR_ERR (1<<7) 121 122 #define PCH_UART_MSR_DCTS 0x00000001 123 #define PCH_UART_MSR_DDSR 0x00000002 124 #define PCH_UART_MSR_TERI 0x00000004 125 #define PCH_UART_MSR_DDCD 0x00000008 126 #define PCH_UART_MSR_CTS 0x00000010 127 #define PCH_UART_MSR_DSR 0x00000020 128 #define PCH_UART_MSR_RI 0x00000040 129 #define PCH_UART_MSR_DCD 0x00000080 130 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\ 131 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD) 132 133 #define PCH_UART_DLL 0x00 134 #define PCH_UART_DLM 0x01 135 136 #define PCH_UART_BRCSR 0x0E 137 138 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI) 139 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI) 140 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI) 141 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI) 142 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI) 143 144 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP) 145 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP) 146 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP) 147 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P) 148 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P) 149 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT) 150 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT) 151 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT) 152 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT) 153 #define PCH_UART_HAL_STB1 0 154 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB) 155 156 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR) 157 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR) 158 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \ 159 PCH_UART_HAL_CLR_RX_FIFO) 160 161 #define PCH_UART_HAL_DMA_MODE0 0 162 #define PCH_UART_HAL_FIFO_DIS 0 163 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE) 164 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \ 165 PCH_UART_FCR_FIFO256) 166 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256) 167 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1) 168 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64) 169 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128) 170 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224) 171 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16) 172 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32) 173 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56) 174 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4) 175 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8) 176 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14) 177 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64) 178 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128) 179 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224) 180 181 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI) 182 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI) 183 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI) 184 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI) 185 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK) 186 187 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR) 188 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS) 189 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT) 190 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP) 191 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE) 192 193 #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */ 194 #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */ 195 #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */ 196 #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */ 197 #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */ 198 #define MINNOW_UARTCLK 50000000 /* 50.0000 MHz */ 199 200 struct pch_uart_buffer { 201 unsigned char *buf; 202 int size; 203 }; 204 205 struct eg20t_port { 206 struct uart_port port; 207 int port_type; 208 void __iomem *membase; 209 resource_size_t mapbase; 210 unsigned int iobase; 211 struct pci_dev *pdev; 212 int fifo_size; 213 unsigned int uartclk; 214 int start_tx; 215 int start_rx; 216 int tx_empty; 217 int trigger; 218 int trigger_level; 219 struct pch_uart_buffer rxbuf; 220 unsigned int dmsr; 221 unsigned int fcr; 222 unsigned int mcr; 223 unsigned int use_dma; 224 struct dma_async_tx_descriptor *desc_tx; 225 struct dma_async_tx_descriptor *desc_rx; 226 struct pch_dma_slave param_tx; 227 struct pch_dma_slave param_rx; 228 struct dma_chan *chan_tx; 229 struct dma_chan *chan_rx; 230 struct scatterlist *sg_tx_p; 231 int nent; 232 int orig_nent; 233 struct scatterlist sg_rx; 234 int tx_dma_use; 235 void *rx_buf_virt; 236 dma_addr_t rx_buf_dma; 237 238 #define IRQ_NAME_SIZE 17 239 char irq_name[IRQ_NAME_SIZE]; 240 }; 241 242 /** 243 * struct pch_uart_driver_data - private data structure for UART-DMA 244 * @port_type: The type of UART port 245 * @line_no: UART port line number (0, 1, 2...) 246 */ 247 struct pch_uart_driver_data { 248 int port_type; 249 int line_no; 250 }; 251 252 enum pch_uart_num_t { 253 pch_et20t_uart0 = 0, 254 pch_et20t_uart1, 255 pch_et20t_uart2, 256 pch_et20t_uart3, 257 pch_ml7213_uart0, 258 pch_ml7213_uart1, 259 pch_ml7213_uart2, 260 pch_ml7223_uart0, 261 pch_ml7223_uart1, 262 pch_ml7831_uart0, 263 pch_ml7831_uart1, 264 }; 265 266 static struct pch_uart_driver_data drv_dat[] = { 267 [pch_et20t_uart0] = {PORT_PCH_8LINE, 0}, 268 [pch_et20t_uart1] = {PORT_PCH_2LINE, 1}, 269 [pch_et20t_uart2] = {PORT_PCH_2LINE, 2}, 270 [pch_et20t_uart3] = {PORT_PCH_2LINE, 3}, 271 [pch_ml7213_uart0] = {PORT_PCH_8LINE, 0}, 272 [pch_ml7213_uart1] = {PORT_PCH_2LINE, 1}, 273 [pch_ml7213_uart2] = {PORT_PCH_2LINE, 2}, 274 [pch_ml7223_uart0] = {PORT_PCH_8LINE, 0}, 275 [pch_ml7223_uart1] = {PORT_PCH_2LINE, 1}, 276 [pch_ml7831_uart0] = {PORT_PCH_8LINE, 0}, 277 [pch_ml7831_uart1] = {PORT_PCH_2LINE, 1}, 278 }; 279 280 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 281 static struct eg20t_port *pch_uart_ports[PCH_UART_NR]; 282 #endif 283 static unsigned int default_baud = 9600; 284 static unsigned int user_uartclk = 0; 285 static const int trigger_level_256[4] = { 1, 64, 128, 224 }; 286 static const int trigger_level_64[4] = { 1, 16, 32, 56 }; 287 static const int trigger_level_16[4] = { 1, 4, 8, 14 }; 288 static const int trigger_level_1[4] = { 1, 1, 1, 1 }; 289 290 #define PCH_REGS_BUFSIZE 1024 291 292 293 static ssize_t port_show_regs(struct file *file, char __user *user_buf, 294 size_t count, loff_t *ppos) 295 { 296 struct eg20t_port *priv = file->private_data; 297 char *buf; 298 u32 len = 0; 299 ssize_t ret; 300 unsigned char lcr; 301 302 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL); 303 if (!buf) 304 return 0; 305 306 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 307 "PCH EG20T port[%d] regs:\n", priv->port.line); 308 309 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 310 "=================================\n"); 311 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 312 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER)); 313 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 314 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR)); 315 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 316 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR)); 317 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 318 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR)); 319 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 320 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR)); 321 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 322 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR)); 323 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 324 "BRCSR: \t0x%02x\n", 325 ioread8(priv->membase + PCH_UART_BRCSR)); 326 327 lcr = ioread8(priv->membase + UART_LCR); 328 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 329 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 330 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL)); 331 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 332 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM)); 333 iowrite8(lcr, priv->membase + UART_LCR); 334 335 if (len > PCH_REGS_BUFSIZE) 336 len = PCH_REGS_BUFSIZE; 337 338 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); 339 kfree(buf); 340 return ret; 341 } 342 343 static const struct file_operations port_regs_ops = { 344 .owner = THIS_MODULE, 345 .open = simple_open, 346 .read = port_show_regs, 347 .llseek = default_llseek, 348 }; 349 350 static const struct dmi_system_id pch_uart_dmi_table[] = { 351 { 352 .ident = "CM-iTC", 353 { 354 DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"), 355 }, 356 (void *)CMITC_UARTCLK, 357 }, 358 { 359 .ident = "FRI2", 360 { 361 DMI_MATCH(DMI_BIOS_VERSION, "FRI2"), 362 }, 363 (void *)FRI2_64_UARTCLK, 364 }, 365 { 366 .ident = "Fish River Island II", 367 { 368 DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"), 369 }, 370 (void *)FRI2_48_UARTCLK, 371 }, 372 { 373 .ident = "COMe-mTT", 374 { 375 DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"), 376 }, 377 (void *)NTC1_UARTCLK, 378 }, 379 { 380 .ident = "nanoETXexpress-TT", 381 { 382 DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"), 383 }, 384 (void *)NTC1_UARTCLK, 385 }, 386 { 387 .ident = "MinnowBoard", 388 { 389 DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"), 390 }, 391 (void *)MINNOW_UARTCLK, 392 }, 393 { } 394 }; 395 396 /* Return UART clock, checking for board specific clocks. */ 397 static unsigned int pch_uart_get_uartclk(void) 398 { 399 const struct dmi_system_id *d; 400 401 if (user_uartclk) 402 return user_uartclk; 403 404 d = dmi_first_match(pch_uart_dmi_table); 405 if (d) 406 return (unsigned long)d->driver_data; 407 408 return DEFAULT_UARTCLK; 409 } 410 411 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv, 412 unsigned int flag) 413 { 414 u8 ier = ioread8(priv->membase + UART_IER); 415 ier |= flag & PCH_UART_IER_MASK; 416 iowrite8(ier, priv->membase + UART_IER); 417 } 418 419 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv, 420 unsigned int flag) 421 { 422 u8 ier = ioread8(priv->membase + UART_IER); 423 ier &= ~(flag & PCH_UART_IER_MASK); 424 iowrite8(ier, priv->membase + UART_IER); 425 } 426 427 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud, 428 unsigned int parity, unsigned int bits, 429 unsigned int stb) 430 { 431 unsigned int dll, dlm, lcr; 432 int div; 433 434 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud); 435 if (div < 0 || USHRT_MAX <= div) { 436 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div); 437 return -EINVAL; 438 } 439 440 dll = (unsigned int)div & 0x00FFU; 441 dlm = ((unsigned int)div >> 8) & 0x00FFU; 442 443 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) { 444 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity); 445 return -EINVAL; 446 } 447 448 if (bits & ~PCH_UART_LCR_WLS) { 449 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits); 450 return -EINVAL; 451 } 452 453 if (stb & ~PCH_UART_LCR_STB) { 454 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb); 455 return -EINVAL; 456 } 457 458 lcr = parity; 459 lcr |= bits; 460 lcr |= stb; 461 462 dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n", 463 __func__, baud, div, lcr, jiffies); 464 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 465 iowrite8(dll, priv->membase + PCH_UART_DLL); 466 iowrite8(dlm, priv->membase + PCH_UART_DLM); 467 iowrite8(lcr, priv->membase + UART_LCR); 468 469 return 0; 470 } 471 472 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv, 473 unsigned int flag) 474 { 475 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) { 476 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n", 477 __func__, flag); 478 return -EINVAL; 479 } 480 481 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); 482 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, 483 priv->membase + UART_FCR); 484 iowrite8(priv->fcr, priv->membase + UART_FCR); 485 486 return 0; 487 } 488 489 static int pch_uart_hal_set_fifo(struct eg20t_port *priv, 490 unsigned int dmamode, 491 unsigned int fifo_size, unsigned int trigger) 492 { 493 u8 fcr; 494 495 if (dmamode & ~PCH_UART_FCR_DMS) { 496 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n", 497 __func__, dmamode); 498 return -EINVAL; 499 } 500 501 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) { 502 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n", 503 __func__, fifo_size); 504 return -EINVAL; 505 } 506 507 if (trigger & ~PCH_UART_FCR_RFTL) { 508 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n", 509 __func__, trigger); 510 return -EINVAL; 511 } 512 513 switch (priv->fifo_size) { 514 case 256: 515 priv->trigger_level = 516 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 517 break; 518 case 64: 519 priv->trigger_level = 520 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 521 break; 522 case 16: 523 priv->trigger_level = 524 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 525 break; 526 default: 527 priv->trigger_level = 528 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 529 break; 530 } 531 fcr = 532 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR; 533 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); 534 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR, 535 priv->membase + UART_FCR); 536 iowrite8(fcr, priv->membase + UART_FCR); 537 priv->fcr = fcr; 538 539 return 0; 540 } 541 542 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv) 543 { 544 unsigned int msr = ioread8(priv->membase + UART_MSR); 545 priv->dmsr = msr & PCH_UART_MSR_DELTA; 546 return (u8)msr; 547 } 548 549 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf, 550 int rx_size) 551 { 552 int i; 553 u8 rbr, lsr; 554 struct uart_port *port = &priv->port; 555 556 lsr = ioread8(priv->membase + UART_LSR); 557 for (i = 0, lsr = ioread8(priv->membase + UART_LSR); 558 i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI); 559 lsr = ioread8(priv->membase + UART_LSR)) { 560 rbr = ioread8(priv->membase + PCH_UART_RBR); 561 562 if (lsr & UART_LSR_BI) { 563 port->icount.brk++; 564 if (uart_handle_break(port)) 565 continue; 566 } 567 if (uart_prepare_sysrq_char(port, rbr)) 568 continue; 569 570 buf[i++] = rbr; 571 } 572 return i; 573 } 574 575 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv) 576 { 577 return ioread8(priv->membase + UART_IIR) &\ 578 (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP); 579 } 580 581 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv) 582 { 583 return ioread8(priv->membase + UART_LSR); 584 } 585 586 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on) 587 { 588 unsigned int lcr; 589 590 lcr = ioread8(priv->membase + UART_LCR); 591 if (on) 592 lcr |= PCH_UART_LCR_SB; 593 else 594 lcr &= ~PCH_UART_LCR_SB; 595 596 iowrite8(lcr, priv->membase + UART_LCR); 597 } 598 599 static void push_rx(struct eg20t_port *priv, const unsigned char *buf, 600 int size) 601 { 602 struct uart_port *port = &priv->port; 603 struct tty_port *tport = &port->state->port; 604 605 tty_insert_flip_string(tport, buf, size); 606 tty_flip_buffer_push(tport); 607 } 608 609 static int dma_push_rx(struct eg20t_port *priv, int size) 610 { 611 int room; 612 struct uart_port *port = &priv->port; 613 struct tty_port *tport = &port->state->port; 614 615 room = tty_buffer_request_room(tport, size); 616 617 if (room < size) 618 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", 619 size - room); 620 if (!room) 621 return 0; 622 623 tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size); 624 625 port->icount.rx += room; 626 627 return room; 628 } 629 630 static void pch_free_dma(struct uart_port *port) 631 { 632 struct eg20t_port *priv; 633 priv = container_of(port, struct eg20t_port, port); 634 635 if (priv->chan_tx) { 636 dma_release_channel(priv->chan_tx); 637 priv->chan_tx = NULL; 638 } 639 if (priv->chan_rx) { 640 dma_release_channel(priv->chan_rx); 641 priv->chan_rx = NULL; 642 } 643 644 if (priv->rx_buf_dma) { 645 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt, 646 priv->rx_buf_dma); 647 priv->rx_buf_virt = NULL; 648 priv->rx_buf_dma = 0; 649 } 650 651 return; 652 } 653 654 static bool filter(struct dma_chan *chan, void *slave) 655 { 656 struct pch_dma_slave *param = slave; 657 658 if ((chan->chan_id == param->chan_id) && (param->dma_dev == 659 chan->device->dev)) { 660 chan->private = param; 661 return true; 662 } else { 663 return false; 664 } 665 } 666 667 static void pch_request_dma(struct uart_port *port) 668 { 669 dma_cap_mask_t mask; 670 struct dma_chan *chan; 671 struct pci_dev *dma_dev; 672 struct pch_dma_slave *param; 673 struct eg20t_port *priv = 674 container_of(port, struct eg20t_port, port); 675 dma_cap_zero(mask); 676 dma_cap_set(DMA_SLAVE, mask); 677 678 /* Get DMA's dev information */ 679 dma_dev = pci_get_slot(priv->pdev->bus, 680 PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0)); 681 682 /* Set Tx DMA */ 683 param = &priv->param_tx; 684 param->dma_dev = &dma_dev->dev; 685 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */ 686 687 param->tx_reg = port->mapbase + UART_TX; 688 chan = dma_request_channel(mask, filter, param); 689 if (!chan) { 690 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n", 691 __func__); 692 pci_dev_put(dma_dev); 693 return; 694 } 695 priv->chan_tx = chan; 696 697 /* Set Rx DMA */ 698 param = &priv->param_rx; 699 param->dma_dev = &dma_dev->dev; 700 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */ 701 702 param->rx_reg = port->mapbase + UART_RX; 703 chan = dma_request_channel(mask, filter, param); 704 if (!chan) { 705 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n", 706 __func__); 707 dma_release_channel(priv->chan_tx); 708 priv->chan_tx = NULL; 709 pci_dev_put(dma_dev); 710 return; 711 } 712 713 /* Get Consistent memory for DMA */ 714 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, 715 &priv->rx_buf_dma, GFP_KERNEL); 716 priv->chan_rx = chan; 717 718 pci_dev_put(dma_dev); 719 } 720 721 static void pch_dma_rx_complete(void *arg) 722 { 723 struct eg20t_port *priv = arg; 724 struct uart_port *port = &priv->port; 725 int count; 726 727 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE); 728 count = dma_push_rx(priv, priv->trigger_level); 729 if (count) 730 tty_flip_buffer_push(&port->state->port); 731 async_tx_ack(priv->desc_rx); 732 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | 733 PCH_UART_HAL_RX_ERR_INT); 734 } 735 736 static void pch_dma_tx_complete(void *arg) 737 { 738 struct eg20t_port *priv = arg; 739 struct uart_port *port = &priv->port; 740 struct scatterlist *sg = priv->sg_tx_p; 741 int i; 742 743 for (i = 0; i < priv->nent; i++, sg++) 744 uart_xmit_advance(port, sg_dma_len(sg)); 745 746 async_tx_ack(priv->desc_tx); 747 dma_unmap_sg(port->dev, priv->sg_tx_p, priv->orig_nent, DMA_TO_DEVICE); 748 priv->tx_dma_use = 0; 749 priv->nent = 0; 750 priv->orig_nent = 0; 751 kfree(priv->sg_tx_p); 752 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 753 } 754 755 static int handle_rx_to(struct eg20t_port *priv) 756 { 757 struct pch_uart_buffer *buf; 758 int rx_size; 759 760 if (!priv->start_rx) { 761 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | 762 PCH_UART_HAL_RX_ERR_INT); 763 return 0; 764 } 765 buf = &priv->rxbuf; 766 do { 767 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size); 768 push_rx(priv, buf->buf, rx_size); 769 } while (rx_size == buf->size); 770 771 return PCH_UART_HANDLED_RX_INT; 772 } 773 774 static int dma_handle_rx(struct eg20t_port *priv) 775 { 776 struct uart_port *port = &priv->port; 777 struct dma_async_tx_descriptor *desc; 778 struct scatterlist *sg; 779 780 priv = container_of(port, struct eg20t_port, port); 781 sg = &priv->sg_rx; 782 783 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */ 784 785 sg_dma_len(sg) = priv->trigger_level; 786 787 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt), 788 sg_dma_len(sg), offset_in_page(priv->rx_buf_virt)); 789 790 sg_dma_address(sg) = priv->rx_buf_dma; 791 792 desc = dmaengine_prep_slave_sg(priv->chan_rx, 793 sg, 1, DMA_DEV_TO_MEM, 794 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 795 796 if (!desc) 797 return 0; 798 799 priv->desc_rx = desc; 800 desc->callback = pch_dma_rx_complete; 801 desc->callback_param = priv; 802 desc->tx_submit(desc); 803 dma_async_issue_pending(priv->chan_rx); 804 805 return PCH_UART_HANDLED_RX_INT; 806 } 807 808 static unsigned int handle_tx(struct eg20t_port *priv) 809 { 810 struct uart_port *port = &priv->port; 811 struct circ_buf *xmit = &port->state->xmit; 812 int fifo_size; 813 int tx_empty; 814 815 if (!priv->start_tx) { 816 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 817 __func__, jiffies); 818 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 819 priv->tx_empty = 1; 820 return 0; 821 } 822 823 fifo_size = max(priv->fifo_size, 1); 824 tx_empty = 1; 825 if (port->x_char) { 826 iowrite8(port->x_char, priv->membase + PCH_UART_THR); 827 port->icount.tx++; 828 port->x_char = 0; 829 tx_empty = 0; 830 fifo_size--; 831 } 832 833 while (!uart_tx_stopped(port) && !uart_circ_empty(xmit) && fifo_size) { 834 iowrite8(xmit->buf[xmit->tail], priv->membase + PCH_UART_THR); 835 uart_xmit_advance(port, 1); 836 fifo_size--; 837 tx_empty = 0; 838 } 839 840 priv->tx_empty = tx_empty; 841 842 if (tx_empty) { 843 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 844 uart_write_wakeup(port); 845 } 846 847 return PCH_UART_HANDLED_TX_INT; 848 } 849 850 static unsigned int dma_handle_tx(struct eg20t_port *priv) 851 { 852 struct uart_port *port = &priv->port; 853 struct circ_buf *xmit = &port->state->xmit; 854 struct scatterlist *sg; 855 int nent; 856 int fifo_size; 857 struct dma_async_tx_descriptor *desc; 858 int num; 859 int i; 860 int bytes; 861 int size; 862 int rem; 863 864 if (!priv->start_tx) { 865 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 866 __func__, jiffies); 867 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 868 priv->tx_empty = 1; 869 return 0; 870 } 871 872 if (priv->tx_dma_use) { 873 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n", 874 __func__, jiffies); 875 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 876 priv->tx_empty = 1; 877 return 0; 878 } 879 880 fifo_size = max(priv->fifo_size, 1); 881 882 if (port->x_char) { 883 iowrite8(port->x_char, priv->membase + PCH_UART_THR); 884 port->icount.tx++; 885 port->x_char = 0; 886 fifo_size--; 887 } 888 889 bytes = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 890 if (!bytes) { 891 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__); 892 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 893 uart_write_wakeup(port); 894 return 0; 895 } 896 897 if (bytes > fifo_size) { 898 num = bytes / fifo_size + 1; 899 size = fifo_size; 900 rem = bytes % fifo_size; 901 } else { 902 num = 1; 903 size = bytes; 904 rem = bytes; 905 } 906 907 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n", 908 __func__, num, size, rem); 909 910 priv->tx_dma_use = 1; 911 912 priv->sg_tx_p = kmalloc_array(num, sizeof(struct scatterlist), GFP_ATOMIC); 913 if (!priv->sg_tx_p) { 914 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__); 915 return 0; 916 } 917 918 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ 919 sg = priv->sg_tx_p; 920 921 for (i = 0; i < num; i++, sg++) { 922 if (i == (num - 1)) 923 sg_set_page(sg, virt_to_page(xmit->buf), 924 rem, fifo_size * i); 925 else 926 sg_set_page(sg, virt_to_page(xmit->buf), 927 size, fifo_size * i); 928 } 929 930 sg = priv->sg_tx_p; 931 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE); 932 if (!nent) { 933 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__); 934 return 0; 935 } 936 priv->orig_nent = num; 937 priv->nent = nent; 938 939 for (i = 0; i < nent; i++, sg++) { 940 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) + 941 fifo_size * i; 942 sg_dma_address(sg) = (sg_dma_address(sg) & 943 ~(UART_XMIT_SIZE - 1)) + sg->offset; 944 if (i == (nent - 1)) 945 sg_dma_len(sg) = rem; 946 else 947 sg_dma_len(sg) = size; 948 } 949 950 desc = dmaengine_prep_slave_sg(priv->chan_tx, 951 priv->sg_tx_p, nent, DMA_MEM_TO_DEV, 952 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 953 if (!desc) { 954 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n", 955 __func__); 956 return 0; 957 } 958 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE); 959 priv->desc_tx = desc; 960 desc->callback = pch_dma_tx_complete; 961 desc->callback_param = priv; 962 963 desc->tx_submit(desc); 964 965 dma_async_issue_pending(priv->chan_tx); 966 967 return PCH_UART_HANDLED_TX_INT; 968 } 969 970 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr) 971 { 972 struct uart_port *port = &priv->port; 973 struct tty_struct *tty = tty_port_tty_get(&port->state->port); 974 char *error_msg[5] = {}; 975 int i = 0; 976 977 if (lsr & PCH_UART_LSR_ERR) 978 error_msg[i++] = "Error data in FIFO\n"; 979 980 if (lsr & UART_LSR_FE) { 981 port->icount.frame++; 982 error_msg[i++] = " Framing Error\n"; 983 } 984 985 if (lsr & UART_LSR_PE) { 986 port->icount.parity++; 987 error_msg[i++] = " Parity Error\n"; 988 } 989 990 if (lsr & UART_LSR_OE) { 991 port->icount.overrun++; 992 error_msg[i++] = " Overrun Error\n"; 993 } 994 995 if (tty == NULL) { 996 for (i = 0; error_msg[i] != NULL; i++) 997 dev_err(&priv->pdev->dev, error_msg[i]); 998 } else { 999 tty_kref_put(tty); 1000 } 1001 } 1002 1003 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id) 1004 { 1005 struct eg20t_port *priv = dev_id; 1006 unsigned int handled; 1007 u8 lsr; 1008 int ret = 0; 1009 unsigned char iid; 1010 int next = 1; 1011 u8 msr; 1012 1013 uart_port_lock(&priv->port); 1014 handled = 0; 1015 while (next) { 1016 iid = pch_uart_hal_get_iid(priv); 1017 if (iid & PCH_UART_IIR_IP) /* No Interrupt */ 1018 break; 1019 switch (iid) { 1020 case PCH_UART_IID_RLS: /* Receiver Line Status */ 1021 lsr = pch_uart_hal_get_line_status(priv); 1022 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE | 1023 UART_LSR_PE | UART_LSR_OE)) { 1024 pch_uart_err_ir(priv, lsr); 1025 ret = PCH_UART_HANDLED_RX_ERR_INT; 1026 } else { 1027 ret = PCH_UART_HANDLED_LS_INT; 1028 } 1029 break; 1030 case PCH_UART_IID_RDR: /* Received Data Ready */ 1031 if (priv->use_dma) { 1032 pch_uart_hal_disable_interrupt(priv, 1033 PCH_UART_HAL_RX_INT | 1034 PCH_UART_HAL_RX_ERR_INT); 1035 ret = dma_handle_rx(priv); 1036 if (!ret) 1037 pch_uart_hal_enable_interrupt(priv, 1038 PCH_UART_HAL_RX_INT | 1039 PCH_UART_HAL_RX_ERR_INT); 1040 } else { 1041 ret = handle_rx_to(priv); 1042 } 1043 break; 1044 case PCH_UART_IID_RDR_TO: /* Received Data Ready 1045 (FIFO Timeout) */ 1046 ret = handle_rx_to(priv); 1047 break; 1048 case PCH_UART_IID_THRE: /* Transmitter Holding Register 1049 Empty */ 1050 if (priv->use_dma) 1051 ret = dma_handle_tx(priv); 1052 else 1053 ret = handle_tx(priv); 1054 break; 1055 case PCH_UART_IID_MS: /* Modem Status */ 1056 msr = pch_uart_hal_get_modem(priv); 1057 next = 0; /* MS ir prioirty is the lowest. So, MS ir 1058 means final interrupt */ 1059 if ((msr & UART_MSR_ANY_DELTA) == 0) 1060 break; 1061 ret |= PCH_UART_HANDLED_MS_INT; 1062 break; 1063 default: /* Never junp to this label */ 1064 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__, 1065 iid, jiffies); 1066 ret = -1; 1067 next = 0; 1068 break; 1069 } 1070 handled |= (unsigned int)ret; 1071 } 1072 1073 uart_unlock_and_check_sysrq(&priv->port); 1074 return IRQ_RETVAL(handled); 1075 } 1076 1077 /* This function tests whether the transmitter fifo and shifter for the port 1078 described by 'port' is empty. */ 1079 static unsigned int pch_uart_tx_empty(struct uart_port *port) 1080 { 1081 struct eg20t_port *priv; 1082 1083 priv = container_of(port, struct eg20t_port, port); 1084 if (priv->tx_empty) 1085 return TIOCSER_TEMT; 1086 else 1087 return 0; 1088 } 1089 1090 /* Returns the current state of modem control inputs. */ 1091 static unsigned int pch_uart_get_mctrl(struct uart_port *port) 1092 { 1093 struct eg20t_port *priv; 1094 u8 modem; 1095 unsigned int ret = 0; 1096 1097 priv = container_of(port, struct eg20t_port, port); 1098 modem = pch_uart_hal_get_modem(priv); 1099 1100 if (modem & UART_MSR_DCD) 1101 ret |= TIOCM_CAR; 1102 1103 if (modem & UART_MSR_RI) 1104 ret |= TIOCM_RNG; 1105 1106 if (modem & UART_MSR_DSR) 1107 ret |= TIOCM_DSR; 1108 1109 if (modem & UART_MSR_CTS) 1110 ret |= TIOCM_CTS; 1111 1112 return ret; 1113 } 1114 1115 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1116 { 1117 u32 mcr = 0; 1118 struct eg20t_port *priv = container_of(port, struct eg20t_port, port); 1119 1120 if (mctrl & TIOCM_DTR) 1121 mcr |= UART_MCR_DTR; 1122 if (mctrl & TIOCM_RTS) 1123 mcr |= UART_MCR_RTS; 1124 if (mctrl & TIOCM_LOOP) 1125 mcr |= UART_MCR_LOOP; 1126 1127 if (priv->mcr & UART_MCR_AFE) 1128 mcr |= UART_MCR_AFE; 1129 1130 if (mctrl) 1131 iowrite8(mcr, priv->membase + UART_MCR); 1132 } 1133 1134 static void pch_uart_stop_tx(struct uart_port *port) 1135 { 1136 struct eg20t_port *priv; 1137 priv = container_of(port, struct eg20t_port, port); 1138 priv->start_tx = 0; 1139 priv->tx_dma_use = 0; 1140 } 1141 1142 static void pch_uart_start_tx(struct uart_port *port) 1143 { 1144 struct eg20t_port *priv; 1145 1146 priv = container_of(port, struct eg20t_port, port); 1147 1148 if (priv->use_dma) { 1149 if (priv->tx_dma_use) { 1150 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n", 1151 __func__); 1152 return; 1153 } 1154 } 1155 1156 priv->start_tx = 1; 1157 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 1158 } 1159 1160 static void pch_uart_stop_rx(struct uart_port *port) 1161 { 1162 struct eg20t_port *priv; 1163 priv = container_of(port, struct eg20t_port, port); 1164 priv->start_rx = 0; 1165 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | 1166 PCH_UART_HAL_RX_ERR_INT); 1167 } 1168 1169 /* Enable the modem status interrupts. */ 1170 static void pch_uart_enable_ms(struct uart_port *port) 1171 { 1172 struct eg20t_port *priv; 1173 priv = container_of(port, struct eg20t_port, port); 1174 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT); 1175 } 1176 1177 /* Control the transmission of a break signal. */ 1178 static void pch_uart_break_ctl(struct uart_port *port, int ctl) 1179 { 1180 struct eg20t_port *priv; 1181 unsigned long flags; 1182 1183 priv = container_of(port, struct eg20t_port, port); 1184 uart_port_lock_irqsave(&priv->port, &flags); 1185 pch_uart_hal_set_break(priv, ctl); 1186 uart_port_unlock_irqrestore(&priv->port, flags); 1187 } 1188 1189 /* Grab any interrupt resources and initialise any low level driver state. */ 1190 static int pch_uart_startup(struct uart_port *port) 1191 { 1192 struct eg20t_port *priv; 1193 int ret; 1194 int fifo_size; 1195 int trigger_level; 1196 1197 priv = container_of(port, struct eg20t_port, port); 1198 priv->tx_empty = 1; 1199 1200 if (port->uartclk) 1201 priv->uartclk = port->uartclk; 1202 else 1203 port->uartclk = priv->uartclk; 1204 1205 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1206 ret = pch_uart_hal_set_line(priv, default_baud, 1207 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT, 1208 PCH_UART_HAL_STB1); 1209 if (ret) 1210 return ret; 1211 1212 switch (priv->fifo_size) { 1213 case 256: 1214 fifo_size = PCH_UART_HAL_FIFO256; 1215 break; 1216 case 64: 1217 fifo_size = PCH_UART_HAL_FIFO64; 1218 break; 1219 case 16: 1220 fifo_size = PCH_UART_HAL_FIFO16; 1221 break; 1222 case 1: 1223 default: 1224 fifo_size = PCH_UART_HAL_FIFO_DIS; 1225 break; 1226 } 1227 1228 switch (priv->trigger) { 1229 case PCH_UART_HAL_TRIGGER1: 1230 trigger_level = 1; 1231 break; 1232 case PCH_UART_HAL_TRIGGER_L: 1233 trigger_level = priv->fifo_size / 4; 1234 break; 1235 case PCH_UART_HAL_TRIGGER_M: 1236 trigger_level = priv->fifo_size / 2; 1237 break; 1238 case PCH_UART_HAL_TRIGGER_H: 1239 default: 1240 trigger_level = priv->fifo_size - (priv->fifo_size / 8); 1241 break; 1242 } 1243 1244 priv->trigger_level = trigger_level; 1245 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1246 fifo_size, priv->trigger); 1247 if (ret < 0) 1248 return ret; 1249 1250 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, 1251 priv->irq_name, priv); 1252 if (ret < 0) 1253 return ret; 1254 1255 if (priv->use_dma) 1256 pch_request_dma(port); 1257 1258 priv->start_rx = 1; 1259 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | 1260 PCH_UART_HAL_RX_ERR_INT); 1261 uart_update_timeout(port, CS8, default_baud); 1262 1263 return 0; 1264 } 1265 1266 static void pch_uart_shutdown(struct uart_port *port) 1267 { 1268 struct eg20t_port *priv; 1269 int ret; 1270 1271 priv = container_of(port, struct eg20t_port, port); 1272 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1273 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO); 1274 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1275 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1); 1276 if (ret) 1277 dev_err(priv->port.dev, 1278 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret); 1279 1280 pch_free_dma(port); 1281 1282 free_irq(priv->port.irq, priv); 1283 } 1284 1285 /* Change the port parameters, including word length, parity, stop 1286 *bits. Update read_status_mask and ignore_status_mask to indicate 1287 *the types of events we are interested in receiving. */ 1288 static void pch_uart_set_termios(struct uart_port *port, 1289 struct ktermios *termios, 1290 const struct ktermios *old) 1291 { 1292 int rtn; 1293 unsigned int baud, parity, bits, stb; 1294 struct eg20t_port *priv; 1295 unsigned long flags; 1296 1297 priv = container_of(port, struct eg20t_port, port); 1298 switch (termios->c_cflag & CSIZE) { 1299 case CS5: 1300 bits = PCH_UART_HAL_5BIT; 1301 break; 1302 case CS6: 1303 bits = PCH_UART_HAL_6BIT; 1304 break; 1305 case CS7: 1306 bits = PCH_UART_HAL_7BIT; 1307 break; 1308 default: /* CS8 */ 1309 bits = PCH_UART_HAL_8BIT; 1310 break; 1311 } 1312 if (termios->c_cflag & CSTOPB) 1313 stb = PCH_UART_HAL_STB2; 1314 else 1315 stb = PCH_UART_HAL_STB1; 1316 1317 if (termios->c_cflag & PARENB) { 1318 if (termios->c_cflag & PARODD) 1319 parity = PCH_UART_HAL_PARITY_ODD; 1320 else 1321 parity = PCH_UART_HAL_PARITY_EVEN; 1322 1323 } else 1324 parity = PCH_UART_HAL_PARITY_NONE; 1325 1326 /* Only UART0 has auto hardware flow function */ 1327 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256)) 1328 priv->mcr |= UART_MCR_AFE; 1329 else 1330 priv->mcr &= ~UART_MCR_AFE; 1331 1332 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ 1333 1334 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 1335 1336 uart_port_lock_irqsave(port, &flags); 1337 1338 uart_update_timeout(port, termios->c_cflag, baud); 1339 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb); 1340 if (rtn) 1341 goto out; 1342 1343 pch_uart_set_mctrl(&priv->port, priv->port.mctrl); 1344 /* Don't rewrite B0 */ 1345 if (tty_termios_baud_rate(termios)) 1346 tty_termios_encode_baud_rate(termios, baud, baud); 1347 1348 out: 1349 uart_port_unlock_irqrestore(port, flags); 1350 } 1351 1352 static const char *pch_uart_type(struct uart_port *port) 1353 { 1354 return KBUILD_MODNAME; 1355 } 1356 1357 static void pch_uart_release_port(struct uart_port *port) 1358 { 1359 struct eg20t_port *priv; 1360 1361 priv = container_of(port, struct eg20t_port, port); 1362 pci_iounmap(priv->pdev, priv->membase); 1363 pci_release_regions(priv->pdev); 1364 } 1365 1366 static int pch_uart_request_port(struct uart_port *port) 1367 { 1368 struct eg20t_port *priv; 1369 int ret; 1370 void __iomem *membase; 1371 1372 priv = container_of(port, struct eg20t_port, port); 1373 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME); 1374 if (ret < 0) 1375 return -EBUSY; 1376 1377 membase = pci_iomap(priv->pdev, 1, 0); 1378 if (!membase) { 1379 pci_release_regions(priv->pdev); 1380 return -EBUSY; 1381 } 1382 priv->membase = port->membase = membase; 1383 1384 return 0; 1385 } 1386 1387 static void pch_uart_config_port(struct uart_port *port, int type) 1388 { 1389 struct eg20t_port *priv; 1390 1391 priv = container_of(port, struct eg20t_port, port); 1392 if (type & UART_CONFIG_TYPE) { 1393 port->type = priv->port_type; 1394 pch_uart_request_port(port); 1395 } 1396 } 1397 1398 static int pch_uart_verify_port(struct uart_port *port, 1399 struct serial_struct *serinfo) 1400 { 1401 struct eg20t_port *priv; 1402 1403 priv = container_of(port, struct eg20t_port, port); 1404 if (serinfo->flags & UPF_LOW_LATENCY) { 1405 dev_info(priv->port.dev, 1406 "PCH UART : Use PIO Mode (without DMA)\n"); 1407 priv->use_dma = 0; 1408 serinfo->flags &= ~UPF_LOW_LATENCY; 1409 } else { 1410 #ifndef CONFIG_PCH_DMA 1411 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n", 1412 __func__); 1413 return -EOPNOTSUPP; 1414 #endif 1415 if (!priv->use_dma) { 1416 pch_request_dma(port); 1417 if (priv->chan_rx) 1418 priv->use_dma = 1; 1419 } 1420 dev_info(priv->port.dev, "PCH UART: %s\n", 1421 priv->use_dma ? 1422 "Use DMA Mode" : "No DMA"); 1423 } 1424 1425 return 0; 1426 } 1427 1428 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE) 1429 /* 1430 * Wait for transmitter & holding register to empty 1431 */ 1432 static void wait_for_xmitr(struct eg20t_port *up, int bits) 1433 { 1434 unsigned int status, tmout = 10000; 1435 1436 /* Wait up to 10ms for the character(s) to be sent. */ 1437 for (;;) { 1438 status = ioread8(up->membase + UART_LSR); 1439 1440 if ((status & bits) == bits) 1441 break; 1442 if (--tmout == 0) 1443 break; 1444 udelay(1); 1445 } 1446 1447 /* Wait up to 1s for flow control if necessary */ 1448 if (up->port.flags & UPF_CONS_FLOW) { 1449 unsigned int tmout; 1450 for (tmout = 1000000; tmout; tmout--) { 1451 unsigned int msr = ioread8(up->membase + UART_MSR); 1452 if (msr & UART_MSR_CTS) 1453 break; 1454 udelay(1); 1455 touch_nmi_watchdog(); 1456 } 1457 } 1458 } 1459 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */ 1460 1461 #ifdef CONFIG_CONSOLE_POLL 1462 /* 1463 * Console polling routines for communicate via uart while 1464 * in an interrupt or debug context. 1465 */ 1466 static int pch_uart_get_poll_char(struct uart_port *port) 1467 { 1468 struct eg20t_port *priv = 1469 container_of(port, struct eg20t_port, port); 1470 u8 lsr = ioread8(priv->membase + UART_LSR); 1471 1472 if (!(lsr & UART_LSR_DR)) 1473 return NO_POLL_CHAR; 1474 1475 return ioread8(priv->membase + PCH_UART_RBR); 1476 } 1477 1478 1479 static void pch_uart_put_poll_char(struct uart_port *port, 1480 unsigned char c) 1481 { 1482 unsigned int ier; 1483 struct eg20t_port *priv = 1484 container_of(port, struct eg20t_port, port); 1485 1486 /* 1487 * First save the IER then disable the interrupts 1488 */ 1489 ier = ioread8(priv->membase + UART_IER); 1490 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1491 1492 wait_for_xmitr(priv, UART_LSR_THRE); 1493 /* 1494 * Send the character out. 1495 */ 1496 iowrite8(c, priv->membase + PCH_UART_THR); 1497 1498 /* 1499 * Finally, wait for transmitter to become empty 1500 * and restore the IER 1501 */ 1502 wait_for_xmitr(priv, UART_LSR_BOTH_EMPTY); 1503 iowrite8(ier, priv->membase + UART_IER); 1504 } 1505 #endif /* CONFIG_CONSOLE_POLL */ 1506 1507 static const struct uart_ops pch_uart_ops = { 1508 .tx_empty = pch_uart_tx_empty, 1509 .set_mctrl = pch_uart_set_mctrl, 1510 .get_mctrl = pch_uart_get_mctrl, 1511 .stop_tx = pch_uart_stop_tx, 1512 .start_tx = pch_uart_start_tx, 1513 .stop_rx = pch_uart_stop_rx, 1514 .enable_ms = pch_uart_enable_ms, 1515 .break_ctl = pch_uart_break_ctl, 1516 .startup = pch_uart_startup, 1517 .shutdown = pch_uart_shutdown, 1518 .set_termios = pch_uart_set_termios, 1519 /* .pm = pch_uart_pm, Not supported yet */ 1520 .type = pch_uart_type, 1521 .release_port = pch_uart_release_port, 1522 .request_port = pch_uart_request_port, 1523 .config_port = pch_uart_config_port, 1524 .verify_port = pch_uart_verify_port, 1525 #ifdef CONFIG_CONSOLE_POLL 1526 .poll_get_char = pch_uart_get_poll_char, 1527 .poll_put_char = pch_uart_put_poll_char, 1528 #endif 1529 }; 1530 1531 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1532 1533 static void pch_console_putchar(struct uart_port *port, unsigned char ch) 1534 { 1535 struct eg20t_port *priv = 1536 container_of(port, struct eg20t_port, port); 1537 1538 wait_for_xmitr(priv, UART_LSR_THRE); 1539 iowrite8(ch, priv->membase + PCH_UART_THR); 1540 } 1541 1542 /* 1543 * Print a string to the serial port trying not to disturb 1544 * any possible real use of the port... 1545 * 1546 * The console_lock must be held when we get here. 1547 */ 1548 static void 1549 pch_console_write(struct console *co, const char *s, unsigned int count) 1550 { 1551 struct eg20t_port *priv; 1552 unsigned long flags; 1553 int locked = 1; 1554 u8 ier; 1555 1556 priv = pch_uart_ports[co->index]; 1557 1558 touch_nmi_watchdog(); 1559 1560 if (oops_in_progress) 1561 locked = uart_port_trylock_irqsave(&priv->port, &flags); 1562 else 1563 uart_port_lock_irqsave(&priv->port, &flags); 1564 1565 /* 1566 * First save the IER then disable the interrupts 1567 */ 1568 ier = ioread8(priv->membase + UART_IER); 1569 1570 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1571 1572 uart_console_write(&priv->port, s, count, pch_console_putchar); 1573 1574 /* 1575 * Finally, wait for transmitter to become empty 1576 * and restore the IER 1577 */ 1578 wait_for_xmitr(priv, UART_LSR_BOTH_EMPTY); 1579 iowrite8(ier, priv->membase + UART_IER); 1580 1581 if (locked) 1582 uart_port_unlock_irqrestore(&priv->port, flags); 1583 } 1584 1585 static int __init pch_console_setup(struct console *co, char *options) 1586 { 1587 struct uart_port *port; 1588 int baud = default_baud; 1589 int bits = 8; 1590 int parity = 'n'; 1591 int flow = 'n'; 1592 1593 /* 1594 * Check whether an invalid uart number has been specified, and 1595 * if so, search for the first available port that does have 1596 * console support. 1597 */ 1598 if (co->index >= PCH_UART_NR) 1599 co->index = 0; 1600 port = &pch_uart_ports[co->index]->port; 1601 1602 if (!port || (!port->iobase && !port->membase)) 1603 return -ENODEV; 1604 1605 port->uartclk = pch_uart_get_uartclk(); 1606 1607 if (options) 1608 uart_parse_options(options, &baud, &parity, &bits, &flow); 1609 1610 return uart_set_options(port, co, baud, parity, bits, flow); 1611 } 1612 1613 static struct uart_driver pch_uart_driver; 1614 1615 static struct console pch_console = { 1616 .name = PCH_UART_DRIVER_DEVICE, 1617 .write = pch_console_write, 1618 .device = uart_console_device, 1619 .setup = pch_console_setup, 1620 .flags = CON_PRINTBUFFER | CON_ANYTIME, 1621 .index = -1, 1622 .data = &pch_uart_driver, 1623 }; 1624 1625 #define PCH_CONSOLE (&pch_console) 1626 #else 1627 #define PCH_CONSOLE NULL 1628 #endif /* CONFIG_SERIAL_PCH_UART_CONSOLE */ 1629 1630 static struct uart_driver pch_uart_driver = { 1631 .owner = THIS_MODULE, 1632 .driver_name = KBUILD_MODNAME, 1633 .dev_name = PCH_UART_DRIVER_DEVICE, 1634 .major = 0, 1635 .minor = 0, 1636 .nr = PCH_UART_NR, 1637 .cons = PCH_CONSOLE, 1638 }; 1639 1640 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev, 1641 const struct pci_device_id *id) 1642 { 1643 struct eg20t_port *priv; 1644 int ret; 1645 unsigned int iobase; 1646 unsigned int mapbase; 1647 unsigned char *rxbuf; 1648 int fifosize; 1649 int port_type; 1650 struct pch_uart_driver_data *board; 1651 char name[32]; 1652 1653 board = &drv_dat[id->driver_data]; 1654 port_type = board->port_type; 1655 1656 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL); 1657 if (priv == NULL) 1658 goto init_port_alloc_err; 1659 1660 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL); 1661 if (!rxbuf) 1662 goto init_port_free_txbuf; 1663 1664 switch (port_type) { 1665 case PORT_PCH_8LINE: 1666 fifosize = 256; /* EG20T/ML7213: UART0 */ 1667 break; 1668 case PORT_PCH_2LINE: 1669 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ 1670 break; 1671 default: 1672 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); 1673 goto init_port_hal_free; 1674 } 1675 1676 pci_enable_msi(pdev); 1677 pci_set_master(pdev); 1678 1679 iobase = pci_resource_start(pdev, 0); 1680 mapbase = pci_resource_start(pdev, 1); 1681 priv->mapbase = mapbase; 1682 priv->iobase = iobase; 1683 priv->pdev = pdev; 1684 priv->tx_empty = 1; 1685 priv->rxbuf.buf = rxbuf; 1686 priv->rxbuf.size = PAGE_SIZE; 1687 1688 priv->fifo_size = fifosize; 1689 priv->uartclk = pch_uart_get_uartclk(); 1690 priv->port_type = port_type; 1691 priv->port.dev = &pdev->dev; 1692 priv->port.iobase = iobase; 1693 priv->port.membase = NULL; 1694 priv->port.mapbase = mapbase; 1695 priv->port.irq = pdev->irq; 1696 priv->port.iotype = UPIO_PORT; 1697 priv->port.ops = &pch_uart_ops; 1698 priv->port.flags = UPF_BOOT_AUTOCONF; 1699 priv->port.fifosize = fifosize; 1700 priv->port.line = board->line_no; 1701 priv->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PCH_UART_CONSOLE); 1702 priv->trigger = PCH_UART_HAL_TRIGGER_M; 1703 1704 snprintf(priv->irq_name, IRQ_NAME_SIZE, 1705 KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d", 1706 priv->port.line); 1707 1708 pci_set_drvdata(pdev, priv); 1709 priv->trigger_level = 1; 1710 priv->fcr = 0; 1711 1712 if (pdev->dev.of_node) 1713 of_property_read_u32(pdev->dev.of_node, "clock-frequency" 1714 , &user_uartclk); 1715 1716 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1717 pch_uart_ports[board->line_no] = priv; 1718 #endif 1719 ret = uart_add_one_port(&pch_uart_driver, &priv->port); 1720 if (ret < 0) 1721 goto init_port_hal_free; 1722 1723 snprintf(name, sizeof(name), "uart%d_regs", priv->port.line); 1724 debugfs_create_file(name, S_IFREG | S_IRUGO, NULL, priv, 1725 &port_regs_ops); 1726 1727 return priv; 1728 1729 init_port_hal_free: 1730 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1731 pch_uart_ports[board->line_no] = NULL; 1732 #endif 1733 free_page((unsigned long)rxbuf); 1734 init_port_free_txbuf: 1735 kfree(priv); 1736 init_port_alloc_err: 1737 1738 return NULL; 1739 } 1740 1741 static void pch_uart_exit_port(struct eg20t_port *priv) 1742 { 1743 char name[32]; 1744 1745 snprintf(name, sizeof(name), "uart%d_regs", priv->port.line); 1746 debugfs_lookup_and_remove(name, NULL); 1747 uart_remove_one_port(&pch_uart_driver, &priv->port); 1748 free_page((unsigned long)priv->rxbuf.buf); 1749 } 1750 1751 static void pch_uart_pci_remove(struct pci_dev *pdev) 1752 { 1753 struct eg20t_port *priv = pci_get_drvdata(pdev); 1754 1755 pci_disable_msi(pdev); 1756 1757 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1758 pch_uart_ports[priv->port.line] = NULL; 1759 #endif 1760 pch_uart_exit_port(priv); 1761 pci_disable_device(pdev); 1762 kfree(priv); 1763 return; 1764 } 1765 1766 static int __maybe_unused pch_uart_pci_suspend(struct device *dev) 1767 { 1768 struct eg20t_port *priv = dev_get_drvdata(dev); 1769 1770 uart_suspend_port(&pch_uart_driver, &priv->port); 1771 1772 return 0; 1773 } 1774 1775 static int __maybe_unused pch_uart_pci_resume(struct device *dev) 1776 { 1777 struct eg20t_port *priv = dev_get_drvdata(dev); 1778 1779 uart_resume_port(&pch_uart_driver, &priv->port); 1780 1781 return 0; 1782 } 1783 1784 static const struct pci_device_id pch_uart_pci_id[] = { 1785 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811), 1786 .driver_data = pch_et20t_uart0}, 1787 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812), 1788 .driver_data = pch_et20t_uart1}, 1789 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813), 1790 .driver_data = pch_et20t_uart2}, 1791 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814), 1792 .driver_data = pch_et20t_uart3}, 1793 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027), 1794 .driver_data = pch_ml7213_uart0}, 1795 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028), 1796 .driver_data = pch_ml7213_uart1}, 1797 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029), 1798 .driver_data = pch_ml7213_uart2}, 1799 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C), 1800 .driver_data = pch_ml7223_uart0}, 1801 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D), 1802 .driver_data = pch_ml7223_uart1}, 1803 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811), 1804 .driver_data = pch_ml7831_uart0}, 1805 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812), 1806 .driver_data = pch_ml7831_uart1}, 1807 {0,}, 1808 }; 1809 1810 static int pch_uart_pci_probe(struct pci_dev *pdev, 1811 const struct pci_device_id *id) 1812 { 1813 int ret; 1814 struct eg20t_port *priv; 1815 1816 ret = pci_enable_device(pdev); 1817 if (ret < 0) 1818 goto probe_error; 1819 1820 priv = pch_uart_init_port(pdev, id); 1821 if (!priv) { 1822 ret = -EBUSY; 1823 goto probe_disable_device; 1824 } 1825 pci_set_drvdata(pdev, priv); 1826 1827 return ret; 1828 1829 probe_disable_device: 1830 pci_disable_msi(pdev); 1831 pci_disable_device(pdev); 1832 probe_error: 1833 return ret; 1834 } 1835 1836 static SIMPLE_DEV_PM_OPS(pch_uart_pci_pm_ops, 1837 pch_uart_pci_suspend, 1838 pch_uart_pci_resume); 1839 1840 static struct pci_driver pch_uart_pci_driver = { 1841 .name = "pch_uart", 1842 .id_table = pch_uart_pci_id, 1843 .probe = pch_uart_pci_probe, 1844 .remove = pch_uart_pci_remove, 1845 .driver.pm = &pch_uart_pci_pm_ops, 1846 }; 1847 1848 static int __init pch_uart_module_init(void) 1849 { 1850 int ret; 1851 1852 /* register as UART driver */ 1853 ret = uart_register_driver(&pch_uart_driver); 1854 if (ret < 0) 1855 return ret; 1856 1857 /* register as PCI driver */ 1858 ret = pci_register_driver(&pch_uart_pci_driver); 1859 if (ret < 0) 1860 uart_unregister_driver(&pch_uart_driver); 1861 1862 return ret; 1863 } 1864 module_init(pch_uart_module_init); 1865 1866 static void __exit pch_uart_module_exit(void) 1867 { 1868 pci_unregister_driver(&pch_uart_pci_driver); 1869 uart_unregister_driver(&pch_uart_driver); 1870 } 1871 module_exit(pch_uart_module_exit); 1872 1873 MODULE_LICENSE("GPL v2"); 1874 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver"); 1875 MODULE_DEVICE_TABLE(pci, pch_uart_pci_id); 1876 1877 module_param(default_baud, uint, S_IRUGO); 1878 MODULE_PARM_DESC(default_baud, 1879 "Default BAUD for initial driver state and console (default 9600)"); 1880 module_param(user_uartclk, uint, S_IRUGO); 1881 MODULE_PARM_DESC(user_uartclk, 1882 "Override UART default or board specific UART clock"); 1883