xref: /linux/drivers/tty/serial/pch_uart.c (revision 2da68a77)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4  */
5 #include <linux/kernel.h>
6 #include <linux/serial.h>
7 #include <linux/serial_reg.h>
8 #include <linux/slab.h>
9 #include <linux/module.h>
10 #include <linux/pci.h>
11 #include <linux/console.h>
12 #include <linux/serial_core.h>
13 #include <linux/tty.h>
14 #include <linux/tty_flip.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/dmi.h>
18 #include <linux/nmi.h>
19 #include <linux/delay.h>
20 #include <linux/of.h>
21 
22 #include <linux/debugfs.h>
23 #include <linux/dmaengine.h>
24 #include <linux/pch_dma.h>
25 
26 enum {
27 	PCH_UART_HANDLED_RX_INT_SHIFT,
28 	PCH_UART_HANDLED_TX_INT_SHIFT,
29 	PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
30 	PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
31 	PCH_UART_HANDLED_MS_INT_SHIFT,
32 	PCH_UART_HANDLED_LS_INT_SHIFT,
33 };
34 
35 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
36 
37 /* Set the max number of UART port
38  * Intel EG20T PCH: 4 port
39  * LAPIS Semiconductor ML7213 IOH: 3 port
40  * LAPIS Semiconductor ML7223 IOH: 2 port
41 */
42 #define PCH_UART_NR	4
43 
44 #define PCH_UART_HANDLED_RX_INT	(1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
45 #define PCH_UART_HANDLED_TX_INT	(1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
46 #define PCH_UART_HANDLED_RX_ERR_INT	(1<<((\
47 					PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
48 #define PCH_UART_HANDLED_RX_TRG_INT	(1<<((\
49 					PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
50 #define PCH_UART_HANDLED_MS_INT	(1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
51 
52 #define PCH_UART_HANDLED_LS_INT	(1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
53 
54 #define PCH_UART_RBR		0x00
55 #define PCH_UART_THR		0x00
56 
57 #define PCH_UART_IER_MASK	(PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
58 				PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
59 #define PCH_UART_IER_ERBFI	0x00000001
60 #define PCH_UART_IER_ETBEI	0x00000002
61 #define PCH_UART_IER_ELSI	0x00000004
62 #define PCH_UART_IER_EDSSI	0x00000008
63 
64 #define PCH_UART_IIR_IP			0x00000001
65 #define PCH_UART_IIR_IID		0x00000006
66 #define PCH_UART_IIR_MSI		0x00000000
67 #define PCH_UART_IIR_TRI		0x00000002
68 #define PCH_UART_IIR_RRI		0x00000004
69 #define PCH_UART_IIR_REI		0x00000006
70 #define PCH_UART_IIR_TOI		0x00000008
71 #define PCH_UART_IIR_FIFO256		0x00000020
72 #define PCH_UART_IIR_FIFO64		PCH_UART_IIR_FIFO256
73 #define PCH_UART_IIR_FE			0x000000C0
74 
75 #define PCH_UART_FCR_FIFOE		0x00000001
76 #define PCH_UART_FCR_RFR		0x00000002
77 #define PCH_UART_FCR_TFR		0x00000004
78 #define PCH_UART_FCR_DMS		0x00000008
79 #define PCH_UART_FCR_FIFO256		0x00000020
80 #define PCH_UART_FCR_RFTL		0x000000C0
81 
82 #define PCH_UART_FCR_RFTL1		0x00000000
83 #define PCH_UART_FCR_RFTL64		0x00000040
84 #define PCH_UART_FCR_RFTL128		0x00000080
85 #define PCH_UART_FCR_RFTL224		0x000000C0
86 #define PCH_UART_FCR_RFTL16		PCH_UART_FCR_RFTL64
87 #define PCH_UART_FCR_RFTL32		PCH_UART_FCR_RFTL128
88 #define PCH_UART_FCR_RFTL56		PCH_UART_FCR_RFTL224
89 #define PCH_UART_FCR_RFTL4		PCH_UART_FCR_RFTL64
90 #define PCH_UART_FCR_RFTL8		PCH_UART_FCR_RFTL128
91 #define PCH_UART_FCR_RFTL14		PCH_UART_FCR_RFTL224
92 #define PCH_UART_FCR_RFTL_SHIFT		6
93 
94 #define PCH_UART_LCR_WLS	0x00000003
95 #define PCH_UART_LCR_STB	0x00000004
96 #define PCH_UART_LCR_PEN	0x00000008
97 #define PCH_UART_LCR_EPS	0x00000010
98 #define PCH_UART_LCR_SP		0x00000020
99 #define PCH_UART_LCR_SB		0x00000040
100 #define PCH_UART_LCR_DLAB	0x00000080
101 #define PCH_UART_LCR_NP		0x00000000
102 #define PCH_UART_LCR_OP		PCH_UART_LCR_PEN
103 #define PCH_UART_LCR_EP		(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
104 #define PCH_UART_LCR_1P		(PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
105 #define PCH_UART_LCR_0P		(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
106 				PCH_UART_LCR_SP)
107 
108 #define PCH_UART_LCR_5BIT	0x00000000
109 #define PCH_UART_LCR_6BIT	0x00000001
110 #define PCH_UART_LCR_7BIT	0x00000002
111 #define PCH_UART_LCR_8BIT	0x00000003
112 
113 #define PCH_UART_MCR_DTR	0x00000001
114 #define PCH_UART_MCR_RTS	0x00000002
115 #define PCH_UART_MCR_OUT	0x0000000C
116 #define PCH_UART_MCR_LOOP	0x00000010
117 #define PCH_UART_MCR_AFE	0x00000020
118 
119 #define PCH_UART_LSR_DR		0x00000001
120 #define PCH_UART_LSR_ERR	(1<<7)
121 
122 #define PCH_UART_MSR_DCTS	0x00000001
123 #define PCH_UART_MSR_DDSR	0x00000002
124 #define PCH_UART_MSR_TERI	0x00000004
125 #define PCH_UART_MSR_DDCD	0x00000008
126 #define PCH_UART_MSR_CTS	0x00000010
127 #define PCH_UART_MSR_DSR	0x00000020
128 #define PCH_UART_MSR_RI		0x00000040
129 #define PCH_UART_MSR_DCD	0x00000080
130 #define PCH_UART_MSR_DELTA	(PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
131 				PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
132 
133 #define PCH_UART_DLL		0x00
134 #define PCH_UART_DLM		0x01
135 
136 #define PCH_UART_BRCSR		0x0E
137 
138 #define PCH_UART_IID_RLS	(PCH_UART_IIR_REI)
139 #define PCH_UART_IID_RDR	(PCH_UART_IIR_RRI)
140 #define PCH_UART_IID_RDR_TO	(PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
141 #define PCH_UART_IID_THRE	(PCH_UART_IIR_TRI)
142 #define PCH_UART_IID_MS		(PCH_UART_IIR_MSI)
143 
144 #define PCH_UART_HAL_PARITY_NONE	(PCH_UART_LCR_NP)
145 #define PCH_UART_HAL_PARITY_ODD		(PCH_UART_LCR_OP)
146 #define PCH_UART_HAL_PARITY_EVEN	(PCH_UART_LCR_EP)
147 #define PCH_UART_HAL_PARITY_FIX1	(PCH_UART_LCR_1P)
148 #define PCH_UART_HAL_PARITY_FIX0	(PCH_UART_LCR_0P)
149 #define PCH_UART_HAL_5BIT		(PCH_UART_LCR_5BIT)
150 #define PCH_UART_HAL_6BIT		(PCH_UART_LCR_6BIT)
151 #define PCH_UART_HAL_7BIT		(PCH_UART_LCR_7BIT)
152 #define PCH_UART_HAL_8BIT		(PCH_UART_LCR_8BIT)
153 #define PCH_UART_HAL_STB1		0
154 #define PCH_UART_HAL_STB2		(PCH_UART_LCR_STB)
155 
156 #define PCH_UART_HAL_CLR_TX_FIFO	(PCH_UART_FCR_TFR)
157 #define PCH_UART_HAL_CLR_RX_FIFO	(PCH_UART_FCR_RFR)
158 #define PCH_UART_HAL_CLR_ALL_FIFO	(PCH_UART_HAL_CLR_TX_FIFO | \
159 					PCH_UART_HAL_CLR_RX_FIFO)
160 
161 #define PCH_UART_HAL_DMA_MODE0		0
162 #define PCH_UART_HAL_FIFO_DIS		0
163 #define PCH_UART_HAL_FIFO16		(PCH_UART_FCR_FIFOE)
164 #define PCH_UART_HAL_FIFO256		(PCH_UART_FCR_FIFOE | \
165 					PCH_UART_FCR_FIFO256)
166 #define PCH_UART_HAL_FIFO64		(PCH_UART_HAL_FIFO256)
167 #define PCH_UART_HAL_TRIGGER1		(PCH_UART_FCR_RFTL1)
168 #define PCH_UART_HAL_TRIGGER64		(PCH_UART_FCR_RFTL64)
169 #define PCH_UART_HAL_TRIGGER128		(PCH_UART_FCR_RFTL128)
170 #define PCH_UART_HAL_TRIGGER224		(PCH_UART_FCR_RFTL224)
171 #define PCH_UART_HAL_TRIGGER16		(PCH_UART_FCR_RFTL16)
172 #define PCH_UART_HAL_TRIGGER32		(PCH_UART_FCR_RFTL32)
173 #define PCH_UART_HAL_TRIGGER56		(PCH_UART_FCR_RFTL56)
174 #define PCH_UART_HAL_TRIGGER4		(PCH_UART_FCR_RFTL4)
175 #define PCH_UART_HAL_TRIGGER8		(PCH_UART_FCR_RFTL8)
176 #define PCH_UART_HAL_TRIGGER14		(PCH_UART_FCR_RFTL14)
177 #define PCH_UART_HAL_TRIGGER_L		(PCH_UART_FCR_RFTL64)
178 #define PCH_UART_HAL_TRIGGER_M		(PCH_UART_FCR_RFTL128)
179 #define PCH_UART_HAL_TRIGGER_H		(PCH_UART_FCR_RFTL224)
180 
181 #define PCH_UART_HAL_RX_INT		(PCH_UART_IER_ERBFI)
182 #define PCH_UART_HAL_TX_INT		(PCH_UART_IER_ETBEI)
183 #define PCH_UART_HAL_RX_ERR_INT		(PCH_UART_IER_ELSI)
184 #define PCH_UART_HAL_MS_INT		(PCH_UART_IER_EDSSI)
185 #define PCH_UART_HAL_ALL_INT		(PCH_UART_IER_MASK)
186 
187 #define PCH_UART_HAL_DTR		(PCH_UART_MCR_DTR)
188 #define PCH_UART_HAL_RTS		(PCH_UART_MCR_RTS)
189 #define PCH_UART_HAL_OUT		(PCH_UART_MCR_OUT)
190 #define PCH_UART_HAL_LOOP		(PCH_UART_MCR_LOOP)
191 #define PCH_UART_HAL_AFE		(PCH_UART_MCR_AFE)
192 
193 #define DEFAULT_UARTCLK   1843200 /*   1.8432 MHz */
194 #define CMITC_UARTCLK   192000000 /* 192.0000 MHz */
195 #define FRI2_64_UARTCLK  64000000 /*  64.0000 MHz */
196 #define FRI2_48_UARTCLK  48000000 /*  48.0000 MHz */
197 #define NTC1_UARTCLK     64000000 /*  64.0000 MHz */
198 #define MINNOW_UARTCLK   50000000 /*  50.0000 MHz */
199 
200 struct pch_uart_buffer {
201 	unsigned char *buf;
202 	int size;
203 };
204 
205 struct eg20t_port {
206 	struct uart_port port;
207 	int port_type;
208 	void __iomem *membase;
209 	resource_size_t mapbase;
210 	unsigned int iobase;
211 	struct pci_dev *pdev;
212 	int fifo_size;
213 	unsigned int uartclk;
214 	int start_tx;
215 	int start_rx;
216 	int tx_empty;
217 	int trigger;
218 	int trigger_level;
219 	struct pch_uart_buffer rxbuf;
220 	unsigned int dmsr;
221 	unsigned int fcr;
222 	unsigned int mcr;
223 	unsigned int use_dma;
224 	struct dma_async_tx_descriptor	*desc_tx;
225 	struct dma_async_tx_descriptor	*desc_rx;
226 	struct pch_dma_slave		param_tx;
227 	struct pch_dma_slave		param_rx;
228 	struct dma_chan			*chan_tx;
229 	struct dma_chan			*chan_rx;
230 	struct scatterlist		*sg_tx_p;
231 	int				nent;
232 	int				orig_nent;
233 	struct scatterlist		sg_rx;
234 	int				tx_dma_use;
235 	void				*rx_buf_virt;
236 	dma_addr_t			rx_buf_dma;
237 
238 #define IRQ_NAME_SIZE 17
239 	char				irq_name[IRQ_NAME_SIZE];
240 
241 	/* protect the eg20t_port private structure and io access to membase */
242 	spinlock_t lock;
243 };
244 
245 /**
246  * struct pch_uart_driver_data - private data structure for UART-DMA
247  * @port_type:			The type of UART port
248  * @line_no:			UART port line number (0, 1, 2...)
249  */
250 struct pch_uart_driver_data {
251 	int port_type;
252 	int line_no;
253 };
254 
255 enum pch_uart_num_t {
256 	pch_et20t_uart0 = 0,
257 	pch_et20t_uart1,
258 	pch_et20t_uart2,
259 	pch_et20t_uart3,
260 	pch_ml7213_uart0,
261 	pch_ml7213_uart1,
262 	pch_ml7213_uart2,
263 	pch_ml7223_uart0,
264 	pch_ml7223_uart1,
265 	pch_ml7831_uart0,
266 	pch_ml7831_uart1,
267 };
268 
269 static struct pch_uart_driver_data drv_dat[] = {
270 	[pch_et20t_uart0] = {PORT_PCH_8LINE, 0},
271 	[pch_et20t_uart1] = {PORT_PCH_2LINE, 1},
272 	[pch_et20t_uart2] = {PORT_PCH_2LINE, 2},
273 	[pch_et20t_uart3] = {PORT_PCH_2LINE, 3},
274 	[pch_ml7213_uart0] = {PORT_PCH_8LINE, 0},
275 	[pch_ml7213_uart1] = {PORT_PCH_2LINE, 1},
276 	[pch_ml7213_uart2] = {PORT_PCH_2LINE, 2},
277 	[pch_ml7223_uart0] = {PORT_PCH_8LINE, 0},
278 	[pch_ml7223_uart1] = {PORT_PCH_2LINE, 1},
279 	[pch_ml7831_uart0] = {PORT_PCH_8LINE, 0},
280 	[pch_ml7831_uart1] = {PORT_PCH_2LINE, 1},
281 };
282 
283 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
284 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
285 #endif
286 static unsigned int default_baud = 9600;
287 static unsigned int user_uartclk = 0;
288 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
289 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
290 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
291 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
292 
293 #define PCH_REGS_BUFSIZE	1024
294 
295 
296 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
297 				size_t count, loff_t *ppos)
298 {
299 	struct eg20t_port *priv = file->private_data;
300 	char *buf;
301 	u32 len = 0;
302 	ssize_t ret;
303 	unsigned char lcr;
304 
305 	buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
306 	if (!buf)
307 		return 0;
308 
309 	len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
310 			"PCH EG20T port[%d] regs:\n", priv->port.line);
311 
312 	len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
313 			"=================================\n");
314 	len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
315 			"IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
316 	len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
317 			"IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
318 	len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
319 			"LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
320 	len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
321 			"MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
322 	len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
323 			"LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
324 	len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
325 			"MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
326 	len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
327 			"BRCSR: \t0x%02x\n",
328 			ioread8(priv->membase + PCH_UART_BRCSR));
329 
330 	lcr = ioread8(priv->membase + UART_LCR);
331 	iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
332 	len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
333 			"DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
334 	len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len,
335 			"DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
336 	iowrite8(lcr, priv->membase + UART_LCR);
337 
338 	if (len > PCH_REGS_BUFSIZE)
339 		len = PCH_REGS_BUFSIZE;
340 
341 	ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
342 	kfree(buf);
343 	return ret;
344 }
345 
346 static const struct file_operations port_regs_ops = {
347 	.owner		= THIS_MODULE,
348 	.open		= simple_open,
349 	.read		= port_show_regs,
350 	.llseek		= default_llseek,
351 };
352 
353 static const struct dmi_system_id pch_uart_dmi_table[] = {
354 	{
355 		.ident = "CM-iTC",
356 		{
357 			DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
358 		},
359 		(void *)CMITC_UARTCLK,
360 	},
361 	{
362 		.ident = "FRI2",
363 		{
364 			DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
365 		},
366 		(void *)FRI2_64_UARTCLK,
367 	},
368 	{
369 		.ident = "Fish River Island II",
370 		{
371 			DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
372 		},
373 		(void *)FRI2_48_UARTCLK,
374 	},
375 	{
376 		.ident = "COMe-mTT",
377 		{
378 			DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
379 		},
380 		(void *)NTC1_UARTCLK,
381 	},
382 	{
383 		.ident = "nanoETXexpress-TT",
384 		{
385 			DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
386 		},
387 		(void *)NTC1_UARTCLK,
388 	},
389 	{
390 		.ident = "MinnowBoard",
391 		{
392 			DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
393 		},
394 		(void *)MINNOW_UARTCLK,
395 	},
396 	{ }
397 };
398 
399 /* Return UART clock, checking for board specific clocks. */
400 static unsigned int pch_uart_get_uartclk(void)
401 {
402 	const struct dmi_system_id *d;
403 
404 	if (user_uartclk)
405 		return user_uartclk;
406 
407 	d = dmi_first_match(pch_uart_dmi_table);
408 	if (d)
409 		return (unsigned long)d->driver_data;
410 
411 	return DEFAULT_UARTCLK;
412 }
413 
414 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
415 					  unsigned int flag)
416 {
417 	u8 ier = ioread8(priv->membase + UART_IER);
418 	ier |= flag & PCH_UART_IER_MASK;
419 	iowrite8(ier, priv->membase + UART_IER);
420 }
421 
422 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
423 					   unsigned int flag)
424 {
425 	u8 ier = ioread8(priv->membase + UART_IER);
426 	ier &= ~(flag & PCH_UART_IER_MASK);
427 	iowrite8(ier, priv->membase + UART_IER);
428 }
429 
430 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
431 				 unsigned int parity, unsigned int bits,
432 				 unsigned int stb)
433 {
434 	unsigned int dll, dlm, lcr;
435 	int div;
436 
437 	div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
438 	if (div < 0 || USHRT_MAX <= div) {
439 		dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
440 		return -EINVAL;
441 	}
442 
443 	dll = (unsigned int)div & 0x00FFU;
444 	dlm = ((unsigned int)div >> 8) & 0x00FFU;
445 
446 	if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
447 		dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
448 		return -EINVAL;
449 	}
450 
451 	if (bits & ~PCH_UART_LCR_WLS) {
452 		dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
453 		return -EINVAL;
454 	}
455 
456 	if (stb & ~PCH_UART_LCR_STB) {
457 		dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
458 		return -EINVAL;
459 	}
460 
461 	lcr = parity;
462 	lcr |= bits;
463 	lcr |= stb;
464 
465 	dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
466 		 __func__, baud, div, lcr, jiffies);
467 	iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
468 	iowrite8(dll, priv->membase + PCH_UART_DLL);
469 	iowrite8(dlm, priv->membase + PCH_UART_DLM);
470 	iowrite8(lcr, priv->membase + UART_LCR);
471 
472 	return 0;
473 }
474 
475 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
476 				    unsigned int flag)
477 {
478 	if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
479 		dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
480 			__func__, flag);
481 		return -EINVAL;
482 	}
483 
484 	iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
485 	iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
486 		 priv->membase + UART_FCR);
487 	iowrite8(priv->fcr, priv->membase + UART_FCR);
488 
489 	return 0;
490 }
491 
492 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
493 				 unsigned int dmamode,
494 				 unsigned int fifo_size, unsigned int trigger)
495 {
496 	u8 fcr;
497 
498 	if (dmamode & ~PCH_UART_FCR_DMS) {
499 		dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
500 			__func__, dmamode);
501 		return -EINVAL;
502 	}
503 
504 	if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
505 		dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
506 			__func__, fifo_size);
507 		return -EINVAL;
508 	}
509 
510 	if (trigger & ~PCH_UART_FCR_RFTL) {
511 		dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
512 			__func__, trigger);
513 		return -EINVAL;
514 	}
515 
516 	switch (priv->fifo_size) {
517 	case 256:
518 		priv->trigger_level =
519 		    trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
520 		break;
521 	case 64:
522 		priv->trigger_level =
523 		    trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
524 		break;
525 	case 16:
526 		priv->trigger_level =
527 		    trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
528 		break;
529 	default:
530 		priv->trigger_level =
531 		    trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
532 		break;
533 	}
534 	fcr =
535 	    dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
536 	iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
537 	iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
538 		 priv->membase + UART_FCR);
539 	iowrite8(fcr, priv->membase + UART_FCR);
540 	priv->fcr = fcr;
541 
542 	return 0;
543 }
544 
545 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
546 {
547 	unsigned int msr = ioread8(priv->membase + UART_MSR);
548 	priv->dmsr = msr & PCH_UART_MSR_DELTA;
549 	return (u8)msr;
550 }
551 
552 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
553 			     int rx_size)
554 {
555 	int i;
556 	u8 rbr, lsr;
557 	struct uart_port *port = &priv->port;
558 
559 	lsr = ioread8(priv->membase + UART_LSR);
560 	for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
561 	     i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
562 	     lsr = ioread8(priv->membase + UART_LSR)) {
563 		rbr = ioread8(priv->membase + PCH_UART_RBR);
564 
565 		if (lsr & UART_LSR_BI) {
566 			port->icount.brk++;
567 			if (uart_handle_break(port))
568 				continue;
569 		}
570 		if (uart_handle_sysrq_char(port, rbr))
571 			continue;
572 
573 		buf[i++] = rbr;
574 	}
575 	return i;
576 }
577 
578 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
579 {
580 	return ioread8(priv->membase + UART_IIR) &\
581 		      (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
582 }
583 
584 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
585 {
586 	return ioread8(priv->membase + UART_LSR);
587 }
588 
589 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
590 {
591 	unsigned int lcr;
592 
593 	lcr = ioread8(priv->membase + UART_LCR);
594 	if (on)
595 		lcr |= PCH_UART_LCR_SB;
596 	else
597 		lcr &= ~PCH_UART_LCR_SB;
598 
599 	iowrite8(lcr, priv->membase + UART_LCR);
600 }
601 
602 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
603 		   int size)
604 {
605 	struct uart_port *port = &priv->port;
606 	struct tty_port *tport = &port->state->port;
607 
608 	tty_insert_flip_string(tport, buf, size);
609 	tty_flip_buffer_push(tport);
610 
611 	return 0;
612 }
613 
614 static int dma_push_rx(struct eg20t_port *priv, int size)
615 {
616 	int room;
617 	struct uart_port *port = &priv->port;
618 	struct tty_port *tport = &port->state->port;
619 
620 	room = tty_buffer_request_room(tport, size);
621 
622 	if (room < size)
623 		dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
624 			 size - room);
625 	if (!room)
626 		return 0;
627 
628 	tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
629 
630 	port->icount.rx += room;
631 
632 	return room;
633 }
634 
635 static void pch_free_dma(struct uart_port *port)
636 {
637 	struct eg20t_port *priv;
638 	priv = container_of(port, struct eg20t_port, port);
639 
640 	if (priv->chan_tx) {
641 		dma_release_channel(priv->chan_tx);
642 		priv->chan_tx = NULL;
643 	}
644 	if (priv->chan_rx) {
645 		dma_release_channel(priv->chan_rx);
646 		priv->chan_rx = NULL;
647 	}
648 
649 	if (priv->rx_buf_dma) {
650 		dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
651 				  priv->rx_buf_dma);
652 		priv->rx_buf_virt = NULL;
653 		priv->rx_buf_dma = 0;
654 	}
655 
656 	return;
657 }
658 
659 static bool filter(struct dma_chan *chan, void *slave)
660 {
661 	struct pch_dma_slave *param = slave;
662 
663 	if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
664 						  chan->device->dev)) {
665 		chan->private = param;
666 		return true;
667 	} else {
668 		return false;
669 	}
670 }
671 
672 static void pch_request_dma(struct uart_port *port)
673 {
674 	dma_cap_mask_t mask;
675 	struct dma_chan *chan;
676 	struct pci_dev *dma_dev;
677 	struct pch_dma_slave *param;
678 	struct eg20t_port *priv =
679 				container_of(port, struct eg20t_port, port);
680 	dma_cap_zero(mask);
681 	dma_cap_set(DMA_SLAVE, mask);
682 
683 	/* Get DMA's dev information */
684 	dma_dev = pci_get_slot(priv->pdev->bus,
685 			PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0));
686 
687 	/* Set Tx DMA */
688 	param = &priv->param_tx;
689 	param->dma_dev = &dma_dev->dev;
690 	param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
691 
692 	param->tx_reg = port->mapbase + UART_TX;
693 	chan = dma_request_channel(mask, filter, param);
694 	if (!chan) {
695 		dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
696 			__func__);
697 		return;
698 	}
699 	priv->chan_tx = chan;
700 
701 	/* Set Rx DMA */
702 	param = &priv->param_rx;
703 	param->dma_dev = &dma_dev->dev;
704 	param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
705 
706 	param->rx_reg = port->mapbase + UART_RX;
707 	chan = dma_request_channel(mask, filter, param);
708 	if (!chan) {
709 		dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
710 			__func__);
711 		dma_release_channel(priv->chan_tx);
712 		priv->chan_tx = NULL;
713 		return;
714 	}
715 
716 	/* Get Consistent memory for DMA */
717 	priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
718 				    &priv->rx_buf_dma, GFP_KERNEL);
719 	priv->chan_rx = chan;
720 }
721 
722 static void pch_dma_rx_complete(void *arg)
723 {
724 	struct eg20t_port *priv = arg;
725 	struct uart_port *port = &priv->port;
726 	int count;
727 
728 	dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
729 	count = dma_push_rx(priv, priv->trigger_level);
730 	if (count)
731 		tty_flip_buffer_push(&port->state->port);
732 	async_tx_ack(priv->desc_rx);
733 	pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
734 					    PCH_UART_HAL_RX_ERR_INT);
735 }
736 
737 static void pch_dma_tx_complete(void *arg)
738 {
739 	struct eg20t_port *priv = arg;
740 	struct uart_port *port = &priv->port;
741 	struct circ_buf *xmit = &port->state->xmit;
742 	struct scatterlist *sg = priv->sg_tx_p;
743 	int i;
744 
745 	for (i = 0; i < priv->nent; i++, sg++) {
746 		xmit->tail += sg_dma_len(sg);
747 		port->icount.tx += sg_dma_len(sg);
748 	}
749 	xmit->tail &= UART_XMIT_SIZE - 1;
750 	async_tx_ack(priv->desc_tx);
751 	dma_unmap_sg(port->dev, sg, priv->orig_nent, DMA_TO_DEVICE);
752 	priv->tx_dma_use = 0;
753 	priv->nent = 0;
754 	priv->orig_nent = 0;
755 	kfree(priv->sg_tx_p);
756 	pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
757 }
758 
759 static int handle_rx_to(struct eg20t_port *priv)
760 {
761 	struct pch_uart_buffer *buf;
762 	int rx_size;
763 	int ret;
764 	if (!priv->start_rx) {
765 		pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
766 						     PCH_UART_HAL_RX_ERR_INT);
767 		return 0;
768 	}
769 	buf = &priv->rxbuf;
770 	do {
771 		rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
772 		ret = push_rx(priv, buf->buf, rx_size);
773 		if (ret)
774 			return 0;
775 	} while (rx_size == buf->size);
776 
777 	return PCH_UART_HANDLED_RX_INT;
778 }
779 
780 static int handle_rx(struct eg20t_port *priv)
781 {
782 	return handle_rx_to(priv);
783 }
784 
785 static int dma_handle_rx(struct eg20t_port *priv)
786 {
787 	struct uart_port *port = &priv->port;
788 	struct dma_async_tx_descriptor *desc;
789 	struct scatterlist *sg;
790 
791 	priv = container_of(port, struct eg20t_port, port);
792 	sg = &priv->sg_rx;
793 
794 	sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
795 
796 	sg_dma_len(sg) = priv->trigger_level;
797 
798 	sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
799 		     sg_dma_len(sg), offset_in_page(priv->rx_buf_virt));
800 
801 	sg_dma_address(sg) = priv->rx_buf_dma;
802 
803 	desc = dmaengine_prep_slave_sg(priv->chan_rx,
804 			sg, 1, DMA_DEV_TO_MEM,
805 			DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
806 
807 	if (!desc)
808 		return 0;
809 
810 	priv->desc_rx = desc;
811 	desc->callback = pch_dma_rx_complete;
812 	desc->callback_param = priv;
813 	desc->tx_submit(desc);
814 	dma_async_issue_pending(priv->chan_rx);
815 
816 	return PCH_UART_HANDLED_RX_INT;
817 }
818 
819 static unsigned int handle_tx(struct eg20t_port *priv)
820 {
821 	struct uart_port *port = &priv->port;
822 	struct circ_buf *xmit = &port->state->xmit;
823 	int fifo_size;
824 	int tx_empty;
825 
826 	if (!priv->start_tx) {
827 		dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
828 			__func__, jiffies);
829 		pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
830 		priv->tx_empty = 1;
831 		return 0;
832 	}
833 
834 	fifo_size = max(priv->fifo_size, 1);
835 	tx_empty = 1;
836 	if (port->x_char) {
837 		iowrite8(port->x_char, priv->membase + PCH_UART_THR);
838 		port->icount.tx++;
839 		port->x_char = 0;
840 		tx_empty = 0;
841 		fifo_size--;
842 	}
843 
844 	while (!uart_tx_stopped(port) && !uart_circ_empty(xmit) && fifo_size) {
845 		iowrite8(xmit->buf[xmit->tail], priv->membase + PCH_UART_THR);
846 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
847 		port->icount.tx++;
848 		fifo_size--;
849 		tx_empty = 0;
850 	}
851 
852 	priv->tx_empty = tx_empty;
853 
854 	if (tx_empty) {
855 		pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
856 		uart_write_wakeup(port);
857 	}
858 
859 	return PCH_UART_HANDLED_TX_INT;
860 }
861 
862 static unsigned int dma_handle_tx(struct eg20t_port *priv)
863 {
864 	struct uart_port *port = &priv->port;
865 	struct circ_buf *xmit = &port->state->xmit;
866 	struct scatterlist *sg;
867 	int nent;
868 	int fifo_size;
869 	struct dma_async_tx_descriptor *desc;
870 	int num;
871 	int i;
872 	int bytes;
873 	int size;
874 	int rem;
875 
876 	if (!priv->start_tx) {
877 		dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
878 			__func__, jiffies);
879 		pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
880 		priv->tx_empty = 1;
881 		return 0;
882 	}
883 
884 	if (priv->tx_dma_use) {
885 		dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
886 			__func__, jiffies);
887 		pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
888 		priv->tx_empty = 1;
889 		return 0;
890 	}
891 
892 	fifo_size = max(priv->fifo_size, 1);
893 
894 	if (port->x_char) {
895 		iowrite8(port->x_char, priv->membase + PCH_UART_THR);
896 		port->icount.tx++;
897 		port->x_char = 0;
898 		fifo_size--;
899 	}
900 
901 	bytes = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
902 	if (!bytes) {
903 		dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
904 		pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
905 		uart_write_wakeup(port);
906 		return 0;
907 	}
908 
909 	if (bytes > fifo_size) {
910 		num = bytes / fifo_size + 1;
911 		size = fifo_size;
912 		rem = bytes % fifo_size;
913 	} else {
914 		num = 1;
915 		size = bytes;
916 		rem = bytes;
917 	}
918 
919 	dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
920 		__func__, num, size, rem);
921 
922 	priv->tx_dma_use = 1;
923 
924 	priv->sg_tx_p = kmalloc_array(num, sizeof(struct scatterlist), GFP_ATOMIC);
925 	if (!priv->sg_tx_p) {
926 		dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
927 		return 0;
928 	}
929 
930 	sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
931 	sg = priv->sg_tx_p;
932 
933 	for (i = 0; i < num; i++, sg++) {
934 		if (i == (num - 1))
935 			sg_set_page(sg, virt_to_page(xmit->buf),
936 				    rem, fifo_size * i);
937 		else
938 			sg_set_page(sg, virt_to_page(xmit->buf),
939 				    size, fifo_size * i);
940 	}
941 
942 	sg = priv->sg_tx_p;
943 	nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
944 	if (!nent) {
945 		dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
946 		return 0;
947 	}
948 	priv->orig_nent = num;
949 	priv->nent = nent;
950 
951 	for (i = 0; i < nent; i++, sg++) {
952 		sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
953 			      fifo_size * i;
954 		sg_dma_address(sg) = (sg_dma_address(sg) &
955 				    ~(UART_XMIT_SIZE - 1)) + sg->offset;
956 		if (i == (nent - 1))
957 			sg_dma_len(sg) = rem;
958 		else
959 			sg_dma_len(sg) = size;
960 	}
961 
962 	desc = dmaengine_prep_slave_sg(priv->chan_tx,
963 					priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
964 					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
965 	if (!desc) {
966 		dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n",
967 			__func__);
968 		return 0;
969 	}
970 	dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
971 	priv->desc_tx = desc;
972 	desc->callback = pch_dma_tx_complete;
973 	desc->callback_param = priv;
974 
975 	desc->tx_submit(desc);
976 
977 	dma_async_issue_pending(priv->chan_tx);
978 
979 	return PCH_UART_HANDLED_TX_INT;
980 }
981 
982 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
983 {
984 	struct uart_port *port = &priv->port;
985 	struct tty_struct *tty = tty_port_tty_get(&port->state->port);
986 	char   *error_msg[5] = {};
987 	int    i = 0;
988 
989 	if (lsr & PCH_UART_LSR_ERR)
990 		error_msg[i++] = "Error data in FIFO\n";
991 
992 	if (lsr & UART_LSR_FE) {
993 		port->icount.frame++;
994 		error_msg[i++] = "  Framing Error\n";
995 	}
996 
997 	if (lsr & UART_LSR_PE) {
998 		port->icount.parity++;
999 		error_msg[i++] = "  Parity Error\n";
1000 	}
1001 
1002 	if (lsr & UART_LSR_OE) {
1003 		port->icount.overrun++;
1004 		error_msg[i++] = "  Overrun Error\n";
1005 	}
1006 
1007 	if (tty == NULL) {
1008 		for (i = 0; error_msg[i] != NULL; i++)
1009 			dev_err(&priv->pdev->dev, error_msg[i]);
1010 	} else {
1011 		tty_kref_put(tty);
1012 	}
1013 }
1014 
1015 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1016 {
1017 	struct eg20t_port *priv = dev_id;
1018 	unsigned int handled;
1019 	u8 lsr;
1020 	int ret = 0;
1021 	unsigned char iid;
1022 	unsigned long flags;
1023 	int next = 1;
1024 	u8 msr;
1025 
1026 	spin_lock_irqsave(&priv->lock, flags);
1027 	handled = 0;
1028 	while (next) {
1029 		iid = pch_uart_hal_get_iid(priv);
1030 		if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1031 			break;
1032 		switch (iid) {
1033 		case PCH_UART_IID_RLS:	/* Receiver Line Status */
1034 			lsr = pch_uart_hal_get_line_status(priv);
1035 			if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1036 						UART_LSR_PE | UART_LSR_OE)) {
1037 				pch_uart_err_ir(priv, lsr);
1038 				ret = PCH_UART_HANDLED_RX_ERR_INT;
1039 			} else {
1040 				ret = PCH_UART_HANDLED_LS_INT;
1041 			}
1042 			break;
1043 		case PCH_UART_IID_RDR:	/* Received Data Ready */
1044 			if (priv->use_dma) {
1045 				pch_uart_hal_disable_interrupt(priv,
1046 						PCH_UART_HAL_RX_INT |
1047 						PCH_UART_HAL_RX_ERR_INT);
1048 				ret = dma_handle_rx(priv);
1049 				if (!ret)
1050 					pch_uart_hal_enable_interrupt(priv,
1051 						PCH_UART_HAL_RX_INT |
1052 						PCH_UART_HAL_RX_ERR_INT);
1053 			} else {
1054 				ret = handle_rx(priv);
1055 			}
1056 			break;
1057 		case PCH_UART_IID_RDR_TO:	/* Received Data Ready
1058 						   (FIFO Timeout) */
1059 			ret = handle_rx_to(priv);
1060 			break;
1061 		case PCH_UART_IID_THRE:	/* Transmitter Holding Register
1062 						   Empty */
1063 			if (priv->use_dma)
1064 				ret = dma_handle_tx(priv);
1065 			else
1066 				ret = handle_tx(priv);
1067 			break;
1068 		case PCH_UART_IID_MS:	/* Modem Status */
1069 			msr = pch_uart_hal_get_modem(priv);
1070 			next = 0; /* MS ir prioirty is the lowest. So, MS ir
1071 				     means final interrupt */
1072 			if ((msr & UART_MSR_ANY_DELTA) == 0)
1073 				break;
1074 			ret |= PCH_UART_HANDLED_MS_INT;
1075 			break;
1076 		default:	/* Never junp to this label */
1077 			dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1078 				iid, jiffies);
1079 			ret = -1;
1080 			next = 0;
1081 			break;
1082 		}
1083 		handled |= (unsigned int)ret;
1084 	}
1085 
1086 	spin_unlock_irqrestore(&priv->lock, flags);
1087 	return IRQ_RETVAL(handled);
1088 }
1089 
1090 /* This function tests whether the transmitter fifo and shifter for the port
1091 						described by 'port' is empty. */
1092 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1093 {
1094 	struct eg20t_port *priv;
1095 
1096 	priv = container_of(port, struct eg20t_port, port);
1097 	if (priv->tx_empty)
1098 		return TIOCSER_TEMT;
1099 	else
1100 		return 0;
1101 }
1102 
1103 /* Returns the current state of modem control inputs. */
1104 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1105 {
1106 	struct eg20t_port *priv;
1107 	u8 modem;
1108 	unsigned int ret = 0;
1109 
1110 	priv = container_of(port, struct eg20t_port, port);
1111 	modem = pch_uart_hal_get_modem(priv);
1112 
1113 	if (modem & UART_MSR_DCD)
1114 		ret |= TIOCM_CAR;
1115 
1116 	if (modem & UART_MSR_RI)
1117 		ret |= TIOCM_RNG;
1118 
1119 	if (modem & UART_MSR_DSR)
1120 		ret |= TIOCM_DSR;
1121 
1122 	if (modem & UART_MSR_CTS)
1123 		ret |= TIOCM_CTS;
1124 
1125 	return ret;
1126 }
1127 
1128 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1129 {
1130 	u32 mcr = 0;
1131 	struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1132 
1133 	if (mctrl & TIOCM_DTR)
1134 		mcr |= UART_MCR_DTR;
1135 	if (mctrl & TIOCM_RTS)
1136 		mcr |= UART_MCR_RTS;
1137 	if (mctrl & TIOCM_LOOP)
1138 		mcr |= UART_MCR_LOOP;
1139 
1140 	if (priv->mcr & UART_MCR_AFE)
1141 		mcr |= UART_MCR_AFE;
1142 
1143 	if (mctrl)
1144 		iowrite8(mcr, priv->membase + UART_MCR);
1145 }
1146 
1147 static void pch_uart_stop_tx(struct uart_port *port)
1148 {
1149 	struct eg20t_port *priv;
1150 	priv = container_of(port, struct eg20t_port, port);
1151 	priv->start_tx = 0;
1152 	priv->tx_dma_use = 0;
1153 }
1154 
1155 static void pch_uart_start_tx(struct uart_port *port)
1156 {
1157 	struct eg20t_port *priv;
1158 
1159 	priv = container_of(port, struct eg20t_port, port);
1160 
1161 	if (priv->use_dma) {
1162 		if (priv->tx_dma_use) {
1163 			dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1164 				__func__);
1165 			return;
1166 		}
1167 	}
1168 
1169 	priv->start_tx = 1;
1170 	pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1171 }
1172 
1173 static void pch_uart_stop_rx(struct uart_port *port)
1174 {
1175 	struct eg20t_port *priv;
1176 	priv = container_of(port, struct eg20t_port, port);
1177 	priv->start_rx = 0;
1178 	pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1179 					     PCH_UART_HAL_RX_ERR_INT);
1180 }
1181 
1182 /* Enable the modem status interrupts. */
1183 static void pch_uart_enable_ms(struct uart_port *port)
1184 {
1185 	struct eg20t_port *priv;
1186 	priv = container_of(port, struct eg20t_port, port);
1187 	pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1188 }
1189 
1190 /* Control the transmission of a break signal. */
1191 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1192 {
1193 	struct eg20t_port *priv;
1194 	unsigned long flags;
1195 
1196 	priv = container_of(port, struct eg20t_port, port);
1197 	spin_lock_irqsave(&priv->lock, flags);
1198 	pch_uart_hal_set_break(priv, ctl);
1199 	spin_unlock_irqrestore(&priv->lock, flags);
1200 }
1201 
1202 /* Grab any interrupt resources and initialise any low level driver state. */
1203 static int pch_uart_startup(struct uart_port *port)
1204 {
1205 	struct eg20t_port *priv;
1206 	int ret;
1207 	int fifo_size;
1208 	int trigger_level;
1209 
1210 	priv = container_of(port, struct eg20t_port, port);
1211 	priv->tx_empty = 1;
1212 
1213 	if (port->uartclk)
1214 		priv->uartclk = port->uartclk;
1215 	else
1216 		port->uartclk = priv->uartclk;
1217 
1218 	pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1219 	ret = pch_uart_hal_set_line(priv, default_baud,
1220 			      PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1221 			      PCH_UART_HAL_STB1);
1222 	if (ret)
1223 		return ret;
1224 
1225 	switch (priv->fifo_size) {
1226 	case 256:
1227 		fifo_size = PCH_UART_HAL_FIFO256;
1228 		break;
1229 	case 64:
1230 		fifo_size = PCH_UART_HAL_FIFO64;
1231 		break;
1232 	case 16:
1233 		fifo_size = PCH_UART_HAL_FIFO16;
1234 		break;
1235 	case 1:
1236 	default:
1237 		fifo_size = PCH_UART_HAL_FIFO_DIS;
1238 		break;
1239 	}
1240 
1241 	switch (priv->trigger) {
1242 	case PCH_UART_HAL_TRIGGER1:
1243 		trigger_level = 1;
1244 		break;
1245 	case PCH_UART_HAL_TRIGGER_L:
1246 		trigger_level = priv->fifo_size / 4;
1247 		break;
1248 	case PCH_UART_HAL_TRIGGER_M:
1249 		trigger_level = priv->fifo_size / 2;
1250 		break;
1251 	case PCH_UART_HAL_TRIGGER_H:
1252 	default:
1253 		trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1254 		break;
1255 	}
1256 
1257 	priv->trigger_level = trigger_level;
1258 	ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1259 				    fifo_size, priv->trigger);
1260 	if (ret < 0)
1261 		return ret;
1262 
1263 	ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1264 			priv->irq_name, priv);
1265 	if (ret < 0)
1266 		return ret;
1267 
1268 	if (priv->use_dma)
1269 		pch_request_dma(port);
1270 
1271 	priv->start_rx = 1;
1272 	pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1273 					    PCH_UART_HAL_RX_ERR_INT);
1274 	uart_update_timeout(port, CS8, default_baud);
1275 
1276 	return 0;
1277 }
1278 
1279 static void pch_uart_shutdown(struct uart_port *port)
1280 {
1281 	struct eg20t_port *priv;
1282 	int ret;
1283 
1284 	priv = container_of(port, struct eg20t_port, port);
1285 	pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1286 	pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1287 	ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1288 			      PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1289 	if (ret)
1290 		dev_err(priv->port.dev,
1291 			"pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1292 
1293 	pch_free_dma(port);
1294 
1295 	free_irq(priv->port.irq, priv);
1296 }
1297 
1298 /* Change the port parameters, including word length, parity, stop
1299  *bits.  Update read_status_mask and ignore_status_mask to indicate
1300  *the types of events we are interested in receiving.  */
1301 static void pch_uart_set_termios(struct uart_port *port,
1302 				 struct ktermios *termios,
1303 				 const struct ktermios *old)
1304 {
1305 	int rtn;
1306 	unsigned int baud, parity, bits, stb;
1307 	struct eg20t_port *priv;
1308 	unsigned long flags;
1309 
1310 	priv = container_of(port, struct eg20t_port, port);
1311 	switch (termios->c_cflag & CSIZE) {
1312 	case CS5:
1313 		bits = PCH_UART_HAL_5BIT;
1314 		break;
1315 	case CS6:
1316 		bits = PCH_UART_HAL_6BIT;
1317 		break;
1318 	case CS7:
1319 		bits = PCH_UART_HAL_7BIT;
1320 		break;
1321 	default:		/* CS8 */
1322 		bits = PCH_UART_HAL_8BIT;
1323 		break;
1324 	}
1325 	if (termios->c_cflag & CSTOPB)
1326 		stb = PCH_UART_HAL_STB2;
1327 	else
1328 		stb = PCH_UART_HAL_STB1;
1329 
1330 	if (termios->c_cflag & PARENB) {
1331 		if (termios->c_cflag & PARODD)
1332 			parity = PCH_UART_HAL_PARITY_ODD;
1333 		else
1334 			parity = PCH_UART_HAL_PARITY_EVEN;
1335 
1336 	} else
1337 		parity = PCH_UART_HAL_PARITY_NONE;
1338 
1339 	/* Only UART0 has auto hardware flow function */
1340 	if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1341 		priv->mcr |= UART_MCR_AFE;
1342 	else
1343 		priv->mcr &= ~UART_MCR_AFE;
1344 
1345 	termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1346 
1347 	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1348 
1349 	spin_lock_irqsave(&priv->lock, flags);
1350 	spin_lock(&port->lock);
1351 
1352 	uart_update_timeout(port, termios->c_cflag, baud);
1353 	rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1354 	if (rtn)
1355 		goto out;
1356 
1357 	pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1358 	/* Don't rewrite B0 */
1359 	if (tty_termios_baud_rate(termios))
1360 		tty_termios_encode_baud_rate(termios, baud, baud);
1361 
1362 out:
1363 	spin_unlock(&port->lock);
1364 	spin_unlock_irqrestore(&priv->lock, flags);
1365 }
1366 
1367 static const char *pch_uart_type(struct uart_port *port)
1368 {
1369 	return KBUILD_MODNAME;
1370 }
1371 
1372 static void pch_uart_release_port(struct uart_port *port)
1373 {
1374 	struct eg20t_port *priv;
1375 
1376 	priv = container_of(port, struct eg20t_port, port);
1377 	pci_iounmap(priv->pdev, priv->membase);
1378 	pci_release_regions(priv->pdev);
1379 }
1380 
1381 static int pch_uart_request_port(struct uart_port *port)
1382 {
1383 	struct eg20t_port *priv;
1384 	int ret;
1385 	void __iomem *membase;
1386 
1387 	priv = container_of(port, struct eg20t_port, port);
1388 	ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1389 	if (ret < 0)
1390 		return -EBUSY;
1391 
1392 	membase = pci_iomap(priv->pdev, 1, 0);
1393 	if (!membase) {
1394 		pci_release_regions(priv->pdev);
1395 		return -EBUSY;
1396 	}
1397 	priv->membase = port->membase = membase;
1398 
1399 	return 0;
1400 }
1401 
1402 static void pch_uart_config_port(struct uart_port *port, int type)
1403 {
1404 	struct eg20t_port *priv;
1405 
1406 	priv = container_of(port, struct eg20t_port, port);
1407 	if (type & UART_CONFIG_TYPE) {
1408 		port->type = priv->port_type;
1409 		pch_uart_request_port(port);
1410 	}
1411 }
1412 
1413 static int pch_uart_verify_port(struct uart_port *port,
1414 				struct serial_struct *serinfo)
1415 {
1416 	struct eg20t_port *priv;
1417 
1418 	priv = container_of(port, struct eg20t_port, port);
1419 	if (serinfo->flags & UPF_LOW_LATENCY) {
1420 		dev_info(priv->port.dev,
1421 			"PCH UART : Use PIO Mode (without DMA)\n");
1422 		priv->use_dma = 0;
1423 		serinfo->flags &= ~UPF_LOW_LATENCY;
1424 	} else {
1425 #ifndef CONFIG_PCH_DMA
1426 		dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1427 			__func__);
1428 		return -EOPNOTSUPP;
1429 #endif
1430 		if (!priv->use_dma) {
1431 			pch_request_dma(port);
1432 			if (priv->chan_rx)
1433 				priv->use_dma = 1;
1434 		}
1435 		dev_info(priv->port.dev, "PCH UART: %s\n",
1436 				priv->use_dma ?
1437 				"Use DMA Mode" : "No DMA");
1438 	}
1439 
1440 	return 0;
1441 }
1442 
1443 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
1444 /*
1445  *	Wait for transmitter & holding register to empty
1446  */
1447 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1448 {
1449 	unsigned int status, tmout = 10000;
1450 
1451 	/* Wait up to 10ms for the character(s) to be sent. */
1452 	for (;;) {
1453 		status = ioread8(up->membase + UART_LSR);
1454 
1455 		if ((status & bits) == bits)
1456 			break;
1457 		if (--tmout == 0)
1458 			break;
1459 		udelay(1);
1460 	}
1461 
1462 	/* Wait up to 1s for flow control if necessary */
1463 	if (up->port.flags & UPF_CONS_FLOW) {
1464 		unsigned int tmout;
1465 		for (tmout = 1000000; tmout; tmout--) {
1466 			unsigned int msr = ioread8(up->membase + UART_MSR);
1467 			if (msr & UART_MSR_CTS)
1468 				break;
1469 			udelay(1);
1470 			touch_nmi_watchdog();
1471 		}
1472 	}
1473 }
1474 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
1475 
1476 #ifdef CONFIG_CONSOLE_POLL
1477 /*
1478  * Console polling routines for communicate via uart while
1479  * in an interrupt or debug context.
1480  */
1481 static int pch_uart_get_poll_char(struct uart_port *port)
1482 {
1483 	struct eg20t_port *priv =
1484 		container_of(port, struct eg20t_port, port);
1485 	u8 lsr = ioread8(priv->membase + UART_LSR);
1486 
1487 	if (!(lsr & UART_LSR_DR))
1488 		return NO_POLL_CHAR;
1489 
1490 	return ioread8(priv->membase + PCH_UART_RBR);
1491 }
1492 
1493 
1494 static void pch_uart_put_poll_char(struct uart_port *port,
1495 			 unsigned char c)
1496 {
1497 	unsigned int ier;
1498 	struct eg20t_port *priv =
1499 		container_of(port, struct eg20t_port, port);
1500 
1501 	/*
1502 	 * First save the IER then disable the interrupts
1503 	 */
1504 	ier = ioread8(priv->membase + UART_IER);
1505 	pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1506 
1507 	wait_for_xmitr(priv, UART_LSR_THRE);
1508 	/*
1509 	 * Send the character out.
1510 	 */
1511 	iowrite8(c, priv->membase + PCH_UART_THR);
1512 
1513 	/*
1514 	 * Finally, wait for transmitter to become empty
1515 	 * and restore the IER
1516 	 */
1517 	wait_for_xmitr(priv, UART_LSR_BOTH_EMPTY);
1518 	iowrite8(ier, priv->membase + UART_IER);
1519 }
1520 #endif /* CONFIG_CONSOLE_POLL */
1521 
1522 static const struct uart_ops pch_uart_ops = {
1523 	.tx_empty = pch_uart_tx_empty,
1524 	.set_mctrl = pch_uart_set_mctrl,
1525 	.get_mctrl = pch_uart_get_mctrl,
1526 	.stop_tx = pch_uart_stop_tx,
1527 	.start_tx = pch_uart_start_tx,
1528 	.stop_rx = pch_uart_stop_rx,
1529 	.enable_ms = pch_uart_enable_ms,
1530 	.break_ctl = pch_uart_break_ctl,
1531 	.startup = pch_uart_startup,
1532 	.shutdown = pch_uart_shutdown,
1533 	.set_termios = pch_uart_set_termios,
1534 /*	.pm		= pch_uart_pm,		Not supported yet */
1535 	.type = pch_uart_type,
1536 	.release_port = pch_uart_release_port,
1537 	.request_port = pch_uart_request_port,
1538 	.config_port = pch_uart_config_port,
1539 	.verify_port = pch_uart_verify_port,
1540 #ifdef CONFIG_CONSOLE_POLL
1541 	.poll_get_char = pch_uart_get_poll_char,
1542 	.poll_put_char = pch_uart_put_poll_char,
1543 #endif
1544 };
1545 
1546 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1547 
1548 static void pch_console_putchar(struct uart_port *port, unsigned char ch)
1549 {
1550 	struct eg20t_port *priv =
1551 		container_of(port, struct eg20t_port, port);
1552 
1553 	wait_for_xmitr(priv, UART_LSR_THRE);
1554 	iowrite8(ch, priv->membase + PCH_UART_THR);
1555 }
1556 
1557 /*
1558  *	Print a string to the serial port trying not to disturb
1559  *	any possible real use of the port...
1560  *
1561  *	The console_lock must be held when we get here.
1562  */
1563 static void
1564 pch_console_write(struct console *co, const char *s, unsigned int count)
1565 {
1566 	struct eg20t_port *priv;
1567 	unsigned long flags;
1568 	int priv_locked = 1;
1569 	int port_locked = 1;
1570 	u8 ier;
1571 
1572 	priv = pch_uart_ports[co->index];
1573 
1574 	touch_nmi_watchdog();
1575 
1576 	local_irq_save(flags);
1577 	if (priv->port.sysrq) {
1578 		/* call to uart_handle_sysrq_char already took the priv lock */
1579 		priv_locked = 0;
1580 		/* serial8250_handle_port() already took the port lock */
1581 		port_locked = 0;
1582 	} else if (oops_in_progress) {
1583 		priv_locked = spin_trylock(&priv->lock);
1584 		port_locked = spin_trylock(&priv->port.lock);
1585 	} else {
1586 		spin_lock(&priv->lock);
1587 		spin_lock(&priv->port.lock);
1588 	}
1589 
1590 	/*
1591 	 *	First save the IER then disable the interrupts
1592 	 */
1593 	ier = ioread8(priv->membase + UART_IER);
1594 
1595 	pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1596 
1597 	uart_console_write(&priv->port, s, count, pch_console_putchar);
1598 
1599 	/*
1600 	 *	Finally, wait for transmitter to become empty
1601 	 *	and restore the IER
1602 	 */
1603 	wait_for_xmitr(priv, UART_LSR_BOTH_EMPTY);
1604 	iowrite8(ier, priv->membase + UART_IER);
1605 
1606 	if (port_locked)
1607 		spin_unlock(&priv->port.lock);
1608 	if (priv_locked)
1609 		spin_unlock(&priv->lock);
1610 	local_irq_restore(flags);
1611 }
1612 
1613 static int __init pch_console_setup(struct console *co, char *options)
1614 {
1615 	struct uart_port *port;
1616 	int baud = default_baud;
1617 	int bits = 8;
1618 	int parity = 'n';
1619 	int flow = 'n';
1620 
1621 	/*
1622 	 * Check whether an invalid uart number has been specified, and
1623 	 * if so, search for the first available port that does have
1624 	 * console support.
1625 	 */
1626 	if (co->index >= PCH_UART_NR)
1627 		co->index = 0;
1628 	port = &pch_uart_ports[co->index]->port;
1629 
1630 	if (!port || (!port->iobase && !port->membase))
1631 		return -ENODEV;
1632 
1633 	port->uartclk = pch_uart_get_uartclk();
1634 
1635 	if (options)
1636 		uart_parse_options(options, &baud, &parity, &bits, &flow);
1637 
1638 	return uart_set_options(port, co, baud, parity, bits, flow);
1639 }
1640 
1641 static struct uart_driver pch_uart_driver;
1642 
1643 static struct console pch_console = {
1644 	.name		= PCH_UART_DRIVER_DEVICE,
1645 	.write		= pch_console_write,
1646 	.device		= uart_console_device,
1647 	.setup		= pch_console_setup,
1648 	.flags		= CON_PRINTBUFFER | CON_ANYTIME,
1649 	.index		= -1,
1650 	.data		= &pch_uart_driver,
1651 };
1652 
1653 #define PCH_CONSOLE	(&pch_console)
1654 #else
1655 #define PCH_CONSOLE	NULL
1656 #endif	/* CONFIG_SERIAL_PCH_UART_CONSOLE */
1657 
1658 static struct uart_driver pch_uart_driver = {
1659 	.owner = THIS_MODULE,
1660 	.driver_name = KBUILD_MODNAME,
1661 	.dev_name = PCH_UART_DRIVER_DEVICE,
1662 	.major = 0,
1663 	.minor = 0,
1664 	.nr = PCH_UART_NR,
1665 	.cons = PCH_CONSOLE,
1666 };
1667 
1668 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1669 					     const struct pci_device_id *id)
1670 {
1671 	struct eg20t_port *priv;
1672 	int ret;
1673 	unsigned int iobase;
1674 	unsigned int mapbase;
1675 	unsigned char *rxbuf;
1676 	int fifosize;
1677 	int port_type;
1678 	struct pch_uart_driver_data *board;
1679 	char name[32];
1680 
1681 	board = &drv_dat[id->driver_data];
1682 	port_type = board->port_type;
1683 
1684 	priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1685 	if (priv == NULL)
1686 		goto init_port_alloc_err;
1687 
1688 	rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1689 	if (!rxbuf)
1690 		goto init_port_free_txbuf;
1691 
1692 	switch (port_type) {
1693 	case PORT_PCH_8LINE:
1694 		fifosize = 256; /* EG20T/ML7213: UART0 */
1695 		break;
1696 	case PORT_PCH_2LINE:
1697 		fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1698 		break;
1699 	default:
1700 		dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1701 		goto init_port_hal_free;
1702 	}
1703 
1704 	pci_enable_msi(pdev);
1705 	pci_set_master(pdev);
1706 
1707 	spin_lock_init(&priv->lock);
1708 
1709 	iobase = pci_resource_start(pdev, 0);
1710 	mapbase = pci_resource_start(pdev, 1);
1711 	priv->mapbase = mapbase;
1712 	priv->iobase = iobase;
1713 	priv->pdev = pdev;
1714 	priv->tx_empty = 1;
1715 	priv->rxbuf.buf = rxbuf;
1716 	priv->rxbuf.size = PAGE_SIZE;
1717 
1718 	priv->fifo_size = fifosize;
1719 	priv->uartclk = pch_uart_get_uartclk();
1720 	priv->port_type = port_type;
1721 	priv->port.dev = &pdev->dev;
1722 	priv->port.iobase = iobase;
1723 	priv->port.membase = NULL;
1724 	priv->port.mapbase = mapbase;
1725 	priv->port.irq = pdev->irq;
1726 	priv->port.iotype = UPIO_PORT;
1727 	priv->port.ops = &pch_uart_ops;
1728 	priv->port.flags = UPF_BOOT_AUTOCONF;
1729 	priv->port.fifosize = fifosize;
1730 	priv->port.line = board->line_no;
1731 	priv->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PCH_UART_CONSOLE);
1732 	priv->trigger = PCH_UART_HAL_TRIGGER_M;
1733 
1734 	snprintf(priv->irq_name, IRQ_NAME_SIZE,
1735 		 KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
1736 		 priv->port.line);
1737 
1738 	spin_lock_init(&priv->port.lock);
1739 
1740 	pci_set_drvdata(pdev, priv);
1741 	priv->trigger_level = 1;
1742 	priv->fcr = 0;
1743 
1744 	if (pdev->dev.of_node)
1745 		of_property_read_u32(pdev->dev.of_node, "clock-frequency"
1746 					 , &user_uartclk);
1747 
1748 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1749 	pch_uart_ports[board->line_no] = priv;
1750 #endif
1751 	ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1752 	if (ret < 0)
1753 		goto init_port_hal_free;
1754 
1755 	snprintf(name, sizeof(name), "uart%d_regs", priv->port.line);
1756 	debugfs_create_file(name, S_IFREG | S_IRUGO, NULL, priv,
1757 			    &port_regs_ops);
1758 
1759 	return priv;
1760 
1761 init_port_hal_free:
1762 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1763 	pch_uart_ports[board->line_no] = NULL;
1764 #endif
1765 	free_page((unsigned long)rxbuf);
1766 init_port_free_txbuf:
1767 	kfree(priv);
1768 init_port_alloc_err:
1769 
1770 	return NULL;
1771 }
1772 
1773 static void pch_uart_exit_port(struct eg20t_port *priv)
1774 {
1775 	char name[32];
1776 
1777 	snprintf(name, sizeof(name), "uart%d_regs", priv->port.line);
1778 	debugfs_remove(debugfs_lookup(name, NULL));
1779 	uart_remove_one_port(&pch_uart_driver, &priv->port);
1780 	free_page((unsigned long)priv->rxbuf.buf);
1781 }
1782 
1783 static void pch_uart_pci_remove(struct pci_dev *pdev)
1784 {
1785 	struct eg20t_port *priv = pci_get_drvdata(pdev);
1786 
1787 	pci_disable_msi(pdev);
1788 
1789 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1790 	pch_uart_ports[priv->port.line] = NULL;
1791 #endif
1792 	pch_uart_exit_port(priv);
1793 	pci_disable_device(pdev);
1794 	kfree(priv);
1795 	return;
1796 }
1797 
1798 static int __maybe_unused pch_uart_pci_suspend(struct device *dev)
1799 {
1800 	struct eg20t_port *priv = dev_get_drvdata(dev);
1801 
1802 	uart_suspend_port(&pch_uart_driver, &priv->port);
1803 
1804 	return 0;
1805 }
1806 
1807 static int __maybe_unused pch_uart_pci_resume(struct device *dev)
1808 {
1809 	struct eg20t_port *priv = dev_get_drvdata(dev);
1810 
1811 	uart_resume_port(&pch_uart_driver, &priv->port);
1812 
1813 	return 0;
1814 }
1815 
1816 static const struct pci_device_id pch_uart_pci_id[] = {
1817 	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1818 	 .driver_data = pch_et20t_uart0},
1819 	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1820 	 .driver_data = pch_et20t_uart1},
1821 	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1822 	 .driver_data = pch_et20t_uart2},
1823 	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1824 	 .driver_data = pch_et20t_uart3},
1825 	{PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1826 	 .driver_data = pch_ml7213_uart0},
1827 	{PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1828 	 .driver_data = pch_ml7213_uart1},
1829 	{PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1830 	 .driver_data = pch_ml7213_uart2},
1831 	{PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1832 	 .driver_data = pch_ml7223_uart0},
1833 	{PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1834 	 .driver_data = pch_ml7223_uart1},
1835 	{PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1836 	 .driver_data = pch_ml7831_uart0},
1837 	{PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1838 	 .driver_data = pch_ml7831_uart1},
1839 	{0,},
1840 };
1841 
1842 static int pch_uart_pci_probe(struct pci_dev *pdev,
1843 					const struct pci_device_id *id)
1844 {
1845 	int ret;
1846 	struct eg20t_port *priv;
1847 
1848 	ret = pci_enable_device(pdev);
1849 	if (ret < 0)
1850 		goto probe_error;
1851 
1852 	priv = pch_uart_init_port(pdev, id);
1853 	if (!priv) {
1854 		ret = -EBUSY;
1855 		goto probe_disable_device;
1856 	}
1857 	pci_set_drvdata(pdev, priv);
1858 
1859 	return ret;
1860 
1861 probe_disable_device:
1862 	pci_disable_msi(pdev);
1863 	pci_disable_device(pdev);
1864 probe_error:
1865 	return ret;
1866 }
1867 
1868 static SIMPLE_DEV_PM_OPS(pch_uart_pci_pm_ops,
1869 			 pch_uart_pci_suspend,
1870 			 pch_uart_pci_resume);
1871 
1872 static struct pci_driver pch_uart_pci_driver = {
1873 	.name = "pch_uart",
1874 	.id_table = pch_uart_pci_id,
1875 	.probe = pch_uart_pci_probe,
1876 	.remove = pch_uart_pci_remove,
1877 	.driver.pm = &pch_uart_pci_pm_ops,
1878 };
1879 
1880 static int __init pch_uart_module_init(void)
1881 {
1882 	int ret;
1883 
1884 	/* register as UART driver */
1885 	ret = uart_register_driver(&pch_uart_driver);
1886 	if (ret < 0)
1887 		return ret;
1888 
1889 	/* register as PCI driver */
1890 	ret = pci_register_driver(&pch_uart_pci_driver);
1891 	if (ret < 0)
1892 		uart_unregister_driver(&pch_uart_driver);
1893 
1894 	return ret;
1895 }
1896 module_init(pch_uart_module_init);
1897 
1898 static void __exit pch_uart_module_exit(void)
1899 {
1900 	pci_unregister_driver(&pch_uart_pci_driver);
1901 	uart_unregister_driver(&pch_uart_driver);
1902 }
1903 module_exit(pch_uart_module_exit);
1904 
1905 MODULE_LICENSE("GPL v2");
1906 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1907 MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);
1908 
1909 module_param(default_baud, uint, S_IRUGO);
1910 MODULE_PARM_DESC(default_baud,
1911                  "Default BAUD for initial driver state and console (default 9600)");
1912 module_param(user_uartclk, uint, S_IRUGO);
1913 MODULE_PARM_DESC(user_uartclk,
1914                  "Override UART default or board specific UART clock");
1915